]>
Commit | Line | Data |
---|---|---|
23308c54 MB |
1 | /* |
2 | * arch/powerpc/platforms/83xx/mpc832x_rdb.c | |
3 | * | |
4 | * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved. | |
5 | * | |
6 | * Description: | |
7 | * MPC832x RDB board specific routines. | |
8 | * This file is based on mpc832x_mds.c and mpc8313_rdb.c | |
9 | * Author: Michael Barkowski <michael.barkowski@freescale.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
ba3bdff5 | 18 | #include <linux/interrupt.h> |
8237bf08 | 19 | #include <linux/spi/spi.h> |
ba3bdff5 AV |
20 | #include <linux/spi/mmc_spi.h> |
21 | #include <linux/mmc/host.h> | |
882407b9 | 22 | #include <linux/of_platform.h> |
23308c54 | 23 | |
23308c54 MB |
24 | #include <asm/time.h> |
25 | #include <asm/ipic.h> | |
26 | #include <asm/udbg.h> | |
27 | #include <asm/qe.h> | |
28 | #include <asm/qe_ic.h> | |
8237bf08 | 29 | #include <sysdev/fsl_soc.h> |
23308c54 MB |
30 | |
31 | #include "mpc83xx.h" | |
32 | ||
33 | #undef DEBUG | |
34 | #ifdef DEBUG | |
35 | #define DBG(fmt...) udbg_printf(fmt) | |
36 | #else | |
37 | #define DBG(fmt...) | |
38 | #endif | |
39 | ||
8237bf08 AV |
40 | static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity) |
41 | { | |
42 | pr_debug("%s %d %d\n", __func__, cs, polarity); | |
43 | par_io_data_set(3, 13, polarity); | |
44 | } | |
45 | ||
46 | static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity) | |
47 | { | |
48 | pr_debug("%s %d %d\n", __func__, cs, polarity); | |
49 | par_io_data_set(3, 13, !polarity); | |
50 | } | |
51 | ||
ba3bdff5 AV |
52 | static struct mmc_spi_platform_data mpc832x_mmc_pdata = { |
53 | .ocr_mask = MMC_VDD_33_34, | |
54 | }; | |
55 | ||
8237bf08 AV |
56 | static struct spi_board_info mpc832x_spi_boardinfo = { |
57 | .bus_num = 0x4c0, | |
58 | .chip_select = 0, | |
59 | .max_speed_hz = 50000000, | |
ba3bdff5 AV |
60 | .modalias = "mmc_spi", |
61 | .platform_data = &mpc832x_mmc_pdata, | |
8237bf08 AV |
62 | }; |
63 | ||
64 | static int __init mpc832x_spi_init(void) | |
65 | { | |
8237bf08 AV |
66 | par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */ |
67 | par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */ | |
68 | par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */ | |
69 | par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */ | |
70 | ||
71 | par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */ | |
72 | par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */ | |
73 | par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */ | |
74 | ||
75 | return fsl_spi_init(&mpc832x_spi_boardinfo, 1, | |
76 | mpc83xx_spi_activate_cs, | |
77 | mpc83xx_spi_deactivate_cs); | |
78 | } | |
79 | ||
6392f184 | 80 | machine_device_initcall(mpc832x_rdb, mpc832x_spi_init); |
8237bf08 | 81 | |
23308c54 MB |
82 | /* ************************************************************************ |
83 | * | |
84 | * Setup the architecture | |
85 | * | |
86 | */ | |
87 | static void __init mpc832x_rdb_setup_arch(void) | |
88 | { | |
c9ec87e5 | 89 | #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE) |
23308c54 | 90 | struct device_node *np; |
c9ec87e5 | 91 | #endif |
23308c54 MB |
92 | |
93 | if (ppc_md.progress) | |
94 | ppc_md.progress("mpc832x_rdb_setup_arch()", 0); | |
95 | ||
96 | #ifdef CONFIG_PCI | |
c9438aff | 97 | for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") |
09b55f76 | 98 | mpc83xx_add_bridge(np); |
23308c54 MB |
99 | #endif |
100 | ||
101 | #ifdef CONFIG_QUICC_ENGINE | |
102 | qe_reset(); | |
103 | ||
104 | if ((np = of_find_node_by_name(np, "par_io")) != NULL) { | |
105 | par_io_init(np); | |
106 | of_node_put(np); | |
107 | ||
108 | for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) | |
109 | par_io_of_config(np); | |
110 | } | |
111 | #endif /* CONFIG_QUICC_ENGINE */ | |
112 | } | |
113 | ||
114 | static struct of_device_id mpc832x_ids[] = { | |
115 | { .type = "soc", }, | |
116 | { .compatible = "soc", }, | |
117 | { .type = "qe", }, | |
a2dd70a1 | 118 | { .compatible = "fsl,qe", }, |
23308c54 MB |
119 | {}, |
120 | }; | |
121 | ||
122 | static int __init mpc832x_declare_of_platform_devices(void) | |
123 | { | |
23308c54 MB |
124 | /* Publish the QE devices */ |
125 | of_platform_bus_probe(NULL, mpc832x_ids, NULL); | |
126 | ||
127 | return 0; | |
128 | } | |
6392f184 | 129 | machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices); |
23308c54 MB |
130 | |
131 | void __init mpc832x_rdb_init_IRQ(void) | |
132 | { | |
133 | ||
134 | struct device_node *np; | |
135 | ||
136 | np = of_find_node_by_type(NULL, "ipic"); | |
137 | if (!np) | |
138 | return; | |
139 | ||
140 | ipic_init(np, 0); | |
141 | ||
142 | /* Initialize the default interrupt mapping priorities, | |
143 | * in case the boot rom changed something on us. | |
144 | */ | |
145 | ipic_set_default_priority(); | |
146 | of_node_put(np); | |
147 | ||
148 | #ifdef CONFIG_QUICC_ENGINE | |
a2dd70a1 AV |
149 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); |
150 | if (!np) { | |
151 | np = of_find_node_by_type(NULL, "qeic"); | |
152 | if (!np) | |
153 | return; | |
154 | } | |
cccd2102 | 155 | qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); |
23308c54 MB |
156 | of_node_put(np); |
157 | #endif /* CONFIG_QUICC_ENGINE */ | |
158 | } | |
159 | ||
160 | /* | |
161 | * Called very early, MMU is off, device-tree isn't unflattened | |
162 | */ | |
163 | static int __init mpc832x_rdb_probe(void) | |
164 | { | |
165 | unsigned long root = of_get_flat_dt_root(); | |
166 | ||
167 | return of_flat_dt_is_compatible(root, "MPC832xRDB"); | |
168 | } | |
169 | ||
170 | define_machine(mpc832x_rdb) { | |
171 | .name = "MPC832x RDB", | |
172 | .probe = mpc832x_rdb_probe, | |
173 | .setup_arch = mpc832x_rdb_setup_arch, | |
174 | .init_IRQ = mpc832x_rdb_init_IRQ, | |
175 | .get_irq = ipic_get_irq, | |
176 | .restart = mpc83xx_restart, | |
177 | .time_init = mpc83xx_time_init, | |
178 | .calibrate_decr = generic_calibrate_decr, | |
179 | .progress = udbg_progress, | |
180 | }; |