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Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
ab2f4892 KG |
2 | /* |
3 | * Corenet based SoC DS Setup | |
4 | * | |
5 | * Maintained by Kumar Gala (see MAINTAINERS for contact information) | |
6 | * | |
b9a43342 | 7 | * Copyright 2009-2011 Freescale Semiconductor Inc. |
ab2f4892 KG |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/kdev_t.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/interrupt.h> | |
ab2f4892 | 15 | |
ab2f4892 KG |
16 | #include <asm/time.h> |
17 | #include <asm/machdep.h> | |
18 | #include <asm/pci-bridge.h> | |
84f44cc5 | 19 | #include <asm/pgtable.h> |
6d251ddf | 20 | #include <asm/ppc-pci.h> |
ab2f4892 KG |
21 | #include <mm/mmu_decl.h> |
22 | #include <asm/prom.h> | |
23 | #include <asm/udbg.h> | |
24 | #include <asm/mpic.h> | |
512e267f | 25 | #include <asm/ehv_pic.h> |
4a605e2d | 26 | #include <asm/swiotlb.h> |
7aa1aa6e | 27 | #include <soc/fsl/qe/qe_ic.h> |
ab2f4892 KG |
28 | |
29 | #include <linux/of_platform.h> | |
30 | #include <sysdev/fsl_soc.h> | |
31 | #include <sysdev/fsl_pci.h> | |
582d3e09 | 32 | #include "smp.h" |
0f5a8696 | 33 | #include "mpc85xx.h" |
ab2f4892 | 34 | |
befe7c12 | 35 | void __init corenet_gen_pic_init(void) |
ab2f4892 KG |
36 | { |
37 | struct mpic *mpic; | |
e55d7f73 KM |
38 | unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | |
39 | MPIC_NO_RESET; | |
ab2f4892 | 40 | |
0f5a8696 ZQ |
41 | struct device_node *np; |
42 | ||
ab2f4892 KG |
43 | if (ppc_md.get_irq == mpic_get_coreint_irq) |
44 | flags |= MPIC_ENABLE_COREINT; | |
45 | ||
b9faa360 | 46 | mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC "); |
ab2f4892 KG |
47 | BUG_ON(mpic == NULL); |
48 | ||
49 | mpic_init(mpic); | |
0f5a8696 ZQ |
50 | |
51 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | |
52 | if (np) { | |
53 | qe_ic_init(np, 0, qe_ic_cascade_low_mpic, | |
54 | qe_ic_cascade_high_mpic); | |
55 | of_node_put(np); | |
56 | } | |
ab2f4892 KG |
57 | } |
58 | ||
ab2f4892 KG |
59 | /* |
60 | * Setup the architecture | |
61 | */ | |
befe7c12 | 62 | void __init corenet_gen_setup_arch(void) |
ab2f4892 | 63 | { |
ab2f4892 | 64 | mpc85xx_smp_init(); |
ab2f4892 | 65 | |
905e75c4 JH |
66 | swiotlb_detect_4g(); |
67 | ||
497c8b60 | 68 | pr_info("%s board\n", ppc_md.name); |
0f5a8696 ZQ |
69 | |
70 | mpc85xx_qe_init(); | |
ab2f4892 KG |
71 | } |
72 | ||
cad5cef6 | 73 | static const struct of_device_id of_device_ids[] = { |
ab2f4892 KG |
74 | { |
75 | .compatible = "simple-bus" | |
76 | }, | |
a189243c AF |
77 | { |
78 | .compatible = "mdio-mux-gpio" | |
79 | }, | |
2e6e9966 SK |
80 | { |
81 | .compatible = "fsl,fpga-ngpixis" | |
82 | }, | |
83 | { | |
84 | .compatible = "fsl,fpga-qixis" | |
85 | }, | |
ab2f4892 | 86 | { |
077200cb | 87 | .compatible = "fsl,srio", |
ab2f4892 | 88 | }, |
b9a43342 KG |
89 | { |
90 | .compatible = "fsl,p4080-pcie", | |
91 | }, | |
92 | { | |
93 | .compatible = "fsl,qoriq-pcie-v2.2", | |
94 | }, | |
4c30c143 TT |
95 | { |
96 | .compatible = "fsl,qoriq-pcie-v2.3", | |
97 | }, | |
98 | { | |
99 | .compatible = "fsl,qoriq-pcie-v2.4", | |
100 | }, | |
b9faa360 KG |
101 | { |
102 | .compatible = "fsl,qoriq-pcie-v3.0", | |
103 | }, | |
0f5a8696 ZQ |
104 | { |
105 | .compatible = "fsl,qe", | |
106 | }, | |
3907ab26 TT |
107 | /* The following two are for the Freescale hypervisor */ |
108 | { | |
109 | .name = "hypervisor", | |
110 | }, | |
111 | { | |
112 | .name = "handles", | |
113 | }, | |
ab2f4892 KG |
114 | {} |
115 | }; | |
116 | ||
befe7c12 | 117 | int __init corenet_gen_publish_devices(void) |
ab2f4892 KG |
118 | { |
119 | return of_platform_bus_probe(NULL, of_device_ids, NULL); | |
120 | } | |
512e267f KH |
121 | |
122 | static const char * const boards[] __initconst = { | |
123 | "fsl,P2041RDB", | |
124 | "fsl,P3041DS", | |
2b09c603 | 125 | "fsl,OCA4080", |
512e267f KH |
126 | "fsl,P4080DS", |
127 | "fsl,P5020DS", | |
128 | "fsl,P5040DS", | |
4c18be2b | 129 | "fsl,T2080QDS", |
78eb9094 | 130 | "fsl,T2080RDB", |
4c18be2b | 131 | "fsl,T2081QDS", |
512e267f | 132 | "fsl,T4240QDS", |
36a2a09d | 133 | "fsl,T4240RDB", |
512e267f KH |
134 | "fsl,B4860QDS", |
135 | "fsl,B4420QDS", | |
136 | "fsl,B4220QDS", | |
65bf2a05 | 137 | "fsl,T1023RDB", |
2b6029e2 | 138 | "fsl,T1024QDS", |
5afe13fd | 139 | "fsl,T1024RDB", |
0d748ec5 PJ |
140 | "fsl,T1040D4RDB", |
141 | "fsl,T1042D4RDB", | |
0c0fc4d3 PK |
142 | "fsl,T1040QDS", |
143 | "fsl,T1042QDS", | |
0babcd1c PJ |
144 | "fsl,T1040RDB", |
145 | "fsl,T1042RDB", | |
667680f6 | 146 | "fsl,T1042RDB_PI", |
fdc8c4ad | 147 | "keymile,kmcent2", |
497c8b60 | 148 | "keymile,kmcoge4", |
c383ee84 | 149 | "varisys,CYRUS", |
512e267f KH |
150 | NULL |
151 | }; | |
152 | ||
512e267f KH |
153 | /* |
154 | * Called very early, device-tree isn't unflattened | |
155 | */ | |
156 | static int __init corenet_generic_probe(void) | |
157 | { | |
cd115477 LT |
158 | char hv_compat[24]; |
159 | int i; | |
512e267f KH |
160 | #ifdef CONFIG_SMP |
161 | extern struct smp_ops_t smp_85xx_ops; | |
162 | #endif | |
163 | ||
56571384 | 164 | if (of_device_compatible_match(of_root, boards)) |
512e267f KH |
165 | return 1; |
166 | ||
167 | /* Check if we're running under the Freescale hypervisor */ | |
cd115477 LT |
168 | for (i = 0; boards[i]; i++) { |
169 | snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]); | |
56571384 | 170 | if (of_machine_is_compatible(hv_compat)) { |
cd115477 LT |
171 | ppc_md.init_IRQ = ehv_pic_init; |
172 | ||
173 | ppc_md.get_irq = ehv_pic_get_irq; | |
174 | ppc_md.restart = fsl_hv_restart; | |
9178ba29 | 175 | pm_power_off = fsl_hv_halt; |
cd115477 | 176 | ppc_md.halt = fsl_hv_halt; |
512e267f | 177 | #ifdef CONFIG_SMP |
cd115477 LT |
178 | /* |
179 | * Disable the timebase sync operations because we | |
180 | * can't write to the timebase registers under the | |
181 | * hypervisor. | |
182 | */ | |
183 | smp_85xx_ops.give_timebase = NULL; | |
184 | smp_85xx_ops.take_timebase = NULL; | |
512e267f | 185 | #endif |
cd115477 LT |
186 | return 1; |
187 | } | |
512e267f KH |
188 | } |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | define_machine(corenet_generic) { | |
194 | .name = "CoreNet Generic", | |
195 | .probe = corenet_generic_probe, | |
befe7c12 KH |
196 | .setup_arch = corenet_gen_setup_arch, |
197 | .init_IRQ = corenet_gen_pic_init, | |
512e267f KH |
198 | #ifdef CONFIG_PCI |
199 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, | |
48b16180 | 200 | .pcibios_fixup_phb = fsl_pcibios_fixup_phb, |
512e267f | 201 | #endif |
881ea7d3 | 202 | /* |
9f640bf5 | 203 | * Core reset may cause issues if using the proxy mode of MPIC. |
881ea7d3 | 204 | * So, use the mixed mode of MPIC if enabling CPU hotplug. |
9f640bf5 SW |
205 | * |
206 | * Likewise, problems have been seen with kexec when coreint is enabled. | |
881ea7d3 | 207 | */ |
da665885 | 208 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE) |
881ea7d3 | 209 | .get_irq = mpic_get_irq, |
210 | #else | |
512e267f | 211 | .get_irq = mpic_get_coreint_irq, |
881ea7d3 | 212 | #endif |
512e267f KH |
213 | .calibrate_decr = generic_calibrate_decr, |
214 | .progress = udbg_progress, | |
215 | #ifdef CONFIG_PPC64 | |
216 | .power_save = book3e_idle, | |
217 | #else | |
218 | .power_save = e500_idle, | |
219 | #endif | |
220 | }; | |
221 | ||
befe7c12 | 222 | machine_arch_initcall(corenet_generic, corenet_gen_publish_devices); |