[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / platforms / 85xx / ge_imp3a.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * GE IMP3A Board Setup
 *
 * Author Martyn Welch <martyn.welch@ge.com>
 *
 * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
 *
 * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
 * Copyright 2007 Freescale Semiconductor Inc.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>

#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include <asm/nvram.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "smp.h"

#include "mpc85xx.h"
#include <sysdev/ge/ge_pic.h>

void __iomem *imp3a_regs;

void __init ge_imp3a_pic_init(void)
{
	struct mpic *mpic;
	struct device_node *np;
	struct device_node *cascade_node = NULL;

	if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) {
		mpic = mpic_alloc(NULL, 0,
			MPIC_NO_RESET |
			MPIC_BIG_ENDIAN |
			MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	} else {
		mpic = mpic_alloc(NULL, 0,
			  MPIC_BIG_ENDIAN |
			  MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	}

	BUG_ON(mpic == NULL);
	mpic_init(mpic);
	/*
	 * There is a simple interrupt handler in the main FPGA, this needs
	 * to be cascaded into the MPIC
	 */
	for_each_node_by_type(np, "interrupt-controller")
		if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
			cascade_node = np;
			break;
		}

	if (cascade_node == NULL) {
		printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
		return;
	}

	gef_pic_init(cascade_node);
	of_node_put(cascade_node);
}

static void ge_imp3a_pci_assign_primary(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
	struct resource rsrc;

	for_each_node_by_type(np, "pci") {
		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
		    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
		    of_device_is_compatible(np, "fsl,p2020-pcie")) {
			of_address_to_resource(np, 0, &rsrc);
			if ((rsrc.start & 0xfffff) == 0x9000)
				fsl_pci_primary = np;
		}
	}
#endif
}

/*
 * Setup the architecture
 */
static void __init ge_imp3a_setup_arch(void)
{
	struct device_node *regs;

	if (ppc_md.progress)
		ppc_md.progress("ge_imp3a_setup_arch()", 0);

	mpc85xx_smp_init();

	ge_imp3a_pci_assign_primary();

	swiotlb_detect_4g();

	/* Remap basic board registers */
	regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
	if (regs) {
		imp3a_regs = of_iomap(regs, 0);
		if (imp3a_regs == NULL)
			printk(KERN_WARNING "Unable to map board registers\n");
		of_node_put(regs);
	}

#if defined(CONFIG_MMIO_NVRAM)
	mmio_nvram_init();
#endif

	printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
}

/* Return the PCB revision */
static unsigned int ge_imp3a_get_pcb_rev(void)
{
	unsigned int reg;

	reg = ioread16(imp3a_regs);
	return (reg >> 8) & 0xff;
}

/* Return the board (software) revision */
static unsigned int ge_imp3a_get_board_rev(void)
{
	unsigned int reg;

	reg = ioread16(imp3a_regs + 0x2);
	return reg & 0xff;
}

/* Return the FPGA revision */
static unsigned int ge_imp3a_get_fpga_rev(void)
{
	unsigned int reg;

	reg = ioread16(imp3a_regs + 0x2);
	return (reg >> 8) & 0xff;
}

/* Return compactPCI Geographical Address */
static unsigned int ge_imp3a_get_cpci_geo_addr(void)
{
	unsigned int reg;

	reg = ioread16(imp3a_regs + 0x6);
	return (reg & 0x0f00) >> 8;
}

/* Return compactPCI System Controller Status */
static unsigned int ge_imp3a_get_cpci_is_syscon(void)
{
	unsigned int reg;

	reg = ioread16(imp3a_regs + 0x6);
	return reg & (1 << 12);
}

static void ge_imp3a_show_cpuinfo(struct seq_file *m)
{
	seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");

	seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
		('A' + ge_imp3a_get_board_rev() - 1));

	seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());

	seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());

	seq_printf(m, "cPCI syscon\t: %s\n",
		ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
}

/*
 * Called very early, device-tree isn't unflattened
 */
static int __init ge_imp3a_probe(void)
{
	return of_machine_is_compatible("ge,IMP3A");
}

machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);

define_machine(ge_imp3a) {
	.name			= "GE_IMP3A",
	.probe			= ge_imp3a_probe,
	.setup_arch		= ge_imp3a_setup_arch,
	.init_IRQ		= ge_imp3a_pic_init,
	.show_cpuinfo		= ge_imp3a_show_cpuinfo,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
	.get_irq		= mpic_get_irq,
	.calibrate_decr		= generic_calibrate_decr,
	.progress		= udbg_progress,
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
e041013a MW	2	/*
	3	* GE IMP3A Board Setup
	4	*
	5	* Author Martyn Welch <martyn.welch@ge.com>
	6	*
	7	* Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
	8	*
e041013a MW	9	* Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
	10	* Copyright 2007 Freescale Semiconductor Inc.
	11	*/
	12
	13	#include <linux/stddef.h>
	14	#include <linux/kernel.h>
	15	#include <linux/pci.h>
	16	#include <linux/kdev_t.h>
	17	#include <linux/delay.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/of_platform.h>
e041013a	21
e041013a MW	22	#include <asm/time.h>
	23	#include <asm/machdep.h>
	24	#include <asm/pci-bridge.h>
	25	#include <mm/mmu_decl.h>
	26	#include <asm/prom.h>
	27	#include <asm/udbg.h>
	28	#include <asm/mpic.h>
	29	#include <asm/swiotlb.h>
	30	#include <asm/nvram.h>
	31
	32	#include <sysdev/fsl_soc.h>
	33	#include <sysdev/fsl_pci.h>
	34	#include "smp.h"
	35
	36	#include "mpc85xx.h"
	37	#include <sysdev/ge/ge_pic.h>
	38
	39	void __iomem *imp3a_regs;
	40
	41	void __init ge_imp3a_pic_init(void)
	42	{
	43	struct mpic *mpic;
	44	struct device_node *np;
	45	struct device_node *cascade_node = NULL;
e041013a	46
b2827883	47	if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) {
e041013a MW	48	mpic = mpic_alloc(NULL, 0,
	49	MPIC_NO_RESET \|
	50	MPIC_BIG_ENDIAN \|
	51	MPIC_SINGLE_DEST_CPU,
	52	0, 256, " OpenPIC ");
	53	} else {
	54	mpic = mpic_alloc(NULL, 0,
	55	MPIC_BIG_ENDIAN \|
	56	MPIC_SINGLE_DEST_CPU,
	57	0, 256, " OpenPIC ");
	58	}
	59
	60	BUG_ON(mpic == NULL);
	61	mpic_init(mpic);
	62	/*
	63	* There is a simple interrupt handler in the main FPGA, this needs
	64	* to be cascaded into the MPIC
	65	*/
	66	for_each_node_by_type(np, "interrupt-controller")
	67	if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
	68	cascade_node = np;
	69	break;
	70	}
	71
	72	if (cascade_node == NULL) {
	73	printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
	74	return;
	75	}
	76
	77	gef_pic_init(cascade_node);
	78	of_node_put(cascade_node);
	79	}
	80
905e75c4	81	static void ge_imp3a_pci_assign_primary(void)
e041013a	82	{
e041013a MW	83	#ifdef CONFIG_PCI
e041013a MW	84	struct device_node *np;
905e75c4	85	struct resource rsrc;
e041013a	86
e041013a MW	87	for_each_node_by_type(np, "pci") {
	88	if (of_device_is_compatible(np, "fsl,mpc8540-pci") \|\|
	89	of_device_is_compatible(np, "fsl,mpc8548-pcie") \|\|
	90	of_device_is_compatible(np, "fsl,p2020-pcie")) {
e041013a	91	of_address_to_resource(np, 0, &rsrc);
905e75c4 JH	92	if ((rsrc.start & 0xfffff) == 0x9000)
905e75c4 JH	93	fsl_pci_primary = np;
e041013a MW	94	}
	95	}
	96	#endif
905e75c4 JH	97	}
	98
	99	/*
	100	* Setup the architecture
	101	*/
	102	static void __init ge_imp3a_setup_arch(void)
	103	{
	104	struct device_node *regs;
	105
	106	if (ppc_md.progress)
	107	ppc_md.progress("ge_imp3a_setup_arch()", 0);
e041013a MW	108
	109	mpc85xx_smp_init();
	110
905e75c4 JH	111	ge_imp3a_pci_assign_primary();
	112
	113	swiotlb_detect_4g();
e041013a MW	114
	115	/* Remap basic board registers */
	116	regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
	117	if (regs) {
	118	imp3a_regs = of_iomap(regs, 0);
	119	if (imp3a_regs == NULL)
	120	printk(KERN_WARNING "Unable to map board registers\n");
	121	of_node_put(regs);
	122	}
	123
	124	#if defined(CONFIG_MMIO_NVRAM)
	125	mmio_nvram_init();
	126	#endif
	127
	128	printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
	129	}
	130
	131	/* Return the PCB revision */
	132	static unsigned int ge_imp3a_get_pcb_rev(void)
	133	{
	134	unsigned int reg;
	135
	136	reg = ioread16(imp3a_regs);
	137	return (reg >> 8) & 0xff;
	138	}
	139
	140	/* Return the board (software) revision */
	141	static unsigned int ge_imp3a_get_board_rev(void)
	142	{
	143	unsigned int reg;
	144
	145	reg = ioread16(imp3a_regs + 0x2);
	146	return reg & 0xff;
	147	}
	148
	149	/* Return the FPGA revision */
	150	static unsigned int ge_imp3a_get_fpga_rev(void)
	151	{
	152	unsigned int reg;
	153
	154	reg = ioread16(imp3a_regs + 0x2);
	155	return (reg >> 8) & 0xff;
	156	}
	157
	158	/* Return compactPCI Geographical Address */
	159	static unsigned int ge_imp3a_get_cpci_geo_addr(void)
	160	{
	161	unsigned int reg;
	162
	163	reg = ioread16(imp3a_regs + 0x6);
	164	return (reg & 0x0f00) >> 8;
	165	}
	166
	167	/* Return compactPCI System Controller Status */
	168	static unsigned int ge_imp3a_get_cpci_is_syscon(void)
	169	{
	170	unsigned int reg;
	171
	172	reg = ioread16(imp3a_regs + 0x6);
	173	return reg & (1 << 12);
	174	}
	175
	176	static void ge_imp3a_show_cpuinfo(struct seq_file *m)
	177	{
178	seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
179
180	seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
181	('A' + ge_imp3a_get_board_rev() - 1));
182
183	seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
184
185	seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
186
187	seq_printf(m, "cPCI syscon\t: %s\n",
188	ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
189	}
190
191	/*
192	* Called very early, device-tree isn't unflattened
193	*/
194	static int __init ge_imp3a_probe(void)
195	{
56571384	196	return of_machine_is_compatible("ge,IMP3A");
e041013a MW	197	}
e041013a MW	198
905e75c4	199	machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);
e041013a	200
e041013a MW	201	define_machine(ge_imp3a) {
	202	.name = "GE_IMP3A",
	203	.probe = ge_imp3a_probe,
	204	.setup_arch = ge_imp3a_setup_arch,
	205	.init_IRQ = ge_imp3a_pic_init,
	206	.show_cpuinfo = ge_imp3a_show_cpuinfo,
	207	#ifdef CONFIG_PCI
	208	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	209	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
e041013a MW	210	#endif
e041013a MW	211	.get_irq = mpic_get_irq,
e041013a MW	212	.calibrate_decr = generic_calibrate_decr,
	213	.progress = udbg_progress,
	214	};