[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / 85xx / mpc85xx_cds.c

/*
 * MPC85xx setup and early boot code plus other random bits.
 *
 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
 *
 * Copyright 2005 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/fsl_devices.h>

#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/ipic.h>
#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/i8259.h>

#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc85xx.h"

static int cds_pci_slot = 2;
static volatile u8 *cadmus;

#ifdef CONFIG_PCI

#define ARCADIA_HOST_BRIDGE_IDSEL	17
#define ARCADIA_2ND_BRIDGE_IDSEL	3

static int mpc85xx_exclude_device(struct pci_controller *hose,
				  u_char bus, u_char devfn)
{
	/* We explicitly do not go past the Tundra 320 Bridge */
	if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
		return PCIBIOS_DEVICE_NOT_FOUND;
	if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
		return PCIBIOS_DEVICE_NOT_FOUND;
	else
		return PCIBIOS_SUCCESSFUL;
}

static void mpc85xx_cds_restart(char *cmd)
{
	struct pci_dev *dev;
	u_char tmp;

	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
					NULL))) {

		/* Use the VIA Super Southbridge to force a PCI reset */
		pci_read_config_byte(dev, 0x47, &tmp);
		pci_write_config_byte(dev, 0x47, tmp | 1);

		/* Flush the outbound PCI write queues */
		pci_read_config_byte(dev, 0x47, &tmp);

		/*
		 *  At this point, the harware reset should have triggered.
		 *  However, if it doesn't work for some mysterious reason,
		 *  just fall through to the default reset below.
		 */

		pci_dev_put(dev);
	}

	/*
	 *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
	 *  or the VIA chip reset didn't work, just use the default reset.
	 */
	mpc85xx_restart(NULL);
}

static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
{
	u_char c;
	if (dev->vendor == PCI_VENDOR_ID_VIA) {
		switch (dev->device) {
		case PCI_DEVICE_ID_VIA_82C586_1:
			/*
			 * U-Boot does not set the enable bits
			 * for the IDE device. Force them on here.
			 */
			pci_read_config_byte(dev, 0x40, &c);
			c |= 0x03; /* IDE: Chip Enable Bits */
			pci_write_config_byte(dev, 0x40, c);

			/*
			 * Since only primary interface works, force the
			 * IDE function to standard primary IDE interrupt
			 * w/ 8259 offset
			 */
			dev->irq = 14;
			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
			break;
		/*
		 * Force legacy USB interrupt routing
		 */
		case PCI_DEVICE_ID_VIA_82C586_2:
		/* There are two USB controllers.
		 * Identify them by functon number
		 */
			if (PCI_FUNC(dev->devfn) == 3)
				dev->irq = 11;
			else
				dev->irq = 10;
			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
		default:
			break;
		}
	}
}

static void __devinit skip_fake_bridge(struct pci_dev *dev)
{
	/* Make it an error to skip the fake bridge
	 * in pci_setup_device() in probe.c */
	dev->hdr_type = 0x7f;
}
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);

#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade_handler(unsigned int irq,
					 struct irq_desc *desc)
{
	unsigned int cascade_irq = i8259_irq();

	if (cascade_irq != NO_IRQ)
		/* handle an interrupt from the 8259 */
		generic_handle_irq(cascade_irq);

	/* check for any interrupts from the shared IRQ line */
	handle_fasteoi_irq(irq, desc);
}

static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
{
	return IRQ_HANDLED;
}

static struct irqaction mpc85xxcds_8259_irqaction = {
	.handler = mpc85xx_8259_cascade_action,
	.flags = IRQF_SHARED,
	.mask = CPU_MASK_NONE,
	.name = "8259 cascade",
};
#endif /* PPC_I8259 */
#endif /* CONFIG_PCI */

static void __init mpc85xx_cds_pic_init(void)
{
	struct mpic *mpic;
	struct resource r;
	struct device_node *np = NULL;

	np = of_find_node_by_type(np, "open-pic");

	if (np == NULL) {
		printk(KERN_ERR "Could not find open-pic node\n");
		return;
	}

	if (of_address_to_resource(np, 0, &r)) {
		printk(KERN_ERR "Failed to map mpic register space\n");
		of_node_put(np);
		return;
	}

	mpic = mpic_alloc(np, r.start,
			MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);

	/* Return the mpic node */
	of_node_put(np);

	mpic_init(mpic);
}

#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
static int mpc85xx_cds_8259_attach(void)
{
	int ret;
	struct device_node *np = NULL;
	struct device_node *cascade_node = NULL;
	int cascade_irq;

	if (!machine_is(mpc85xx_cds))
		return 0;

	/* Initialize the i8259 controller */
	for_each_node_by_type(np, "interrupt-controller")
		if (of_device_is_compatible(np, "chrp,iic")) {
			cascade_node = np;
			break;
		}

	if (cascade_node == NULL) {
		printk(KERN_DEBUG "Could not find i8259 PIC\n");
		return -ENODEV;
	}

	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	if (cascade_irq == NO_IRQ) {
		printk(KERN_ERR "Failed to map cascade interrupt\n");
		return -ENXIO;
	}

	i8259_init(cascade_node, 0);
	of_node_put(cascade_node);

	/*
	 *  Hook the interrupt to make sure desc->action is never NULL.
	 *  This is required to ensure that the interrupt does not get
	 *  disabled when the last user of the shared IRQ line frees their
	 *  interrupt.
	 */
	if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
		printk(KERN_ERR "Failed to setup cascade interrupt\n");
		return ret;
	}

	/* Success. Connect our low-level cascade handler. */
	set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);

	return 0;
}

device_initcall(mpc85xx_cds_8259_attach);

#endif /* CONFIG_PPC_I8259 */

/*
 * Setup the architecture
 */
static void __init mpc85xx_cds_setup_arch(void)
{
	struct device_node *cpu;
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_cds_setup_arch()", 0);

	cpu = of_find_node_by_type(NULL, "cpu");
	if (cpu != 0) {
		const unsigned int *fp;

		fp = of_get_property(cpu, "clock-frequency", NULL);
		if (fp != 0)
			loops_per_jiffy = *fp / HZ;
		else
			loops_per_jiffy = 500000000 / HZ;
		of_node_put(cpu);
	}

	cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
	cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;

	if (ppc_md.progress) {
		char buf[40];
		snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
				cadmus[CM_VER], cds_pci_slot);
		ppc_md.progress(buf, 0);
	}

#ifdef CONFIG_PCI
	for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
		struct resource rsrc;
		of_address_to_resource(np, 0, &rsrc);
		if ((rsrc.start & 0xfffff) == 0x8000)
			fsl_add_bridge(np, 1);
		else
			fsl_add_bridge(np, 0);
	}
	ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
}

static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{
	uint pvid, svid, phid1;
	uint memsize = total_memory;

	pvid = mfspr(SPRN_PVR);
	svid = mfspr(SPRN_SVR);

	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	seq_printf(m, "SVR\t\t: 0x%x\n", svid);

	/* Display cpu Pll setting */
	phid1 = mfspr(SPRN_HID1);
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));

	/* Display the amount of memory */
	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}


/*
 * Called very early, device-tree isn't unflattened
 */
static int __init mpc85xx_cds_probe(void)
{
        unsigned long root = of_get_flat_dt_root();

        return of_flat_dt_is_compatible(root, "MPC85xxCDS");
}

define_machine(mpc85xx_cds) {
	.name		= "MPC85xx CDS",
	.probe		= mpc85xx_cds_probe,
	.setup_arch	= mpc85xx_cds_setup_arch,
	.init_IRQ	= mpc85xx_cds_pic_init,
	.show_cpuinfo	= mpc85xx_cds_show_cpuinfo,
	.get_irq	= mpic_get_irq,
#ifdef CONFIG_PCI
	.restart	= mpc85xx_cds_restart,
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
#else
	.restart	= mpc85xx_restart,
#endif
	.calibrate_decr = generic_calibrate_decr,
	.progress	= udbg_progress,
};
Commit	Line	Data
591f0a42 AF	1	/*
	2	* MPC85xx setup and early boot code plus other random bits.
	3	*
	4	* Maintained by Kumar Gala (see MAINTAINERS for contact information)
	5	*
	6	* Copyright 2005 Freescale Semiconductor Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
591f0a42 AF	14	#include <linux/stddef.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/errno.h>
	18	#include <linux/reboot.h>
	19	#include <linux/pci.h>
	20	#include <linux/kdev_t.h>
	21	#include <linux/major.h>
	22	#include <linux/console.h>
	23	#include <linux/delay.h>
	24	#include <linux/seq_file.h>
591f0a42 AF	25	#include <linux/initrd.h>
591f0a42 AF	26	#include <linux/module.h>
3620fc1d	27	#include <linux/interrupt.h>
591f0a42 AF	28	#include <linux/fsl_devices.h>
	29
	30	#include <asm/system.h>
	31	#include <asm/pgtable.h>
	32	#include <asm/page.h>
	33	#include <asm/atomic.h>
	34	#include <asm/time.h>
	35	#include <asm/io.h>
	36	#include <asm/machdep.h>
	37	#include <asm/ipic.h>
	38	#include <asm/bootinfo.h>
	39	#include <asm/pci-bridge.h>
	40	#include <asm/mpc85xx.h>
	41	#include <asm/irq.h>
	42	#include <mm/mmu_decl.h>
	43	#include <asm/prom.h>
	44	#include <asm/udbg.h>
	45	#include <asm/mpic.h>
	46	#include <asm/i8259.h>
	47
	48	#include <sysdev/fsl_soc.h>
3f6c5dae	49	#include <sysdev/fsl_pci.h>
591f0a42 AF	50	#include "mpc85xx.h"
591f0a42 AF	51
591f0a42 AF	52	static int cds_pci_slot = 2;
	53	static volatile u8 *cadmus;
	54
591f0a42	55	#ifdef CONFIG_PCI
591f0a42 AF	56
	57	#define ARCADIA_HOST_BRIDGE_IDSEL 17
	58	#define ARCADIA_2ND_BRIDGE_IDSEL 3
	59
7d52c7b0 KG	60	static int mpc85xx_exclude_device(struct pci_controller *hose,
7d52c7b0 KG	61	u_char bus, u_char devfn)
591f0a42	62	{
591f0a42 AF	63	/* We explicitly do not go past the Tundra 320 Bridge */
	64	if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
	65	return PCIBIOS_DEVICE_NOT_FOUND;
	66	if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
	67	return PCIBIOS_DEVICE_NOT_FOUND;
	68	else
	69	return PCIBIOS_SUCCESSFUL;
	70	}
	71
637e9e13 RV	72	static void mpc85xx_cds_restart(char *cmd)
	73	{
	74	struct pci_dev *dev;
	75	u_char tmp;
	76
	77	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
	78	NULL))) {
	79
	80	/* Use the VIA Super Southbridge to force a PCI reset */
	81	pci_read_config_byte(dev, 0x47, &tmp);
	82	pci_write_config_byte(dev, 0x47, tmp \| 1);
	83
	84	/* Flush the outbound PCI write queues */
	85	pci_read_config_byte(dev, 0x47, &tmp);
	86
	87	/*
	88	* At this point, the harware reset should have triggered.
	89	* However, if it doesn't work for some mysterious reason,
	90	* just fall through to the default reset below.
	91	*/
	92
	93	pci_dev_put(dev);
	94	}
	95
	96	/*
	97	* If we can't find the VIA chip (maybe the P2P bridge is disabled)
	98	* or the VIA chip reset didn't work, just use the default reset.
	99	*/
	100	mpc85xx_restart(NULL);
	101	}
	102
749e8081	103	static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
591f0a42	104	{
749e8081 RZ	105	u_char c;
	106	if (dev->vendor == PCI_VENDOR_ID_VIA) {
	107	switch (dev->device) {
	108	case PCI_DEVICE_ID_VIA_82C586_1:
	109	/*
	110	* U-Boot does not set the enable bits
	111	* for the IDE device. Force them on here.
	112	*/
	113	pci_read_config_byte(dev, 0x40, &c);
	114	c \|= 0x03; /* IDE: Chip Enable Bits */
	115	pci_write_config_byte(dev, 0x40, c);
	116
	117	/*
	118	* Since only primary interface works, force the
	119	* IDE function to standard primary IDE interrupt
	120	* w/ 8259 offset
	121	*/
	122	dev->irq = 14;
	123	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	124	break;
591f0a42	125	/*
749e8081	126	* Force legacy USB interrupt routing
591f0a42	127	*/
749e8081 RZ	128	case PCI_DEVICE_ID_VIA_82C586_2:
	129	/* There are two USB controllers.
	130	* Identify them by functon number
591f0a42	131	*/
8d7bc8f9	132	if (PCI_FUNC(dev->devfn) == 3)
749e8081 RZ	133	dev->irq = 11;
	134	else
	135	dev->irq = 10;
	136	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	137	default:
	138	break;
	139	}
591f0a42	140	}
ddd64159 AF	141	}
ddd64159 AF	142
4e798211 KG	143	static void __devinit skip_fake_bridge(struct pci_dev *dev)
	144	{
	145	/* Make it an error to skip the fake bridge
	146	* in pci_setup_device() in probe.c */
	147	dev->hdr_type = 0x7f;
	148	}
	149	DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
	150	DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
	151	DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
	152
ddd64159	153	#ifdef CONFIG_PPC_I8259
3620fc1d RV	154	static void mpc85xx_8259_cascade_handler(unsigned int irq,
3620fc1d RV	155	struct irq_desc *desc)
ddd64159	156	{
35a84c2f	157	unsigned int cascade_irq = i8259_irq();
ddd64159 AF	158
ddd64159 AF	159	if (cascade_irq != NO_IRQ)
3620fc1d	160	/* handle an interrupt from the 8259 */
49f19ce4	161	generic_handle_irq(cascade_irq);
ddd64159	162
3620fc1d RV	163	/* check for any interrupts from the shared IRQ line */
3620fc1d RV	164	handle_fasteoi_irq(irq, desc);
591f0a42	165	}
3620fc1d RV	166
	167	static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
	168	{
	169	return IRQ_HANDLED;
	170	}
	171
	172	static struct irqaction mpc85xxcds_8259_irqaction = {
	173	.handler = mpc85xx_8259_cascade_action,
	174	.flags = IRQF_SHARED,
	175	.mask = CPU_MASK_NONE,
	176	.name = "8259 cascade",
	177	};
ddd64159	178	#endif /* PPC_I8259 */
591f0a42 AF	179	#endif /* CONFIG_PCI */
591f0a42 AF	180
27630bec	181	static void __init mpc85xx_cds_pic_init(void)
591f0a42	182	{
ddd64159 AF	183	struct mpic *mpic;
	184	struct resource r;
	185	struct device_node *np = NULL;
591f0a42	186
ddd64159 AF	187	np = of_find_node_by_type(np, "open-pic");
	188
	189	if (np == NULL) {
	190	printk(KERN_ERR "Could not find open-pic node\n");
	191	return;
	192	}
591f0a42	193
ddd64159 AF	194	if (of_address_to_resource(np, 0, &r)) {
	195	printk(KERN_ERR "Failed to map mpic register space\n");
	196	of_node_put(np);
	197	return;
	198	}
	199
	200	mpic = mpic_alloc(np, r.start,
591f0a42	201	MPIC_PRIMARY \| MPIC_WANTS_RESET \| MPIC_BIG_ENDIAN,
b533f8ae	202	0, 256, " OpenPIC ");
ddd64159 AF	203	BUG_ON(mpic == NULL);
	204
	205	/* Return the mpic node */
	206	of_node_put(np);
	207
ddd64159	208	mpic_init(mpic);
bca03c6b	209	}
ddd64159	210
3620fc1d	211	#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
bca03c6b RV	212	static int mpc85xx_cds_8259_attach(void)
	213	{
	214	int ret;
	215	struct device_node *np = NULL;
	216	struct device_node *cascade_node = NULL;
	217	int cascade_irq;
	218
	219	if (!machine_is(mpc85xx_cds))
	220	return 0;
	221
ddd64159 AF	222	/* Initialize the i8259 controller */
ddd64159 AF	223	for_each_node_by_type(np, "interrupt-controller")
55b61fec	224	if (of_device_is_compatible(np, "chrp,iic")) {
ddd64159 AF	225	cascade_node = np;
	226	break;
	227	}
	228
	229	if (cascade_node == NULL) {
	230	printk(KERN_DEBUG "Could not find i8259 PIC\n");
bca03c6b	231	return -ENODEV;
ddd64159	232	}
591f0a42	233
ddd64159 AF	234	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
	235	if (cascade_irq == NO_IRQ) {
	236	printk(KERN_ERR "Failed to map cascade interrupt\n");
bca03c6b	237	return -ENXIO;
ddd64159	238	}
591f0a42	239
ddd64159 AF	240	i8259_init(cascade_node, 0);
	241	of_node_put(cascade_node);
	242
3620fc1d RV	243	/*
	244	* Hook the interrupt to make sure desc->action is never NULL.
	245	* This is required to ensure that the interrupt does not get
	246	* disabled when the last user of the shared IRQ line frees their
	247	* interrupt.
	248	*/
bca03c6b	249	if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
3620fc1d	250	printk(KERN_ERR "Failed to setup cascade interrupt\n");
bca03c6b RV	251	return ret;
	252	}
	253
	254	/* Success. Connect our low-level cascade handler. */
	255	set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
	256
	257	return 0;
591f0a42 AF	258	}
591f0a42 AF	259
bca03c6b RV	260	device_initcall(mpc85xx_cds_8259_attach);
	261
	262	#endif /* CONFIG_PPC_I8259 */
	263
591f0a42 AF	264	/*
	265	* Setup the architecture
	266	*/
27630bec	267	static void __init mpc85xx_cds_setup_arch(void)
591f0a42 AF	268	{
	269	struct device_node *cpu;
	270	#ifdef CONFIG_PCI
	271	struct device_node *np;
	272	#endif
	273
	274	if (ppc_md.progress)
	275	ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
	276
	277	cpu = of_find_node_by_type(NULL, "cpu");
	278	if (cpu != 0) {
8efca493	279	const unsigned int *fp;
591f0a42	280
e2eb6392	281	fp = of_get_property(cpu, "clock-frequency", NULL);
591f0a42 AF	282	if (fp != 0)
	283	loops_per_jiffy = *fp / HZ;
	284	else
	285	loops_per_jiffy = 500000000 / HZ;
	286	of_node_put(cpu);
	287	}
	288
	289	cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
	290	cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
	291
	292	if (ppc_md.progress) {
	293	char buf[40];
	294	snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
	295	cadmus[CM_VER], cds_pci_slot);
	296	ppc_md.progress(buf, 0);
	297	}
	298
	299	#ifdef CONFIG_PCI
3f6c5dae RZ	300	for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
	301	struct resource rsrc;
	302	of_address_to_resource(np, 0, &rsrc);
8d7bc8f9	303	if ((rsrc.start & 0xfffff) == 0x8000)
3f6c5dae	304	fsl_add_bridge(np, 1);
8d7bc8f9 RV	305	else
8d7bc8f9 RV	306	fsl_add_bridge(np, 0);
3f6c5dae	307	}
749e8081	308	ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
591f0a42 AF	309	ppc_md.pci_exclude_device = mpc85xx_exclude_device;
591f0a42 AF	310	#endif
591f0a42 AF	311	}
591f0a42 AF	312
27630bec	313	static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
591f0a42 AF	314	{
	315	uint pvid, svid, phid1;
	316	uint memsize = total_memory;
	317
	318	pvid = mfspr(SPRN_PVR);
	319	svid = mfspr(SPRN_SVR);
	320
	321	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	322	seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
	323	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	324	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
	325
	326	/* Display cpu Pll setting */
	327	phid1 = mfspr(SPRN_HID1);
	328	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
	329
	330	/* Display the amount of memory */
	331	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
	332	}
	333
	334
	335	/*
	336	* Called very early, device-tree isn't unflattened
	337	*/
	338	static int __init mpc85xx_cds_probe(void)
	339	{
6936c625 KG	340	unsigned long root = of_get_flat_dt_root();
	341
	342	return of_flat_dt_is_compatible(root, "MPC85xxCDS");
591f0a42 AF	343	}
	344
	345	define_machine(mpc85xx_cds) {
	346	.name = "MPC85xx CDS",
	347	.probe = mpc85xx_cds_probe,
	348	.setup_arch = mpc85xx_cds_setup_arch,
	349	.init_IRQ = mpc85xx_cds_pic_init,
	350	.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
	351	.get_irq = mpic_get_irq,
637e9e13 RV	352	#ifdef CONFIG_PCI
637e9e13 RV	353	.restart = mpc85xx_cds_restart,
2af8569d	354	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
637e9e13	355	#else
591f0a42	356	.restart = mpc85xx_restart,
637e9e13	357	#endif
591f0a42 AF	358	.calibrate_decr = generic_calibrate_decr,
	359	.progress = udbg_progress,
	360	};