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Commit | Line | Data |
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591f0a42 AF |
1 | /* |
2 | * MPC85xx setup and early boot code plus other random bits. | |
3 | * | |
4 | * Maintained by Kumar Gala (see MAINTAINERS for contact information) | |
5 | * | |
6 | * Copyright 2005 Freescale Semiconductor Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
591f0a42 AF |
14 | #include <linux/stddef.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/reboot.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/kdev_t.h> | |
21 | #include <linux/major.h> | |
22 | #include <linux/console.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/seq_file.h> | |
591f0a42 AF |
25 | #include <linux/initrd.h> |
26 | #include <linux/module.h> | |
27 | #include <linux/fsl_devices.h> | |
28 | ||
29 | #include <asm/system.h> | |
30 | #include <asm/pgtable.h> | |
31 | #include <asm/page.h> | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/time.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/machdep.h> | |
36 | #include <asm/ipic.h> | |
37 | #include <asm/bootinfo.h> | |
38 | #include <asm/pci-bridge.h> | |
39 | #include <asm/mpc85xx.h> | |
40 | #include <asm/irq.h> | |
41 | #include <mm/mmu_decl.h> | |
42 | #include <asm/prom.h> | |
43 | #include <asm/udbg.h> | |
44 | #include <asm/mpic.h> | |
45 | #include <asm/i8259.h> | |
46 | ||
47 | #include <sysdev/fsl_soc.h> | |
3f6c5dae | 48 | #include <sysdev/fsl_pci.h> |
591f0a42 AF |
49 | #include "mpc85xx.h" |
50 | ||
591f0a42 AF |
51 | static int cds_pci_slot = 2; |
52 | static volatile u8 *cadmus; | |
53 | ||
591f0a42 | 54 | #ifdef CONFIG_PCI |
591f0a42 AF |
55 | |
56 | #define ARCADIA_HOST_BRIDGE_IDSEL 17 | |
57 | #define ARCADIA_2ND_BRIDGE_IDSEL 3 | |
58 | ||
7d52c7b0 KG |
59 | static int mpc85xx_exclude_device(struct pci_controller *hose, |
60 | u_char bus, u_char devfn) | |
591f0a42 | 61 | { |
591f0a42 AF |
62 | /* We explicitly do not go past the Tundra 320 Bridge */ |
63 | if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) | |
64 | return PCIBIOS_DEVICE_NOT_FOUND; | |
65 | if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) | |
66 | return PCIBIOS_DEVICE_NOT_FOUND; | |
67 | else | |
68 | return PCIBIOS_SUCCESSFUL; | |
69 | } | |
70 | ||
749e8081 | 71 | static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) |
591f0a42 | 72 | { |
749e8081 RZ |
73 | u_char c; |
74 | if (dev->vendor == PCI_VENDOR_ID_VIA) { | |
75 | switch (dev->device) { | |
76 | case PCI_DEVICE_ID_VIA_82C586_1: | |
77 | /* | |
78 | * U-Boot does not set the enable bits | |
79 | * for the IDE device. Force them on here. | |
80 | */ | |
81 | pci_read_config_byte(dev, 0x40, &c); | |
82 | c |= 0x03; /* IDE: Chip Enable Bits */ | |
83 | pci_write_config_byte(dev, 0x40, c); | |
84 | ||
85 | /* | |
86 | * Since only primary interface works, force the | |
87 | * IDE function to standard primary IDE interrupt | |
88 | * w/ 8259 offset | |
89 | */ | |
90 | dev->irq = 14; | |
91 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | |
92 | break; | |
591f0a42 | 93 | /* |
749e8081 | 94 | * Force legacy USB interrupt routing |
591f0a42 | 95 | */ |
749e8081 RZ |
96 | case PCI_DEVICE_ID_VIA_82C586_2: |
97 | /* There are two USB controllers. | |
98 | * Identify them by functon number | |
591f0a42 | 99 | */ |
749e8081 RZ |
100 | if (PCI_FUNC(dev->devfn)) |
101 | dev->irq = 11; | |
102 | else | |
103 | dev->irq = 10; | |
104 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | |
105 | default: | |
106 | break; | |
107 | } | |
591f0a42 | 108 | } |
ddd64159 AF |
109 | } |
110 | ||
111 | #ifdef CONFIG_PPC_I8259 | |
112 | #warning The i8259 PIC support is currently broken | |
35a84c2f | 113 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
ddd64159 | 114 | { |
35a84c2f | 115 | unsigned int cascade_irq = i8259_irq(); |
ddd64159 AF |
116 | |
117 | if (cascade_irq != NO_IRQ) | |
49f19ce4 | 118 | generic_handle_irq(cascade_irq); |
ddd64159 AF |
119 | |
120 | desc->chip->eoi(irq); | |
591f0a42 | 121 | } |
ddd64159 | 122 | #endif /* PPC_I8259 */ |
591f0a42 AF |
123 | #endif /* CONFIG_PCI */ |
124 | ||
27630bec | 125 | static void __init mpc85xx_cds_pic_init(void) |
591f0a42 | 126 | { |
ddd64159 AF |
127 | struct mpic *mpic; |
128 | struct resource r; | |
129 | struct device_node *np = NULL; | |
35a84c2f | 130 | #ifdef CONFIG_PPC_I8259 |
ddd64159 AF |
131 | struct device_node *cascade_node = NULL; |
132 | int cascade_irq; | |
35a84c2f | 133 | #endif |
591f0a42 | 134 | |
ddd64159 AF |
135 | np = of_find_node_by_type(np, "open-pic"); |
136 | ||
137 | if (np == NULL) { | |
138 | printk(KERN_ERR "Could not find open-pic node\n"); | |
139 | return; | |
140 | } | |
591f0a42 | 141 | |
ddd64159 AF |
142 | if (of_address_to_resource(np, 0, &r)) { |
143 | printk(KERN_ERR "Failed to map mpic register space\n"); | |
144 | of_node_put(np); | |
145 | return; | |
146 | } | |
147 | ||
148 | mpic = mpic_alloc(np, r.start, | |
591f0a42 | 149 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, |
b533f8ae | 150 | 0, 256, " OpenPIC "); |
ddd64159 AF |
151 | BUG_ON(mpic == NULL); |
152 | ||
153 | /* Return the mpic node */ | |
154 | of_node_put(np); | |
155 | ||
ddd64159 AF |
156 | mpic_init(mpic); |
157 | ||
158 | #ifdef CONFIG_PPC_I8259 | |
159 | /* Initialize the i8259 controller */ | |
160 | for_each_node_by_type(np, "interrupt-controller") | |
55b61fec | 161 | if (of_device_is_compatible(np, "chrp,iic")) { |
ddd64159 AF |
162 | cascade_node = np; |
163 | break; | |
164 | } | |
165 | ||
166 | if (cascade_node == NULL) { | |
167 | printk(KERN_DEBUG "Could not find i8259 PIC\n"); | |
168 | return; | |
169 | } | |
591f0a42 | 170 | |
ddd64159 AF |
171 | cascade_irq = irq_of_parse_and_map(cascade_node, 0); |
172 | if (cascade_irq == NO_IRQ) { | |
173 | printk(KERN_ERR "Failed to map cascade interrupt\n"); | |
174 | return; | |
175 | } | |
591f0a42 | 176 | |
ddd64159 AF |
177 | i8259_init(cascade_node, 0); |
178 | of_node_put(cascade_node); | |
179 | ||
180 | set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); | |
181 | #endif /* CONFIG_PPC_I8259 */ | |
591f0a42 AF |
182 | } |
183 | ||
591f0a42 AF |
184 | /* |
185 | * Setup the architecture | |
186 | */ | |
27630bec | 187 | static void __init mpc85xx_cds_setup_arch(void) |
591f0a42 AF |
188 | { |
189 | struct device_node *cpu; | |
190 | #ifdef CONFIG_PCI | |
191 | struct device_node *np; | |
192 | #endif | |
193 | ||
194 | if (ppc_md.progress) | |
195 | ppc_md.progress("mpc85xx_cds_setup_arch()", 0); | |
196 | ||
197 | cpu = of_find_node_by_type(NULL, "cpu"); | |
198 | if (cpu != 0) { | |
8efca493 | 199 | const unsigned int *fp; |
591f0a42 | 200 | |
e2eb6392 | 201 | fp = of_get_property(cpu, "clock-frequency", NULL); |
591f0a42 AF |
202 | if (fp != 0) |
203 | loops_per_jiffy = *fp / HZ; | |
204 | else | |
205 | loops_per_jiffy = 500000000 / HZ; | |
206 | of_node_put(cpu); | |
207 | } | |
208 | ||
209 | cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE); | |
210 | cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; | |
211 | ||
212 | if (ppc_md.progress) { | |
213 | char buf[40]; | |
214 | snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n", | |
215 | cadmus[CM_VER], cds_pci_slot); | |
216 | ppc_md.progress(buf, 0); | |
217 | } | |
218 | ||
219 | #ifdef CONFIG_PCI | |
3f6c5dae RZ |
220 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { |
221 | struct resource rsrc; | |
222 | of_address_to_resource(np, 0, &rsrc); | |
223 | if ((rsrc.start & 0xfffff) == 0x9000) | |
224 | fsl_add_bridge(np, 0); | |
225 | else | |
226 | fsl_add_bridge(np, 1); | |
227 | } | |
749e8081 | 228 | ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup; |
591f0a42 AF |
229 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; |
230 | #endif | |
591f0a42 AF |
231 | } |
232 | ||
27630bec | 233 | static void mpc85xx_cds_show_cpuinfo(struct seq_file *m) |
591f0a42 AF |
234 | { |
235 | uint pvid, svid, phid1; | |
236 | uint memsize = total_memory; | |
237 | ||
238 | pvid = mfspr(SPRN_PVR); | |
239 | svid = mfspr(SPRN_SVR); | |
240 | ||
241 | seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); | |
242 | seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]); | |
243 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); | |
244 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
245 | ||
246 | /* Display cpu Pll setting */ | |
247 | phid1 = mfspr(SPRN_HID1); | |
248 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); | |
249 | ||
250 | /* Display the amount of memory */ | |
251 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); | |
252 | } | |
253 | ||
254 | ||
255 | /* | |
256 | * Called very early, device-tree isn't unflattened | |
257 | */ | |
258 | static int __init mpc85xx_cds_probe(void) | |
259 | { | |
6936c625 KG |
260 | unsigned long root = of_get_flat_dt_root(); |
261 | ||
262 | return of_flat_dt_is_compatible(root, "MPC85xxCDS"); | |
591f0a42 AF |
263 | } |
264 | ||
265 | define_machine(mpc85xx_cds) { | |
266 | .name = "MPC85xx CDS", | |
267 | .probe = mpc85xx_cds_probe, | |
268 | .setup_arch = mpc85xx_cds_setup_arch, | |
269 | .init_IRQ = mpc85xx_cds_pic_init, | |
270 | .show_cpuinfo = mpc85xx_cds_show_cpuinfo, | |
271 | .get_irq = mpic_get_irq, | |
272 | .restart = mpc85xx_restart, | |
273 | .calibrate_decr = generic_calibrate_decr, | |
274 | .progress = udbg_progress, | |
275 | }; |