[mirror_ubuntu-kernels.git] / arch / powerpc / platforms / 85xx / mpc85xx_mds.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * Author: Andy Fleming <afleming@freescale.com>
 *
 * Based on 83xx/mpc8360e_pb.c by:
 *	   Li Yang <LeoLi@freescale.com>
 *	   Yin Olivia <Hong-hua.Yin@freescale.com>
 *
 * Description:
 * MPC85xx MDS board specific routines.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/phy.h>
#include <linux/memblock.h>
#include <linux/fsl/guts.h>

#include <linux/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
#include <soc/fsl/qe/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include "smp.h"

#include "mpc85xx.h"

#undef DEBUG
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#else
#define DBG(fmt...)
#endif

#if IS_BUILTIN(CONFIG_PHYLIB)

#define MV88E1111_SCR	0x10
#define MV88E1111_SCR_125CLK	0x0010
static int mpc8568_fixup_125_clock(struct phy_device *phydev)
{
	int scr;
	int err;

	/* Workaround for the 125 CLK Toggle */
	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));

	if (err)
		return err;

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err)
		return err;

	scr = phy_read(phydev, MV88E1111_SCR);

	if (scr < 0)
		return scr;

	err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);

	return err;
}

static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
{
	int temp;
	int err;

	/* Errata */
	err = phy_write(phydev,29, 0x0006);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = (temp & (~0x8000)) | 0x4000;
	err = phy_write(phydev,30, temp);

	if (err)
		return err;

	err = phy_write(phydev,29, 0x000a);

	if (err)
		return err;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp = phy_read(phydev, 30);

	if (temp < 0)
		return temp;

	temp &= ~0x0020;

	err = phy_write(phydev,30,temp);

	if (err)
		return err;

	/* Disable automatic MDI/MDIX selection */
	temp = phy_read(phydev, 16);

	if (temp < 0)
		return temp;

	temp &= ~0x0060;
	err = phy_write(phydev,16,temp);

	return err;
}

#endif

/* ************************************************************************
 *
 * Setup the architecture
 *
 */
#ifdef CONFIG_QUICC_ENGINE
static void __init mpc85xx_mds_reset_ucc_phys(void)
{
	struct device_node *np;
	static u8 __iomem *bcsr_regs;

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (!np)
		return;

	bcsr_regs = of_iomap(np, 0);
	of_node_put(np);
	if (!bcsr_regs)
		return;

	if (machine_is(mpc8568_mds)) {
#define BCSR_UCC1_GETH_EN	(0x1 << 7)
#define BCSR_UCC2_GETH_EN	(0x1 << 7)
#define BCSR_UCC1_MODE_MSK	(0x3 << 4)
#define BCSR_UCC2_MODE_MSK	(0x3 << 0)

		/* Turn off UCC1 & UCC2 */
		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);

		/* Mode is RGMII, all bits clear */
		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
					 BCSR_UCC2_MODE_MSK);

		/* Turn UCC1 & UCC2 on */
		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	} else if (machine_is(mpc8569_mds)) {
#define BCSR7_UCC12_GETHnRST	(0x1 << 2)
#define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
#define BCSR_UCC_RGMII		(0x1 << 6)
#define BCSR_UCC_RTBI		(0x1 << 5)
		/*
		 * U-Boot mangles interrupt polarity for Marvell PHYs,
		 * so reset built-in and UEM Marvell PHYs, this puts
		 * the PHYs into their normal state.
		 */
		clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
		setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

		setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
		clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);

		for_each_compatible_node(np, "network", "ucc_geth") {
			const unsigned int *prop;
			int ucc_num;

			prop = of_get_property(np, "cell-index", NULL);
			if (prop == NULL)
				continue;

			ucc_num = *prop - 1;

			prop = of_get_property(np, "phy-connection-type", NULL);
			if (prop == NULL)
				continue;

			if (strcmp("rtbi", (const char *)prop) == 0)
				clrsetbits_8(&bcsr_regs[7 + ucc_num],
					BCSR_UCC_RGMII, BCSR_UCC_RTBI);
		}
	} else if (machine_is(p1021_mds)) {
#define BCSR11_ENET_MICRST     (0x1 << 5)
		/* Reset Micrel PHY */
		clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
		setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
	}

	iounmap(bcsr_regs);
}

static void __init mpc85xx_mds_qe_init(void)
{
	struct device_node *np;

	mpc85xx_qe_init();
	mpc85xx_qe_par_io_init();
	mpc85xx_mds_reset_ucc_phys();

	if (machine_is(p1021_mds)) {

		struct ccsr_guts __iomem *guts;

		np = of_find_node_by_name(NULL, "global-utilities");
		if (np) {
			guts = of_iomap(np, 0);
			if (!guts)
				pr_err("mpc85xx-rdb: could not map global utilities register\n");
			else{
			/* P1021 has pins muxed for QE and other functions. To
			 * enable QE UEC mode, we need to set bit QE0 for UCC1
			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
			 * and QE12 for QE MII management signals in PMUXCR
			 * register.
			 */
				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
						  MPC85xx_PMUXCR_QE(3) |
						  MPC85xx_PMUXCR_QE(9) |
						  MPC85xx_PMUXCR_QE(12));
				iounmap(guts);
			}
			of_node_put(np);
		}

	}
}

static void __init mpc85xx_mds_qeic_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	if (!of_device_is_available(np)) {
		of_node_put(np);
		return;
	}

	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	if (!np) {
		np = of_find_node_by_type(NULL, "qeic");
		if (!np)
			return;
	}

	if (machine_is(p1021_mds))
		qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
				qe_ic_cascade_high_mpic);
	else
		qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	of_node_put(np);
}
#else
static void __init mpc85xx_mds_qe_init(void) { }
static void __init mpc85xx_mds_qeic_init(void) { }
#endif	/* CONFIG_QUICC_ENGINE */

static void __init mpc85xx_mds_setup_arch(void)
{
	if (ppc_md.progress)
		ppc_md.progress("mpc85xx_mds_setup_arch()", 0);

	mpc85xx_smp_init();

	mpc85xx_mds_qe_init();

	fsl_pci_assign_primary();

	swiotlb_detect_4g();
}

#if IS_BUILTIN(CONFIG_PHYLIB)

static int __init board_fixups(void)
{
	char phy_id[20];
	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	struct device_node *mdio;
	struct resource res;
	int i;

	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
		mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);

		of_address_to_resource(mdio, 0, &res);
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 1);

		phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		/* Register a workaround for errata */
		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
			(unsigned long long)res.start, 7);
		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);

		of_node_put(mdio);
	}

	return 0;
}

machine_arch_initcall(mpc8568_mds, board_fixups);
machine_arch_initcall(mpc8569_mds, board_fixups);

#endif

static int __init mpc85xx_publish_devices(void)
{
	if (machine_is(mpc8568_mds))
		simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
	if (machine_is(mpc8569_mds))
		simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");

	return mpc85xx_common_publish_devices();
}

machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);

static void __init mpc85xx_mds_pic_init(void)
{
	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
			MPIC_SINGLE_DEST_CPU,
			0, 256, " OpenPIC  ");
	BUG_ON(mpic == NULL);

	mpic_init(mpic);
	mpc85xx_mds_qeic_init();
}

static int __init mpc85xx_mds_probe(void)
{
	return of_machine_is_compatible("MPC85xxMDS");
}

define_machine(mpc8568_mds) {
	.name		= "MPC8568 MDS",
	.probe		= mpc85xx_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
};

static int __init mpc8569_mds_probe(void)
{
	return of_machine_is_compatible("fsl,MPC8569EMDS");
}

define_machine(mpc8569_mds) {
	.name		= "MPC8569 MDS",
	.probe		= mpc8569_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
};

static int __init p1021_mds_probe(void)
{
	return of_machine_is_compatible("fsl,P1021MDS");

}

define_machine(p1021_mds) {
	.name		= "P1021 MDS",
	.probe		= p1021_mds_probe,
	.setup_arch	= mpc85xx_mds_setup_arch,
	.init_IRQ	= mpc85xx_mds_pic_init,
	.get_irq	= mpic_get_irq,
	.calibrate_decr	= generic_calibrate_decr,
	.progress	= udbg_progress,
#ifdef CONFIG_PCI
	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
#endif
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
c2882bb1	2	/*
72c916ae	3	* Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
c141b38f	4	* All rights reserved.
c2882bb1 AF	5	*
	6	* Author: Andy Fleming <afleming@freescale.com>
	7	*
	8	* Based on 83xx/mpc8360e_pb.c by:
	9	* Li Yang <LeoLi@freescale.com>
	10	* Yin Olivia <Hong-hua.Yin@freescale.com>
	11	*
	12	* Description:
23f510bc	13	* MPC85xx MDS board specific routines.
c2882bb1 AF	14	*/
	15
	16	#include <linux/stddef.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/errno.h>
	20	#include <linux/reboot.h>
	21	#include <linux/pci.h>
	22	#include <linux/kdev_t.h>
	23	#include <linux/major.h>
	24	#include <linux/console.h>
	25	#include <linux/delay.h>
	26	#include <linux/seq_file.h>
c2882bb1	27	#include <linux/initrd.h>
c2882bb1	28	#include <linux/fsl_devices.h>
882407b9 JL	29	#include <linux/of_platform.h>
882407b9 JL	30	#include <linux/of_device.h>
94833a42	31	#include <linux/phy.h>
95f72d1e	32	#include <linux/memblock.h>
94848654	33	#include <linux/fsl/guts.h>
c2882bb1	34
60063497	35	#include <linux/atomic.h>
c2882bb1 AF	36	#include <asm/time.h>
	37	#include <asm/io.h>
	38	#include <asm/machdep.h>
c2882bb1	39	#include <asm/pci-bridge.h>
c2882bb1 AF	40	#include <asm/irq.h>
	41	#include <mm/mmu_decl.h>
	42	#include <asm/prom.h>
	43	#include <asm/udbg.h>
	44	#include <sysdev/fsl_soc.h>
3f6c5dae	45	#include <sysdev/fsl_pci.h>
9b9d401b	46	#include <sysdev/simple_gpio.h>
7aa1aa6e ZQ	47	#include <soc/fsl/qe/qe.h>
7aa1aa6e ZQ	48	#include <soc/fsl/qe/qe_ic.h>
c2882bb1	49	#include <asm/mpic.h>
152d0182	50	#include <asm/swiotlb.h>
582d3e09	51	#include "smp.h"
c2882bb1	52
543a07b1 DES	53	#include "mpc85xx.h"
543a07b1 DES	54
c2882bb1 AF	55	#undef DEBUG
	56	#ifdef DEBUG
	57	#define DBG(fmt...) udbg_printf(fmt)
	58	#else
	59	#define DBG(fmt...)
	60	#endif
	61
93c4ea38 AS	62	#if IS_BUILTIN(CONFIG_PHYLIB)
93c4ea38 AS	63
94833a42 AF	64	#define MV88E1111_SCR 0x10
	65	#define MV88E1111_SCR_125CLK 0x0010
	66	static int mpc8568_fixup_125_clock(struct phy_device *phydev)
	67	{
	68	int scr;
	69	int err;
	70
	71	/* Workaround for the 125 CLK Toggle */
	72	scr = phy_read(phydev, MV88E1111_SCR);
	73
	74	if (scr < 0)
	75	return scr;
	76
	77	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
	78
	79	if (err)
	80	return err;
	81
	82	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	83
	84	if (err)
	85	return err;
	86
	87	scr = phy_read(phydev, MV88E1111_SCR);
	88
	89	if (scr < 0)
29827b02	90	return scr;
94833a42 AF	91
	92	err = phy_write(phydev, MV88E1111_SCR, scr \| 0x0008);
	93
	94	return err;
	95	}
	96
	97	static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
	98	{
	99	int temp;
	100	int err;
	101
	102	/* Errata */
	103	err = phy_write(phydev,29, 0x0006);
	104
	105	if (err)
	106	return err;
	107
	108	temp = phy_read(phydev, 30);
	109
	110	if (temp < 0)
	111	return temp;
	112
	113	temp = (temp & (~0x8000)) \| 0x4000;
	114	err = phy_write(phydev,30, temp);
	115
	116	if (err)
	117	return err;
	118
	119	err = phy_write(phydev,29, 0x000a);
	120
	121	if (err)
	122	return err;
	123
	124	temp = phy_read(phydev, 30);
	125
	126	if (temp < 0)
	127	return temp;
	128
	129	temp = phy_read(phydev, 30);
	130
	131	if (temp < 0)
	132	return temp;
	133
	134	temp &= ~0x0020;
	135
	136	err = phy_write(phydev,30,temp);
	137
	138	if (err)
	139	return err;
	140
	141	/* Disable automatic MDI/MDIX selection */
	142	temp = phy_read(phydev, 16);
	143
	144	if (temp < 0)
	145	return temp;
	146
	147	temp &= ~0x0060;
	148	err = phy_write(phydev,16,temp);
	149
	150	return err;
	151	}
	152
93c4ea38 AS	153	#endif
93c4ea38 AS	154
c2882bb1 AF	155	/* ************************************************************************
	156	*
	157	* Setup the architecture
	158	*
	159	*/
dee9ad71	160	#ifdef CONFIG_QUICC_ENGINE
99d8238f	161	static void __init mpc85xx_mds_reset_ucc_phys(void)
c2882bb1 AF	162	{
c2882bb1 AF	163	struct device_node *np;
99d8238f	164	static u8 __iomem *bcsr_regs;
c2882bb1	165
c2882bb1 AF	166	/* Map BCSR area */
c2882bb1 AF	167	np = of_find_node_by_name(NULL, "bcsr");
99d8238f AV	168	if (!np)
99d8238f AV	169	return;
c2882bb1	170
99d8238f AV	171	bcsr_regs = of_iomap(np, 0);
	172	of_node_put(np);
	173	if (!bcsr_regs)
	174	return;
c2882bb1	175
99d8238f AV	176	if (machine_is(mpc8568_mds)) {
	177	#define BCSR_UCC1_GETH_EN (0x1 << 7)
	178	#define BCSR_UCC2_GETH_EN (0x1 << 7)
	179	#define BCSR_UCC1_MODE_MSK (0x3 << 4)
	180	#define BCSR_UCC2_MODE_MSK (0x3 << 0)
152d0182	181
99d8238f AV	182	/* Turn off UCC1 & UCC2 */
	183	clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	184	clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	185
	186	/* Mode is RGMII, all bits clear */
	187	clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK \|
	188	BCSR_UCC2_MODE_MSK);
	189
	190	/* Turn UCC1 & UCC2 on */
	191	setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
	192	setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
	193	} else if (machine_is(mpc8569_mds)) {
	194	#define BCSR7_UCC12_GETHnRST (0x1 << 2)
	195	#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
	196	#define BCSR_UCC_RGMII (0x1 << 6)
	197	#define BCSR_UCC_RTBI (0x1 << 5)
	198	/*
	199	* U-Boot mangles interrupt polarity for Marvell PHYs,
	200	* so reset built-in and UEM Marvell PHYs, this puts
	201	* the PHYs into their normal state.
	202	*/
	203	clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	204	setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	205
	206	setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
	207	clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
	208
5444d639	209	for_each_compatible_node(np, "network", "ucc_geth") {
99d8238f AV	210	const unsigned int *prop;
	211	int ucc_num;
	212
	213	prop = of_get_property(np, "cell-index", NULL);
	214	if (prop == NULL)
	215	continue;
	216
	217	ucc_num = *prop - 1;
	218
	219	prop = of_get_property(np, "phy-connection-type", NULL);
	220	if (prop == NULL)
	221	continue;
	222
	223	if (strcmp("rtbi", (const char *)prop) == 0)
	224	clrsetbits_8(&bcsr_regs[7 + ucc_num],
	225	BCSR_UCC_RGMII, BCSR_UCC_RTBI);
c9438aff	226	}
99d8238f AV	227	} else if (machine_is(p1021_mds)) {
	228	#define BCSR11_ENET_MICRST (0x1 << 5)
	229	/* Reset Micrel PHY */
	230	clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
	231	setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
c9438aff	232	}
c2882bb1	233
99d8238f AV	234	iounmap(bcsr_regs);
99d8238f AV	235	}
48936a08	236
99d8238f AV	237	static void __init mpc85xx_mds_qe_init(void)
	238	{
	239	struct device_node *np;
48936a08	240
72c916ae	241	mpc85xx_qe_init();
706f4aa0	242	mpc85xx_qe_par_io_init();
99d8238f	243	mpc85xx_mds_reset_ucc_phys();
48936a08 HW	244
48936a08 HW	245	if (machine_is(p1021_mds)) {
48936a08	246
9cb6abcb	247	struct ccsr_guts __iomem *guts;
48936a08	248
c141b38f	249	np = of_find_node_by_name(NULL, "global-utilities");
48936a08	250	if (np) {
c141b38f ZF	251	guts = of_iomap(np, 0);
	252	if (!guts)
	253	pr_err("mpc85xx-rdb: could not map global utilities register\n");
	254	else{
48936a08 HW	255	/* P1021 has pins muxed for QE and other functions. To
	256	* enable QE UEC mode, we need to set bit QE0 for UCC1
	257	* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
8dd11f80	258	* and QE12 for QE MII management signals in PMUXCR
48936a08 HW	259	* register.
48936a08 HW	260	*/
c141b38f ZF	261	setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) \|
	262	MPC85xx_PMUXCR_QE(3) \|
	263	MPC85xx_PMUXCR_QE(9) \|
	264	MPC85xx_PMUXCR_QE(12));
	265	iounmap(guts);
	266	}
48936a08 HW	267	of_node_put(np);
	268	}
	269
	270	}
99d8238f AV	271	}
	272
	273	static void __init mpc85xx_mds_qeic_init(void)
	274	{
	275	struct device_node *np;
	276
	277	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
	278	if (!of_device_is_available(np)) {
	279	of_node_put(np);
	280	return;
	281	}
	282
	283	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
	284	if (!np) {
	285	np = of_find_node_by_type(NULL, "qeic");
	286	if (!np)
	287	return;
	288	}
	289
	290	if (machine_is(p1021_mds))
	291	qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
	292	qe_ic_cascade_high_mpic);
	293	else
	294	qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
	295	of_node_put(np);
	296	}
	297	#else
99d8238f AV	298	static void __init mpc85xx_mds_qe_init(void) { }
99d8238f AV	299	static void __init mpc85xx_mds_qeic_init(void) { }
c2882bb1	300	#endif /* CONFIG_QUICC_ENGINE */
152d0182	301
99d8238f AV	302	static void __init mpc85xx_mds_setup_arch(void)
99d8238f AV	303	{
99d8238f AV	304	if (ppc_md.progress)
	305	ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
	306
99d8238f	307	mpc85xx_smp_init();
99d8238f AV	308
	309	mpc85xx_mds_qe_init();
	310
905e75c4 JH	311	fsl_pci_assign_primary();
	312
	313	swiotlb_detect_4g();
c2882bb1 AF	314	}
c2882bb1 AF	315
93c4ea38	316	#if IS_BUILTIN(CONFIG_PHYLIB)
94833a42 AF	317
	318	static int __init board_fixups(void)
	319	{
aab0d375	320	char phy_id[20];
94833a42 AF	321	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
	322	struct device_node *mdio;
	323	struct resource res;
	324	int i;
	325
	326	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
	327	mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
	328
	329	of_address_to_resource(mdio, 0, &res);
aab0d375	330	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	331	(unsigned long long)res.start, 1);
94833a42 AF	332
	333	phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
	334	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	335
	336	/* Register a workaround for errata */
aab0d375	337	snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
24a99596	338	(unsigned long long)res.start, 7);
94833a42 AF	339	phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
	340
	341	of_node_put(mdio);
	342	}
	343
	344	return 0;
	345	}
93c4ea38	346
ea5130dc	347	machine_arch_initcall(mpc8568_mds, board_fixups);
4b3b42b3	348	machine_arch_initcall(mpc8569_mds, board_fixups);
94833a42	349
93c4ea38 AS	350	#endif
93c4ea38 AS	351
23f510bc	352	static int __init mpc85xx_publish_devices(void)
c2882bb1	353	{
e98efaf3 AV	354	if (machine_is(mpc8568_mds))
e98efaf3 AV	355	simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
9b9d401b AV	356	if (machine_is(mpc8569_mds))
	357	simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
	358
8a95bc8d	359	return mpc85xx_common_publish_devices();
48936a08 HW	360	}
48936a08 HW	361
905e75c4 JH	362	machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
	363	machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
	364	machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
c2882bb1	365
23f510bc	366	static void __init mpc85xx_mds_pic_init(void)
c2882bb1	367	{
e55d7f73	368	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN \|
5019609f	369	MPIC_SINGLE_DEST_CPU,
b533f8ae	370	0, 256, " OpenPIC ");
c2882bb1	371	BUG_ON(mpic == NULL);
c2882bb1	372
c2882bb1	373	mpic_init(mpic);
99d8238f	374	mpc85xx_mds_qeic_init();
c2882bb1 AF	375	}
c2882bb1 AF	376
23f510bc	377	static int __init mpc85xx_mds_probe(void)
c2882bb1	378	{
56571384	379	return of_machine_is_compatible("MPC85xxMDS");
c2882bb1 AF	380	}
c2882bb1 AF	381
ea5130dc HW	382	define_machine(mpc8568_mds) {
ea5130dc HW	383	.name = "MPC8568 MDS",
23f510bc KG	384	.probe = mpc85xx_mds_probe,
	385	.setup_arch = mpc85xx_mds_setup_arch,
	386	.init_IRQ = mpc85xx_mds_pic_init,
c2882bb1	387	.get_irq = mpic_get_irq,
c2882bb1 AF	388	.calibrate_decr = generic_calibrate_decr,
c2882bb1 AF	389	.progress = udbg_progress,
2af8569d	390	#ifdef CONFIG_PCI
aa3c1121	391	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	392	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
2af8569d	393	#endif
c2882bb1	394	};
4b3b42b3 HW	395
	396	static int __init mpc8569_mds_probe(void)
	397	{
56571384	398	return of_machine_is_compatible("fsl,MPC8569EMDS");
4b3b42b3 HW	399	}
	400
	401	define_machine(mpc8569_mds) {
	402	.name = "MPC8569 MDS",
	403	.probe = mpc8569_mds_probe,
	404	.setup_arch = mpc85xx_mds_setup_arch,
	405	.init_IRQ = mpc85xx_mds_pic_init,
	406	.get_irq = mpic_get_irq,
4b3b42b3 HW	407	.calibrate_decr = generic_calibrate_decr,
	408	.progress = udbg_progress,
	409	#ifdef CONFIG_PCI
	410	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	411	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
4b3b42b3 HW	412	#endif
4b3b42b3 HW	413	};
48936a08 HW	414
	415	static int __init p1021_mds_probe(void)
	416	{
56571384	417	return of_machine_is_compatible("fsl,P1021MDS");
48936a08 HW	418
	419	}
	420
	421	define_machine(p1021_mds) {
	422	.name = "P1021 MDS",
	423	.probe = p1021_mds_probe,
	424	.setup_arch = mpc85xx_mds_setup_arch,
	425	.init_IRQ = mpc85xx_mds_pic_init,
	426	.get_irq = mpic_get_irq,
48936a08 HW	427	.calibrate_decr = generic_calibrate_decr,
	428	.progress = udbg_progress,
	429	#ifdef CONFIG_PCI
	430	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
48b16180	431	.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
48936a08 HW	432	#endif
48936a08 HW	433	};