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4ca4b627 JL |
1 | /* |
2 | * Author: Xianghua Xiao <x.xiao@freescale.com> | |
3 | * Zhang Wei <wei.zhang@freescale.com> | |
4 | * | |
5 | * Copyright 2006 Freescale Semiconductor Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
4ca4b627 JL |
13 | #include <linux/stddef.h> |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | ||
aaddd3ea | 18 | #include <asm/code-patching.h> |
4ca4b627 | 19 | #include <asm/page.h> |
f1a1eb29 | 20 | #include <asm/pgtable.h> |
4ca4b627 | 21 | #include <asm/pci-bridge.h> |
b8b572e1 | 22 | #include <asm/mpic.h> |
4ca4b627 JL |
23 | #include <asm/cacheflush.h> |
24 | ||
25 | #include <sysdev/fsl_soc.h> | |
26 | ||
27 | #include "mpc86xx.h" | |
28 | ||
29 | extern void __secondary_start_mpc86xx(void); | |
4ca4b627 | 30 | |
1e76dff2 KG |
31 | #define MCM_PORT_CONFIG_OFFSET 0x10 |
32 | ||
33 | /* Offset from CCSRBAR */ | |
34 | #define MPC86xx_MCM_OFFSET (0x1000) | |
35 | #define MPC86xx_MCM_SIZE (0x1000) | |
4ca4b627 JL |
36 | |
37 | static void __init | |
38 | smp_86xx_release_core(int nr) | |
39 | { | |
9ad494f6 KG |
40 | __be32 __iomem *mcm_vaddr; |
41 | unsigned long pcr; | |
4ca4b627 JL |
42 | |
43 | if (nr < 0 || nr >= NR_CPUS) | |
44 | return; | |
45 | ||
46 | /* | |
47 | * Startup Core #nr. | |
48 | */ | |
49 | mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET, | |
50 | MPC86xx_MCM_SIZE); | |
9ad494f6 | 51 | pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2)); |
4ca4b627 | 52 | pcr |= 1 << (nr + 24); |
9ad494f6 | 53 | out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr); |
1e76dff2 KG |
54 | |
55 | iounmap(mcm_vaddr); | |
4ca4b627 JL |
56 | } |
57 | ||
58 | ||
de300974 | 59 | static int __init |
4ca4b627 JL |
60 | smp_86xx_kick_cpu(int nr) |
61 | { | |
62 | unsigned int save_vector; | |
63 | unsigned long target, flags; | |
64 | int n = 0; | |
e7a57273 | 65 | unsigned int *vector = (unsigned int *)(KERNELBASE + 0x100); |
4ca4b627 JL |
66 | |
67 | if (nr < 0 || nr >= NR_CPUS) | |
de300974 | 68 | return -ENOENT; |
4ca4b627 JL |
69 | |
70 | pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr); | |
71 | ||
72 | local_irq_save(flags); | |
4ca4b627 JL |
73 | |
74 | /* Save reset vector */ | |
75 | save_vector = *vector; | |
76 | ||
77 | /* Setup fake reset vector to call __secondary_start_mpc86xx. */ | |
78 | target = (unsigned long) __secondary_start_mpc86xx; | |
e7a57273 | 79 | patch_branch(vector, target, BRANCH_SET_LINK); |
4ca4b627 JL |
80 | |
81 | /* Kick that CPU */ | |
82 | smp_86xx_release_core(nr); | |
83 | ||
84 | /* Wait a bit for the CPU to take the exception. */ | |
85 | while ((__secondary_hold_acknowledge != nr) && (n++, n < 1000)) | |
86 | mdelay(1); | |
87 | ||
88 | /* Restore the exception vector */ | |
89 | *vector = save_vector; | |
90 | flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); | |
91 | ||
92 | local_irq_restore(flags); | |
93 | ||
94 | pr_debug("wait CPU #%d for %d msecs.\n", nr, n); | |
de300974 ME |
95 | |
96 | return 0; | |
4ca4b627 JL |
97 | } |
98 | ||
99 | ||
100 | static void __init | |
101 | smp_86xx_setup_cpu(int cpu_nr) | |
102 | { | |
103 | mpic_setup_this_cpu(); | |
104 | } | |
105 | ||
106 | ||
107 | struct smp_ops_t smp_86xx_ops = { | |
c64af645 | 108 | .cause_nmi_ipi = NULL, |
4ca4b627 JL |
109 | .message_pass = smp_mpic_message_pass, |
110 | .probe = smp_mpic_probe, | |
111 | .kick_cpu = smp_86xx_kick_cpu, | |
112 | .setup_cpu = smp_86xx_setup_cpu, | |
113 | .take_timebase = smp_generic_take_timebase, | |
114 | .give_timebase = smp_generic_give_timebase, | |
115 | }; | |
116 | ||
117 | ||
118 | void __init | |
119 | mpc86xx_smp_init(void) | |
120 | { | |
121 | smp_ops = &smp_86xx_ops; | |
122 | } |