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11c146cc SW |
1 | /* |
2 | * Platform setup for the Embedded Planet EP88xC board | |
3 | * | |
4 | * Author: Scott Wood <scottwood@freescale.com> | |
5 | * Copyright 2007 Freescale Semiconductor, Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/of_platform.h> | |
14 | ||
15 | #include <asm/machdep.h> | |
16 | #include <asm/io.h> | |
17 | #include <asm/udbg.h> | |
b5677d84 | 18 | #include <asm/cpm1.h> |
11c146cc | 19 | |
49b51545 | 20 | #include "mpc8xx.h" |
11c146cc SW |
21 | |
22 | struct cpm_pin { | |
23 | int port, pin, flags; | |
24 | }; | |
25 | ||
26 | static struct cpm_pin ep88xc_pins[] = { | |
27 | /* SMC1 */ | |
28 | {1, 24, CPM_PIN_INPUT}, /* RX */ | |
29 | {1, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */ | |
30 | ||
31 | /* SCC2 */ | |
32 | {0, 12, CPM_PIN_INPUT}, /* TX */ | |
33 | {0, 13, CPM_PIN_INPUT}, /* RX */ | |
34 | {2, 8, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CD */ | |
35 | {2, 9, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CTS */ | |
36 | {2, 14, CPM_PIN_INPUT}, /* RTS */ | |
37 | ||
38 | /* MII1 */ | |
39 | {0, 0, CPM_PIN_INPUT}, | |
40 | {0, 1, CPM_PIN_INPUT}, | |
41 | {0, 2, CPM_PIN_INPUT}, | |
42 | {0, 3, CPM_PIN_INPUT}, | |
43 | {0, 4, CPM_PIN_OUTPUT}, | |
44 | {0, 10, CPM_PIN_OUTPUT}, | |
45 | {0, 11, CPM_PIN_OUTPUT}, | |
46 | {1, 19, CPM_PIN_INPUT}, | |
47 | {1, 31, CPM_PIN_INPUT}, | |
48 | {2, 12, CPM_PIN_INPUT}, | |
49 | {2, 13, CPM_PIN_INPUT}, | |
50 | {3, 8, CPM_PIN_INPUT}, | |
51 | {4, 30, CPM_PIN_OUTPUT}, | |
52 | {4, 31, CPM_PIN_OUTPUT}, | |
53 | ||
54 | /* MII2 */ | |
55 | {4, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
56 | {4, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
57 | {4, 16, CPM_PIN_OUTPUT}, | |
58 | {4, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
59 | {4, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
60 | {4, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
61 | {4, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | |
62 | {4, 21, CPM_PIN_OUTPUT}, | |
63 | {4, 22, CPM_PIN_OUTPUT}, | |
64 | {4, 23, CPM_PIN_OUTPUT}, | |
65 | {4, 24, CPM_PIN_OUTPUT}, | |
66 | {4, 25, CPM_PIN_OUTPUT}, | |
67 | {4, 26, CPM_PIN_OUTPUT}, | |
68 | {4, 27, CPM_PIN_OUTPUT}, | |
69 | {4, 28, CPM_PIN_OUTPUT}, | |
70 | {4, 29, CPM_PIN_OUTPUT}, | |
71 | ||
72 | /* USB */ | |
73 | {0, 6, CPM_PIN_INPUT}, /* CLK2 */ | |
74 | {0, 14, CPM_PIN_INPUT}, /* USBOE */ | |
75 | {0, 15, CPM_PIN_INPUT}, /* USBRXD */ | |
76 | {2, 6, CPM_PIN_OUTPUT}, /* USBTXN */ | |
77 | {2, 7, CPM_PIN_OUTPUT}, /* USBTXP */ | |
78 | {2, 10, CPM_PIN_INPUT}, /* USBRXN */ | |
79 | {2, 11, CPM_PIN_INPUT}, /* USBRXP */ | |
80 | ||
81 | /* Misc */ | |
82 | {1, 26, CPM_PIN_INPUT}, /* BRGO2 */ | |
83 | {1, 27, CPM_PIN_INPUT}, /* BRGO1 */ | |
84 | }; | |
85 | ||
86 | static void __init init_ioports(void) | |
87 | { | |
88 | int i; | |
89 | ||
90 | for (i = 0; i < ARRAY_SIZE(ep88xc_pins); i++) { | |
91 | struct cpm_pin *pin = &ep88xc_pins[i]; | |
92 | cpm1_set_pin(pin->port, pin->pin, pin->flags); | |
93 | } | |
94 | ||
95 | cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); | |
96 | cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_TX); /* USB */ | |
97 | cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX); | |
98 | cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX); | |
99 | cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX); | |
100 | } | |
101 | ||
102 | static u8 __iomem *ep88xc_bcsr; | |
103 | ||
104 | #define BCSR7_SCC2_ENABLE 0x10 | |
105 | ||
106 | #define BCSR8_PHY1_ENABLE 0x80 | |
107 | #define BCSR8_PHY1_POWER 0x40 | |
108 | #define BCSR8_PHY2_ENABLE 0x20 | |
109 | #define BCSR8_PHY2_POWER 0x10 | |
110 | ||
111 | #define BCSR9_USB_ENABLE 0x80 | |
112 | #define BCSR9_USB_POWER 0x40 | |
113 | #define BCSR9_USB_HOST 0x20 | |
114 | #define BCSR9_USB_FULL_SPEED_TARGET 0x10 | |
115 | ||
116 | static void __init ep88xc_setup_arch(void) | |
117 | { | |
118 | struct device_node *np; | |
119 | ||
120 | cpm_reset(); | |
121 | init_ioports(); | |
122 | ||
123 | np = of_find_compatible_node(NULL, NULL, "fsl,ep88xc-bcsr"); | |
124 | if (!np) { | |
125 | printk(KERN_CRIT "Could not find fsl,ep88xc-bcsr node\n"); | |
126 | return; | |
127 | } | |
128 | ||
129 | ep88xc_bcsr = of_iomap(np, 0); | |
130 | of_node_put(np); | |
131 | ||
132 | if (!ep88xc_bcsr) { | |
133 | printk(KERN_CRIT "Could not remap BCSR\n"); | |
134 | return; | |
135 | } | |
136 | ||
137 | setbits8(&ep88xc_bcsr[7], BCSR7_SCC2_ENABLE); | |
138 | setbits8(&ep88xc_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER | | |
139 | BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER); | |
140 | } | |
141 | ||
142 | static int __init ep88xc_probe(void) | |
143 | { | |
144 | unsigned long root = of_get_flat_dt_root(); | |
145 | return of_flat_dt_is_compatible(root, "fsl,ep88xc"); | |
146 | } | |
147 | ||
148 | static struct of_device_id __initdata of_bus_ids[] = { | |
149 | { .name = "soc", }, | |
150 | { .name = "cpm", }, | |
151 | { .name = "localbus", }, | |
152 | {}, | |
153 | }; | |
154 | ||
155 | static int __init declare_of_platform_devices(void) | |
156 | { | |
157 | /* Publish the QE devices */ | |
6869e4ad | 158 | of_platform_bus_probe(NULL, of_bus_ids, NULL); |
11c146cc SW |
159 | |
160 | return 0; | |
161 | } | |
6869e4ad | 162 | machine_device_initcall(ep88xc, declare_of_platform_devices); |
11c146cc SW |
163 | |
164 | define_machine(ep88xc) { | |
165 | .name = "Embedded Planet EP88xC", | |
166 | .probe = ep88xc_probe, | |
167 | .setup_arch = ep88xc_setup_arch, | |
d0a02a06 | 168 | .init_IRQ = mpc8xx_pics_init, |
11c146cc SW |
169 | .get_irq = mpc8xx_get_irq, |
170 | .restart = mpc8xx_restart, | |
171 | .calibrate_decr = mpc8xx_calibrate_decr, | |
172 | .set_rtc_time = mpc8xx_set_rtc_time, | |
173 | .get_rtc_time = mpc8xx_get_rtc_time, | |
174 | .progress = udbg_progress, | |
175 | }; |