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df34403d VB |
1 | /*arch/ppc/platforms/mpc885ads-setup.c |
2 | * | |
3 | * Platform setup for the Freescale mpc885ads board | |
4 | * | |
5 | * Vitaly Bordug <vbordug@ru.mvista.com> | |
6 | * | |
7 | * Copyright 2005 MontaVista Software Inc. | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public License | |
10 | * version 2. This program is licensed "as is" without any warranty of any | |
11 | * kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/param.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/root_dev.h> | |
22 | ||
23 | #include <linux/fs_enet_pd.h> | |
24 | #include <linux/fs_uart_pd.h> | |
25 | #include <linux/mii.h> | |
26 | ||
27 | #include <asm/delay.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/machdep.h> | |
30 | #include <asm/page.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/system.h> | |
33 | #include <asm/time.h> | |
34 | #include <asm/ppcboot.h> | |
35 | #include <asm/mpc8xx.h> | |
36 | #include <asm/8xx_immap.h> | |
37 | #include <asm/commproc.h> | |
38 | #include <asm/fs_pd.h> | |
39 | #include <asm/prom.h> | |
40 | ||
41 | extern void cpm_reset(void); | |
42 | extern void mpc8xx_show_cpuinfo(struct seq_file*); | |
43 | extern void mpc8xx_restart(char *cmd); | |
44 | extern void mpc8xx_calibrate_decr(void); | |
45 | extern int mpc8xx_set_rtc_time(struct rtc_time *tm); | |
46 | extern void mpc8xx_get_rtc_time(struct rtc_time *tm); | |
47 | extern void m8xx_pic_init(void); | |
48 | extern unsigned int mpc8xx_get_irq(void); | |
49 | ||
50 | static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi); | |
51 | static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi); | |
52 | static void init_scc3_ioports(struct fs_platform_info* ptr); | |
53 | ||
54 | void __init mpc885ads_board_setup(void) | |
55 | { | |
56 | cpm8xx_t *cp; | |
57 | unsigned int *bcsr_io; | |
58 | u8 tmpval8; | |
59 | ||
60 | #ifdef CONFIG_FS_ENET | |
61 | iop8xx_t *io_port; | |
62 | #endif | |
63 | ||
64 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); | |
65 | cp = (cpm8xx_t *)immr_map(im_cpm); | |
66 | ||
67 | if (bcsr_io == NULL) { | |
68 | printk(KERN_CRIT "Could not remap BCSR\n"); | |
69 | return; | |
70 | } | |
71 | #ifdef CONFIG_SERIAL_CPM_SMC1 | |
72 | clrbits32(bcsr_io, BCSR1_RS232EN_1); | |
73 | clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */ | |
74 | tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX); | |
75 | out_8(&(cp->cp_smc[0].smc_smcm), tmpval8); | |
76 | clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */ | |
77 | #else | |
78 | setbits32(bcsr_io,BCSR1_RS232EN_1); | |
79 | out_be16(&cp->cp_smc[0].smc_smcmr, 0); | |
80 | out_8(&cp->cp_smc[0].smc_smce, 0); | |
81 | #endif | |
82 | ||
83 | #ifdef CONFIG_SERIAL_CPM_SMC2 | |
84 | clrbits32(bcsr_io,BCSR1_RS232EN_2); | |
85 | clrbits32(&cp->cp_simode, 0xe0000000 >> 1); | |
86 | setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */ | |
87 | tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX); | |
88 | out_8(&(cp->cp_smc[1].smc_smcm), tmpval8); | |
89 | clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
90 | ||
91 | init_smc2_uart_ioports(0); | |
92 | #else | |
93 | setbits32(bcsr_io,BCSR1_RS232EN_2); | |
94 | out_be16(&cp->cp_smc[1].smc_smcmr, 0); | |
95 | out_8(&cp->cp_smc[1].smc_smce, 0); | |
96 | #endif | |
97 | immr_unmap(cp); | |
98 | iounmap(bcsr_io); | |
99 | ||
100 | #ifdef CONFIG_FS_ENET | |
101 | /* use MDC for MII (common) */ | |
102 | io_port = (iop8xx_t*)immr_map(im_ioport); | |
103 | setbits16(&io_port->iop_pdpar, 0x0080); | |
104 | clrbits16(&io_port->iop_pddir, 0x0080); | |
105 | ||
106 | bcsr_io = ioremap(BCSR5, sizeof(unsigned long)); | |
107 | clrbits32(bcsr_io,BCSR5_MII1_EN); | |
108 | clrbits32(bcsr_io,BCSR5_MII1_RST); | |
109 | #ifndef CONFIG_FC_ENET_HAS_SCC | |
110 | clrbits32(bcsr_io,BCSR5_MII2_EN); | |
111 | clrbits32(bcsr_io,BCSR5_MII2_RST); | |
112 | ||
113 | #endif | |
114 | iounmap(bcsr_io); | |
115 | immr_unmap(io_port); | |
116 | ||
117 | #endif | |
118 | } | |
119 | ||
120 | ||
121 | static void init_fec1_ioports(struct fs_platform_info* ptr) | |
122 | { | |
123 | cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm); | |
124 | iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport); | |
125 | ||
126 | /* configure FEC1 pins */ | |
127 | setbits16(&io_port->iop_papar, 0xf830); | |
128 | setbits16(&io_port->iop_padir, 0x0830); | |
129 | clrbits16(&io_port->iop_padir, 0xf000); | |
130 | ||
131 | setbits32(&cp->cp_pbpar, 0x00001001); | |
132 | clrbits32(&cp->cp_pbdir, 0x00001001); | |
133 | ||
134 | setbits16(&io_port->iop_pcpar, 0x000c); | |
135 | clrbits16(&io_port->iop_pcdir, 0x000c); | |
136 | ||
137 | setbits32(&cp->cp_pepar, 0x00000003); | |
138 | setbits32(&cp->cp_pedir, 0x00000003); | |
139 | clrbits32(&cp->cp_peso, 0x00000003); | |
140 | clrbits32(&cp->cp_cptr, 0x00000100); | |
141 | ||
142 | immr_unmap(io_port); | |
143 | immr_unmap(cp); | |
144 | } | |
145 | ||
146 | ||
147 | static void init_fec2_ioports(struct fs_platform_info* ptr) | |
148 | { | |
149 | cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm); | |
150 | iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport); | |
151 | ||
152 | /* configure FEC2 pins */ | |
153 | setbits32(&cp->cp_pepar, 0x0003fffc); | |
154 | setbits32(&cp->cp_pedir, 0x0003fffc); | |
155 | clrbits32(&cp->cp_peso, 0x000087fc); | |
156 | setbits32(&cp->cp_peso, 0x00037800); | |
157 | clrbits32(&cp->cp_cptr, 0x00000080); | |
158 | ||
159 | immr_unmap(io_port); | |
160 | immr_unmap(cp); | |
161 | } | |
162 | ||
163 | void init_fec_ioports(struct fs_platform_info *fpi) | |
164 | { | |
165 | int fec_no = fs_get_fec_index(fpi->fs_no); | |
166 | ||
167 | switch (fec_no) { | |
168 | case 0: | |
169 | init_fec1_ioports(fpi); | |
170 | break; | |
171 | case 1: | |
172 | init_fec2_ioports(fpi); | |
173 | break; | |
174 | default: | |
175 | printk(KERN_ERR "init_fec_ioports: invalid FEC number\n"); | |
176 | return; | |
177 | } | |
178 | } | |
179 | ||
180 | static void init_scc3_ioports(struct fs_platform_info* fpi) | |
181 | { | |
182 | unsigned *bcsr_io; | |
183 | iop8xx_t *io_port; | |
184 | cpm8xx_t *cp; | |
185 | ||
186 | bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE); | |
187 | io_port = (iop8xx_t *)immr_map(im_ioport); | |
188 | cp = (cpm8xx_t *)immr_map(im_cpm); | |
189 | ||
190 | if (bcsr_io == NULL) { | |
191 | printk(KERN_CRIT "Could not remap BCSR\n"); | |
192 | return; | |
193 | } | |
194 | ||
195 | /* Enable the PHY. | |
196 | */ | |
197 | clrbits32(bcsr_io+4, BCSR4_ETH10_RST); | |
198 | udelay(1000); | |
199 | setbits32(bcsr_io+4, BCSR4_ETH10_RST); | |
200 | /* Configure port A pins for Txd and Rxd. | |
201 | */ | |
202 | setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD); | |
203 | clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD); | |
204 | ||
205 | /* Configure port C pins to enable CLSN and RENA. | |
206 | */ | |
207 | clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA); | |
208 | clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA); | |
209 | setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA); | |
210 | ||
211 | /* Configure port E for TCLK and RCLK. | |
212 | */ | |
213 | setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK); | |
214 | clrbits32(&cp->cp_pepar, PE_ENET_TENA); | |
215 | clrbits32(&cp->cp_pedir, | |
216 | PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA); | |
217 | clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK); | |
218 | setbits32(&cp->cp_peso, PE_ENET_TENA); | |
219 | ||
220 | /* Configure Serial Interface clock routing. | |
221 | * First, clear all SCC bits to zero, then set the ones we want. | |
222 | */ | |
223 | clrbits32(&cp->cp_sicr, SICR_ENET_MASK); | |
224 | setbits32(&cp->cp_sicr, SICR_ENET_CLKRT); | |
225 | ||
226 | /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used. | |
227 | */ | |
228 | clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
229 | /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode | |
230 | * by H/W setting after reset. SCC ethernet controller support only half duplex. | |
231 | * This discrepancy of modes causes a lot of carrier lost errors. | |
232 | */ | |
233 | ||
234 | /* In the original SCC enet driver the following code is placed at | |
235 | the end of the initialization */ | |
236 | setbits32(&cp->cp_pepar, PE_ENET_TENA); | |
237 | clrbits32(&cp->cp_pedir, PE_ENET_TENA); | |
238 | setbits32(&cp->cp_peso, PE_ENET_TENA); | |
239 | ||
240 | setbits32(bcsr_io+4, BCSR1_ETHEN); | |
241 | iounmap(bcsr_io); | |
242 | immr_unmap(io_port); | |
243 | immr_unmap(cp); | |
244 | } | |
245 | ||
246 | void init_scc_ioports(struct fs_platform_info *fpi) | |
247 | { | |
248 | int scc_no = fs_get_scc_index(fpi->fs_no); | |
249 | ||
250 | switch (scc_no) { | |
251 | case 2: | |
252 | init_scc3_ioports(fpi); | |
253 | break; | |
254 | default: | |
255 | printk(KERN_ERR "init_scc_ioports: invalid SCC number\n"); | |
256 | return; | |
257 | } | |
258 | } | |
259 | ||
260 | ||
261 | ||
262 | static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr) | |
263 | { | |
264 | unsigned *bcsr_io; | |
265 | cpm8xx_t *cp; | |
266 | ||
267 | cp = (cpm8xx_t *)immr_map(im_cpm); | |
268 | setbits32(&cp->cp_pepar, 0x000000c0); | |
269 | clrbits32(&cp->cp_pedir, 0x000000c0); | |
270 | clrbits32(&cp->cp_peso, 0x00000040); | |
271 | setbits32(&cp->cp_peso, 0x00000080); | |
272 | immr_unmap(cp); | |
273 | ||
274 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); | |
275 | ||
276 | if (bcsr_io == NULL) { | |
277 | printk(KERN_CRIT "Could not remap BCSR1\n"); | |
278 | return; | |
279 | } | |
280 | clrbits32(bcsr_io,BCSR1_RS232EN_1); | |
281 | iounmap(bcsr_io); | |
282 | } | |
283 | ||
284 | static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi) | |
285 | { | |
286 | unsigned *bcsr_io; | |
287 | cpm8xx_t *cp; | |
288 | ||
289 | cp = (cpm8xx_t *)immr_map(im_cpm); | |
290 | setbits32(&cp->cp_pepar, 0x00000c00); | |
291 | clrbits32(&cp->cp_pedir, 0x00000c00); | |
292 | clrbits32(&cp->cp_peso, 0x00000400); | |
293 | setbits32(&cp->cp_peso, 0x00000800); | |
294 | immr_unmap(cp); | |
295 | ||
296 | bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); | |
297 | ||
298 | if (bcsr_io == NULL) { | |
299 | printk(KERN_CRIT "Could not remap BCSR1\n"); | |
300 | return; | |
301 | } | |
302 | clrbits32(bcsr_io,BCSR1_RS232EN_2); | |
303 | iounmap(bcsr_io); | |
304 | } | |
305 | ||
306 | void init_smc_ioports(struct fs_uart_platform_info *data) | |
307 | { | |
308 | int smc_no = fs_uart_id_fsid2smc(data->fs_no); | |
309 | ||
310 | switch (smc_no) { | |
311 | case 0: | |
312 | init_smc1_uart_ioports(data); | |
313 | data->brg = data->clk_rx; | |
314 | break; | |
315 | case 1: | |
316 | init_smc2_uart_ioports(data); | |
317 | data->brg = data->clk_rx; | |
318 | break; | |
319 | default: | |
320 | printk(KERN_ERR "init_scc_ioports: invalid SCC number\n"); | |
321 | return; | |
322 | } | |
323 | } | |
324 | ||
e2eb6392 | 325 | int platform_device_skip(const char *model, int id) |
df34403d VB |
326 | { |
327 | #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3 | |
328 | const char *dev = "FEC"; | |
329 | int n = 2; | |
330 | #else | |
331 | const char *dev = "SCC"; | |
332 | int n = 3; | |
333 | #endif | |
334 | ||
335 | if (!strcmp(model, dev) && n == id) | |
336 | return 1; | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
341 | static void __init mpc885ads_setup_arch(void) | |
342 | { | |
343 | struct device_node *cpu; | |
344 | ||
345 | cpu = of_find_node_by_type(NULL, "cpu"); | |
346 | if (cpu != 0) { | |
347 | const unsigned int *fp; | |
348 | ||
e2eb6392 | 349 | fp = of_get_property(cpu, "clock-frequency", NULL); |
df34403d VB |
350 | if (fp != 0) |
351 | loops_per_jiffy = *fp / HZ; | |
352 | else | |
353 | loops_per_jiffy = 50000000 / HZ; | |
354 | of_node_put(cpu); | |
355 | } | |
356 | ||
357 | cpm_reset(); | |
358 | ||
359 | mpc885ads_board_setup(); | |
360 | ||
361 | ROOT_DEV = Root_NFS; | |
362 | } | |
363 | ||
364 | static int __init mpc885ads_probe(void) | |
365 | { | |
366 | char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), | |
367 | "model", NULL); | |
368 | if (model == NULL) | |
369 | return 0; | |
370 | if (strcmp(model, "MPC885ADS")) | |
371 | return 0; | |
372 | ||
373 | return 1; | |
374 | } | |
375 | ||
376 | define_machine(mpc885_ads) { | |
377 | .name = "MPC885 ADS", | |
378 | .probe = mpc885ads_probe, | |
379 | .setup_arch = mpc885ads_setup_arch, | |
380 | .init_IRQ = m8xx_pic_init, | |
381 | .show_cpuinfo = mpc8xx_show_cpuinfo, | |
382 | .get_irq = mpc8xx_get_irq, | |
383 | .restart = mpc8xx_restart, | |
384 | .calibrate_decr = mpc8xx_calibrate_decr, | |
385 | .set_rtc_time = mpc8xx_set_rtc_time, | |
386 | .get_rtc_time = mpc8xx_get_rtc_time, | |
387 | }; |