]>
Commit | Line | Data |
---|---|---|
a0ae9c7c AB |
1 | config PPC64 |
2 | bool "64-bit kernel" | |
3 | default n | |
4 | help | |
5 | This option selects whether a 32-bit or a 64-bit kernel | |
6 | will be built. | |
7 | ||
8 | menu "Processor support" | |
9 | choice | |
10 | prompt "Processor Type" | |
11 | depends on PPC32 | |
a0ae9c7c | 12 | help |
b9fd305d AB |
13 | There are five families of 32 bit PowerPC chips supported. |
14 | The most common ones are the desktop and server CPUs (601, 603, | |
15 | 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their | |
e177edcd | 16 | embedded 512x/52xx/82xx/83xx/86xx counterparts. |
b9fd305d AB |
17 | The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500 |
18 | (85xx) each form a family of their own that is not compatible | |
19 | with the others. | |
20 | ||
21 | If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. | |
22 | ||
48c93112 | 23 | config PPC_BOOK3S_32 |
e177edcd | 24 | bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" |
a0ae9c7c AB |
25 | select PPC_FPU |
26 | ||
a0ae9c7c AB |
27 | config PPC_85xx |
28 | bool "Freescale 85xx" | |
29 | select E500 | |
a0ae9c7c | 30 | |
a0ae9c7c AB |
31 | config PPC_8xx |
32 | bool "Freescale 8xx" | |
33 | select FSL_SOC | |
34 | select 8xx | |
1088a209 | 35 | select PPC_LIB_RHEAP |
a0ae9c7c AB |
36 | |
37 | config 40x | |
38 | bool "AMCC 40x" | |
39 | select PPC_DCR_NATIVE | |
9dae8afd | 40 | select PPC_UDBG_16550 |
93173ce2 | 41 | select 4xx_SOC |
b500563b | 42 | select PPC_PCI_CHOICE |
a0ae9c7c AB |
43 | |
44 | config 44x | |
e7f75ad0 | 45 | bool "AMCC 44x, 46x or 47x" |
a0ae9c7c | 46 | select PPC_DCR_NATIVE |
1d5499b5 | 47 | select PPC_UDBG_16550 |
93173ce2 | 48 | select 4xx_SOC |
b500563b | 49 | select PPC_PCI_CHOICE |
4ee7084e | 50 | select PHYS_64BIT |
a0ae9c7c AB |
51 | |
52 | config E200 | |
53 | bool "Freescale e200" | |
54 | ||
55 | endchoice | |
56 | ||
2d27cfd3 BH |
57 | choice |
58 | prompt "Processor Type" | |
5b7c3c91 | 59 | depends on PPC64 |
2d27cfd3 BH |
60 | help |
61 | There are two families of 64 bit PowerPC chips supported. | |
62 | The most common ones are the desktop and server CPUs | |
63 | (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...) | |
64 | ||
65 | The other are the "embedded" processors compliant with the | |
66 | "Book 3E" variant of the architecture | |
67 | ||
68 | config PPC_BOOK3S_64 | |
69 | bool "Server processors" | |
5b7c3c91 | 70 | select PPC_FPU |
5adfd346 | 71 | select PPC_HAVE_PMU_SUPPORT |
41151e77 | 72 | select SYS_SUPPORTS_HUGETLBFS |
5b7c3c91 | 73 | |
2d27cfd3 BH |
74 | config PPC_BOOK3E_64 |
75 | bool "Embedded processors" | |
76 | select PPC_FPU # Make it a choice ? | |
1ece355b | 77 | select PPC_SMP_MUXED_IPI |
2d27cfd3 BH |
78 | |
79 | endchoice | |
80 | ||
48c93112 BH |
81 | config PPC_BOOK3S |
82 | def_bool y | |
83 | depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 | |
28794d34 | 84 | |
2d27cfd3 BH |
85 | config PPC_BOOK3E |
86 | def_bool y | |
87 | depends on PPC_BOOK3E_64 | |
88 | ||
a0ae9c7c AB |
89 | config POWER4_ONLY |
90 | bool "Optimize for POWER4" | |
28794d34 | 91 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
92 | default n |
93 | ---help--- | |
94 | Cause the compiler to optimize for POWER4/POWER5/PPC970 processors. | |
95 | The resulting binary will not work on POWER3 or RS64 processors | |
96 | when compiled with binutils 2.15 or later. | |
97 | ||
5b7c3c91 BH |
98 | config 6xx |
99 | def_bool y | |
100 | depends on PPC32 && PPC_BOOK3S | |
7325927e | 101 | select PPC_HAVE_PMU_SUPPORT |
5b7c3c91 | 102 | |
a0ae9c7c AB |
103 | config POWER3 |
104 | bool | |
28794d34 | 105 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
106 | default y if !POWER4_ONLY |
107 | ||
108 | config POWER4 | |
28794d34 | 109 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
110 | def_bool y |
111 | ||
76b4eda8 BH |
112 | config PPC_A2 |
113 | bool | |
114 | depends on PPC_BOOK3E_64 | |
115 | ||
3164cccd AB |
116 | config TUNE_CELL |
117 | bool "Optimize for Cell Broadband Engine" | |
28794d34 | 118 | depends on PPC64 && PPC_BOOK3S |
3164cccd AB |
119 | help |
120 | Cause the compiler to optimize for the PPE of the Cell Broadband | |
121 | Engine. This will make the code run considerably faster on Cell | |
122 | but somewhat slower on other machines. This option only changes | |
123 | the scheduling of instructions, not the selection of instructions | |
124 | itself, so the resulting kernel will keep running on all other | |
125 | machines. When building a kernel that is supposed to run only | |
126 | on Cell, you should also select the POWER4_ONLY option. | |
127 | ||
a0ae9c7c AB |
128 | # this is temp to handle compat with arch=ppc |
129 | config 8xx | |
130 | bool | |
131 | ||
a0ae9c7c | 132 | config E500 |
39aef685 | 133 | select FSL_EMB_PERFMON |
4490c06b | 134 | select PPC_FSL_BOOK3E |
a0ae9c7c AB |
135 | bool |
136 | ||
3dfa8773 KG |
137 | config PPC_E500MC |
138 | bool "e500mc Support" | |
139 | select PPC_FPU | |
140 | depends on E500 | |
141 | ||
a0ae9c7c AB |
142 | config PPC_FPU |
143 | bool | |
144 | default y if PPC64 | |
145 | ||
5753c082 KG |
146 | config FSL_EMB_PERFMON |
147 | bool "Freescale Embedded Perfmon" | |
148 | depends on E500 || PPC_83xx | |
149 | help | |
150 | This is the Performance Monitor support found on the e500 core | |
151 | and some e300 cores (c3 and c4). Select this only if your | |
152 | core supports the Embedded Performance Monitor APU | |
153 | ||
a1110654 SW |
154 | config FSL_EMB_PERF_EVENT |
155 | bool | |
156 | depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS | |
157 | default y | |
158 | ||
159 | config FSL_EMB_PERF_EVENT_E500 | |
160 | bool | |
161 | depends on FSL_EMB_PERF_EVENT && E500 | |
162 | default y | |
163 | ||
a0ae9c7c AB |
164 | config 4xx |
165 | bool | |
166 | depends on 40x || 44x | |
167 | default y | |
168 | ||
169 | config BOOKE | |
170 | bool | |
2d27cfd3 | 171 | depends on E200 || E500 || 44x || PPC_BOOK3E |
a0ae9c7c AB |
172 | default y |
173 | ||
174 | config FSL_BOOKE | |
175 | bool | |
4490c06b | 176 | depends on (E200 || E500) && PPC32 |
a0ae9c7c AB |
177 | default y |
178 | ||
4490c06b KG |
179 | # this is for common code between PPC32 & PPC64 FSL BOOKE |
180 | config PPC_FSL_BOOK3E | |
181 | bool | |
182 | select FSL_EMB_PERFMON | |
1ece355b | 183 | select PPC_SMP_MUXED_IPI |
a475c8ec | 184 | select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 |
4490c06b | 185 | default y if FSL_BOOKE |
39aef685 | 186 | |
a0ae9c7c AB |
187 | config PTE_64BIT |
188 | bool | |
4ee7084e BB |
189 | depends on 44x || E500 || PPC_86xx |
190 | default y if PHYS_64BIT | |
a0ae9c7c AB |
191 | |
192 | config PHYS_64BIT | |
4ee7084e BB |
193 | bool 'Large physical address support' if E500 || PPC_86xx |
194 | depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx | |
a0ae9c7c AB |
195 | ---help--- |
196 | This option enables kernel support for larger than 32-bit physical | |
4ee7084e BB |
197 | addresses. This feature may not be available on all cores. |
198 | ||
199 | If you have more than 3.5GB of RAM or so, you also need to enable | |
200 | SWIOTLB under Kernel Options for this to work. The actual number | |
201 | is platform-dependent. | |
a0ae9c7c AB |
202 | |
203 | If in doubt, say N here. | |
204 | ||
205 | config ALTIVEC | |
206 | bool "AltiVec Support" | |
28794d34 | 207 | depends on 6xx || POWER4 |
a0ae9c7c AB |
208 | ---help--- |
209 | This option enables kernel support for the Altivec extensions to the | |
210 | PowerPC processor. The kernel currently supports saving and restoring | |
211 | altivec registers, and turning on the 'altivec enable' bit so user | |
212 | processes can execute altivec instructions. | |
213 | ||
214 | This option is only usefully if you have a processor that supports | |
215 | altivec (G4, otherwise known as 74xx series), but does not have | |
216 | any affect on a non-altivec cpu (it does, however add code to the | |
217 | kernel). | |
218 | ||
219 | If in doubt, say Y here. | |
220 | ||
96d5b52c MN |
221 | config VSX |
222 | bool "VSX Support" | |
223 | depends on POWER4 && ALTIVEC && PPC_FPU | |
224 | ---help--- | |
225 | ||
226 | This option enables kernel support for the Vector Scaler extensions | |
227 | to the PowerPC processor. The kernel currently supports saving and | |
228 | restoring VSX registers, and turning on the 'VSX enable' bit so user | |
229 | processes can execute VSX instructions. | |
230 | ||
231 | This option is only useful if you have a processor that supports | |
232 | VSX (P7 and above), but does not have any affect on a non-VSX | |
233 | CPUs (it does, however add code to the kernel). | |
234 | ||
235 | If in doubt, say Y here. | |
236 | ||
851d2e2f THFL |
237 | config PPC_ICSWX |
238 | bool "Support for PowerPC icswx coprocessor instruction" | |
fac26ad4 | 239 | depends on POWER4 || PPC_A2 |
851d2e2f THFL |
240 | default n |
241 | ---help--- | |
242 | ||
243 | This option enables kernel support for the PowerPC Initiate | |
244 | Coprocessor Store Word (icswx) coprocessor instruction on POWER7 | |
245 | or newer processors. | |
246 | ||
247 | This option is only useful if you have a processor that supports | |
248 | the icswx coprocessor instruction. It does not have any effect | |
249 | on processors without the icswx coprocessor instruction. | |
250 | ||
251 | This option slightly increases kernel memory usage. | |
252 | ||
253 | If in doubt, say N here. | |
254 | ||
9d670280 JX |
255 | config PPC_ICSWX_PID |
256 | bool "icswx requires direct PID management" | |
257 | depends on PPC_ICSWX && POWER4 | |
258 | default y | |
259 | ---help--- | |
c3dcf53a | 260 | The PID register in server is used explicitly for ICSWX. In |
9d670280 JX |
261 | embedded systems PID managment is done by the system. |
262 | ||
c3dcf53a JX |
263 | config PPC_ICSWX_USE_SIGILL |
264 | bool "Should a bad CT cause a SIGILL?" | |
265 | depends on PPC_ICSWX | |
266 | default n | |
267 | ---help--- | |
268 | Should a bad CT used for "non-record form ICSWX" cause an | |
269 | illegal intruction signal or should it be silent as | |
270 | architected. | |
271 | ||
272 | If in doubt, say N here. | |
273 | ||
a0ae9c7c AB |
274 | config SPE |
275 | bool "SPE Support" | |
3dfa8773 | 276 | depends on E200 || (E500 && !PPC_E500MC) |
a0ae9c7c AB |
277 | default y |
278 | ---help--- | |
279 | This option enables kernel support for the Signal Processing | |
280 | Extensions (SPE) to the PowerPC processor. The kernel currently | |
281 | supports saving and restoring SPE registers, and turning on the | |
282 | 'spe enable' bit so user processes can execute SPE instructions. | |
283 | ||
284 | This option is only useful if you have a processor that supports | |
285 | SPE (e500, otherwise known as 85xx series), but does not have any | |
286 | effect on a non-spe cpu (it does, however add code to the kernel). | |
287 | ||
288 | If in doubt, say Y here. | |
289 | ||
290 | config PPC_STD_MMU | |
5b7c3c91 BH |
291 | def_bool y |
292 | depends on PPC_BOOK3S | |
a0ae9c7c AB |
293 | |
294 | config PPC_STD_MMU_32 | |
295 | def_bool y | |
296 | depends on PPC_STD_MMU && PPC32 | |
297 | ||
5e696617 BH |
298 | config PPC_STD_MMU_64 |
299 | def_bool y | |
300 | depends on PPC_STD_MMU && PPC64 | |
301 | ||
302 | config PPC_MMU_NOHASH | |
303 | def_bool y | |
304 | depends on !PPC_STD_MMU | |
305 | ||
70fe3af8 KG |
306 | config PPC_BOOK3E_MMU |
307 | def_bool y | |
2d27cfd3 | 308 | depends on FSL_BOOKE || PPC_BOOK3E |
70fe3af8 | 309 | |
a0ae9c7c AB |
310 | config PPC_MM_SLICES |
311 | bool | |
a475c8ec | 312 | default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES) |
a0ae9c7c AB |
313 | default n |
314 | ||
315 | config VIRT_CPU_ACCOUNTING | |
316 | bool "Deterministic task and CPU time accounting" | |
317 | depends on PPC64 | |
318 | default y | |
319 | help | |
320 | Select this option to enable more accurate task and CPU time | |
321 | accounting. This is done by reading a CPU counter on each | |
322 | kernel entry and exit and on transitions within the kernel | |
323 | between system, softirq and hardirq state, so there is a | |
324 | small performance impact. This also enables accounting of | |
325 | stolen time on logically-partitioned systems running on | |
326 | IBM POWER5-based machines. | |
327 | ||
328 | If in doubt, say Y here. | |
329 | ||
105988c0 PM |
330 | config PPC_HAVE_PMU_SUPPORT |
331 | bool | |
332 | ||
333 | config PPC_PERF_CTRS | |
334 | def_bool y | |
cdd6c482 | 335 | depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT |
105988c0 | 336 | help |
cdd6c482 | 337 | This enables the powerpc-specific perf_event back-end. |
105988c0 | 338 | |
a0ae9c7c | 339 | config SMP |
e7f75ad0 | 340 | depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x |
a0ae9c7c AB |
341 | bool "Symmetric multi-processing support" |
342 | ---help--- | |
343 | This enables support for systems with more than one CPU. If you have | |
344 | a system with only one CPU, say N. If you have a system with more | |
345 | than one CPU, say Y. Note that the kernel does not currently | |
346 | support SMP machines with 603/603e/603ev or PPC750 ("G3") processors | |
347 | since they have inadequate hardware support for multiprocessor | |
348 | operation. | |
349 | ||
350 | If you say N here, the kernel will run on single and multiprocessor | |
351 | machines, but will use only one CPU of a multiprocessor machine. If | |
352 | you say Y here, the kernel will run on single-processor machines. | |
353 | On a single-processor machine, the kernel will run faster if you say | |
354 | N here. | |
355 | ||
356 | If you don't know what to do here, say N. | |
357 | ||
358 | config NR_CPUS | |
2d8ae638 MN |
359 | int "Maximum number of CPUs (2-8192)" |
360 | range 2 8192 | |
a0ae9c7c AB |
361 | depends on SMP |
362 | default "32" if PPC64 | |
363 | default "4" | |
364 | ||
365 | config NOT_COHERENT_CACHE | |
366 | bool | |
b91a143b | 367 | depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON |
e7f75ad0 | 368 | default n if PPC_47x |
a0ae9c7c AB |
369 | default y |
370 | ||
f8eb77d6 | 371 | config CHECK_CACHE_COHERENCY |
a0ae9c7c AB |
372 | bool |
373 | ||
374 | endmenu |