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Commit | Line | Data |
---|---|---|
c01ea72a | 1 | obj-$(CONFIG_PPC_CELL_NATIVE) += interrupt.o iommu.o setup.o \ |
014da7ff | 2 | cbe_regs.o spider-pic.o \ |
7cfb62a2 IK |
3 | pervasive.o pmu.o io-workarounds.o \ |
4 | spider-pci.o | |
c01ea72a | 5 | obj-$(CONFIG_CBE_RAS) += ras.o |
c902be71 | 6 | |
b3d7dc19 | 7 | obj-$(CONFIG_CBE_THERM) += cbe_thermal.o |
74889e41 CK |
8 | obj-$(CONFIG_CBE_CPUFREQ_PMI) += cbe_cpufreq_pmi.o |
9 | obj-$(CONFIG_CBE_CPUFREQ) += cbe-cpufreq.o | |
10 | cbe-cpufreq-y += cbe_cpufreq_pervasive.o cbe_cpufreq.o | |
b3d7dc19 | 11 | |
c01ea72a GL |
12 | ifeq ($(CONFIG_SMP),y) |
13 | obj-$(CONFIG_PPC_CELL_NATIVE) += smp.o | |
14 | endif | |
f0831acc | 15 | |
2dd14934 | 16 | # needed only when building loadable spufs.ko |
c01ea72a | 17 | spu-priv1-$(CONFIG_PPC_CELL_NATIVE) += spu_priv1_mmio.o |
2dd14934 | 18 | |
c9868fe0 IK |
19 | spu-manage-$(CONFIG_PPC_CELLEB) += spu_manage.o |
20 | spu-manage-$(CONFIG_PPC_CELL_NATIVE) += spu_manage.o | |
21 | ||
c01ea72a | 22 | obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \ |
aed3a8c9 | 23 | spu_notify.o \ |
7cd58e43 | 24 | spu_syscalls.o spu_fault.o \ |
c9868fe0 IK |
25 | $(spu-priv1-y) \ |
26 | $(spu-manage-y) \ | |
27 | spufs/ | |
ce21b3c9 ME |
28 | |
29 | obj-$(CONFIG_PCI_MSI) += axon_msi.o | |
6ec859e1 IK |
30 | |
31 | ||
32 | # celleb stuff | |
33 | ifeq ($(CONFIG_PPC_CELLEB),y) | |
116bdc42 | 34 | obj-y += celleb_setup.o \ |
11eef455 IK |
35 | celleb_pci.o celleb_scc_epci.o \ |
36 | celleb_scc_uhc.o \ | |
5a96dfe8 IK |
37 | io-workarounds.o spider-pci.o \ |
38 | beat_hvCall.o | |
11eef455 IK |
39 | |
40 | obj-$(CONFIG_SERIAL_TXX9) += celleb_scc_sio.o | |
6ec859e1 | 41 | endif |