[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / cell / axon_msi.c

/*
 * Copyright 2007, Michael Ellerman, IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */


#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/of_platform.h>
#include <linux/debugfs.h>

#include <asm/dcr.h>
#include <asm/machdep.h>
#include <asm/prom.h>


/*
 * MSIC registers, specified as offsets from dcr_base
 */
#define MSIC_CTRL_REG	0x0

/* Base Address registers specify FIFO location in BE memory */
#define MSIC_BASE_ADDR_HI_REG	0x3
#define MSIC_BASE_ADDR_LO_REG	0x4

/* Hold the read/write offsets into the FIFO */
#define MSIC_READ_OFFSET_REG	0x5
#define MSIC_WRITE_OFFSET_REG	0x6


/* MSIC control register flags */
#define MSIC_CTRL_ENABLE		0x0001
#define MSIC_CTRL_FIFO_FULL_ENABLE	0x0002
#define MSIC_CTRL_IRQ_ENABLE		0x0008
#define MSIC_CTRL_FULL_STOP_ENABLE	0x0010

/*
 * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
 * Currently we're using a 64KB FIFO size.
 */
#define MSIC_FIFO_SIZE_SHIFT	16
#define MSIC_FIFO_SIZE_BYTES	(1 << MSIC_FIFO_SIZE_SHIFT)

/*
 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
 * 8-9 of the MSIC control reg.
 */
#define MSIC_CTRL_FIFO_SIZE	(((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)

/*
 * We need to mask the read/write offsets to make sure they stay within
 * the bounds of the FIFO. Also they should always be 16-byte aligned.
 */
#define MSIC_FIFO_SIZE_MASK	((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)

/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
#define MSIC_FIFO_ENTRY_SIZE	0x10


struct axon_msic {
	struct irq_host *irq_host;
	__le32 *fifo_virt;
	dma_addr_t fifo_phys;
	dcr_host_t dcr_host;
	u32 read_offset;
#ifdef DEBUG
	u32 __iomem *trigger;
#endif
};

#ifdef DEBUG
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
#else
static inline void axon_msi_debug_setup(struct device_node *dn,
					struct axon_msic *msic) { }
#endif


static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{
	pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);

	dcr_write(msic->dcr_host, dcr_n, val);
}

static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct axon_msic *msic = get_irq_data(irq);
	u32 write_offset, msi;
	int idx;

	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
	pr_debug("axon_msi: original write_offset 0x%x\n", write_offset);

	/* write_offset doesn't wrap properly, so we have to mask it */
	write_offset &= MSIC_FIFO_SIZE_MASK;

	while (msic->read_offset != write_offset) {
		idx  = msic->read_offset / sizeof(__le32);
		msi  = le32_to_cpu(msic->fifo_virt[idx]);
		msi &= 0xFFFF;

		pr_debug("axon_msi: woff %x roff %x msi %x\n",
			  write_offset, msic->read_offset, msi);

		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
		msic->read_offset &= MSIC_FIFO_SIZE_MASK;

		if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host)
			generic_handle_irq(msi);
		else
			pr_debug("axon_msi: invalid irq 0x%x!\n", msi);
	}

	desc->chip->eoi(irq);
}

static struct axon_msic *find_msi_translator(struct pci_dev *dev)
{
	struct irq_host *irq_host;
	struct device_node *dn, *tmp;
	const phandle *ph;
	struct axon_msic *msic = NULL;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return NULL;
	}

	for (; dn; dn = of_get_next_parent(dn)) {
		ph = of_get_property(dn, "msi-translator", NULL);
		if (ph)
			break;
	}

	if (!ph) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-translator property found\n");
		goto out_error;
	}

	tmp = dn;
	dn = of_find_node_by_phandle(*ph);
	of_node_put(tmp);
	if (!dn) {
		dev_dbg(&dev->dev,
			"axon_msi: msi-translator doesn't point to a node\n");
		goto out_error;
	}

	irq_host = irq_find_host(dn);
	if (!irq_host) {
		dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
			dn->full_name);
		goto out_error;
	}

	msic = irq_host->host_data;

out_error:
	of_node_put(dn);

	return msic;
}

static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
	if (!find_msi_translator(dev))
		return -ENODEV;

	return 0;
}

static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
{
	struct device_node *dn;
	struct msi_desc *entry;
	int len;
	const u32 *prop;

	dn = of_node_get(pci_device_to_OF_node(dev));
	if (!dn) {
		dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
		return -ENODEV;
	}

	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);

	for (; dn; dn = of_get_next_parent(dn)) {
		if (entry->msi_attrib.is_64) {
			prop = of_get_property(dn, "msi-address-64", &len);
			if (prop)
				break;
		}

		prop = of_get_property(dn, "msi-address-32", &len);
		if (prop)
			break;
	}

	if (!prop) {
		dev_dbg(&dev->dev,
			"axon_msi: no msi-address-(32|64) properties found\n");
		return -ENOENT;
	}

	switch (len) {
	case 8:
		msg->address_hi = prop[0];
		msg->address_lo = prop[1];
		break;
	case 4:
		msg->address_hi = 0;
		msg->address_lo = prop[0];
		break;
	default:
		dev_dbg(&dev->dev,
			"axon_msi: malformed msi-address-(32|64) property\n");
		of_node_put(dn);
		return -EINVAL;
	}

	of_node_put(dn);

	return 0;
}

static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	unsigned int virq, rc;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct axon_msic *msic;

	msic = find_msi_translator(dev);
	if (!msic)
		return -ENODEV;

	rc = setup_msi_msg_address(dev, &msg);
	if (rc)
		return rc;

	/* We rely on being able to stash a virq in a u16 */
	BUILD_BUG_ON(NR_IRQS > 65536);

	list_for_each_entry(entry, &dev->msi_list, list) {
		virq = irq_create_direct_mapping(msic->irq_host);
		if (virq == NO_IRQ) {
			dev_warn(&dev->dev,
				 "axon_msi: virq allocation failed!\n");
			return -1;
		}
		dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);

		set_irq_msi(virq, entry);
		msg.data = virq;
		write_msi_msg(virq, &msg);
	}

	return 0;
}

static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *entry;

	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");

	list_for_each_entry(entry, &dev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;

		set_irq_msi(entry->irq, NULL);
		irq_dispose_mapping(entry->irq);
	}
}

static struct irq_chip msic_irq_chip = {
	.mask		= mask_msi_irq,
	.unmask		= unmask_msi_irq,
	.shutdown	= unmask_msi_irq,
	.typename	= "AXON-MSI",
};

static int msic_host_map(struct irq_host *h, unsigned int virq,
			 irq_hw_number_t hw)
{
	set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);

	return 0;
}

static struct irq_host_ops msic_host_ops = {
	.map	= msic_host_map,
};

static int axon_msi_shutdown(struct of_device *device)
{
	struct axon_msic *msic = device->dev.platform_data;
	u32 tmp;

	pr_debug("axon_msi: disabling %s\n",
		  msic->irq_host->of_node->full_name);
	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);

	return 0;
}

static int axon_msi_probe(struct of_device *device,
			  const struct of_device_id *device_id)
{
	struct device_node *dn = device->node;
	struct axon_msic *msic;
	unsigned int virq;
	int dcr_base, dcr_len;

	pr_debug("axon_msi: setting up dn %s\n", dn->full_name);

	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	if (!msic) {
		printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
		       dn->full_name);
		goto out;
	}

	dcr_base = dcr_resource_start(dn, 0);
	dcr_len = dcr_resource_len(dn, 0);

	if (dcr_base == 0 || dcr_len == 0) {
		printk(KERN_ERR
		       "axon_msi: couldn't parse dcr properties on %s\n",
			dn->full_name);
		goto out;
	}

	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
	if (!DCR_MAP_OK(msic->dcr_host)) {
		printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
					     &msic->fifo_phys, GFP_KERNEL);
	if (!msic->fifo_virt) {
		printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
		       dn->full_name);
		goto out_free_msic;
	}

	virq = irq_of_parse_and_map(dn, 0);
	if (virq == NO_IRQ) {
		printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}

	msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
					NR_IRQS, &msic_host_ops, 0);
	if (!msic->irq_host) {
		printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
		       dn->full_name);
		goto out_free_fifo;
	}

	msic->irq_host->host_data = msic;

	set_irq_data(virq, msic);
	set_irq_chained_handler(virq, axon_msi_cascade);
	pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq);

	/* Enable the MSIC hardware */
	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
				  msic->fifo_phys & 0xFFFFFFFF);
	msic_dcr_write(msic, MSIC_CTRL_REG,
			MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
			MSIC_CTRL_FIFO_SIZE);

	device->dev.platform_data = msic;

	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	ppc_md.msi_check_device = axon_msi_check_device;

	axon_msi_debug_setup(dn, msic);

	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);

	return 0;

out_free_fifo:
	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
			  msic->fifo_phys);
out_free_msic:
	kfree(msic);
out:

	return -1;
}

static const struct of_device_id axon_msi_device_id[] = {
	{
		.compatible	= "ibm,axon-msic"
	},
	{}
};

static struct of_platform_driver axon_msi_driver = {
	.match_table	= axon_msi_device_id,
	.probe		= axon_msi_probe,
	.shutdown	= axon_msi_shutdown,
	.driver		= {
		.name	= "axon-msi"
	},
};

static int __init axon_msi_init(void)
{
	return of_register_platform_driver(&axon_msi_driver);
}
subsys_initcall(axon_msi_init);


#ifdef DEBUG
static int msic_set(void *data, u64 val)
{
	struct axon_msic *msic = data;
	out_le32(msic->trigger, val);
	return 0;
}

static int msic_get(void *data, u64 *val)
{
	*val = 0;
	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");

void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
{
	char name[8];
	u64 addr;

	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	if (addr == OF_BAD_ADDR) {
		pr_debug("axon_msi: couldn't translate reg property\n");
		return;
	}

	msic->trigger = ioremap(addr, 0x4);
	if (!msic->trigger) {
		pr_debug("axon_msi: ioremap failed\n");
		return;
	}

	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));

	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
				 msic, &fops_msic)) {
		pr_debug("axon_msi: debugfs_create_file failed!\n");
		return;
	}
}
#endif /* DEBUG */
Commit	Line	Data
ce21b3c9 ME	1	/*
	2	* Copyright 2007, Michael Ellerman, IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/irq.h>
	13	#include <linux/kernel.h>
	14	#include <linux/pci.h>
	15	#include <linux/msi.h>
e4347dfb	16	#include <linux/of_platform.h>
72cac213	17	#include <linux/debugfs.h>
ce21b3c9 ME	18
	19	#include <asm/dcr.h>
	20	#include <asm/machdep.h>
	21	#include <asm/prom.h>
	22
	23
	24	/*
	25	* MSIC registers, specified as offsets from dcr_base
	26	*/
	27	#define MSIC_CTRL_REG 0x0
	28
	29	/* Base Address registers specify FIFO location in BE memory */
	30	#define MSIC_BASE_ADDR_HI_REG 0x3
	31	#define MSIC_BASE_ADDR_LO_REG 0x4
	32
	33	/* Hold the read/write offsets into the FIFO */
	34	#define MSIC_READ_OFFSET_REG 0x5
	35	#define MSIC_WRITE_OFFSET_REG 0x6
	36
	37
	38	/* MSIC control register flags */
	39	#define MSIC_CTRL_ENABLE 0x0001
	40	#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
	41	#define MSIC_CTRL_IRQ_ENABLE 0x0008
	42	#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
	43
	44	/*
	45	* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
	46	* Currently we're using a 64KB FIFO size.
	47	*/
	48	#define MSIC_FIFO_SIZE_SHIFT 16
	49	#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
	50
	51	/*
	52	* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
	53	* 8-9 of the MSIC control reg.
	54	*/
	55	#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
	56
	57	/*
	58	* We need to mask the read/write offsets to make sure they stay within
	59	* the bounds of the FIFO. Also they should always be 16-byte aligned.
	60	*/
	61	#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
	62
	63	/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
	64	#define MSIC_FIFO_ENTRY_SIZE 0x10
	65
	66
	67	struct axon_msic {
ce21b3c9	68	struct irq_host *irq_host;
de4c928b ME	69	__le32 *fifo_virt;
de4c928b ME	70	dma_addr_t fifo_phys;
ce21b3c9	71	dcr_host_t dcr_host;
ce21b3c9	72	u32 read_offset;
72cac213 ME	73	#ifdef DEBUG
	74	u32 __iomem *trigger;
	75	#endif
ce21b3c9 ME	76	};
ce21b3c9 ME	77
72cac213 ME	78	#ifdef DEBUG
	79	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic);
	80	#else
	81	static inline void axon_msi_debug_setup(struct device_node *dn,
	82	struct axon_msic *msic) { }
	83	#endif
	84
	85
ce21b3c9 ME	86	static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
	87	{
	88	pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
	89
83f34df4	90	dcr_write(msic->dcr_host, dcr_n, val);
ce21b3c9 ME	91	}
ce21b3c9 ME	92
ce21b3c9 ME	93	static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
	94	{
	95	struct axon_msic *msic = get_irq_data(irq);
	96	u32 write_offset, msi;
	97	int idx;
	98
2843e7f7	99	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
ce21b3c9 ME	100	pr_debug("axon_msi: original write_offset 0x%x\n", write_offset);
	101
	102	/* write_offset doesn't wrap properly, so we have to mask it */
	103	write_offset &= MSIC_FIFO_SIZE_MASK;
	104
	105	while (msic->read_offset != write_offset) {
	106	idx = msic->read_offset / sizeof(__le32);
de4c928b	107	msi = le32_to_cpu(msic->fifo_virt[idx]);
ce21b3c9 ME	108	msi &= 0xFFFF;
	109
	110	pr_debug("axon_msi: woff %x roff %x msi %x\n",
	111	write_offset, msic->read_offset, msi);
	112
	113	msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
	114	msic->read_offset &= MSIC_FIFO_SIZE_MASK;
	115
	116	if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host)
	117	generic_handle_irq(msi);
	118	else
	119	pr_debug("axon_msi: invalid irq 0x%x!\n", msi);
	120	}
	121
	122	desc->chip->eoi(irq);
	123	}
	124
	125	static struct axon_msic find_msi_translator(struct pci_dev dev)
	126	{
	127	struct irq_host *irq_host;
	128	struct device_node dn, tmp;
	129	const phandle *ph;
	130	struct axon_msic *msic = NULL;
	131
db220b23	132	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	133	if (!dn) {
	134	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	135	return NULL;
	136	}
	137
988479eb	138	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	139	ph = of_get_property(dn, "msi-translator", NULL);
	140	if (ph)
	141	break;
	142	}
	143
	144	if (!ph) {
	145	dev_dbg(&dev->dev,
	146	"axon_msi: no msi-translator property found\n");
	147	goto out_error;
	148	}
	149
	150	tmp = dn;
	151	dn = of_find_node_by_phandle(*ph);
c6d01179	152	of_node_put(tmp);
ce21b3c9 ME	153	if (!dn) {
	154	dev_dbg(&dev->dev,
	155	"axon_msi: msi-translator doesn't point to a node\n");
	156	goto out_error;
	157	}
	158
	159	irq_host = irq_find_host(dn);
	160	if (!irq_host) {
	161	dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
	162	dn->full_name);
	163	goto out_error;
	164	}
	165
	166	msic = irq_host->host_data;
	167
	168	out_error:
	169	of_node_put(dn);
ce21b3c9 ME	170
	171	return msic;
	172	}
	173
	174	static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
	175	{
	176	if (!find_msi_translator(dev))
	177	return -ENODEV;
	178
	179	return 0;
	180	}
	181
	182	static int setup_msi_msg_address(struct pci_dev dev, struct msi_msg msg)
	183	{
988479eb	184	struct device_node *dn;
ce21b3c9 ME	185	struct msi_desc *entry;
	186	int len;
	187	const u32 *prop;
	188
db220b23	189	dn = of_node_get(pci_device_to_OF_node(dev));
ce21b3c9 ME	190	if (!dn) {
	191	dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
	192	return -ENODEV;
	193	}
	194
	195	entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
	196
988479eb	197	for (; dn; dn = of_get_next_parent(dn)) {
ce21b3c9 ME	198	if (entry->msi_attrib.is_64) {
	199	prop = of_get_property(dn, "msi-address-64", &len);
	200	if (prop)
	201	break;
	202	}
	203
	204	prop = of_get_property(dn, "msi-address-32", &len);
	205	if (prop)
	206	break;
	207	}
	208
	209	if (!prop) {
	210	dev_dbg(&dev->dev,
	211	"axon_msi: no msi-address-(32\|64) properties found\n");
	212	return -ENOENT;
	213	}
	214
	215	switch (len) {
	216	case 8:
	217	msg->address_hi = prop[0];
	218	msg->address_lo = prop[1];
	219	break;
	220	case 4:
	221	msg->address_hi = 0;
	222	msg->address_lo = prop[0];
	223	break;
	224	default:
	225	dev_dbg(&dev->dev,
	226	"axon_msi: malformed msi-address-(32\|64) property\n");
	227	of_node_put(dn);
	228	return -EINVAL;
	229	}
	230
	231	of_node_put(dn);
	232
	233	return 0;
	234	}
	235
	236	static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	237	{
	238	unsigned int virq, rc;
	239	struct msi_desc *entry;
	240	struct msi_msg msg;
	241	struct axon_msic *msic;
	242
	243	msic = find_msi_translator(dev);
	244	if (!msic)
	245	return -ENODEV;
	246
	247	rc = setup_msi_msg_address(dev, &msg);
	248	if (rc)
	249	return rc;
	250
	251	/* We rely on being able to stash a virq in a u16 */
	252	BUILD_BUG_ON(NR_IRQS > 65536);
	253
	254	list_for_each_entry(entry, &dev->msi_list, list) {
	255	virq = irq_create_direct_mapping(msic->irq_host);
	256	if (virq == NO_IRQ) {
	257	dev_warn(&dev->dev,
	258	"axon_msi: virq allocation failed!\n");
	259	return -1;
	260	}
	261	dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
262
263	set_irq_msi(virq, entry);
264	msg.data = virq;
265	write_msi_msg(virq, &msg);
266	}
267
268	return 0;
269	}
270
271	static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
272	{
273	struct msi_desc *entry;
274
275	dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
276
277	list_for_each_entry(entry, &dev->msi_list, list) {
278	if (entry->irq == NO_IRQ)
279	continue;
280
281	set_irq_msi(entry->irq, NULL);
282	irq_dispose_mapping(entry->irq);
283	}
284	}
285
286	static struct irq_chip msic_irq_chip = {
287	.mask = mask_msi_irq,
288	.unmask = unmask_msi_irq,
289	.shutdown = unmask_msi_irq,
290	.typename = "AXON-MSI",
291	};
292
293	static int msic_host_map(struct irq_host *h, unsigned int virq,
294	irq_hw_number_t hw)
295	{
296	set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
297
298	return 0;
299	}
300
ce21b3c9	301	static struct irq_host_ops msic_host_ops = {
ce21b3c9 ME	302	.map = msic_host_map,
	303	};
	304
e4347dfb	305	static int axon_msi_shutdown(struct of_device *device)
ce21b3c9	306	{
e4347dfb	307	struct axon_msic *msic = device->dev.platform_data;
ce21b3c9 ME	308	u32 tmp;
ce21b3c9 ME	309
e4347dfb ME	310	pr_debug("axon_msi: disabling %s\n",
	311	msic->irq_host->of_node->full_name);
	312	tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
	313	tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
	314	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
ce21b3c9 ME	315
	316	return 0;
	317	}
	318
e4347dfb ME	319	static int axon_msi_probe(struct of_device *device,
e4347dfb ME	320	const struct of_device_id *device_id)
ce21b3c9	321	{
e4347dfb	322	struct device_node *dn = device->node;
ce21b3c9 ME	323	struct axon_msic *msic;
ce21b3c9 ME	324	unsigned int virq;
4acb8896	325	int dcr_base, dcr_len;
ce21b3c9 ME	326
	327	pr_debug("axon_msi: setting up dn %s\n", dn->full_name);
	328
	329	msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
	330	if (!msic) {
	331	printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
	332	dn->full_name);
	333	goto out;
	334	}
	335
4acb8896	336	dcr_base = dcr_resource_start(dn, 0);
ce21b3c9 ME	337	dcr_len = dcr_resource_len(dn, 0);
ce21b3c9 ME	338
4acb8896	339	if (dcr_base == 0 \|\| dcr_len == 0) {
ce21b3c9 ME	340	printk(KERN_ERR
	341	"axon_msi: couldn't parse dcr properties on %s\n",
	342	dn->full_name);
	343	goto out;
	344	}
	345
4acb8896	346	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
ce21b3c9 ME	347	if (!DCR_MAP_OK(msic->dcr_host)) {
	348	printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
	349	dn->full_name);
	350	goto out_free_msic;
	351	}
	352
de4c928b ME	353	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
	354	&msic->fifo_phys, GFP_KERNEL);
	355	if (!msic->fifo_virt) {
ce21b3c9 ME	356	printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
	357	dn->full_name);
	358	goto out_free_msic;
	359	}
	360
997526db ME	361	virq = irq_of_parse_and_map(dn, 0);
	362	if (virq == NO_IRQ) {
	363	printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
	364	dn->full_name);
	365	goto out_free_fifo;
	366	}
	367
19fc65b5	368	msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
52964f87	369	NR_IRQS, &msic_host_ops, 0);
ce21b3c9 ME	370	if (!msic->irq_host) {
	371	printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
	372	dn->full_name);
	373	goto out_free_fifo;
	374	}
	375
	376	msic->irq_host->host_data = msic;
	377
ce21b3c9 ME	378	set_irq_data(virq, msic);
	379	set_irq_chained_handler(virq, axon_msi_cascade);
	380	pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq);
	381
	382	/* Enable the MSIC hardware */
de4c928b	383	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
ce21b3c9	384	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
de4c928b	385	msic->fifo_phys & 0xFFFFFFFF);
ce21b3c9 ME	386	msic_dcr_write(msic, MSIC_CTRL_REG,
	387	MSIC_CTRL_IRQ_ENABLE \| MSIC_CTRL_ENABLE \|
	388	MSIC_CTRL_FIFO_SIZE);
	389
e4347dfb ME	390	device->dev.platform_data = msic;
	391
	392	ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
	393	ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
	394	ppc_md.msi_check_device = axon_msi_check_device;
ce21b3c9	395
72cac213 ME	396	axon_msi_debug_setup(dn, msic);
72cac213 ME	397
ce21b3c9 ME	398	printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
	399
	400	return 0;
	401
ce21b3c9	402	out_free_fifo:
de4c928b ME	403	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
de4c928b ME	404	msic->fifo_phys);
ce21b3c9 ME	405	out_free_msic:
	406	kfree(msic);
	407	out:
	408
	409	return -1;
	410	}
	411
e4347dfb ME	412	static const struct of_device_id axon_msi_device_id[] = {
	413	{
	414	.compatible = "ibm,axon-msic"
	415	},
	416	{}
	417	};
ce21b3c9	418
e4347dfb ME	419	static struct of_platform_driver axon_msi_driver = {
	420	.match_table = axon_msi_device_id,
	421	.probe = axon_msi_probe,
	422	.shutdown = axon_msi_shutdown,
	423	.driver = {
	424	.name = "axon-msi"
	425	},
	426	};
ce21b3c9	427
e4347dfb ME	428	static int __init axon_msi_init(void)
	429	{
	430	return of_register_platform_driver(&axon_msi_driver);
ce21b3c9	431	}
e4347dfb	432	subsys_initcall(axon_msi_init);
72cac213 ME	433
	434
	435	#ifdef DEBUG
	436	static int msic_set(void *data, u64 val)
	437	{
	438	struct axon_msic *msic = data;
	439	out_le32(msic->trigger, val);
	440	return 0;
	441	}
	442
	443	static int msic_get(void data, u64 val)
	444	{
	445	*val = 0;
	446	return 0;
	447	}
	448
	449	DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
	450
	451	void axon_msi_debug_setup(struct device_node dn, struct axon_msic msic)
	452	{
	453	char name[8];
	454	u64 addr;
	455
	456	addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
	457	if (addr == OF_BAD_ADDR) {
	458	pr_debug("axon_msi: couldn't translate reg property\n");
	459	return;
	460	}
	461
	462	msic->trigger = ioremap(addr, 0x4);
	463	if (!msic->trigger) {
	464	pr_debug("axon_msi: ioremap failed\n");
	465	return;
	466	}
	467
	468	snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
	469
	470	if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
	471	msic, &fops_msic)) {
	472	pr_debug("axon_msi: debugfs_create_file failed!\n");
	473	return;
	474	}
	475	}
	476	#endif /* DEBUG */