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Commit | Line | Data |
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fef1c772 | 1 | /* |
f3f66f59 | 2 | * linux/arch/powerpc/platforms/cell/cell_setup.c |
fef1c772 AB |
3 | * |
4 | * Copyright (C) 1995 Linus Torvalds | |
5 | * Adapted from 'alpha' version by Gary Thomas | |
6 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
7 | * Modified by PPC64 Team, IBM Corp | |
f3f66f59 | 8 | * Modified by Cell Team, IBM Deutschland Entwicklung GmbH |
fef1c772 AB |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | #undef DEBUG | |
16 | ||
fef1c772 AB |
17 | #include <linux/sched.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/stddef.h> | |
66b15db6 | 21 | #include <linux/export.h> |
fef1c772 | 22 | #include <linux/unistd.h> |
fef1c772 AB |
23 | #include <linux/user.h> |
24 | #include <linux/reboot.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/seq_file.h> | |
29 | #include <linux/root_dev.h> | |
30 | #include <linux/console.h> | |
bed120c6 JS |
31 | #include <linux/mutex.h> |
32 | #include <linux/memory_hotplug.h> | |
d8caf74f | 33 | #include <linux/of_platform.h> |
fef1c772 AB |
34 | |
35 | #include <asm/mmu.h> | |
36 | #include <asm/processor.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/prom.h> | |
40 | #include <asm/rtas.h> | |
41 | #include <asm/pci-bridge.h> | |
42 | #include <asm/iommu.h> | |
43 | #include <asm/dma.h> | |
44 | #include <asm/machdep.h> | |
45 | #include <asm/time.h> | |
46 | #include <asm/nvram.h> | |
47 | #include <asm/cputable.h> | |
d387899f | 48 | #include <asm/ppc-pci.h> |
40ef8cbc | 49 | #include <asm/irq.h> |
bed120c6 | 50 | #include <asm/spu.h> |
540270d8 | 51 | #include <asm/spu_priv1.h> |
609c9991 | 52 | #include <asm/udbg.h> |
21fb5a1d | 53 | #include <asm/mpic.h> |
eef686a0 | 54 | #include <asm/cell-regs.h> |
3cc30d07 | 55 | #include <asm/io-workarounds.h> |
fef1c772 | 56 | |
9c1368fc | 57 | #include "cell.h" |
f3f66f59 | 58 | #include "interrupt.h" |
c902be71 | 59 | #include "pervasive.h" |
acf7d768 | 60 | #include "ras.h" |
fef1c772 AB |
61 | |
62 | #ifdef DEBUG | |
63 | #define DBG(fmt...) udbg_printf(fmt) | |
64 | #else | |
65 | #define DBG(fmt...) | |
66 | #endif | |
67 | ||
8fce10a3 | 68 | static void cell_show_cpuinfo(struct seq_file *m) |
fef1c772 AB |
69 | { |
70 | struct device_node *root; | |
71 | const char *model = ""; | |
72 | ||
73 | root = of_find_node_by_path("/"); | |
74 | if (root) | |
e2eb6392 | 75 | model = of_get_property(root, "model", NULL); |
f3f66f59 | 76 | seq_printf(m, "machine\t\t: CHRP %s\n", model); |
fef1c772 AB |
77 | of_node_put(root); |
78 | } | |
79 | ||
f3f66f59 | 80 | static void cell_progress(char *s, unsigned short hex) |
fef1c772 AB |
81 | { |
82 | printk("*** %04x : %s\n", hex, s ? s : ""); | |
83 | } | |
84 | ||
ebf3a650 ME |
85 | static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev) |
86 | { | |
87 | struct pci_controller *hose; | |
88 | const char *s; | |
89 | int i; | |
90 | ||
91 | if (!machine_is(cell)) | |
92 | return; | |
93 | ||
94 | /* We're searching for a direct child of the PHB */ | |
95 | if (dev->bus->self != NULL || dev->devfn != 0) | |
96 | return; | |
97 | ||
98 | hose = pci_bus_to_host(dev->bus); | |
99 | if (hose == NULL) | |
100 | return; | |
101 | ||
102 | /* Only on PCIE */ | |
103 | if (!of_device_is_compatible(hose->dn, "pciex")) | |
104 | return; | |
105 | ||
106 | /* And only on axon */ | |
107 | s = of_get_property(hose->dn, "model", NULL); | |
108 | if (!s || strcmp(s, "Axon") != 0) | |
109 | return; | |
110 | ||
111 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { | |
112 | dev->resource[i].start = dev->resource[i].end = 0; | |
113 | dev->resource[i].flags = 0; | |
114 | } | |
115 | ||
116 | printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n", | |
117 | pci_name(dev)); | |
118 | } | |
119 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex); | |
120 | ||
cad5cef6 | 121 | static int cell_setup_phb(struct pci_controller *phb) |
7cfb62a2 IK |
122 | { |
123 | const char *model; | |
124 | struct device_node *np; | |
125 | ||
126 | int rc = rtas_setup_phb(phb); | |
127 | if (rc) | |
128 | return rc; | |
129 | ||
130 | np = phb->dn; | |
131 | model = of_get_property(np, "model", NULL); | |
132 | if (model == NULL || strcmp(np->name, "pci")) | |
133 | return 0; | |
134 | ||
9c1368fc DA |
135 | phb->controller_ops = cell_pci_controller_ops; |
136 | ||
7cfb62a2 IK |
137 | /* Setup workarounds for spider */ |
138 | if (strcmp(model, "Spider")) | |
139 | return 0; | |
140 | ||
141 | iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init, | |
142 | (void *)SPIDER_PCI_REG_BASE); | |
7cfb62a2 IK |
143 | return 0; |
144 | } | |
145 | ||
059378e3 | 146 | static const struct of_device_id cell_bus_ids[] __initconst = { |
c0dd394c JB |
147 | { .type = "soc", }, |
148 | { .compatible = "soc", }, | |
149 | { .type = "spider", }, | |
150 | { .type = "axon", }, | |
151 | { .type = "plb5", }, | |
152 | { .type = "plb4", }, | |
153 | { .type = "opb", }, | |
154 | { .type = "ebc", }, | |
155 | {}, | |
156 | }; | |
157 | ||
96289b07 BH |
158 | static int __init cell_publish_devices(void) |
159 | { | |
7cfb62a2 IK |
160 | struct device_node *root = of_find_node_by_path("/"); |
161 | struct device_node *np; | |
d767efe3 BH |
162 | int node; |
163 | ||
86810878 | 164 | /* Publish OF platform devices for southbridge IOs */ |
c0dd394c | 165 | of_platform_bus_probe(NULL, cell_bus_ids, NULL); |
86810878 | 166 | |
7cfb62a2 IK |
167 | /* On spider based blades, we need to manually create the OF |
168 | * platform devices for the PCI host bridges | |
169 | */ | |
170 | for_each_child_of_node(root, np) { | |
171 | if (np->type == NULL || (strcmp(np->type, "pci") != 0 && | |
172 | strcmp(np->type, "pciex") != 0)) | |
173 | continue; | |
174 | of_platform_device_create(np, NULL, NULL); | |
175 | } | |
176 | ||
d767efe3 BH |
177 | /* There is no device for the MIC memory controller, thus we create |
178 | * a platform device for it to attach the EDAC driver to. | |
179 | */ | |
180 | for_each_online_node(node) { | |
181 | if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL) | |
182 | continue; | |
183 | platform_device_register_simple("cbe-mic", node, NULL, 0); | |
184 | } | |
7cfb62a2 | 185 | |
96289b07 BH |
186 | return 0; |
187 | } | |
bb125fb0 | 188 | machine_subsys_initcall(cell, cell_publish_devices); |
96289b07 | 189 | |
21fb5a1d BH |
190 | static void __init mpic_init_IRQ(void) |
191 | { | |
192 | struct device_node *dn; | |
193 | struct mpic *mpic; | |
21fb5a1d BH |
194 | |
195 | for (dn = NULL; | |
196 | (dn = of_find_node_by_name(dn, "interrupt-controller"));) { | |
55b61fec | 197 | if (!of_device_is_compatible(dn, "CBEA,platform-open-pic")) |
21fb5a1d BH |
198 | continue; |
199 | ||
200 | /* The MPIC driver will get everything it needs from the | |
201 | * device-tree, just pass 0 to all arguments | |
202 | */ | |
e55d7f73 KM |
203 | mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET, |
204 | 0, 0, " MPIC "); | |
21fb5a1d BH |
205 | if (mpic == NULL) |
206 | continue; | |
207 | mpic_init(mpic); | |
21fb5a1d BH |
208 | } |
209 | } | |
210 | ||
211 | ||
b9e5b4e6 BH |
212 | static void __init cell_init_irq(void) |
213 | { | |
214 | iic_init_IRQ(); | |
215 | spider_init_IRQ(); | |
21fb5a1d | 216 | mpic_init_IRQ(); |
b9e5b4e6 BH |
217 | } |
218 | ||
f3c1ed97 JO |
219 | static void __init cell_set_dabrx(void) |
220 | { | |
221 | mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); | |
222 | } | |
223 | ||
f3f66f59 | 224 | static void __init cell_setup_arch(void) |
fef1c772 | 225 | { |
540270d8 | 226 | #ifdef CONFIG_SPU_BASE |
e28b0031 GL |
227 | spu_priv1_ops = &spu_priv1_mmio_ops; |
228 | spu_management_ops = &spu_management_of_ops; | |
540270d8 | 229 | #endif |
cebf589c | 230 | |
acf7d768 BH |
231 | cbe_regs_init(); |
232 | ||
f3c1ed97 JO |
233 | cell_set_dabrx(); |
234 | ||
acf7d768 BH |
235 | #ifdef CONFIG_CBE_RAS |
236 | cbe_ras_init(); | |
237 | #endif | |
238 | ||
fef1c772 | 239 | #ifdef CONFIG_SMP |
f3f66f59 | 240 | smp_init_cell(); |
fef1c772 | 241 | #endif |
fef1c772 AB |
242 | /* init to some ~sane value until calibrate_delay() runs */ |
243 | loops_per_jiffy = 50000000; | |
244 | ||
fef1c772 AB |
245 | /* Find and initialize PCI host bridges */ |
246 | init_pci_config_tokens(); | |
7cfb62a2 | 247 | |
acf7d768 | 248 | cbe_pervasive_init(); |
fef1c772 AB |
249 | #ifdef CONFIG_DUMMY_CONSOLE |
250 | conswitchp = &dummy_con; | |
251 | #endif | |
252 | ||
f3f66f59 | 253 | mmio_nvram_init(); |
fef1c772 AB |
254 | } |
255 | ||
e8222502 | 256 | static int __init cell_probe(void) |
fef1c772 | 257 | { |
e8222502 | 258 | unsigned long root = of_get_flat_dt_root(); |
fef1c772 | 259 | |
7d0daae4 ME |
260 | if (!of_flat_dt_is_compatible(root, "IBM,CBEA") && |
261 | !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0")) | |
262 | return 0; | |
263 | ||
264 | hpte_init_native(); | |
9178ba29 | 265 | pm_power_off = rtas_power_off; |
133dda1e | 266 | |
7d0daae4 | 267 | return 1; |
fef1c772 AB |
268 | } |
269 | ||
e8222502 BH |
270 | define_machine(cell) { |
271 | .name = "Cell", | |
f3f66f59 AB |
272 | .probe = cell_probe, |
273 | .setup_arch = cell_setup_arch, | |
f3f66f59 | 274 | .show_cpuinfo = cell_show_cpuinfo, |
fef1c772 | 275 | .restart = rtas_restart, |
fef1c772 AB |
276 | .halt = rtas_halt, |
277 | .get_boot_time = rtas_get_boot_time, | |
278 | .get_rtc_time = rtas_get_rtc_time, | |
279 | .set_rtc_time = rtas_set_rtc_time, | |
280 | .calibrate_decr = generic_calibrate_decr, | |
f3f66f59 | 281 | .progress = cell_progress, |
b9e5b4e6 | 282 | .init_IRQ = cell_init_irq, |
7cfb62a2 | 283 | .pci_setup_phb = cell_setup_phb, |
fef1c772 | 284 | }; |
9c1368fc DA |
285 | |
286 | struct pci_controller_ops cell_pci_controller_ops; |