[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / platforms / cell / spider-pic.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * External Interrupt Controller on Spider South Bridge
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/ioport.h>

#include <linux/pgtable.h>
#include <asm/prom.h>
#include <asm/io.h>

#include "interrupt.h"

/* register layout taken from Spider spec, table 7.4-4 */
enum {
	TIR_DEN		= 0x004, /* Detection Enable Register */
	TIR_MSK		= 0x084, /* Mask Level Register */
	TIR_EDC		= 0x0c0, /* Edge Detection Clear Register */
	TIR_PNDA	= 0x100, /* Pending Register A */
	TIR_PNDB	= 0x104, /* Pending Register B */
	TIR_CS		= 0x144, /* Current Status Register */
	TIR_LCSA	= 0x150, /* Level Current Status Register A */
	TIR_LCSB	= 0x154, /* Level Current Status Register B */
	TIR_LCSC	= 0x158, /* Level Current Status Register C */
	TIR_LCSD	= 0x15c, /* Level Current Status Register D */
	TIR_CFGA	= 0x200, /* Setting Register A0 */
	TIR_CFGB	= 0x204, /* Setting Register B0 */
			/* 0x208 ... 0x3ff Setting Register An/Bn */
	TIR_PPNDA	= 0x400, /* Packet Pending Register A */
	TIR_PPNDB	= 0x404, /* Packet Pending Register B */
	TIR_PIERA	= 0x408, /* Packet Output Error Register A */
	TIR_PIERB	= 0x40c, /* Packet Output Error Register B */
	TIR_PIEN	= 0x444, /* Packet Output Enable Register */
	TIR_PIPND	= 0x454, /* Packet Output Pending Register */
	TIRDID		= 0x484, /* Spider Device ID Register */
	REISTIM		= 0x500, /* Reissue Command Timeout Time Setting */
	REISTIMEN	= 0x504, /* Reissue Command Timeout Setting */
	REISWAITEN	= 0x508, /* Reissue Wait Control*/
};

#define SPIDER_CHIP_COUNT	4
#define SPIDER_SRC_COUNT	64
#define SPIDER_IRQ_INVALID	63

struct spider_pic {
	struct irq_domain		*host;
	void __iomem		*regs;
	unsigned int		node_id;
};
static struct spider_pic spider_pics[SPIDER_CHIP_COUNT];

static struct spider_pic *spider_irq_data_to_pic(struct irq_data *d)
{
	return irq_data_get_irq_chip_data(d);
}

static void __iomem *spider_get_irq_config(struct spider_pic *pic,
					   unsigned int src)
{
	return pic->regs + TIR_CFGA + 8 * src;
}

static void spider_unmask_irq(struct irq_data *d)
{
	struct spider_pic *pic = spider_irq_data_to_pic(d);
	void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));

	out_be32(cfg, in_be32(cfg) | 0x30000000u);
}

static void spider_mask_irq(struct irq_data *d)
{
	struct spider_pic *pic = spider_irq_data_to_pic(d);
	void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));

	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
}

static void spider_ack_irq(struct irq_data *d)
{
	struct spider_pic *pic = spider_irq_data_to_pic(d);
	unsigned int src = irqd_to_hwirq(d);

	/* Reset edge detection logic if necessary
	 */
	if (irqd_is_level_type(d))
		return;

	/* Only interrupts 47 to 50 can be set to edge */
	if (src < 47 || src > 50)
		return;

	/* Perform the clear of the edge logic */
	out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf));
}

static int spider_set_irq_type(struct irq_data *d, unsigned int type)
{
	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
	struct spider_pic *pic = spider_irq_data_to_pic(d);
	unsigned int hw = irqd_to_hwirq(d);
	void __iomem *cfg = spider_get_irq_config(pic, hw);
	u32 old_mask;
	u32 ic;

	/* Note that only level high is supported for most interrupts */
	if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH &&
	    (hw < 47 || hw > 50))
		return -EINVAL;

	/* Decode sense type */
	switch(sense) {
	case IRQ_TYPE_EDGE_RISING:
		ic = 0x3;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		ic = 0x2;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		ic = 0x0;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
	case IRQ_TYPE_NONE:
		ic = 0x1;
		break;
	default:
		return -EINVAL;
	}

	/* Configure the source. One gross hack that was there before and
	 * that I've kept around is the priority to the BE which I set to
	 * be the same as the interrupt source number. I don't know whether
	 * that's supposed to make any kind of sense however, we'll have to
	 * decide that, but for now, I'm not changing the behaviour.
	 */
	old_mask = in_be32(cfg) & 0x30000000u;
	out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) |
		 (pic->node_id << 4) | 0xe);
	out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff));

	return 0;
}

static struct irq_chip spider_pic = {
	.name = "SPIDER",
	.irq_unmask = spider_unmask_irq,
	.irq_mask = spider_mask_irq,
	.irq_ack = spider_ack_irq,
	.irq_set_type = spider_set_irq_type,
};

static int spider_host_map(struct irq_domain *h, unsigned int virq,
			irq_hw_number_t hw)
{
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq);

	/* Set default irq type */
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static int spider_host_xlate(struct irq_domain *h, struct device_node *ct,
			   const u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	/* Spider interrupts have 2 cells, first is the interrupt source,
	 * second, well, I don't know for sure yet ... We mask the top bits
	 * because old device-trees encode a node number in there
	 */
	*out_hwirq = intspec[0] & 0x3f;
	*out_flags = IRQ_TYPE_LEVEL_HIGH;
	return 0;
}

static const struct irq_domain_ops spider_host_ops = {
	.map = spider_host_map,
	.xlate = spider_host_xlate,
};

static void spider_irq_cascade(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct spider_pic *pic = irq_desc_get_handler_data(desc);
	unsigned int cs, virq;

	cs = in_be32(pic->regs + TIR_CS) >> 24;
	if (cs == SPIDER_IRQ_INVALID)
		virq = 0;
	else
		virq = irq_linear_revmap(pic->host, cs);

	if (virq)
		generic_handle_irq(virq);

	chip->irq_eoi(&desc->irq_data);
}

/* For hooking up the cascade we have a problem. Our device-tree is
 * crap and we don't know on which BE iic interrupt we are hooked on at
 * least not the "standard" way. We can reconstitute it based on two
 * informations though: which BE node we are connected to and whether
 * we are connected to IOIF0 or IOIF1. Right now, we really only care
 * about the IBM cell blade and we know that its firmware gives us an
 * interrupt-map property which is pretty strange.
 */
static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
{
	unsigned int virq;
	const u32 *imap, *tmp;
	int imaplen, intsize, unit;
	struct device_node *iic;
	struct device_node *of_node;

	of_node = irq_domain_get_of_node(pic->host);

	/* First, we check whether we have a real "interrupts" in the device
	 * tree in case the device-tree is ever fixed
	 */
	virq = irq_of_parse_and_map(of_node, 0);
	if (virq)
		return virq;

	/* Now do the horrible hacks */
	tmp = of_get_property(of_node, "#interrupt-cells", NULL);
	if (tmp == NULL)
		return 0;
	intsize = *tmp;
	imap = of_get_property(of_node, "interrupt-map", &imaplen);
	if (imap == NULL || imaplen < (intsize + 1))
		return 0;
	iic = of_find_node_by_phandle(imap[intsize]);
	if (iic == NULL)
		return 0;
	imap += intsize + 1;
	tmp = of_get_property(iic, "#interrupt-cells", NULL);
	if (tmp == NULL) {
		of_node_put(iic);
		return 0;
	}
	intsize = *tmp;
	/* Assume unit is last entry of interrupt specifier */
	unit = imap[intsize - 1];
	/* Ok, we have a unit, now let's try to get the node */
	tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL);
	if (tmp == NULL) {
		of_node_put(iic);
		return 0;
	}
	/* ugly as hell but works for now */
	pic->node_id = (*tmp) >> 1;
	of_node_put(iic);

	/* Ok, now let's get cracking. You may ask me why I just didn't match
	 * the iic host from the iic OF node, but that way I'm still compatible
	 * with really really old old firmwares for which we don't have a node
	 */
	/* Manufacture an IIC interrupt number of class 2 */
	virq = irq_create_mapping(NULL,
				  (pic->node_id << IIC_IRQ_NODE_SHIFT) |
				  (2 << IIC_IRQ_CLASS_SHIFT) |
				  unit);
	if (!virq)
		printk(KERN_ERR "spider_pic: failed to map cascade !");
	return virq;
}


static void __init spider_init_one(struct device_node *of_node, int chip,
				   unsigned long addr)
{
	struct spider_pic *pic = &spider_pics[chip];
	int i, virq;

	/* Map registers */
	pic->regs = ioremap(addr, 0x1000);
	if (pic->regs == NULL)
		panic("spider_pic: can't map registers !");

	/* Allocate a host */
	pic->host = irq_domain_add_linear(of_node, SPIDER_SRC_COUNT,
					  &spider_host_ops, pic);
	if (pic->host == NULL)
		panic("spider_pic: can't allocate irq host !");

	/* Go through all sources and disable them */
	for (i = 0; i < SPIDER_SRC_COUNT; i++) {
		void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i;
		out_be32(cfg, in_be32(cfg) & ~0x30000000u);
	}

	/* do not mask any interrupts because of level */
	out_be32(pic->regs + TIR_MSK, 0x0);

	/* enable interrupt packets to be output */
	out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1);

	/* Hook up the cascade interrupt to the iic and nodeid */
	virq = spider_find_cascade_and_node(pic);
	if (!virq)
		return;
	irq_set_handler_data(virq, pic);
	irq_set_chained_handler(virq, spider_irq_cascade);

	printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %pOF\n",
	       pic->node_id, addr, of_node);

	/* Enable the interrupt detection enable bit. Do this last! */
	out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1);
}

void __init spider_init_IRQ(void)
{
	struct resource r;
	struct device_node *dn;
	int chip = 0;

	/* XXX node numbers are totally bogus. We _hope_ we get the device
	 * nodes in the right order here but that's definitely not guaranteed,
	 * we need to get the node from the device tree instead.
	 * There is currently no proper property for it (but our whole
	 * device-tree is bogus anyway) so all we can do is pray or maybe test
	 * the address and deduce the node-id
	 */
	for_each_node_by_name(dn, "interrupt-controller") {
		if (of_device_is_compatible(dn, "CBEA,platform-spider-pic")) {
			if (of_address_to_resource(dn, 0, &r)) {
				printk(KERN_WARNING "spider-pic: Failed\n");
				continue;
			}
		} else if (of_device_is_compatible(dn, "sti,platform-spider-pic")
			   && (chip < 2)) {
			static long hard_coded_pics[] =
				{ 0x24000008000ul, 0x34000008000ul};
			r.start = hard_coded_pics[chip];
		} else
			continue;
		spider_init_one(dn, chip++, r.start);
	}
}
Commit	Line	Data
de6cc651	1	// SPDX-License-Identifier: GPL-2.0-or-later
cebf589c AB	2	/*
	3	* External Interrupt Controller on Spider South Bridge
	4	*
	5	* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
	6	*
	7	* Author: Arnd Bergmann <arndb@de.ibm.com>
cebf589c AB	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/irq.h>
0ebfff14	12	#include <linux/ioport.h>
cebf589c	13
ca5999fd	14	#include <linux/pgtable.h>
cebf589c AB	15	#include <asm/prom.h>
	16	#include <asm/io.h>
	17
f3f66f59	18	#include "interrupt.h"
cebf589c AB	19
	20	/* register layout taken from Spider spec, table 7.4-4 */
	21	enum {
	22	TIR_DEN = 0x004, /* Detection Enable Register */
	23	TIR_MSK = 0x084, /* Mask Level Register */
	24	TIR_EDC = 0x0c0, /* Edge Detection Clear Register */
	25	TIR_PNDA = 0x100, /* Pending Register A */
	26	TIR_PNDB = 0x104, /* Pending Register B */
	27	TIR_CS = 0x144, /* Current Status Register */
	28	TIR_LCSA = 0x150, /* Level Current Status Register A */
	29	TIR_LCSB = 0x154, /* Level Current Status Register B */
	30	TIR_LCSC = 0x158, /* Level Current Status Register C */
	31	TIR_LCSD = 0x15c, /* Level Current Status Register D */
	32	TIR_CFGA = 0x200, /* Setting Register A0 */
	33	TIR_CFGB = 0x204, /* Setting Register B0 */
	34	/* 0x208 ... 0x3ff Setting Register An/Bn */
	35	TIR_PPNDA = 0x400, /* Packet Pending Register A */
	36	TIR_PPNDB = 0x404, /* Packet Pending Register B */
	37	TIR_PIERA = 0x408, /* Packet Output Error Register A */
	38	TIR_PIERB = 0x40c, /* Packet Output Error Register B */
	39	TIR_PIEN = 0x444, /* Packet Output Enable Register */
	40	TIR_PIPND = 0x454, /* Packet Output Pending Register */
	41	TIRDID = 0x484, /* Spider Device ID Register */
	42	REISTIM = 0x500, /* Reissue Command Timeout Time Setting */
	43	REISTIMEN = 0x504, /* Reissue Command Timeout Setting */
	44	REISWAITEN = 0x508, /* Reissue Wait Control*/
	45	};
	46
0ebfff14 BH	47	#define SPIDER_CHIP_COUNT 4
	48	#define SPIDER_SRC_COUNT 64
	49	#define SPIDER_IRQ_INVALID 63
cebf589c	50
0ebfff14	51	struct spider_pic {
bae1d8f1	52	struct irq_domain *host;
0ebfff14 BH	53	void __iomem *regs;
	54	unsigned int node_id;
	55	};
	56	static struct spider_pic spider_pics[SPIDER_CHIP_COUNT];
cebf589c	57
6b0aea44	58	static struct spider_pic spider_irq_data_to_pic(struct irq_data d)
cebf589c	59	{
6b0aea44	60	return irq_data_get_irq_chip_data(d);
cebf589c AB	61	}
cebf589c AB	62
0ebfff14 BH	63	static void __iomem spider_get_irq_config(struct spider_pic pic,
0ebfff14 BH	64	unsigned int src)
cebf589c	65	{
0ebfff14	66	return pic->regs + TIR_CFGA + 8 * src;
cebf589c AB	67	}
cebf589c AB	68
d1ae63d4	69	static void spider_unmask_irq(struct irq_data *d)
cebf589c	70	{
6b0aea44	71	struct spider_pic *pic = spider_irq_data_to_pic(d);
476eb491	72	void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));
cebf589c	73
0ebfff14	74	out_be32(cfg, in_be32(cfg) \| 0x30000000u);
cebf589c AB	75	}
cebf589c AB	76
d1ae63d4	77	static void spider_mask_irq(struct irq_data *d)
cebf589c	78	{
6b0aea44	79	struct spider_pic *pic = spider_irq_data_to_pic(d);
476eb491	80	void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));
cebf589c AB	81
	82	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
	83	}
	84
d1ae63d4	85	static void spider_ack_irq(struct irq_data *d)
cebf589c	86	{
6b0aea44	87	struct spider_pic *pic = spider_irq_data_to_pic(d);
476eb491	88	unsigned int src = irqd_to_hwirq(d);
0ebfff14 BH	89
0ebfff14 BH	90	/* Reset edge detection logic if necessary
b9e5b4e6	91	*/
00e70bad	92	if (irqd_is_level_type(d))
0ebfff14 BH	93	return;
	94
	95	/* Only interrupts 47 to 50 can be set to edge */
	96	if (src < 47 \|\| src > 50)
	97	return;
	98
	99	/* Perform the clear of the edge logic */
	100	out_be32(pic->regs + TIR_EDC, 0x100 \| (src & 0xf));
cebf589c AB	101	}
cebf589c AB	102
d1ae63d4	103	static int spider_set_irq_type(struct irq_data *d, unsigned int type)
cebf589c	104	{
6e99e458	105	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
6b0aea44	106	struct spider_pic *pic = spider_irq_data_to_pic(d);
476eb491	107	unsigned int hw = irqd_to_hwirq(d);
0ebfff14	108	void __iomem *cfg = spider_get_irq_config(pic, hw);
6e99e458	109	u32 old_mask;
0ebfff14 BH	110	u32 ic;
	111
	112	/* Note that only level high is supported for most interrupts */
	113	if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH &&
	114	(hw < 47 \|\| hw > 50))
	115	return -EINVAL;
	116
	117	/* Decode sense type */
	118	switch(sense) {
	119	case IRQ_TYPE_EDGE_RISING:
	120	ic = 0x3;
	121	break;
	122	case IRQ_TYPE_EDGE_FALLING:
	123	ic = 0x2;
	124	break;
	125	case IRQ_TYPE_LEVEL_LOW:
	126	ic = 0x0;
0ebfff14 BH	127	break;
	128	case IRQ_TYPE_LEVEL_HIGH:
	129	case IRQ_TYPE_NONE:
	130	ic = 0x1;
0ebfff14 BH	131	break;
	132	default:
	133	return -EINVAL;
	134	}
cebf589c	135
0ebfff14 BH	136	/* Configure the source. One gross hack that was there before and
0ebfff14 BH	137	* that I've kept around is the priority to the BE which I set to
48fc7f7e	138	* be the same as the interrupt source number. I don't know whether
0ebfff14 BH	139	* that's supposed to make any kind of sense however, we'll have to
	140	* decide that, but for now, I'm not changing the behaviour.
	141	*/
6e99e458 BH	142	old_mask = in_be32(cfg) & 0x30000000u;
	143	out_be32(cfg, old_mask \| (ic << 24) \| (0x7 << 16) \|
	144	(pic->node_id << 4) \| 0xe);
0ebfff14	145	out_be32(cfg + 4, (0x2 << 16) \| (hw & 0xff));
cebf589c	146
6e99e458 BH	147	return 0;
	148	}
	149
	150	static struct irq_chip spider_pic = {
fc380c0c	151	.name = "SPIDER",
d1ae63d4 LB	152	.irq_unmask = spider_unmask_irq,
	153	.irq_mask = spider_mask_irq,
	154	.irq_ack = spider_ack_irq,
	155	.irq_set_type = spider_set_irq_type,
6e99e458 BH	156	};
6e99e458 BH	157
bae1d8f1	158	static int spider_host_map(struct irq_domain *h, unsigned int virq,
6e99e458 BH	159	irq_hw_number_t hw)
6e99e458 BH	160	{
6b0aea44	161	irq_set_chip_data(virq, h->host_data);
ec775d0e	162	irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq);
6e99e458 BH	163
6e99e458 BH	164	/* Set default irq type */
ec775d0e	165	irq_set_irq_type(virq, IRQ_TYPE_NONE);
6e99e458	166
0ebfff14 BH	167	return 0;
	168	}
	169
bae1d8f1	170	static int spider_host_xlate(struct irq_domain h, struct device_node ct,
40d50cf7	171	const u32 *intspec, unsigned int intsize,
0ebfff14 BH	172	irq_hw_number_t out_hwirq, unsigned int out_flags)
	173
	174	{
	175	/* Spider interrupts have 2 cells, first is the interrupt source,
	176	* second, well, I don't know for sure yet ... We mask the top bits
	177	* because old device-trees encode a node number in there
	178	*/
	179	*out_hwirq = intspec[0] & 0x3f;
	180	*out_flags = IRQ_TYPE_LEVEL_HIGH;
	181	return 0;
cebf589c	182	}
d0e57c68	183
9f70b8eb	184	static const struct irq_domain_ops spider_host_ops = {
0ebfff14 BH	185	.map = spider_host_map,
	186	.xlate = spider_host_xlate,
	187	};
	188
bd0b9ac4	189	static void spider_irq_cascade(struct irq_desc *desc)
b9e5b4e6	190	{
ec775d0e TG	191	struct irq_chip *chip = irq_desc_get_chip(desc);
ec775d0e TG	192	struct spider_pic *pic = irq_desc_get_handler_data(desc);
0ebfff14	193	unsigned int cs, virq;
b9e5b4e6	194
0ebfff14 BH	195	cs = in_be32(pic->regs + TIR_CS) >> 24;
0ebfff14 BH	196	if (cs == SPIDER_IRQ_INVALID)
ef24ba70	197	virq = 0;
0ebfff14 BH	198	else
0ebfff14 BH	199	virq = irq_linear_revmap(pic->host, cs);
d1ae63d4	200
ef24ba70	201	if (virq)
7d12e780	202	generic_handle_irq(virq);
d1ae63d4 LB	203
d1ae63d4 LB	204	chip->irq_eoi(&desc->irq_data);
b9e5b4e6 BH	205	}
b9e5b4e6 BH	206
027dfac6	207	/* For hooking up the cascade we have a problem. Our device-tree is
0ebfff14 BH	208	* crap and we don't know on which BE iic interrupt we are hooked on at
0ebfff14 BH	209	* least not the "standard" way. We can reconstitute it based on two
48fc7f7e	210	* informations though: which BE node we are connected to and whether
0ebfff14 BH	211	* we are connected to IOIF0 or IOIF1. Right now, we really only care
	212	* about the IBM cell blade and we know that its firmware gives us an
	213	* interrupt-map property which is pretty strange.
	214	*/
	215	static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
	216	{
	217	unsigned int virq;
c61c27d5	218	const u32 imap, tmp;
0ebfff14 BH	219	int imaplen, intsize, unit;
0ebfff14 BH	220	struct device_node *iic;
5d4c9bc7 MZ	221	struct device_node *of_node;
	222
	223	of_node = irq_domain_get_of_node(pic->host);
0ebfff14	224
48fc7f7e	225	/* First, we check whether we have a real "interrupts" in the device
0ebfff14 BH	226	* tree in case the device-tree is ever fixed
0ebfff14 BH	227	*/
5d4c9bc7	228	virq = irq_of_parse_and_map(of_node, 0);
f7578496 TR	229	if (virq)
f7578496 TR	230	return virq;
0ebfff14 BH	231
0ebfff14 BH	232	/* Now do the horrible hacks */
5d4c9bc7	233	tmp = of_get_property(of_node, "#interrupt-cells", NULL);
0ebfff14	234	if (tmp == NULL)
ef24ba70	235	return 0;
0ebfff14	236	intsize = *tmp;
5d4c9bc7	237	imap = of_get_property(of_node, "interrupt-map", &imaplen);
0ebfff14	238	if (imap == NULL \|\| imaplen < (intsize + 1))
ef24ba70	239	return 0;
0ebfff14 BH	240	iic = of_find_node_by_phandle(imap[intsize]);
0ebfff14 BH	241	if (iic == NULL)
ef24ba70	242	return 0;
0ebfff14	243	imap += intsize + 1;
e2eb6392	244	tmp = of_get_property(iic, "#interrupt-cells", NULL);
182f30e4 JL	245	if (tmp == NULL) {
182f30e4 JL	246	of_node_put(iic);
ef24ba70	247	return 0;
182f30e4	248	}
0ebfff14 BH	249	intsize = *tmp;
	250	/* Assume unit is last entry of interrupt specifier */
	251	unit = imap[intsize - 1];
	252	/* Ok, we have a unit, now let's try to get the node */
e2eb6392	253	tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL);
0ebfff14 BH	254	if (tmp == NULL) {
0ebfff14 BH	255	of_node_put(iic);
ef24ba70	256	return 0;
0ebfff14 BH	257	}
	258	/* ugly as hell but works for now */
	259	pic->node_id = (*tmp) >> 1;
	260	of_node_put(iic);
	261
	262	/* Ok, now let's get cracking. You may ask me why I just didn't match
	263	* the iic host from the iic OF node, but that way I'm still compatible
	264	* with really really old old firmwares for which we don't have a node
	265	*/
0ebfff14	266	/* Manufacture an IIC interrupt number of class 2 */
2e194583 BH	267	virq = irq_create_mapping(NULL,
	268	(pic->node_id << IIC_IRQ_NODE_SHIFT) \|
	269	(2 << IIC_IRQ_CLASS_SHIFT) \|
	270	unit);
ef24ba70	271	if (!virq)
0ebfff14 BH	272	printk(KERN_ERR "spider_pic: failed to map cascade !");
	273	return virq;
	274	}
	275
d0e57c68	276
0ebfff14 BH	277	static void __init spider_init_one(struct device_node *of_node, int chip,
0ebfff14 BH	278	unsigned long addr)
cebf589c	279	{
0ebfff14 BH	280	struct spider_pic *pic = &spider_pics[chip];
0ebfff14 BH	281	int i, virq;
b9e5b4e6	282
0ebfff14 BH	283	/* Map registers */
	284	pic->regs = ioremap(addr, 0x1000);
	285	if (pic->regs == NULL)
b9e5b4e6 BH	286	panic("spider_pic: can't map registers !");
b9e5b4e6 BH	287
0ebfff14	288	/* Allocate a host */
a8db8cf0 GL	289	pic->host = irq_domain_add_linear(of_node, SPIDER_SRC_COUNT,
a8db8cf0 GL	290	&spider_host_ops, pic);
0ebfff14 BH	291	if (pic->host == NULL)
0ebfff14 BH	292	panic("spider_pic: can't allocate irq host !");
b9e5b4e6	293
0ebfff14 BH	294	/* Go through all sources and disable them */
	295	for (i = 0; i < SPIDER_SRC_COUNT; i++) {
	296	void __iomem cfg = pic->regs + TIR_CFGA + 8 i;
	297	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
d0e57c68	298	}
b9e5b4e6 BH	299
b9e5b4e6 BH	300	/* do not mask any interrupts because of level */
0ebfff14	301	out_be32(pic->regs + TIR_MSK, 0x0);
b9e5b4e6 BH	302
b9e5b4e6 BH	303	/* enable interrupt packets to be output */
0ebfff14	304	out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) \| 0x1);
b9e5b4e6	305
0ebfff14 BH	306	/* Hook up the cascade interrupt to the iic and nodeid */
0ebfff14 BH	307	virq = spider_find_cascade_and_node(pic);
ef24ba70	308	if (!virq)
0ebfff14	309	return;
ec775d0e TG	310	irq_set_handler_data(virq, pic);
ec775d0e TG	311	irq_set_chained_handler(virq, spider_irq_cascade);
0ebfff14	312
b7c670d6 RH	313	printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %pOF\n",
b7c670d6 RH	314	pic->node_id, addr, of_node);
b9e5b4e6 BH	315
b9e5b4e6 BH	316	/* Enable the interrupt detection enable bit. Do this last! */
0ebfff14	317	out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) \| 0x1);
d0e57c68 JO	318	}
d0e57c68 JO	319
b9e5b4e6	320	void __init spider_init_IRQ(void)
d0e57c68	321	{
0ebfff14	322	struct resource r;
d0e57c68	323	struct device_node *dn;
0ebfff14 BH	324	int chip = 0;
	325
	326	/* XXX node numbers are totally bogus. We _hope_ we get the device
	327	* nodes in the right order here but that's definitely not guaranteed,
	328	* we need to get the node from the device tree instead.
	329	* There is currently no proper property for it (but our whole
	330	* device-tree is bogus anyway) so all we can do is pray or maybe test
	331	* the address and deduce the node-id
b9e5b4e6	332	*/
0aa8ff9b	333	for_each_node_by_name(dn, "interrupt-controller") {
55b61fec	334	if (of_device_is_compatible(dn, "CBEA,platform-spider-pic")) {
0ebfff14 BH	335	if (of_address_to_resource(dn, 0, &r)) {
	336	printk(KERN_WARNING "spider-pic: Failed\n");
	337	continue;
	338	}
55b61fec	339	} else if (of_device_is_compatible(dn, "sti,platform-spider-pic")
0ebfff14 BH	340	&& (chip < 2)) {
0ebfff14 BH	341	static long hard_coded_pics[] =
43b4f406	342	{ 0x24000008000ul, 0x34000008000ul};
0ebfff14	343	r.start = hard_coded_pics[chip];
d0e57c68 JO	344	} else
d0e57c68 JO	345	continue;
0ebfff14	346	spider_init_one(dn, chip++, r.start);
cebf589c AB	347	}
cebf589c AB	348	}