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67207b96 AB |
1 | /* |
2 | * Low-level SPU handling | |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * | |
6 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
3b3d22cb | 23 | #undef DEBUG |
67207b96 AB |
24 | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/module.h> | |
67207b96 AB |
28 | #include <linux/ptrace.h> |
29 | #include <linux/slab.h> | |
30 | #include <linux/wait.h> | |
e28b0031 GL |
31 | #include <linux/mm.h> |
32 | #include <linux/io.h> | |
14cc3e2b | 33 | #include <linux/mutex.h> |
bce94513 | 34 | #include <linux/linux_logo.h> |
f5a592f7 | 35 | #include <linux/syscore_ops.h> |
67207b96 | 36 | #include <asm/spu.h> |
540270d8 | 37 | #include <asm/spu_priv1.h> |
58bd403c | 38 | #include <asm/spu_csa.h> |
ff8a8f25 | 39 | #include <asm/xmon.h> |
3ad216ca | 40 | #include <asm/prom.h> |
158d5b5e | 41 | #include <asm/kexec.h> |
67207b96 | 42 | |
e28b0031 | 43 | const struct spu_management_ops *spu_management_ops; |
ccf17e9d JK |
44 | EXPORT_SYMBOL_GPL(spu_management_ops); |
45 | ||
540270d8 | 46 | const struct spu_priv1_ops *spu_priv1_ops; |
24140594 | 47 | EXPORT_SYMBOL_GPL(spu_priv1_ops); |
540270d8 | 48 | |
24140594 CH |
49 | struct cbe_spu_info cbe_spu_info[MAX_NUMNODES]; |
50 | EXPORT_SYMBOL_GPL(cbe_spu_info); | |
94b2a439 | 51 | |
3ce2f62b JK |
52 | /* |
53 | * The spufs fault-handling code needs to call force_sig_info to raise signals | |
54 | * on DMA errors. Export it here to avoid general kernel-wide access to this | |
55 | * function | |
56 | */ | |
57 | EXPORT_SYMBOL_GPL(force_sig_info); | |
58 | ||
24140594 CH |
59 | /* |
60 | * Protects cbe_spu_info and spu->number. | |
61 | */ | |
62 | static DEFINE_SPINLOCK(spu_lock); | |
63 | ||
64 | /* | |
65 | * List of all spus in the system. | |
66 | * | |
67 | * This list is iterated by callers from irq context and callers that | |
68 | * want to sleep. Thus modifications need to be done with both | |
69 | * spu_full_list_lock and spu_full_list_mutex held, while iterating | |
70 | * through it requires either of these locks. | |
71 | * | |
72 | * In addition spu_full_list_lock protects all assignmens to | |
73 | * spu->mm. | |
74 | */ | |
75 | static LIST_HEAD(spu_full_list); | |
76 | static DEFINE_SPINLOCK(spu_full_list_lock); | |
77 | static DEFINE_MUTEX(spu_full_list_mutex); | |
540270d8 | 78 | |
58bd403c JK |
79 | struct spu_slb { |
80 | u64 esid, vsid; | |
81 | }; | |
82 | ||
94b2a439 BH |
83 | void spu_invalidate_slbs(struct spu *spu) |
84 | { | |
85 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
c92a1acb | 86 | unsigned long flags; |
94b2a439 | 87 | |
c92a1acb | 88 | spin_lock_irqsave(&spu->register_lock, flags); |
94b2a439 BH |
89 | if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK) |
90 | out_be64(&priv2->slb_invalidate_all_W, 0UL); | |
c92a1acb | 91 | spin_unlock_irqrestore(&spu->register_lock, flags); |
94b2a439 BH |
92 | } |
93 | EXPORT_SYMBOL_GPL(spu_invalidate_slbs); | |
94 | ||
95 | /* This is called by the MM core when a segment size is changed, to | |
96 | * request a flush of all the SPEs using a given mm | |
97 | */ | |
98 | void spu_flush_all_slbs(struct mm_struct *mm) | |
99 | { | |
100 | struct spu *spu; | |
101 | unsigned long flags; | |
102 | ||
24140594 | 103 | spin_lock_irqsave(&spu_full_list_lock, flags); |
94b2a439 BH |
104 | list_for_each_entry(spu, &spu_full_list, full_list) { |
105 | if (spu->mm == mm) | |
106 | spu_invalidate_slbs(spu); | |
107 | } | |
24140594 | 108 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
94b2a439 BH |
109 | } |
110 | ||
111 | /* The hack below stinks... try to do something better one of | |
112 | * these days... Does it even work properly with NR_CPUS == 1 ? | |
113 | */ | |
114 | static inline void mm_needs_global_tlbie(struct mm_struct *mm) | |
115 | { | |
116 | int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1; | |
117 | ||
118 | /* Global TLBIE broadcast required with SPEs. */ | |
56aa4129 | 119 | bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr); |
94b2a439 BH |
120 | } |
121 | ||
122 | void spu_associate_mm(struct spu *spu, struct mm_struct *mm) | |
123 | { | |
124 | unsigned long flags; | |
125 | ||
24140594 | 126 | spin_lock_irqsave(&spu_full_list_lock, flags); |
94b2a439 | 127 | spu->mm = mm; |
24140594 | 128 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
94b2a439 BH |
129 | if (mm) |
130 | mm_needs_global_tlbie(mm); | |
131 | } | |
132 | EXPORT_SYMBOL_GPL(spu_associate_mm); | |
133 | ||
f6eb7d7f JK |
134 | int spu_64k_pages_available(void) |
135 | { | |
136 | return mmu_psize_defs[MMU_PAGE_64K].shift != 0; | |
137 | } | |
138 | EXPORT_SYMBOL_GPL(spu_64k_pages_available); | |
139 | ||
67207b96 AB |
140 | static void spu_restart_dma(struct spu *spu) |
141 | { | |
142 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
5473af04 | 143 | |
8837d921 | 144 | if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags)) |
5473af04 | 145 | out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); |
de102892 LB |
146 | else { |
147 | set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags); | |
148 | mb(); | |
149 | } | |
67207b96 AB |
150 | } |
151 | ||
58bd403c JK |
152 | static inline void spu_load_slb(struct spu *spu, int slbe, struct spu_slb *slb) |
153 | { | |
154 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
155 | ||
fe333321 | 156 | pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n", |
58bd403c JK |
157 | __func__, slbe, slb->vsid, slb->esid); |
158 | ||
159 | out_be64(&priv2->slb_index_W, slbe); | |
cc4b7c18 AB |
160 | /* set invalid before writing vsid */ |
161 | out_be64(&priv2->slb_esid_RW, 0); | |
162 | /* now it's safe to write the vsid */ | |
58bd403c | 163 | out_be64(&priv2->slb_vsid_RW, slb->vsid); |
cc4b7c18 | 164 | /* setting the new esid makes the entry valid again */ |
58bd403c JK |
165 | out_be64(&priv2->slb_esid_RW, slb->esid); |
166 | } | |
167 | ||
67207b96 AB |
168 | static int __spu_trap_data_seg(struct spu *spu, unsigned long ea) |
169 | { | |
8b3d6663 | 170 | struct mm_struct *mm = spu->mm; |
4d43466d | 171 | struct spu_slb slb; |
94b2a439 | 172 | int psize; |
67207b96 | 173 | |
e48b1b45 | 174 | pr_debug("%s\n", __func__); |
67207b96 | 175 | |
4d43466d | 176 | slb.esid = (ea & ESID_MASK) | SLB_ESID_V; |
0afacde3 AB |
177 | |
178 | switch(REGION_ID(ea)) { | |
179 | case USER_REGION_ID: | |
d0f13e3c BH |
180 | #ifdef CONFIG_PPC_MM_SLICES |
181 | psize = get_slice_psize(mm, ea); | |
182 | #else | |
183 | psize = mm->context.user_psize; | |
0afacde3 | 184 | #endif |
4d43466d JK |
185 | slb.vsid = (get_vsid(mm->context.id, ea, MMU_SEGSIZE_256M) |
186 | << SLB_VSID_SHIFT) | SLB_VSID_USER; | |
0afacde3 AB |
187 | break; |
188 | case VMALLOC_REGION_ID: | |
94b2a439 BH |
189 | if (ea < VMALLOC_END) |
190 | psize = mmu_vmalloc_psize; | |
191 | else | |
192 | psize = mmu_io_psize; | |
4d43466d JK |
193 | slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) |
194 | << SLB_VSID_SHIFT) | SLB_VSID_KERNEL; | |
0afacde3 AB |
195 | break; |
196 | case KERNEL_REGION_ID: | |
94b2a439 | 197 | psize = mmu_linear_psize; |
4d43466d JK |
198 | slb.vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) |
199 | << SLB_VSID_SHIFT) | SLB_VSID_KERNEL; | |
0afacde3 AB |
200 | break; |
201 | default: | |
8b3d6663 AB |
202 | /* Future: support kernel segments so that drivers |
203 | * can use SPUs. | |
204 | */ | |
67207b96 AB |
205 | pr_debug("invalid region access at %016lx\n", ea); |
206 | return 1; | |
207 | } | |
4d43466d | 208 | slb.vsid |= mmu_psize_defs[psize].sllp; |
67207b96 | 209 | |
4d43466d | 210 | spu_load_slb(spu, spu->slb_replace, &slb); |
8b3d6663 AB |
211 | |
212 | spu->slb_replace++; | |
67207b96 AB |
213 | if (spu->slb_replace >= 8) |
214 | spu->slb_replace = 0; | |
215 | ||
67207b96 | 216 | spu_restart_dma(spu); |
e9f8a0b6 | 217 | spu->stats.slb_flt++; |
67207b96 AB |
218 | return 0; |
219 | } | |
220 | ||
5473af04 | 221 | extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX |
8b3d6663 | 222 | static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr) |
67207b96 | 223 | { |
2c911a14 LB |
224 | int ret; |
225 | ||
fe333321 | 226 | pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea); |
67207b96 | 227 | |
2c911a14 LB |
228 | /* |
229 | * Handle kernel space hash faults immediately. User hash | |
230 | * faults need to be deferred to process context. | |
231 | */ | |
232 | if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) && | |
233 | (REGION_ID(ea) != USER_REGION_ID)) { | |
234 | ||
235 | spin_unlock(&spu->register_lock); | |
236 | ret = hash_page(ea, _PAGE_PRESENT, 0x300); | |
237 | spin_lock(&spu->register_lock); | |
238 | ||
239 | if (!ret) { | |
240 | spu_restart_dma(spu); | |
241 | return 0; | |
242 | } | |
5473af04 MN |
243 | } |
244 | ||
f3d69e05 LB |
245 | spu->class_1_dar = ea; |
246 | spu->class_1_dsisr = dsisr; | |
247 | ||
248 | spu->stop_callback(spu, 1); | |
d6ad39bc | 249 | |
f3d69e05 LB |
250 | spu->class_1_dar = 0; |
251 | spu->class_1_dsisr = 0; | |
d6ad39bc | 252 | |
67207b96 AB |
253 | return 0; |
254 | } | |
255 | ||
58bd403c JK |
256 | static void __spu_kernel_slb(void *addr, struct spu_slb *slb) |
257 | { | |
258 | unsigned long ea = (unsigned long)addr; | |
259 | u64 llp; | |
260 | ||
261 | if (REGION_ID(ea) == KERNEL_REGION_ID) | |
262 | llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
263 | else | |
264 | llp = mmu_psize_defs[mmu_virtual_psize].sllp; | |
265 | ||
266 | slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) | | |
267 | SLB_VSID_KERNEL | llp; | |
268 | slb->esid = (ea & ESID_MASK) | SLB_ESID_V; | |
269 | } | |
270 | ||
684bd614 JK |
271 | /** |
272 | * Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the | |
273 | * address @new_addr is present. | |
274 | */ | |
275 | static inline int __slb_present(struct spu_slb *slbs, int nr_slbs, | |
276 | void *new_addr) | |
277 | { | |
278 | unsigned long ea = (unsigned long)new_addr; | |
279 | int i; | |
280 | ||
281 | for (i = 0; i < nr_slbs; i++) | |
282 | if (!((slbs[i].esid ^ ea) & ESID_MASK)) | |
283 | return 1; | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
58bd403c JK |
288 | /** |
289 | * Setup the SPU kernel SLBs, in preparation for a context save/restore. We | |
290 | * need to map both the context save area, and the save/restore code. | |
684bd614 JK |
291 | * |
292 | * Because the lscsa and code may cross segment boundaires, we check to see | |
293 | * if mappings are required for the start and end of each range. We currently | |
294 | * assume that the mappings are smaller that one segment - if not, something | |
295 | * is seriously wrong. | |
58bd403c | 296 | */ |
684bd614 JK |
297 | void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa, |
298 | void *code, int code_size) | |
58bd403c | 299 | { |
684bd614 JK |
300 | struct spu_slb slbs[4]; |
301 | int i, nr_slbs = 0; | |
302 | /* start and end addresses of both mappings */ | |
303 | void *addrs[] = { | |
304 | lscsa, (void *)lscsa + sizeof(*lscsa) - 1, | |
305 | code, code + code_size - 1 | |
306 | }; | |
307 | ||
308 | /* check the set of addresses, and create a new entry in the slbs array | |
309 | * if there isn't already a SLB for that address */ | |
310 | for (i = 0; i < ARRAY_SIZE(addrs); i++) { | |
311 | if (__slb_present(slbs, nr_slbs, addrs[i])) | |
312 | continue; | |
313 | ||
314 | __spu_kernel_slb(addrs[i], &slbs[nr_slbs]); | |
315 | nr_slbs++; | |
316 | } | |
58bd403c | 317 | |
c92a1acb | 318 | spin_lock_irq(&spu->register_lock); |
684bd614 JK |
319 | /* Add the set of SLBs */ |
320 | for (i = 0; i < nr_slbs; i++) | |
321 | spu_load_slb(spu, i, &slbs[i]); | |
c92a1acb | 322 | spin_unlock_irq(&spu->register_lock); |
58bd403c JK |
323 | } |
324 | EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs); | |
325 | ||
67207b96 | 326 | static irqreturn_t |
f5a92458 | 327 | spu_irq_class_0(int irq, void *data) |
67207b96 AB |
328 | { |
329 | struct spu *spu; | |
b7f90a40 | 330 | unsigned long stat, mask; |
67207b96 AB |
331 | |
332 | spu = data; | |
b7f90a40 | 333 | |
d6ad39bc | 334 | spin_lock(&spu->register_lock); |
b7f90a40 | 335 | mask = spu_int_mask_get(spu, 0); |
d6ad39bc | 336 | stat = spu_int_stat_get(spu, 0) & mask; |
b7f90a40 | 337 | |
b7f90a40 | 338 | spu->class_0_pending |= stat; |
f3d69e05 | 339 | spu->class_0_dar = spu_mfc_dar_get(spu); |
f3d69e05 | 340 | spu->stop_callback(spu, 0); |
f3d69e05 | 341 | spu->class_0_pending = 0; |
f3d69e05 | 342 | spu->class_0_dar = 0; |
67207b96 | 343 | |
b7f90a40 | 344 | spu_int_stat_clear(spu, 0, stat); |
2c911a14 | 345 | spin_unlock(&spu->register_lock); |
b7f90a40 | 346 | |
67207b96 AB |
347 | return IRQ_HANDLED; |
348 | } | |
349 | ||
67207b96 | 350 | static irqreturn_t |
f5a92458 | 351 | spu_irq_class_1(int irq, void *data) |
67207b96 AB |
352 | { |
353 | struct spu *spu; | |
8b3d6663 | 354 | unsigned long stat, mask, dar, dsisr; |
67207b96 AB |
355 | |
356 | spu = data; | |
8b3d6663 AB |
357 | |
358 | /* atomically read & clear class1 status. */ | |
359 | spin_lock(&spu->register_lock); | |
f0831acc AB |
360 | mask = spu_int_mask_get(spu, 1); |
361 | stat = spu_int_stat_get(spu, 1) & mask; | |
362 | dar = spu_mfc_dar_get(spu); | |
363 | dsisr = spu_mfc_dsisr_get(spu); | |
8af30675 | 364 | if (stat & CLASS1_STORAGE_FAULT_INTR) |
f0831acc AB |
365 | spu_mfc_dsisr_set(spu, 0ul); |
366 | spu_int_stat_clear(spu, 1, stat); | |
67207b96 | 367 | |
e48b1b45 | 368 | pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat, |
c92a1acb AB |
369 | dar, dsisr); |
370 | ||
2c911a14 LB |
371 | if (stat & CLASS1_SEGMENT_FAULT_INTR) |
372 | __spu_trap_data_seg(spu, dar); | |
373 | ||
8af30675 | 374 | if (stat & CLASS1_STORAGE_FAULT_INTR) |
8b3d6663 | 375 | __spu_trap_data_map(spu, dar, dsisr); |
67207b96 | 376 | |
8af30675 | 377 | if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR) |
67207b96 AB |
378 | ; |
379 | ||
8af30675 | 380 | if (stat & CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR) |
67207b96 AB |
381 | ; |
382 | ||
f3d69e05 LB |
383 | spu->class_1_dsisr = 0; |
384 | spu->class_1_dar = 0; | |
385 | ||
2c911a14 LB |
386 | spin_unlock(&spu->register_lock); |
387 | ||
67207b96 AB |
388 | return stat ? IRQ_HANDLED : IRQ_NONE; |
389 | } | |
390 | ||
391 | static irqreturn_t | |
f5a92458 | 392 | spu_irq_class_2(int irq, void *data) |
67207b96 AB |
393 | { |
394 | struct spu *spu; | |
395 | unsigned long stat; | |
3a843d7c | 396 | unsigned long mask; |
8af30675 JK |
397 | const int mailbox_intrs = |
398 | CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR; | |
67207b96 AB |
399 | |
400 | spu = data; | |
ba723fe2 | 401 | spin_lock(&spu->register_lock); |
f0831acc AB |
402 | stat = spu_int_stat_get(spu, 2); |
403 | mask = spu_int_mask_get(spu, 2); | |
ba723fe2 MN |
404 | /* ignore interrupts we're not waiting for */ |
405 | stat &= mask; | |
8af30675 JK |
406 | /* mailbox interrupts are level triggered. mask them now before |
407 | * acknowledging */ | |
408 | if (stat & mailbox_intrs) | |
409 | spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs)); | |
ba723fe2 MN |
410 | /* acknowledge all interrupts before the callbacks */ |
411 | spu_int_stat_clear(spu, 2, stat); | |
67207b96 | 412 | |
3a843d7c | 413 | pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask); |
67207b96 | 414 | |
8af30675 | 415 | if (stat & CLASS2_MAILBOX_INTR) |
ba723fe2 | 416 | spu->ibox_callback(spu); |
67207b96 | 417 | |
8af30675 | 418 | if (stat & CLASS2_SPU_STOP_INTR) |
f3d69e05 | 419 | spu->stop_callback(spu, 2); |
67207b96 | 420 | |
8af30675 | 421 | if (stat & CLASS2_SPU_HALT_INTR) |
f3d69e05 | 422 | spu->stop_callback(spu, 2); |
67207b96 | 423 | |
8af30675 | 424 | if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR) |
ba723fe2 | 425 | spu->mfc_callback(spu); |
67207b96 | 426 | |
8af30675 | 427 | if (stat & CLASS2_MAILBOX_THRESHOLD_INTR) |
ba723fe2 | 428 | spu->wbox_callback(spu); |
67207b96 | 429 | |
e9f8a0b6 | 430 | spu->stats.class2_intr++; |
2c911a14 LB |
431 | |
432 | spin_unlock(&spu->register_lock); | |
433 | ||
67207b96 AB |
434 | return stat ? IRQ_HANDLED : IRQ_NONE; |
435 | } | |
436 | ||
0ebfff14 | 437 | static int spu_request_irqs(struct spu *spu) |
67207b96 | 438 | { |
0ebfff14 | 439 | int ret = 0; |
67207b96 | 440 | |
0ebfff14 BH |
441 | if (spu->irqs[0] != NO_IRQ) { |
442 | snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", | |
443 | spu->number); | |
444 | ret = request_irq(spu->irqs[0], spu_irq_class_0, | |
a3a9f3b4 | 445 | 0, spu->irq_c0, spu); |
0ebfff14 BH |
446 | if (ret) |
447 | goto bail0; | |
448 | } | |
449 | if (spu->irqs[1] != NO_IRQ) { | |
450 | snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", | |
451 | spu->number); | |
452 | ret = request_irq(spu->irqs[1], spu_irq_class_1, | |
a3a9f3b4 | 453 | 0, spu->irq_c1, spu); |
0ebfff14 BH |
454 | if (ret) |
455 | goto bail1; | |
456 | } | |
457 | if (spu->irqs[2] != NO_IRQ) { | |
458 | snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", | |
459 | spu->number); | |
460 | ret = request_irq(spu->irqs[2], spu_irq_class_2, | |
a3a9f3b4 | 461 | 0, spu->irq_c2, spu); |
0ebfff14 BH |
462 | if (ret) |
463 | goto bail2; | |
464 | } | |
465 | return 0; | |
67207b96 | 466 | |
0ebfff14 BH |
467 | bail2: |
468 | if (spu->irqs[1] != NO_IRQ) | |
469 | free_irq(spu->irqs[1], spu); | |
470 | bail1: | |
471 | if (spu->irqs[0] != NO_IRQ) | |
472 | free_irq(spu->irqs[0], spu); | |
473 | bail0: | |
67207b96 AB |
474 | return ret; |
475 | } | |
476 | ||
0ebfff14 | 477 | static void spu_free_irqs(struct spu *spu) |
67207b96 | 478 | { |
0ebfff14 BH |
479 | if (spu->irqs[0] != NO_IRQ) |
480 | free_irq(spu->irqs[0], spu); | |
481 | if (spu->irqs[1] != NO_IRQ) | |
482 | free_irq(spu->irqs[1], spu); | |
483 | if (spu->irqs[2] != NO_IRQ) | |
484 | free_irq(spu->irqs[2], spu); | |
67207b96 AB |
485 | } |
486 | ||
486acd48 | 487 | void spu_init_channels(struct spu *spu) |
67207b96 AB |
488 | { |
489 | static const struct { | |
490 | unsigned channel; | |
491 | unsigned count; | |
492 | } zero_list[] = { | |
493 | { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, }, | |
494 | { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, }, | |
495 | }, count_list[] = { | |
496 | { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, }, | |
497 | { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, }, | |
498 | { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, }, | |
499 | }; | |
6ff730c3 | 500 | struct spu_priv2 __iomem *priv2; |
67207b96 AB |
501 | int i; |
502 | ||
503 | priv2 = spu->priv2; | |
504 | ||
505 | /* initialize all channel data to zero */ | |
506 | for (i = 0; i < ARRAY_SIZE(zero_list); i++) { | |
507 | int count; | |
508 | ||
509 | out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); | |
510 | for (count = 0; count < zero_list[i].count; count++) | |
511 | out_be64(&priv2->spu_chnldata_RW, 0); | |
512 | } | |
513 | ||
514 | /* initialize channel counts to meaningful values */ | |
515 | for (i = 0; i < ARRAY_SIZE(count_list); i++) { | |
516 | out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); | |
517 | out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); | |
518 | } | |
519 | } | |
486acd48 | 520 | EXPORT_SYMBOL_GPL(spu_init_channels); |
67207b96 | 521 | |
1238819a | 522 | static struct sysdev_class spu_sysdev_class = { |
af5ca3f4 | 523 | .name = "spu", |
1d64093f JK |
524 | }; |
525 | ||
e570beb6 CK |
526 | int spu_add_sysdev_attr(struct sysdev_attribute *attr) |
527 | { | |
528 | struct spu *spu; | |
e570beb6 | 529 | |
24140594 | 530 | mutex_lock(&spu_full_list_mutex); |
e570beb6 CK |
531 | list_for_each_entry(spu, &spu_full_list, full_list) |
532 | sysdev_create_file(&spu->sysdev, attr); | |
24140594 | 533 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 534 | |
e570beb6 CK |
535 | return 0; |
536 | } | |
537 | EXPORT_SYMBOL_GPL(spu_add_sysdev_attr); | |
538 | ||
539 | int spu_add_sysdev_attr_group(struct attribute_group *attrs) | |
540 | { | |
541 | struct spu *spu; | |
1e771039 | 542 | int rc = 0; |
e570beb6 | 543 | |
24140594 | 544 | mutex_lock(&spu_full_list_mutex); |
1e771039 JK |
545 | list_for_each_entry(spu, &spu_full_list, full_list) { |
546 | rc = sysfs_create_group(&spu->sysdev.kobj, attrs); | |
547 | ||
548 | /* we're in trouble here, but try unwinding anyway */ | |
549 | if (rc) { | |
550 | printk(KERN_ERR "%s: can't create sysfs group '%s'\n", | |
551 | __func__, attrs->name); | |
552 | ||
553 | list_for_each_entry_continue_reverse(spu, | |
554 | &spu_full_list, full_list) | |
555 | sysfs_remove_group(&spu->sysdev.kobj, attrs); | |
556 | break; | |
557 | } | |
558 | } | |
559 | ||
24140594 | 560 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 | 561 | |
1e771039 | 562 | return rc; |
e570beb6 CK |
563 | } |
564 | EXPORT_SYMBOL_GPL(spu_add_sysdev_attr_group); | |
565 | ||
566 | ||
567 | void spu_remove_sysdev_attr(struct sysdev_attribute *attr) | |
568 | { | |
569 | struct spu *spu; | |
e570beb6 | 570 | |
24140594 | 571 | mutex_lock(&spu_full_list_mutex); |
e570beb6 CK |
572 | list_for_each_entry(spu, &spu_full_list, full_list) |
573 | sysdev_remove_file(&spu->sysdev, attr); | |
24140594 | 574 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 CK |
575 | } |
576 | EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr); | |
577 | ||
578 | void spu_remove_sysdev_attr_group(struct attribute_group *attrs) | |
579 | { | |
580 | struct spu *spu; | |
e570beb6 | 581 | |
24140594 | 582 | mutex_lock(&spu_full_list_mutex); |
e570beb6 CK |
583 | list_for_each_entry(spu, &spu_full_list, full_list) |
584 | sysfs_remove_group(&spu->sysdev.kobj, attrs); | |
24140594 | 585 | mutex_unlock(&spu_full_list_mutex); |
e570beb6 CK |
586 | } |
587 | EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr_group); | |
588 | ||
1d64093f JK |
589 | static int spu_create_sysdev(struct spu *spu) |
590 | { | |
591 | int ret; | |
592 | ||
593 | spu->sysdev.id = spu->number; | |
594 | spu->sysdev.cls = &spu_sysdev_class; | |
595 | ret = sysdev_register(&spu->sysdev); | |
596 | if (ret) { | |
597 | printk(KERN_ERR "Can't register SPU %d with sysfs\n", | |
598 | spu->number); | |
599 | return ret; | |
600 | } | |
601 | ||
0021550c | 602 | sysfs_add_device_to_node(&spu->sysdev, spu->node); |
1d64093f JK |
603 | |
604 | return 0; | |
605 | } | |
606 | ||
e28b0031 | 607 | static int __init create_spu(void *data) |
67207b96 AB |
608 | { |
609 | struct spu *spu; | |
610 | int ret; | |
611 | static int number; | |
94b2a439 | 612 | unsigned long flags; |
27ec41d3 | 613 | struct timespec ts; |
67207b96 AB |
614 | |
615 | ret = -ENOMEM; | |
ecec2177 | 616 | spu = kzalloc(sizeof (*spu), GFP_KERNEL); |
67207b96 AB |
617 | if (!spu) |
618 | goto out; | |
619 | ||
486acd48 CH |
620 | spu->alloc_state = SPU_FREE; |
621 | ||
e28b0031 | 622 | spin_lock_init(&spu->register_lock); |
24140594 | 623 | spin_lock(&spu_lock); |
e28b0031 | 624 | spu->number = number++; |
24140594 | 625 | spin_unlock(&spu_lock); |
e28b0031 GL |
626 | |
627 | ret = spu_create_spu(spu, data); | |
e5267b4b | 628 | |
67207b96 AB |
629 | if (ret) |
630 | goto out_free; | |
631 | ||
24f43b33 | 632 | spu_mfc_sdr_setup(spu); |
f0831acc | 633 | spu_mfc_sr1_set(spu, 0x33); |
67207b96 AB |
634 | ret = spu_request_irqs(spu); |
635 | if (ret) | |
e28b0031 | 636 | goto out_destroy; |
67207b96 | 637 | |
1d64093f JK |
638 | ret = spu_create_sysdev(spu); |
639 | if (ret) | |
640 | goto out_free_irqs; | |
641 | ||
486acd48 | 642 | mutex_lock(&cbe_spu_info[spu->node].list_mutex); |
aa6d5b20 AB |
643 | list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus); |
644 | cbe_spu_info[spu->node].n_spus++; | |
486acd48 | 645 | mutex_unlock(&cbe_spu_info[spu->node].list_mutex); |
24140594 CH |
646 | |
647 | mutex_lock(&spu_full_list_mutex); | |
648 | spin_lock_irqsave(&spu_full_list_lock, flags); | |
e570beb6 | 649 | list_add(&spu->full_list, &spu_full_list); |
24140594 CH |
650 | spin_unlock_irqrestore(&spu_full_list_lock, flags); |
651 | mutex_unlock(&spu_full_list_mutex); | |
67207b96 | 652 | |
27ec41d3 AD |
653 | spu->stats.util_state = SPU_UTIL_IDLE_LOADED; |
654 | ktime_get_ts(&ts); | |
655 | spu->stats.tstamp = timespec_to_ns(&ts); | |
fe2f896d | 656 | |
9d92af62 AB |
657 | INIT_LIST_HEAD(&spu->aff_list); |
658 | ||
67207b96 AB |
659 | goto out; |
660 | ||
1d64093f JK |
661 | out_free_irqs: |
662 | spu_free_irqs(spu); | |
e28b0031 GL |
663 | out_destroy: |
664 | spu_destroy_spu(spu); | |
67207b96 AB |
665 | out_free: |
666 | kfree(spu); | |
667 | out: | |
668 | return ret; | |
669 | } | |
670 | ||
fe2f896d CH |
671 | static const char *spu_state_names[] = { |
672 | "user", "system", "iowait", "idle" | |
673 | }; | |
674 | ||
675 | static unsigned long long spu_acct_time(struct spu *spu, | |
676 | enum spu_utilization_state state) | |
677 | { | |
27ec41d3 | 678 | struct timespec ts; |
fe2f896d CH |
679 | unsigned long long time = spu->stats.times[state]; |
680 | ||
27ec41d3 AD |
681 | /* |
682 | * If the spu is idle or the context is stopped, utilization | |
683 | * statistics are not updated. Apply the time delta from the | |
684 | * last recorded state of the spu. | |
685 | */ | |
686 | if (spu->stats.util_state == state) { | |
687 | ktime_get_ts(&ts); | |
688 | time += timespec_to_ns(&ts) - spu->stats.tstamp; | |
689 | } | |
fe2f896d | 690 | |
27ec41d3 | 691 | return time / NSEC_PER_MSEC; |
fe2f896d CH |
692 | } |
693 | ||
694 | ||
4a0b2b4d AK |
695 | static ssize_t spu_stat_show(struct sys_device *sysdev, |
696 | struct sysdev_attribute *attr, char *buf) | |
fe2f896d CH |
697 | { |
698 | struct spu *spu = container_of(sysdev, struct spu, sysdev); | |
699 | ||
700 | return sprintf(buf, "%s %llu %llu %llu %llu " | |
701 | "%llu %llu %llu %llu %llu %llu %llu %llu\n", | |
27ec41d3 | 702 | spu_state_names[spu->stats.util_state], |
fe2f896d CH |
703 | spu_acct_time(spu, SPU_UTIL_USER), |
704 | spu_acct_time(spu, SPU_UTIL_SYSTEM), | |
705 | spu_acct_time(spu, SPU_UTIL_IOWAIT), | |
27ec41d3 | 706 | spu_acct_time(spu, SPU_UTIL_IDLE_LOADED), |
fe2f896d CH |
707 | spu->stats.vol_ctx_switch, |
708 | spu->stats.invol_ctx_switch, | |
709 | spu->stats.slb_flt, | |
710 | spu->stats.hash_flt, | |
711 | spu->stats.min_flt, | |
712 | spu->stats.maj_flt, | |
713 | spu->stats.class2_intr, | |
714 | spu->stats.libassist); | |
715 | } | |
716 | ||
717 | static SYSDEV_ATTR(stat, 0644, spu_stat_show, NULL); | |
718 | ||
158d5b5e AB |
719 | #ifdef CONFIG_KEXEC |
720 | ||
721 | struct crash_spu_info { | |
722 | struct spu *spu; | |
723 | u32 saved_spu_runcntl_RW; | |
724 | u32 saved_spu_status_R; | |
725 | u32 saved_spu_npc_RW; | |
726 | u64 saved_mfc_sr1_RW; | |
727 | u64 saved_mfc_dar; | |
728 | u64 saved_mfc_dsisr; | |
729 | }; | |
730 | ||
731 | #define CRASH_NUM_SPUS 16 /* Enough for current hardware */ | |
732 | static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS]; | |
733 | ||
734 | static void crash_kexec_stop_spus(void) | |
735 | { | |
736 | struct spu *spu; | |
737 | int i; | |
738 | u64 tmp; | |
739 | ||
740 | for (i = 0; i < CRASH_NUM_SPUS; i++) { | |
741 | if (!crash_spu_info[i].spu) | |
742 | continue; | |
743 | ||
744 | spu = crash_spu_info[i].spu; | |
745 | ||
746 | crash_spu_info[i].saved_spu_runcntl_RW = | |
747 | in_be32(&spu->problem->spu_runcntl_RW); | |
748 | crash_spu_info[i].saved_spu_status_R = | |
749 | in_be32(&spu->problem->spu_status_R); | |
750 | crash_spu_info[i].saved_spu_npc_RW = | |
751 | in_be32(&spu->problem->spu_npc_RW); | |
752 | ||
753 | crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu); | |
754 | crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu); | |
755 | tmp = spu_mfc_sr1_get(spu); | |
756 | crash_spu_info[i].saved_mfc_sr1_RW = tmp; | |
757 | ||
758 | tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; | |
759 | spu_mfc_sr1_set(spu, tmp); | |
760 | ||
761 | __delay(200); | |
762 | } | |
763 | } | |
764 | ||
765 | static void crash_register_spus(struct list_head *list) | |
766 | { | |
767 | struct spu *spu; | |
768 | int ret; | |
769 | ||
770 | list_for_each_entry(spu, list, full_list) { | |
771 | if (WARN_ON(spu->number >= CRASH_NUM_SPUS)) | |
772 | continue; | |
773 | ||
774 | crash_spu_info[spu->number].spu = spu; | |
775 | } | |
776 | ||
777 | ret = crash_shutdown_register(&crash_kexec_stop_spus); | |
778 | if (ret) | |
779 | printk(KERN_ERR "Could not register SPU crash handler"); | |
780 | } | |
781 | ||
782 | #else | |
783 | static inline void crash_register_spus(struct list_head *list) | |
784 | { | |
785 | } | |
786 | #endif | |
787 | ||
f5a592f7 RW |
788 | static void spu_shutdown(void) |
789 | { | |
790 | struct spu *spu; | |
791 | ||
792 | mutex_lock(&spu_full_list_mutex); | |
793 | list_for_each_entry(spu, &spu_full_list, full_list) { | |
794 | spu_free_irqs(spu); | |
795 | spu_destroy_spu(spu); | |
796 | } | |
797 | mutex_unlock(&spu_full_list_mutex); | |
798 | } | |
799 | ||
800 | static struct syscore_ops spu_syscore_ops = { | |
801 | .shutdown = spu_shutdown, | |
802 | }; | |
803 | ||
67207b96 AB |
804 | static int __init init_spu_base(void) |
805 | { | |
befdc746 | 806 | int i, ret = 0; |
67207b96 | 807 | |
aa6d5b20 | 808 | for (i = 0; i < MAX_NUMNODES; i++) { |
486acd48 | 809 | mutex_init(&cbe_spu_info[i].list_mutex); |
aa6d5b20 | 810 | INIT_LIST_HEAD(&cbe_spu_info[i].spus); |
aa6d5b20 | 811 | } |
ccf17e9d | 812 | |
da06aa08 | 813 | if (!spu_management_ops) |
befdc746 | 814 | goto out; |
da06aa08 | 815 | |
1d64093f JK |
816 | /* create sysdev class for spus */ |
817 | ret = sysdev_class_register(&spu_sysdev_class); | |
818 | if (ret) | |
befdc746 | 819 | goto out; |
1d64093f | 820 | |
e28b0031 GL |
821 | ret = spu_enumerate_spus(create_spu); |
822 | ||
bce94513 | 823 | if (ret < 0) { |
e28b0031 | 824 | printk(KERN_WARNING "%s: Error initializing spus\n", |
e48b1b45 | 825 | __func__); |
befdc746 | 826 | goto out_unregister_sysdev_class; |
67207b96 | 827 | } |
ff8a8f25 | 828 | |
ae52bb23 | 829 | if (ret > 0) |
bce94513 | 830 | fb_append_extra_logo(&logo_spe_clut224, ret); |
bce94513 | 831 | |
24140594 | 832 | mutex_lock(&spu_full_list_mutex); |
ff8a8f25 | 833 | xmon_register_spus(&spu_full_list); |
8d2655e6 | 834 | crash_register_spus(&spu_full_list); |
24140594 | 835 | mutex_unlock(&spu_full_list_mutex); |
fe2f896d | 836 | spu_add_sysdev_attr(&attr_stat); |
f5a592f7 | 837 | register_syscore_ops(&spu_syscore_ops); |
fe2f896d | 838 | |
f5996449 | 839 | spu_init_affinity(); |
3ad216ca | 840 | |
befdc746 CH |
841 | return 0; |
842 | ||
843 | out_unregister_sysdev_class: | |
844 | sysdev_class_unregister(&spu_sysdev_class); | |
845 | out: | |
67207b96 AB |
846 | return ret; |
847 | } | |
848 | module_init(init_spu_base); | |
849 | ||
850 | MODULE_LICENSE("GPL"); | |
851 | MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>"); |