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67207b96 AB |
1 | /* |
2 | * Low-level SPU handling | |
3 | * | |
4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
5 | * | |
6 | * Author: Arnd Bergmann <arndb@de.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
3b3d22cb | 23 | #undef DEBUG |
67207b96 AB |
24 | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/module.h> | |
67207b96 AB |
28 | #include <linux/ptrace.h> |
29 | #include <linux/slab.h> | |
30 | #include <linux/wait.h> | |
e28b0031 GL |
31 | #include <linux/mm.h> |
32 | #include <linux/io.h> | |
14cc3e2b | 33 | #include <linux/mutex.h> |
67207b96 | 34 | #include <asm/spu.h> |
540270d8 | 35 | #include <asm/spu_priv1.h> |
ff8a8f25 | 36 | #include <asm/xmon.h> |
67207b96 | 37 | |
e28b0031 | 38 | const struct spu_management_ops *spu_management_ops; |
540270d8 GL |
39 | const struct spu_priv1_ops *spu_priv1_ops; |
40 | ||
41 | EXPORT_SYMBOL_GPL(spu_priv1_ops); | |
42 | ||
67207b96 AB |
43 | static int __spu_trap_invalid_dma(struct spu *spu) |
44 | { | |
45 | pr_debug("%s\n", __FUNCTION__); | |
9add11da | 46 | spu->dma_callback(spu, SPE_EVENT_INVALID_DMA); |
67207b96 AB |
47 | return 0; |
48 | } | |
49 | ||
50 | static int __spu_trap_dma_align(struct spu *spu) | |
51 | { | |
52 | pr_debug("%s\n", __FUNCTION__); | |
9add11da | 53 | spu->dma_callback(spu, SPE_EVENT_DMA_ALIGNMENT); |
67207b96 AB |
54 | return 0; |
55 | } | |
56 | ||
57 | static int __spu_trap_error(struct spu *spu) | |
58 | { | |
59 | pr_debug("%s\n", __FUNCTION__); | |
9add11da | 60 | spu->dma_callback(spu, SPE_EVENT_SPE_ERROR); |
67207b96 AB |
61 | return 0; |
62 | } | |
63 | ||
64 | static void spu_restart_dma(struct spu *spu) | |
65 | { | |
66 | struct spu_priv2 __iomem *priv2 = spu->priv2; | |
5473af04 | 67 | |
8837d921 | 68 | if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags)) |
5473af04 | 69 | out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); |
67207b96 AB |
70 | } |
71 | ||
72 | static int __spu_trap_data_seg(struct spu *spu, unsigned long ea) | |
73 | { | |
8b3d6663 AB |
74 | struct spu_priv2 __iomem *priv2 = spu->priv2; |
75 | struct mm_struct *mm = spu->mm; | |
724bd80e | 76 | u64 esid, vsid, llp; |
67207b96 AB |
77 | |
78 | pr_debug("%s\n", __FUNCTION__); | |
79 | ||
8837d921 | 80 | if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) { |
8b3d6663 AB |
81 | /* SLBs are pre-loaded for context switch, so |
82 | * we should never get here! | |
83 | */ | |
5473af04 MN |
84 | printk("%s: invalid access during switch!\n", __func__); |
85 | return 1; | |
86 | } | |
0afacde3 AB |
87 | esid = (ea & ESID_MASK) | SLB_ESID_V; |
88 | ||
89 | switch(REGION_ID(ea)) { | |
90 | case USER_REGION_ID: | |
91 | #ifdef CONFIG_HUGETLB_PAGE | |
92 | if (in_hugepage_area(mm->context, ea)) | |
93 | llp = mmu_psize_defs[mmu_huge_psize].sllp; | |
94 | else | |
95 | #endif | |
96 | llp = mmu_psize_defs[mmu_virtual_psize].sllp; | |
97 | vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) | | |
98 | SLB_VSID_USER | llp; | |
99 | break; | |
100 | case VMALLOC_REGION_ID: | |
101 | llp = mmu_psize_defs[mmu_virtual_psize].sllp; | |
102 | vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | | |
103 | SLB_VSID_KERNEL | llp; | |
104 | break; | |
105 | case KERNEL_REGION_ID: | |
106 | llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
107 | vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | | |
108 | SLB_VSID_KERNEL | llp; | |
109 | break; | |
110 | default: | |
8b3d6663 AB |
111 | /* Future: support kernel segments so that drivers |
112 | * can use SPUs. | |
113 | */ | |
67207b96 AB |
114 | pr_debug("invalid region access at %016lx\n", ea); |
115 | return 1; | |
116 | } | |
117 | ||
8b3d6663 AB |
118 | out_be64(&priv2->slb_index_W, spu->slb_replace); |
119 | out_be64(&priv2->slb_vsid_RW, vsid); | |
120 | out_be64(&priv2->slb_esid_RW, esid); | |
121 | ||
122 | spu->slb_replace++; | |
67207b96 AB |
123 | if (spu->slb_replace >= 8) |
124 | spu->slb_replace = 0; | |
125 | ||
67207b96 AB |
126 | spu_restart_dma(spu); |
127 | ||
67207b96 AB |
128 | return 0; |
129 | } | |
130 | ||
5473af04 | 131 | extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX |
8b3d6663 | 132 | static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr) |
67207b96 | 133 | { |
a33a7d73 | 134 | pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea); |
67207b96 | 135 | |
5473af04 MN |
136 | /* Handle kernel space hash faults immediately. |
137 | User hash faults need to be deferred to process context. */ | |
138 | if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) | |
139 | && REGION_ID(ea) != USER_REGION_ID | |
140 | && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) { | |
141 | spu_restart_dma(spu); | |
142 | return 0; | |
143 | } | |
144 | ||
8837d921 | 145 | if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) { |
5473af04 MN |
146 | printk("%s: invalid access during switch!\n", __func__); |
147 | return 1; | |
148 | } | |
67207b96 | 149 | |
8b3d6663 AB |
150 | spu->dar = ea; |
151 | spu->dsisr = dsisr; | |
152 | mb(); | |
ba723fe2 | 153 | spu->stop_callback(spu); |
67207b96 AB |
154 | return 0; |
155 | } | |
156 | ||
157 | static irqreturn_t | |
f5a92458 | 158 | spu_irq_class_0(int irq, void *data) |
67207b96 AB |
159 | { |
160 | struct spu *spu; | |
161 | ||
162 | spu = data; | |
163 | spu->class_0_pending = 1; | |
ba723fe2 | 164 | spu->stop_callback(spu); |
67207b96 AB |
165 | |
166 | return IRQ_HANDLED; | |
167 | } | |
168 | ||
5110459f | 169 | int |
67207b96 AB |
170 | spu_irq_class_0_bottom(struct spu *spu) |
171 | { | |
3a843d7c | 172 | unsigned long stat, mask; |
67207b96 AB |
173 | |
174 | spu->class_0_pending = 0; | |
175 | ||
f0831acc AB |
176 | mask = spu_int_mask_get(spu, 0); |
177 | stat = spu_int_stat_get(spu, 0); | |
67207b96 | 178 | |
3a843d7c AB |
179 | stat &= mask; |
180 | ||
2cd90bc8 | 181 | if (stat & 1) /* invalid DMA alignment */ |
67207b96 AB |
182 | __spu_trap_dma_align(spu); |
183 | ||
2cd90bc8 AB |
184 | if (stat & 2) /* invalid MFC DMA */ |
185 | __spu_trap_invalid_dma(spu); | |
186 | ||
67207b96 AB |
187 | if (stat & 4) /* error on SPU */ |
188 | __spu_trap_error(spu); | |
189 | ||
f0831acc | 190 | spu_int_stat_clear(spu, 0, stat); |
5110459f AB |
191 | |
192 | return (stat & 0x7) ? -EIO : 0; | |
67207b96 | 193 | } |
5110459f | 194 | EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom); |
67207b96 AB |
195 | |
196 | static irqreturn_t | |
f5a92458 | 197 | spu_irq_class_1(int irq, void *data) |
67207b96 AB |
198 | { |
199 | struct spu *spu; | |
8b3d6663 | 200 | unsigned long stat, mask, dar, dsisr; |
67207b96 AB |
201 | |
202 | spu = data; | |
8b3d6663 AB |
203 | |
204 | /* atomically read & clear class1 status. */ | |
205 | spin_lock(&spu->register_lock); | |
f0831acc AB |
206 | mask = spu_int_mask_get(spu, 1); |
207 | stat = spu_int_stat_get(spu, 1) & mask; | |
208 | dar = spu_mfc_dar_get(spu); | |
209 | dsisr = spu_mfc_dsisr_get(spu); | |
38307341 | 210 | if (stat & 2) /* mapping fault */ |
f0831acc AB |
211 | spu_mfc_dsisr_set(spu, 0ul); |
212 | spu_int_stat_clear(spu, 1, stat); | |
8b3d6663 | 213 | spin_unlock(&spu->register_lock); |
a33a7d73 AB |
214 | pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat, |
215 | dar, dsisr); | |
67207b96 AB |
216 | |
217 | if (stat & 1) /* segment fault */ | |
218 | __spu_trap_data_seg(spu, dar); | |
219 | ||
220 | if (stat & 2) { /* mapping fault */ | |
8b3d6663 | 221 | __spu_trap_data_map(spu, dar, dsisr); |
67207b96 AB |
222 | } |
223 | ||
224 | if (stat & 4) /* ls compare & suspend on get */ | |
225 | ; | |
226 | ||
227 | if (stat & 8) /* ls compare & suspend on put */ | |
228 | ; | |
229 | ||
67207b96 AB |
230 | return stat ? IRQ_HANDLED : IRQ_NONE; |
231 | } | |
5110459f | 232 | EXPORT_SYMBOL_GPL(spu_irq_class_1_bottom); |
67207b96 AB |
233 | |
234 | static irqreturn_t | |
f5a92458 | 235 | spu_irq_class_2(int irq, void *data) |
67207b96 AB |
236 | { |
237 | struct spu *spu; | |
238 | unsigned long stat; | |
3a843d7c | 239 | unsigned long mask; |
67207b96 AB |
240 | |
241 | spu = data; | |
ba723fe2 | 242 | spin_lock(&spu->register_lock); |
f0831acc AB |
243 | stat = spu_int_stat_get(spu, 2); |
244 | mask = spu_int_mask_get(spu, 2); | |
ba723fe2 MN |
245 | /* ignore interrupts we're not waiting for */ |
246 | stat &= mask; | |
247 | /* | |
248 | * mailbox interrupts (0x1 and 0x10) are level triggered. | |
249 | * mask them now before acknowledging. | |
250 | */ | |
251 | if (stat & 0x11) | |
252 | spu_int_mask_and(spu, 2, ~(stat & 0x11)); | |
253 | /* acknowledge all interrupts before the callbacks */ | |
254 | spu_int_stat_clear(spu, 2, stat); | |
255 | spin_unlock(&spu->register_lock); | |
67207b96 | 256 | |
3a843d7c | 257 | pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask); |
67207b96 | 258 | |
67207b96 | 259 | if (stat & 1) /* PPC core mailbox */ |
ba723fe2 | 260 | spu->ibox_callback(spu); |
67207b96 AB |
261 | |
262 | if (stat & 2) /* SPU stop-and-signal */ | |
ba723fe2 | 263 | spu->stop_callback(spu); |
67207b96 AB |
264 | |
265 | if (stat & 4) /* SPU halted */ | |
ba723fe2 | 266 | spu->stop_callback(spu); |
67207b96 AB |
267 | |
268 | if (stat & 8) /* DMA tag group complete */ | |
ba723fe2 | 269 | spu->mfc_callback(spu); |
67207b96 AB |
270 | |
271 | if (stat & 0x10) /* SPU mailbox threshold */ | |
ba723fe2 | 272 | spu->wbox_callback(spu); |
67207b96 | 273 | |
67207b96 AB |
274 | return stat ? IRQ_HANDLED : IRQ_NONE; |
275 | } | |
276 | ||
0ebfff14 | 277 | static int spu_request_irqs(struct spu *spu) |
67207b96 | 278 | { |
0ebfff14 | 279 | int ret = 0; |
67207b96 | 280 | |
0ebfff14 BH |
281 | if (spu->irqs[0] != NO_IRQ) { |
282 | snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", | |
283 | spu->number); | |
284 | ret = request_irq(spu->irqs[0], spu_irq_class_0, | |
285 | IRQF_DISABLED, | |
286 | spu->irq_c0, spu); | |
287 | if (ret) | |
288 | goto bail0; | |
289 | } | |
290 | if (spu->irqs[1] != NO_IRQ) { | |
291 | snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", | |
292 | spu->number); | |
293 | ret = request_irq(spu->irqs[1], spu_irq_class_1, | |
294 | IRQF_DISABLED, | |
295 | spu->irq_c1, spu); | |
296 | if (ret) | |
297 | goto bail1; | |
298 | } | |
299 | if (spu->irqs[2] != NO_IRQ) { | |
300 | snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", | |
301 | spu->number); | |
302 | ret = request_irq(spu->irqs[2], spu_irq_class_2, | |
303 | IRQF_DISABLED, | |
304 | spu->irq_c2, spu); | |
305 | if (ret) | |
306 | goto bail2; | |
307 | } | |
308 | return 0; | |
67207b96 | 309 | |
0ebfff14 BH |
310 | bail2: |
311 | if (spu->irqs[1] != NO_IRQ) | |
312 | free_irq(spu->irqs[1], spu); | |
313 | bail1: | |
314 | if (spu->irqs[0] != NO_IRQ) | |
315 | free_irq(spu->irqs[0], spu); | |
316 | bail0: | |
67207b96 AB |
317 | return ret; |
318 | } | |
319 | ||
0ebfff14 | 320 | static void spu_free_irqs(struct spu *spu) |
67207b96 | 321 | { |
0ebfff14 BH |
322 | if (spu->irqs[0] != NO_IRQ) |
323 | free_irq(spu->irqs[0], spu); | |
324 | if (spu->irqs[1] != NO_IRQ) | |
325 | free_irq(spu->irqs[1], spu); | |
326 | if (spu->irqs[2] != NO_IRQ) | |
327 | free_irq(spu->irqs[2], spu); | |
67207b96 AB |
328 | } |
329 | ||
a68cf983 | 330 | static struct list_head spu_list[MAX_NUMNODES]; |
e570beb6 | 331 | static LIST_HEAD(spu_full_list); |
14cc3e2b | 332 | static DEFINE_MUTEX(spu_mutex); |
67207b96 AB |
333 | |
334 | static void spu_init_channels(struct spu *spu) | |
335 | { | |
336 | static const struct { | |
337 | unsigned channel; | |
338 | unsigned count; | |
339 | } zero_list[] = { | |
340 | { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, }, | |
341 | { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, }, | |
342 | }, count_list[] = { | |
343 | { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, }, | |
344 | { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, }, | |
345 | { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, }, | |
346 | }; | |
6ff730c3 | 347 | struct spu_priv2 __iomem *priv2; |
67207b96 AB |
348 | int i; |
349 | ||
350 | priv2 = spu->priv2; | |
351 | ||
352 | /* initialize all channel data to zero */ | |
353 | for (i = 0; i < ARRAY_SIZE(zero_list); i++) { | |
354 | int count; | |
355 | ||
356 | out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); | |
357 | for (count = 0; count < zero_list[i].count; count++) | |
358 | out_be64(&priv2->spu_chnldata_RW, 0); | |
359 | } | |
360 | ||
361 | /* initialize channel counts to meaningful values */ | |
362 | for (i = 0; i < ARRAY_SIZE(count_list); i++) { | |
363 | out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); | |
364 | out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); | |
365 | } | |
366 | } | |
367 | ||
a68cf983 | 368 | struct spu *spu_alloc_node(int node) |
67207b96 | 369 | { |
a68cf983 | 370 | struct spu *spu = NULL; |
67207b96 | 371 | |
14cc3e2b | 372 | mutex_lock(&spu_mutex); |
a68cf983 MN |
373 | if (!list_empty(&spu_list[node])) { |
374 | spu = list_entry(spu_list[node].next, struct spu, list); | |
67207b96 | 375 | list_del_init(&spu->list); |
cc21a66d | 376 | pr_debug("Got SPU %d %d\n", spu->number, spu->node); |
a68cf983 | 377 | spu_init_channels(spu); |
67207b96 | 378 | } |
14cc3e2b | 379 | mutex_unlock(&spu_mutex); |
67207b96 | 380 | |
a68cf983 MN |
381 | return spu; |
382 | } | |
383 | EXPORT_SYMBOL_GPL(spu_alloc_node); | |
384 | ||
385 | struct spu *spu_alloc(void) | |
386 | { | |
387 | struct spu *spu = NULL; | |
388 | int node; | |
389 | ||
390 | for (node = 0; node < MAX_NUMNODES; node++) { | |
391 | spu = spu_alloc_node(node); | |
392 | if (spu) | |
393 | break; | |
394 | } | |
67207b96 AB |
395 | |
396 | return spu; | |
397 | } | |
67207b96 AB |
398 | |
399 | void spu_free(struct spu *spu) | |
400 | { | |
14cc3e2b | 401 | mutex_lock(&spu_mutex); |
a68cf983 | 402 | list_add_tail(&spu->list, &spu_list[spu->node]); |
14cc3e2b | 403 | mutex_unlock(&spu_mutex); |
67207b96 | 404 | } |
39c73c33 | 405 | EXPORT_SYMBOL_GPL(spu_free); |
67207b96 | 406 | |
67207b96 AB |
407 | static int spu_handle_mm_fault(struct spu *spu) |
408 | { | |
67207b96 AB |
409 | struct mm_struct *mm = spu->mm; |
410 | struct vm_area_struct *vma; | |
411 | u64 ea, dsisr, is_write; | |
412 | int ret; | |
413 | ||
8b3d6663 AB |
414 | ea = spu->dar; |
415 | dsisr = spu->dsisr; | |
67207b96 AB |
416 | #if 0 |
417 | if (!IS_VALID_EA(ea)) { | |
418 | return -EFAULT; | |
419 | } | |
420 | #endif /* XXX */ | |
421 | if (mm == NULL) { | |
422 | return -EFAULT; | |
423 | } | |
424 | if (mm->pgd == NULL) { | |
425 | return -EFAULT; | |
426 | } | |
427 | ||
428 | down_read(&mm->mmap_sem); | |
429 | vma = find_vma(mm, ea); | |
430 | if (!vma) | |
431 | goto bad_area; | |
432 | if (vma->vm_start <= ea) | |
433 | goto good_area; | |
434 | if (!(vma->vm_flags & VM_GROWSDOWN)) | |
435 | goto bad_area; | |
436 | #if 0 | |
437 | if (expand_stack(vma, ea)) | |
438 | goto bad_area; | |
439 | #endif /* XXX */ | |
440 | good_area: | |
441 | is_write = dsisr & MFC_DSISR_ACCESS_PUT; | |
442 | if (is_write) { | |
443 | if (!(vma->vm_flags & VM_WRITE)) | |
444 | goto bad_area; | |
445 | } else { | |
446 | if (dsisr & MFC_DSISR_ACCESS_DENIED) | |
447 | goto bad_area; | |
448 | if (!(vma->vm_flags & (VM_READ | VM_EXEC))) | |
449 | goto bad_area; | |
450 | } | |
451 | ret = 0; | |
452 | switch (handle_mm_fault(mm, vma, ea, is_write)) { | |
453 | case VM_FAULT_MINOR: | |
454 | current->min_flt++; | |
455 | break; | |
456 | case VM_FAULT_MAJOR: | |
457 | current->maj_flt++; | |
458 | break; | |
459 | case VM_FAULT_SIGBUS: | |
460 | ret = -EFAULT; | |
461 | goto bad_area; | |
462 | case VM_FAULT_OOM: | |
463 | ret = -ENOMEM; | |
464 | goto bad_area; | |
465 | default: | |
466 | BUG(); | |
467 | } | |
468 | up_read(&mm->mmap_sem); | |
469 | return ret; | |
470 | ||
471 | bad_area: | |
472 | up_read(&mm->mmap_sem); | |
473 | return -EFAULT; | |
474 | } | |
475 | ||
5110459f | 476 | int spu_irq_class_1_bottom(struct spu *spu) |
67207b96 | 477 | { |
67207b96 AB |
478 | u64 ea, dsisr, access, error = 0UL; |
479 | int ret = 0; | |
480 | ||
8b3d6663 AB |
481 | ea = spu->dar; |
482 | dsisr = spu->dsisr; | |
79c227a9 | 483 | if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)) { |
f807221d AB |
484 | u64 flags; |
485 | ||
8b3d6663 AB |
486 | access = (_PAGE_PRESENT | _PAGE_USER); |
487 | access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL; | |
f807221d | 488 | local_irq_save(flags); |
67207b96 AB |
489 | if (hash_page(ea, access, 0x300) != 0) |
490 | error |= CLASS1_ENABLE_STORAGE_FAULT_INTR; | |
f807221d | 491 | local_irq_restore(flags); |
67207b96 | 492 | } |
79c227a9 | 493 | if (error & CLASS1_ENABLE_STORAGE_FAULT_INTR) { |
67207b96 AB |
494 | if ((ret = spu_handle_mm_fault(spu)) != 0) |
495 | error |= CLASS1_ENABLE_STORAGE_FAULT_INTR; | |
496 | else | |
497 | error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR; | |
498 | } | |
8b3d6663 AB |
499 | spu->dar = 0UL; |
500 | spu->dsisr = 0UL; | |
501 | if (!error) { | |
67207b96 | 502 | spu_restart_dma(spu); |
8b3d6663 | 503 | } else { |
453d9f72 | 504 | spu->dma_callback(spu, SPE_EVENT_SPE_DATA_STORAGE); |
8b3d6663 | 505 | } |
67207b96 AB |
506 | return ret; |
507 | } | |
508 | ||
1d64093f JK |
509 | struct sysdev_class spu_sysdev_class = { |
510 | set_kset_name("spu") | |
511 | }; | |
512 | ||
e570beb6 CK |
513 | int spu_add_sysdev_attr(struct sysdev_attribute *attr) |
514 | { | |
515 | struct spu *spu; | |
516 | mutex_lock(&spu_mutex); | |
517 | ||
518 | list_for_each_entry(spu, &spu_full_list, full_list) | |
519 | sysdev_create_file(&spu->sysdev, attr); | |
520 | ||
521 | mutex_unlock(&spu_mutex); | |
522 | return 0; | |
523 | } | |
524 | EXPORT_SYMBOL_GPL(spu_add_sysdev_attr); | |
525 | ||
526 | int spu_add_sysdev_attr_group(struct attribute_group *attrs) | |
527 | { | |
528 | struct spu *spu; | |
529 | mutex_lock(&spu_mutex); | |
530 | ||
531 | list_for_each_entry(spu, &spu_full_list, full_list) | |
532 | sysfs_create_group(&spu->sysdev.kobj, attrs); | |
533 | ||
534 | mutex_unlock(&spu_mutex); | |
535 | return 0; | |
536 | } | |
537 | EXPORT_SYMBOL_GPL(spu_add_sysdev_attr_group); | |
538 | ||
539 | ||
540 | void spu_remove_sysdev_attr(struct sysdev_attribute *attr) | |
541 | { | |
542 | struct spu *spu; | |
543 | mutex_lock(&spu_mutex); | |
544 | ||
545 | list_for_each_entry(spu, &spu_full_list, full_list) | |
546 | sysdev_remove_file(&spu->sysdev, attr); | |
547 | ||
548 | mutex_unlock(&spu_mutex); | |
549 | } | |
550 | EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr); | |
551 | ||
552 | void spu_remove_sysdev_attr_group(struct attribute_group *attrs) | |
553 | { | |
554 | struct spu *spu; | |
555 | mutex_lock(&spu_mutex); | |
556 | ||
557 | list_for_each_entry(spu, &spu_full_list, full_list) | |
558 | sysfs_remove_group(&spu->sysdev.kobj, attrs); | |
559 | ||
560 | mutex_unlock(&spu_mutex); | |
561 | } | |
562 | EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr_group); | |
563 | ||
1d64093f JK |
564 | static int spu_create_sysdev(struct spu *spu) |
565 | { | |
566 | int ret; | |
567 | ||
568 | spu->sysdev.id = spu->number; | |
569 | spu->sysdev.cls = &spu_sysdev_class; | |
570 | ret = sysdev_register(&spu->sysdev); | |
571 | if (ret) { | |
572 | printk(KERN_ERR "Can't register SPU %d with sysfs\n", | |
573 | spu->number); | |
574 | return ret; | |
575 | } | |
576 | ||
0021550c | 577 | sysfs_add_device_to_node(&spu->sysdev, spu->node); |
1d64093f JK |
578 | |
579 | return 0; | |
580 | } | |
581 | ||
582 | static void spu_destroy_sysdev(struct spu *spu) | |
583 | { | |
0021550c | 584 | sysfs_remove_device_from_node(&spu->sysdev, spu->node); |
1d64093f JK |
585 | sysdev_unregister(&spu->sysdev); |
586 | } | |
587 | ||
e28b0031 | 588 | static int __init create_spu(void *data) |
67207b96 AB |
589 | { |
590 | struct spu *spu; | |
591 | int ret; | |
592 | static int number; | |
593 | ||
594 | ret = -ENOMEM; | |
ecec2177 | 595 | spu = kzalloc(sizeof (*spu), GFP_KERNEL); |
67207b96 AB |
596 | if (!spu) |
597 | goto out; | |
598 | ||
e28b0031 GL |
599 | spin_lock_init(&spu->register_lock); |
600 | mutex_lock(&spu_mutex); | |
601 | spu->number = number++; | |
602 | mutex_unlock(&spu_mutex); | |
603 | ||
604 | ret = spu_create_spu(spu, data); | |
e5267b4b | 605 | |
67207b96 AB |
606 | if (ret) |
607 | goto out_free; | |
608 | ||
24f43b33 | 609 | spu_mfc_sdr_setup(spu); |
f0831acc | 610 | spu_mfc_sr1_set(spu, 0x33); |
67207b96 AB |
611 | ret = spu_request_irqs(spu); |
612 | if (ret) | |
e28b0031 | 613 | goto out_destroy; |
67207b96 | 614 | |
1d64093f JK |
615 | ret = spu_create_sysdev(spu); |
616 | if (ret) | |
617 | goto out_free_irqs; | |
618 | ||
e28b0031 | 619 | mutex_lock(&spu_mutex); |
a68cf983 | 620 | list_add(&spu->list, &spu_list[spu->node]); |
e570beb6 | 621 | list_add(&spu->full_list, &spu_full_list); |
14cc3e2b | 622 | mutex_unlock(&spu_mutex); |
67207b96 | 623 | |
67207b96 AB |
624 | goto out; |
625 | ||
1d64093f JK |
626 | out_free_irqs: |
627 | spu_free_irqs(spu); | |
e28b0031 GL |
628 | out_destroy: |
629 | spu_destroy_spu(spu); | |
67207b96 AB |
630 | out_free: |
631 | kfree(spu); | |
632 | out: | |
633 | return ret; | |
634 | } | |
635 | ||
636 | static void destroy_spu(struct spu *spu) | |
637 | { | |
638 | list_del_init(&spu->list); | |
e570beb6 CK |
639 | list_del_init(&spu->full_list); |
640 | ||
1d64093f | 641 | spu_destroy_sysdev(spu); |
67207b96 | 642 | spu_free_irqs(spu); |
e28b0031 | 643 | spu_destroy_spu(spu); |
67207b96 AB |
644 | kfree(spu); |
645 | } | |
646 | ||
647 | static void cleanup_spu_base(void) | |
648 | { | |
649 | struct spu *spu, *tmp; | |
a68cf983 MN |
650 | int node; |
651 | ||
14cc3e2b | 652 | mutex_lock(&spu_mutex); |
a68cf983 MN |
653 | for (node = 0; node < MAX_NUMNODES; node++) { |
654 | list_for_each_entry_safe(spu, tmp, &spu_list[node], list) | |
655 | destroy_spu(spu); | |
656 | } | |
14cc3e2b | 657 | mutex_unlock(&spu_mutex); |
1d64093f | 658 | sysdev_class_unregister(&spu_sysdev_class); |
67207b96 AB |
659 | } |
660 | module_exit(cleanup_spu_base); | |
661 | ||
662 | static int __init init_spu_base(void) | |
663 | { | |
a68cf983 | 664 | int i, ret; |
67207b96 | 665 | |
1d64093f JK |
666 | /* create sysdev class for spus */ |
667 | ret = sysdev_class_register(&spu_sysdev_class); | |
668 | if (ret) | |
669 | return ret; | |
670 | ||
a68cf983 MN |
671 | for (i = 0; i < MAX_NUMNODES; i++) |
672 | INIT_LIST_HEAD(&spu_list[i]); | |
673 | ||
e28b0031 GL |
674 | ret = spu_enumerate_spus(create_spu); |
675 | ||
676 | if (ret) { | |
677 | printk(KERN_WARNING "%s: Error initializing spus\n", | |
678 | __FUNCTION__); | |
679 | cleanup_spu_base(); | |
680 | return ret; | |
67207b96 | 681 | } |
ff8a8f25 ME |
682 | |
683 | xmon_register_spus(&spu_full_list); | |
684 | ||
67207b96 AB |
685 | return ret; |
686 | } | |
687 | module_init(init_spu_base); | |
688 | ||
689 | MODULE_LICENSE("GPL"); | |
690 | MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>"); |