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873e65bc | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f0831acc | 2 | /* |
540270d8 GL |
3 | * spu hypervisor abstraction for direct hardware access. |
4 | * | |
5 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 | |
6 | * Copyright 2006 Sony Corp. | |
f0831acc | 7 | */ |
540270d8 | 8 | |
e28b0031 GL |
9 | #include <linux/interrupt.h> |
10 | #include <linux/list.h> | |
e28b0031 | 11 | #include <linux/ptrace.h> |
e28b0031 GL |
12 | #include <linux/wait.h> |
13 | #include <linux/mm.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/mutex.h> | |
16 | #include <linux/device.h> | |
7a214200 | 17 | #include <linux/sched.h> |
f0831acc | 18 | |
f0831acc | 19 | #include <asm/spu.h> |
540270d8 | 20 | #include <asm/spu_priv1.h> |
e28b0031 GL |
21 | #include <asm/firmware.h> |
22 | #include <asm/prom.h> | |
f0831acc | 23 | |
a91942ae | 24 | #include "interrupt.h" |
e28b0031 GL |
25 | #include "spu_priv1_mmio.h" |
26 | ||
540270d8 | 27 | static void int_mask_and(struct spu *spu, int class, u64 mask) |
f0831acc AB |
28 | { |
29 | u64 old_mask; | |
30 | ||
c9868fe0 IK |
31 | old_mask = in_be64(&spu->priv1->int_mask_RW[class]); |
32 | out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); | |
f0831acc | 33 | } |
f0831acc | 34 | |
540270d8 | 35 | static void int_mask_or(struct spu *spu, int class, u64 mask) |
f0831acc AB |
36 | { |
37 | u64 old_mask; | |
38 | ||
c9868fe0 IK |
39 | old_mask = in_be64(&spu->priv1->int_mask_RW[class]); |
40 | out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); | |
f0831acc | 41 | } |
f0831acc | 42 | |
540270d8 | 43 | static void int_mask_set(struct spu *spu, int class, u64 mask) |
f0831acc | 44 | { |
c9868fe0 | 45 | out_be64(&spu->priv1->int_mask_RW[class], mask); |
f0831acc | 46 | } |
f0831acc | 47 | |
540270d8 | 48 | static u64 int_mask_get(struct spu *spu, int class) |
f0831acc | 49 | { |
c9868fe0 | 50 | return in_be64(&spu->priv1->int_mask_RW[class]); |
f0831acc | 51 | } |
f0831acc | 52 | |
540270d8 | 53 | static void int_stat_clear(struct spu *spu, int class, u64 stat) |
f0831acc | 54 | { |
c9868fe0 | 55 | out_be64(&spu->priv1->int_stat_RW[class], stat); |
f0831acc | 56 | } |
f0831acc | 57 | |
540270d8 | 58 | static u64 int_stat_get(struct spu *spu, int class) |
f0831acc | 59 | { |
c9868fe0 | 60 | return in_be64(&spu->priv1->int_stat_RW[class]); |
f0831acc | 61 | } |
f0831acc | 62 | |
a91942ae | 63 | static void cpu_affinity_set(struct spu *spu, int cpu) |
f0831acc | 64 | { |
7a214200 LB |
65 | u64 target; |
66 | u64 route; | |
67 | ||
68 | if (nr_cpus_node(spu->node)) { | |
86c6f274 RR |
69 | const struct cpumask *spumask = cpumask_of_node(spu->node), |
70 | *cpumask = cpumask_of_node(cpu_to_node(cpu)); | |
7a214200 | 71 | |
86c6f274 | 72 | if (!cpumask_intersects(spumask, cpumask)) |
7a214200 LB |
73 | return; |
74 | } | |
75 | ||
76 | target = iic_get_target_id(cpu); | |
77 | route = target << 48 | target << 32 | target << 16; | |
c9868fe0 | 78 | out_be64(&spu->priv1->int_route_RW, route); |
f0831acc | 79 | } |
f0831acc | 80 | |
540270d8 | 81 | static u64 mfc_dar_get(struct spu *spu) |
f0831acc | 82 | { |
c9868fe0 | 83 | return in_be64(&spu->priv1->mfc_dar_RW); |
f0831acc | 84 | } |
f0831acc | 85 | |
540270d8 | 86 | static u64 mfc_dsisr_get(struct spu *spu) |
f0831acc | 87 | { |
c9868fe0 | 88 | return in_be64(&spu->priv1->mfc_dsisr_RW); |
f0831acc | 89 | } |
f0831acc | 90 | |
540270d8 | 91 | static void mfc_dsisr_set(struct spu *spu, u64 dsisr) |
f0831acc | 92 | { |
c9868fe0 | 93 | out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); |
f0831acc | 94 | } |
f0831acc | 95 | |
24f43b33 | 96 | static void mfc_sdr_setup(struct spu *spu) |
f0831acc | 97 | { |
c9868fe0 | 98 | out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1)); |
f0831acc | 99 | } |
f0831acc | 100 | |
540270d8 | 101 | static void mfc_sr1_set(struct spu *spu, u64 sr1) |
f0831acc | 102 | { |
c9868fe0 | 103 | out_be64(&spu->priv1->mfc_sr1_RW, sr1); |
f0831acc | 104 | } |
f0831acc | 105 | |
540270d8 | 106 | static u64 mfc_sr1_get(struct spu *spu) |
f0831acc | 107 | { |
c9868fe0 | 108 | return in_be64(&spu->priv1->mfc_sr1_RW); |
f0831acc | 109 | } |
f0831acc | 110 | |
540270d8 | 111 | static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) |
f0831acc | 112 | { |
c9868fe0 | 113 | out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); |
f0831acc | 114 | } |
f0831acc | 115 | |
540270d8 | 116 | static u64 mfc_tclass_id_get(struct spu *spu) |
f0831acc | 117 | { |
c9868fe0 | 118 | return in_be64(&spu->priv1->mfc_tclass_id_RW); |
f0831acc | 119 | } |
f0831acc | 120 | |
540270d8 | 121 | static void tlb_invalidate(struct spu *spu) |
f0831acc | 122 | { |
c9868fe0 | 123 | out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); |
f0831acc | 124 | } |
f0831acc | 125 | |
540270d8 | 126 | static void resource_allocation_groupID_set(struct spu *spu, u64 id) |
f0831acc | 127 | { |
c9868fe0 | 128 | out_be64(&spu->priv1->resource_allocation_groupID_RW, id); |
f0831acc | 129 | } |
f0831acc | 130 | |
540270d8 | 131 | static u64 resource_allocation_groupID_get(struct spu *spu) |
f0831acc | 132 | { |
c9868fe0 | 133 | return in_be64(&spu->priv1->resource_allocation_groupID_RW); |
f0831acc | 134 | } |
f0831acc | 135 | |
540270d8 | 136 | static void resource_allocation_enable_set(struct spu *spu, u64 enable) |
f0831acc | 137 | { |
c9868fe0 | 138 | out_be64(&spu->priv1->resource_allocation_enable_RW, enable); |
f0831acc | 139 | } |
f0831acc | 140 | |
540270d8 | 141 | static u64 resource_allocation_enable_get(struct spu *spu) |
f0831acc | 142 | { |
c9868fe0 | 143 | return in_be64(&spu->priv1->resource_allocation_enable_RW); |
f0831acc | 144 | } |
540270d8 GL |
145 | |
146 | const struct spu_priv1_ops spu_priv1_mmio_ops = | |
147 | { | |
148 | .int_mask_and = int_mask_and, | |
149 | .int_mask_or = int_mask_or, | |
150 | .int_mask_set = int_mask_set, | |
151 | .int_mask_get = int_mask_get, | |
152 | .int_stat_clear = int_stat_clear, | |
153 | .int_stat_get = int_stat_get, | |
a91942ae | 154 | .cpu_affinity_set = cpu_affinity_set, |
540270d8 GL |
155 | .mfc_dar_get = mfc_dar_get, |
156 | .mfc_dsisr_get = mfc_dsisr_get, | |
157 | .mfc_dsisr_set = mfc_dsisr_set, | |
24f43b33 | 158 | .mfc_sdr_setup = mfc_sdr_setup, |
540270d8 GL |
159 | .mfc_sr1_set = mfc_sr1_set, |
160 | .mfc_sr1_get = mfc_sr1_get, | |
161 | .mfc_tclass_id_set = mfc_tclass_id_set, | |
162 | .mfc_tclass_id_get = mfc_tclass_id_get, | |
163 | .tlb_invalidate = tlb_invalidate, | |
164 | .resource_allocation_groupID_set = resource_allocation_groupID_set, | |
165 | .resource_allocation_groupID_get = resource_allocation_groupID_get, | |
166 | .resource_allocation_enable_set = resource_allocation_enable_set, | |
167 | .resource_allocation_enable_get = resource_allocation_enable_get, | |
168 | }; |