[mirror_ubuntu-focal-kernel.git] / arch / powerpc / platforms / chrp / setup.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  Copyright (C) 1995  Linus Torvalds
 *  Adapted from 'alpha' version by Gary Thomas
 *  Modified by Cort Dougan (cort@cs.nmt.edu)
 */

/*
 * bootup setup stuff..
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/user.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <generated/utsrelease.h>
#include <linux/adb.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/console.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/timer.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/sections.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/mpic.h>
#include <asm/rtas.h>
#include <asm/xmon.h>

#include "chrp.h"
#include "gg2.h"

void rtas_indicator_progress(char *, unsigned short);

int _chrp_type;
EXPORT_SYMBOL(_chrp_type);

static struct mpic *chrp_mpic;

/* Used for doing CHRP event-scans */
DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
unsigned long event_scan_interval;

extern unsigned long loops_per_jiffy;

/* To be replaced by RTAS when available */
static unsigned int __iomem *briq_SPOR;

#ifdef CONFIG_SMP
extern struct smp_ops_t chrp_smp_ops;
#endif

static const char *gg2_memtypes[4] = {
	"FPM", "SDRAM", "EDO", "BEDO"
};
static const char *gg2_cachesizes[4] = {
	"256 KB", "512 KB", "1 MB", "Reserved"
};
static const char *gg2_cachetypes[4] = {
	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	"Pipelined Synchronous"
};
static const char *gg2_cachemodes[4] = {
	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
};

static const char *chrp_names[] = {
	"Unknown",
	"","","",
	"Motorola",
	"IBM or Longtrail",
	"Genesi Pegasos",
	"Total Impact Briq"
};

void chrp_show_cpuinfo(struct seq_file *m)
{
	int i, sdramen;
	unsigned int t;
	struct device_node *root;
	const char *model = "";

	root = of_find_node_by_path("/");
	if (root)
		model = of_get_property(root, "model", NULL);
	seq_printf(m, "machine\t\t: CHRP %s\n", model);

	/* longtrail (goldengate) stuff */
	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
		/* VLSI VAS96011/12 `Golden Gate 2' */
		/* Memory banks */
		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
			   >>31) & 1;
		for (i = 0; i < (sdramen ? 4 : 6); i++) {
			t = in_le32(gg2_pci_config_base+
						 GG2_PCI_DRAM_BANK0+
						 i*4);
			if (!(t & 1))
				continue;
			switch ((t>>8) & 0x1f) {
			case 0x1f:
				model = "4 MB";
				break;
			case 0x1e:
				model = "8 MB";
				break;
			case 0x1c:
				model = "16 MB";
				break;
			case 0x18:
				model = "32 MB";
				break;
			case 0x10:
				model = "64 MB";
				break;
			case 0x00:
				model = "128 MB";
				break;
			default:
				model = "Reserved";
				break;
			}
			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
		}
		/* L2 cache */
		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
		seq_printf(m, "board l2\t: %s %s (%s)\n",
			   gg2_cachesizes[(t>>7) & 3],
			   gg2_cachetypes[(t>>2) & 3],
			   gg2_cachemodes[t & 3]);
	}
	of_node_put(root);
}

/*
 *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 *
 *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 *  for keyboard and mouse
 */
static inline void __init sio_write(u8 val, u8 index)
{
	outb(index, 0x15c);
	outb(val, 0x15d);
}

static inline u8 __init sio_read(u8 index)
{
	outb(index, 0x15c);
	return inb(0x15d);
}

static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
				     u8 type)
{
	u8 level0, type0, active;

	/* select logical device */
	sio_write(device, 0x07);
	active = sio_read(0x30);
	level0 = sio_read(0x70);
	type0 = sio_read(0x71);
	if (level0 != level || type0 != type || !active) {
		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
		       "remapping to level %d, type %d, active\n",
		       name, level0, type0, !active ? "in" : "", level, type);
		sio_write(0x01, 0x30);
		sio_write(level, 0x70);
		sio_write(type, 0x71);
	}
}

static void __init sio_init(void)
{
	struct device_node *root;
	const char *model;

	root = of_find_node_by_path("/");
	if (!root)
		return;

	model = of_get_property(root, "model", NULL);
	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
		/* logical device 0 (KBC/Keyboard) */
		sio_fixup_irq("keyboard", 0, 1, 2);
		/* select logical device 1 (KBC/Mouse) */
		sio_fixup_irq("mouse", 1, 12, 2);
	}

	of_node_put(root);
}


static void __init pegasos_set_l2cr(void)
{
	struct device_node *np;

	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
	if (_chrp_type != _CHRP_Pegasos)
		return;

	/* Enable L2 cache if needed */
	np = of_find_node_by_type(NULL, "cpu");
	if (np != NULL) {
		const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
		if (l2cr == NULL) {
			printk ("Pegasos l2cr : no cpu l2cr property found\n");
			goto out;
		}
		if (!((*l2cr) & 0x80000000)) {
			printk ("Pegasos l2cr : L2 cache was not active, "
				"activating\n");
			_set_L2CR(0);
			_set_L2CR((*l2cr) | 0x80000000);
		}
	}
out:
	of_node_put(np);
}

static void __noreturn briq_restart(char *cmd)
{
	local_irq_disable();
	if (briq_SPOR)
		out_be32(briq_SPOR, 0);
	for(;;);
}

/*
 * Per default, input/output-device points to the keyboard/screen
 * If no card is installed, the built-in serial port is used as a fallback.
 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
 * the the built-in serial node. Instead, a /failsafe node is created.
 */
static __init void chrp_init(void)
{
	struct device_node *node;
	const char *property;

	if (strstr(boot_command_line, "console="))
		return;
	/* find the boot console from /chosen/stdout */
	if (!of_chosen)
		return;
	node = of_find_node_by_path("/");
	if (!node)
		return;
	property = of_get_property(node, "model", NULL);
	if (!property)
		goto out_put;
	if (strcmp(property, "Pegasos2"))
		goto out_put;
	/* this is a Pegasos2 */
	property = of_get_property(of_chosen, "linux,stdout-path", NULL);
	if (!property)
		goto out_put;
	of_node_put(node);
	node = of_find_node_by_path(property);
	if (!node)
		return;
	property = of_get_property(node, "device_type", NULL);
	if (!property)
		goto out_put;
	if (strcmp(property, "serial"))
		goto out_put;
	/*
	 * The 9pin connector is either /failsafe
	 * or /pci@80000000/isa@C/serial@i2F8
	 * The optional graphics card has also type 'serial' in VGA mode.
	 */
	property = of_get_property(node, "name", NULL);
	if (!property)
		goto out_put;
	if (!strcmp(property, "failsafe") || !strcmp(property, "serial"))
		add_preferred_console("ttyS", 0, NULL);
out_put:
	of_node_put(node);
}

void __init chrp_setup_arch(void)
{
	struct device_node *root = of_find_node_by_path("/");
	const char *machine = NULL;

	/* init to some ~sane value until calibrate_delay() runs */
	loops_per_jiffy = 50000000/HZ;

	if (root)
		machine = of_get_property(root, "model", NULL);
	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
		_chrp_type = _CHRP_Pegasos;
	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
		_chrp_type = _CHRP_IBM;
	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
		_chrp_type = _CHRP_Motorola;
	} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
		_chrp_type = _CHRP_briq;
		/* Map the SPOR register on briq and change the restart hook */
		briq_SPOR = ioremap(0xff0000e8, 4);
		ppc_md.restart = briq_restart;
	} else {
		/* Let's assume it is an IBM chrp if all else fails */
		_chrp_type = _CHRP_IBM;
	}
	of_node_put(root);
	printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);

	rtas_initialize();
	if (rtas_token("display-character") >= 0)
		ppc_md.progress = rtas_progress;

	/* use RTAS time-of-day routines if available */
	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
		ppc_md.get_boot_time	= rtas_get_boot_time;
		ppc_md.get_rtc_time	= rtas_get_rtc_time;
		ppc_md.set_rtc_time	= rtas_set_rtc_time;
	}

	/* On pegasos, enable the L2 cache if not already done by OF */
	pegasos_set_l2cr();

	/* Lookup PCI host bridges */
	chrp_find_bridges();

	/*
	 *  Temporary fixes for PCI devices.
	 *  -- Geert
	 */
	hydra_init();		/* Mac I/O */

	/*
	 *  Fix the Super I/O configuration
	 */
	sio_init();

	pci_create_OF_bus_map();

	/*
	 * Print the banner, then scroll down so boot progress
	 * can be printed.  -- Cort
	 */
	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}

static void chrp_8259_cascade(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int cascade_irq = i8259_irq();

	if (cascade_irq)
		generic_handle_irq(cascade_irq);

	chip->irq_eoi(&desc->irq_data);
}

/*
 * Finds the open-pic node and sets up the mpic driver.
 */
static void __init chrp_find_openpic(void)
{
	struct device_node *np, *root;
	int len, i, j;
	int isu_size, idu_size;
	const unsigned int *iranges, *opprop = NULL;
	int oplen = 0;
	unsigned long opaddr;
	int na = 1;

	np = of_find_node_by_type(NULL, "open-pic");
	if (np == NULL)
		return;
	root = of_find_node_by_path("/");
	if (root) {
		opprop = of_get_property(root, "platform-open-pic", &oplen);
		na = of_n_addr_cells(root);
	}
	if (opprop && oplen >= na * sizeof(unsigned int)) {
		opaddr = opprop[na-1];	/* assume 32-bit */
		oplen /= na * sizeof(unsigned int);
	} else {
		struct resource r;
		if (of_address_to_resource(np, 0, &r)) {
			goto bail;
		}
		opaddr = r.start;
		oplen = 0;
	}

	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);

	iranges = of_get_property(np, "interrupt-ranges", &len);
	if (iranges == NULL)
		len = 0;	/* non-distributed mpic */
	else
		len /= 2 * sizeof(unsigned int);

	/*
	 * The first pair of cells in interrupt-ranges refers to the
	 * IDU; subsequent pairs refer to the ISUs.
	 */
	if (oplen < len) {
		printk(KERN_ERR "Insufficient addresses for distributed"
		       " OpenPIC (%d < %d)\n", oplen, len);
		len = oplen;
	}

	isu_size = 0;
	idu_size = 0;
	if (len > 0 && iranges[1] != 0) {
		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
		       iranges[0], iranges[0] + iranges[1] - 1);
		idu_size = iranges[1];
	}
	if (len > 1)
		isu_size = iranges[3];

	chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
			isu_size, 0, " MPIC    ");
	if (chrp_mpic == NULL) {
		printk(KERN_ERR "Failed to allocate MPIC structure\n");
		goto bail;
	}
	j = na - 1;
	for (i = 1; i < len; ++i) {
		iranges += 2;
		j += na;
		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
		       iranges[0], iranges[0] + iranges[1] - 1,
		       opprop[j]);
		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	}

	mpic_init(chrp_mpic);
	ppc_md.get_irq = mpic_get_irq;
 bail:
	of_node_put(root);
	of_node_put(np);
}

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
static struct irqaction xmon_irqaction = {
	.handler = xmon_irq,
	.name = "XMON break",
};
#endif

static void __init chrp_find_8259(void)
{
	struct device_node *np, *pic = NULL;
	unsigned long chrp_int_ack = 0;
	unsigned int cascade_irq;

	/* Look for cascade */
	for_each_node_by_type(np, "interrupt-controller")
		if (of_device_is_compatible(np, "chrp,iic")) {
			pic = np;
			break;
		}
	/* Ok, 8259 wasn't found. We need to handle the case where
	 * we have a pegasos that claims to be chrp but doesn't have
	 * a proper interrupt tree
	 */
	if (pic == NULL && chrp_mpic != NULL) {
		printk(KERN_ERR "i8259: Not found in device-tree"
		       " assuming no legacy interrupts\n");
		return;
	}

	/* Look for intack. In a perfect world, we would look for it on
	 * the ISA bus that holds the 8259 but heh... Works that way. If
	 * we ever see a problem, we can try to re-use the pSeries code here.
	 * Also, Pegasos-type platforms don't have a proper node to start
	 * from anyway
	 */
	for_each_node_by_name(np, "pci") {
		const unsigned int *addrp = of_get_property(np,
				"8259-interrupt-acknowledge", NULL);

		if (addrp == NULL)
			continue;
		chrp_int_ack = addrp[of_n_addr_cells(np)-1];
		break;
	}
	of_node_put(np);
	if (np == NULL)
		printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
		       " address, polling\n");

	i8259_init(pic, chrp_int_ack);
	if (ppc_md.get_irq == NULL) {
		ppc_md.get_irq = i8259_irq;
		irq_set_default_host(i8259_get_host());
	}
	if (chrp_mpic != NULL) {
		cascade_irq = irq_of_parse_and_map(pic, 0);
		if (!cascade_irq)
			printk(KERN_ERR "i8259: failed to map cascade irq\n");
		else
			irq_set_chained_handler(cascade_irq,
						chrp_8259_cascade);
	}
}

void __init chrp_init_IRQ(void)
{
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
	struct device_node *kbd;
#endif
	chrp_find_openpic();
	chrp_find_8259();

#ifdef CONFIG_SMP
	/* Pegasos has no MPIC, those ops would make it crash. It might be an
	 * option to move setting them to after we probe the PIC though
	 */
	if (chrp_mpic != NULL)
		smp_ops = &chrp_smp_ops;
#endif /* CONFIG_SMP */

	if (_chrp_type == _CHRP_Pegasos)
		ppc_md.get_irq        = i8259_irq;

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
	/* see if there is a keyboard in the device tree
	   with a parent of type "adb" */
	for_each_node_by_name(kbd, "keyboard")
		if (kbd->parent && kbd->parent->type
		    && strcmp(kbd->parent->type, "adb") == 0)
			break;
	of_node_put(kbd);
	if (kbd)
		setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
#endif
}

void __init
chrp_init2(void)
{
#ifdef CONFIG_NVRAM
	chrp_nvram_init();
#endif

	request_region(0x20,0x20,"pic1");
	request_region(0xa0,0x20,"pic2");
	request_region(0x00,0x20,"dma1");
	request_region(0x40,0x20,"timer");
	request_region(0x80,0x10,"dma page reg");
	request_region(0xc0,0x20,"dma2");

	if (ppc_md.progress)
		ppc_md.progress("  Have fun!    ", 0x7777);
}

static int __init chrp_probe(void)
{
	const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
						"device_type", NULL);
 	if (dtype == NULL)
 		return 0;
 	if (strcmp(dtype, "chrp"))
		return 0;

	ISA_DMA_THRESHOLD = ~0L;
	DMA_MODE_READ = 0x44;
	DMA_MODE_WRITE = 0x48;

	pm_power_off = rtas_power_off;

	chrp_init();

	return 1;
}

define_machine(chrp) {
	.name			= "CHRP",
	.probe			= chrp_probe,
	.setup_arch		= chrp_setup_arch,
	.init			= chrp_init2,
	.show_cpuinfo		= chrp_show_cpuinfo,
	.init_IRQ		= chrp_init_IRQ,
	.restart		= rtas_restart,
	.halt			= rtas_halt,
	.time_init		= chrp_time_init,
	.set_rtc_time		= chrp_set_rtc_time,
	.get_rtc_time		= chrp_get_rtc_time,
	.calibrate_decr		= generic_calibrate_decr,
	.phys_mem_access_prot	= pci_phys_mem_access_prot,
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
bbd0abda	2	/*
bbd0abda PM	3	* Copyright (C) 1995 Linus Torvalds
	4	* Adapted from 'alpha' version by Gary Thomas
	5	* Modified by Cort Dougan (cort@cs.nmt.edu)
	6	*/
	7
	8	/*
	9	* bootup setup stuff..
	10	*/
	11
bbd0abda PM	12	#include <linux/errno.h>
	13	#include <linux/sched.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mm.h>
	16	#include <linux/stddef.h>
	17	#include <linux/unistd.h>
	18	#include <linux/ptrace.h>
bbd0abda	19	#include <linux/user.h>
bbd0abda PM	20	#include <linux/tty.h>
	21	#include <linux/major.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/reboot.h>
	24	#include <linux/init.h>
	25	#include <linux/pci.h>
273b281f	26	#include <generated/utsrelease.h>
bbd0abda PM	27	#include <linux/adb.h>
	28	#include <linux/module.h>
	29	#include <linux/delay.h>
bbd0abda PM	30	#include <linux/console.h>
	31	#include <linux/seq_file.h>
	32	#include <linux/root_dev.h>
	33	#include <linux/initrd.h>
9618edab	34	#include <linux/timer.h>
bbd0abda PM	35
	36	#include <asm/io.h>
	37	#include <asm/pgtable.h>
	38	#include <asm/prom.h>
bbd0abda PM	39	#include <asm/pci-bridge.h>
	40	#include <asm/dma.h>
	41	#include <asm/machdep.h>
	42	#include <asm/irq.h>
	43	#include <asm/hydra.h>
	44	#include <asm/sections.h>
	45	#include <asm/time.h>
bbd0abda PM	46	#include <asm/i8259.h>
	47	#include <asm/mpic.h>
	48	#include <asm/rtas.h>
	49	#include <asm/xmon.h>
	50
35e95e63	51	#include "chrp.h"
33d71d26	52	#include "gg2.h"
bbd0abda	53
bbd0abda	54	void rtas_indicator_progress(char *, unsigned short);
bbd0abda PM	55
	56	int _chrp_type;
	57	EXPORT_SYMBOL(_chrp_type);
	58
0ebfff14	59	static struct mpic *chrp_mpic;
bbd0abda	60
9618edab PM	61	/* Used for doing CHRP event-scans */
	62	DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
	63	unsigned long event_scan_interval;
	64
bbd0abda PM	65	extern unsigned long loops_per_jiffy;
bbd0abda PM	66
26c5032e	67	/* To be replaced by RTAS when available */
9340b0d3	68	static unsigned int __iomem *briq_SPOR;
26c5032e	69
bbd0abda PM	70	#ifdef CONFIG_SMP
	71	extern struct smp_ops_t chrp_smp_ops;
	72	#endif
	73
	74	static const char *gg2_memtypes[4] = {
	75	"FPM", "SDRAM", "EDO", "BEDO"
	76	};
	77	static const char *gg2_cachesizes[4] = {
	78	"256 KB", "512 KB", "1 MB", "Reserved"
	79	};
	80	static const char *gg2_cachetypes[4] = {
	81	"Asynchronous", "Reserved", "Flow-Through Synchronous",
	82	"Pipelined Synchronous"
	83	};
	84	static const char *gg2_cachemodes[4] = {
	85	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
	86	};
	87
26c5032e BH	88	static const char *chrp_names[] = {
	89	"Unknown",
	90	"","","",
	91	"Motorola",
	92	"IBM or Longtrail",
	93	"Genesi Pegasos",
	94	"Total Impact Briq"
	95	};
	96
bbd0abda PM	97	void chrp_show_cpuinfo(struct seq_file *m)
	98	{
	99	int i, sdramen;
	100	unsigned int t;
	101	struct device_node *root;
	102	const char *model = "";
	103
8c8dc322	104	root = of_find_node_by_path("/");
bbd0abda	105	if (root)
e2eb6392	106	model = of_get_property(root, "model", NULL);
bbd0abda PM	107	seq_printf(m, "machine\t\t: CHRP %s\n", model);
	108
	109	/* longtrail (goldengate) stuff */
9ac71d00	110	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
bbd0abda PM	111	/* VLSI VAS96011/12 `Golden Gate 2' */
	112	/* Memory banks */
	113	sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
	114	>>31) & 1;
	115	for (i = 0; i < (sdramen ? 4 : 6); i++) {
	116	t = in_le32(gg2_pci_config_base+
	117	GG2_PCI_DRAM_BANK0+
	118	i*4);
	119	if (!(t & 1))
	120	continue;
	121	switch ((t>>8) & 0x1f) {
	122	case 0x1f:
	123	model = "4 MB";
	124	break;
	125	case 0x1e:
	126	model = "8 MB";
	127	break;
	128	case 0x1c:
	129	model = "16 MB";
	130	break;
	131	case 0x18:
	132	model = "32 MB";
	133	break;
	134	case 0x10:
	135	model = "64 MB";
	136	break;
	137	case 0x00:
	138	model = "128 MB";
	139	break;
	140	default:
	141	model = "Reserved";
	142	break;
	143	}
	144	seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
	145	gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
	146	}
	147	/* L2 cache */
	148	t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
	149	seq_printf(m, "board l2\t: %s %s (%s)\n",
	150	gg2_cachesizes[(t>>7) & 3],
	151	gg2_cachetypes[(t>>2) & 3],
	152	gg2_cachemodes[t & 3]);
	153	}
8c8dc322	154	of_node_put(root);
bbd0abda PM	155	}
	156
	157	/*
	158	* Fixes for the National Semiconductor PC78308VUL SuperI/O
	159	*
	160	* Some versions of Open Firmware incorrectly initialize the IRQ settings
	161	* for keyboard and mouse
	162	*/
	163	static inline void __init sio_write(u8 val, u8 index)
	164	{
	165	outb(index, 0x15c);
	166	outb(val, 0x15d);
	167	}
	168
	169	static inline u8 __init sio_read(u8 index)
	170	{
	171	outb(index, 0x15c);
	172	return inb(0x15d);
	173	}
	174
	175	static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
	176	u8 type)
	177	{
	178	u8 level0, type0, active;
	179
	180	/* select logical device */
	181	sio_write(device, 0x07);
	182	active = sio_read(0x30);
	183	level0 = sio_read(0x70);
	184	type0 = sio_read(0x71);
	185	if (level0 != level \|\| type0 != type \|\| !active) {
	186	printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
	187	"remapping to level %d, type %d, active\n",
	188	name, level0, type0, !active ? "in" : "", level, type);
	189	sio_write(0x01, 0x30);
	190	sio_write(level, 0x70);
	191	sio_write(type, 0x71);
	192	}
	193	}
	194
	195	static void __init sio_init(void)
	196	{
	197	struct device_node *root;
9ac71d00	198	const char *model;
bbd0abda	199
9ac71d00 CG	200	root = of_find_node_by_path("/");
	201	if (!root)
	202	return;
	203
	204	model = of_get_property(root, "model", NULL);
	205	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
bbd0abda PM	206	/* logical device 0 (KBC/Keyboard) */
	207	sio_fixup_irq("keyboard", 0, 1, 2);
	208	/* select logical device 1 (KBC/Mouse) */
	209	sio_fixup_irq("mouse", 1, 12, 2);
	210	}
9ac71d00	211
8c8dc322	212	of_node_put(root);
bbd0abda PM	213	}
	214
	215
	216	static void __init pegasos_set_l2cr(void)
	217	{
	218	struct device_node *np;
	219
	220	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
	221	if (_chrp_type != _CHRP_Pegasos)
	222	return;
	223
	224	/* Enable L2 cache if needed */
1658ab66	225	np = of_find_node_by_type(NULL, "cpu");
bbd0abda	226	if (np != NULL) {
e2eb6392	227	const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
bbd0abda PM	228	if (l2cr == NULL) {
bbd0abda PM	229	printk ("Pegasos l2cr : no cpu l2cr property found\n");
1658ab66	230	goto out;
bbd0abda PM	231	}
	232	if (!((*l2cr) & 0x80000000)) {
	233	printk ("Pegasos l2cr : L2 cache was not active, "
	234	"activating\n");
	235	_set_L2CR(0);
	236	_set_L2CR((*l2cr) \| 0x80000000);
	237	}
	238	}
1658ab66 SR	239	out:
1658ab66 SR	240	of_node_put(np);
bbd0abda PM	241	}
bbd0abda PM	242
95ec77c0	243	static void __noreturn briq_restart(char *cmd)
26c5032e BH	244	{
	245	local_irq_disable();
	246	if (briq_SPOR)
	247	out_be32(briq_SPOR, 0);
	248	for(;;);
	249	}
	250
5bc97786 OH	251	/*
	252	* Per default, input/output-device points to the keyboard/screen
	253	* If no card is installed, the built-in serial port is used as a fallback.
	254	* But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
	255	* the the built-in serial node. Instead, a /failsafe node is created.
	256	*/
f2d57694	257	static __init void chrp_init(void)
5bc97786 OH	258	{
	259	struct device_node *node;
	260	const char *property;
	261
3e47d147	262	if (strstr(boot_command_line, "console="))
5bc97786 OH	263	return;
	264	/* find the boot console from /chosen/stdout */
	265	if (!of_chosen)
	266	return;
	267	node = of_find_node_by_path("/");
	268	if (!node)
	269	return;
	270	property = of_get_property(node, "model", NULL);
	271	if (!property)
	272	goto out_put;
	273	if (strcmp(property, "Pegasos2"))
	274	goto out_put;
	275	/* this is a Pegasos2 */
	276	property = of_get_property(of_chosen, "linux,stdout-path", NULL);
	277	if (!property)
	278	goto out_put;
	279	of_node_put(node);
	280	node = of_find_node_by_path(property);
	281	if (!node)
	282	return;
	283	property = of_get_property(node, "device_type", NULL);
	284	if (!property)
	285	goto out_put;
	286	if (strcmp(property, "serial"))
	287	goto out_put;
	288	/*
	289	* The 9pin connector is either /failsafe
	290	* or /pci@80000000/isa@C/serial@i2F8
	291	* The optional graphics card has also type 'serial' in VGA mode.
	292	*/
	293	property = of_get_property(node, "name", NULL);
	294	if (!property)
	295	goto out_put;
	296	if (!strcmp(property, "failsafe") \|\| !strcmp(property, "serial"))
	297	add_preferred_console("ttyS", 0, NULL);
	298	out_put:
	299	of_node_put(node);
	300	}
	301
bbd0abda PM	302	void __init chrp_setup_arch(void)
bbd0abda PM	303	{
8c8dc322	304	struct device_node *root = of_find_node_by_path("/");
ae6b4101	305	const char *machine = NULL;
bbd0abda PM	306
	307	/* init to some ~sane value until calibrate_delay() runs */
	308	loops_per_jiffy = 50000000/HZ;
	309
	310	if (root)
e2eb6392	311	machine = of_get_property(root, "model", NULL);
bbd0abda PM	312	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
	313	_chrp_type = _CHRP_Pegasos;
	314	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
	315	_chrp_type = _CHRP_IBM;
	316	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
	317	_chrp_type = _CHRP_Motorola;
26c5032e BH	318	} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
	319	_chrp_type = _CHRP_briq;
	320	/* Map the SPOR register on briq and change the restart hook */
9340b0d3	321	briq_SPOR = ioremap(0xff0000e8, 4);
26c5032e	322	ppc_md.restart = briq_restart;
bbd0abda PM	323	} else {
	324	/* Let's assume it is an IBM chrp if all else fails */
	325	_chrp_type = _CHRP_IBM;
	326	}
8c8dc322	327	of_node_put(root);
26c5032e	328	printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
bbd0abda PM	329
	330	rtas_initialize();
	331	if (rtas_token("display-character") >= 0)
	332	ppc_md.progress = rtas_progress;
	333
49e16b7b PM	334	/* use RTAS time-of-day routines if available */
	335	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
	336	ppc_md.get_boot_time = rtas_get_boot_time;
	337	ppc_md.get_rtc_time = rtas_get_rtc_time;
	338	ppc_md.set_rtc_time = rtas_set_rtc_time;
	339	}
	340
bbd0abda PM	341	/* On pegasos, enable the L2 cache if not already done by OF */
	342	pegasos_set_l2cr();
	343
	344	/* Lookup PCI host bridges */
	345	chrp_find_bridges();
	346
	347	/*
	348	* Temporary fixes for PCI devices.
	349	* -- Geert
	350	*/
	351	hydra_init(); /* Mac I/O */
	352
	353	/*
	354	* Fix the Super I/O configuration
	355	*/
	356	sio_init();
	357
bbd0abda PM	358	pci_create_OF_bus_map();
	359
	360	/*
	361	* Print the banner, then scroll down so boot progress
	362	* can be printed. -- Cort
	363	*/
	364	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
	365	}
	366
bd0b9ac4	367	static void chrp_8259_cascade(struct irq_desc *desc)
b9e5b4e6	368	{
ec775d0e	369	struct irq_chip *chip = irq_desc_get_chip(desc);
35a84c2f	370	unsigned int cascade_irq = i8259_irq();
468eb1ad	371
ef24ba70	372	if (cascade_irq)
49f19ce4	373	generic_handle_irq(cascade_irq);
468eb1ad LB	374
468eb1ad LB	375	chip->irq_eoi(&desc->irq_data);
b9e5b4e6 BH	376	}
b9e5b4e6 BH	377
bbd0abda PM	378	/*
	379	* Finds the open-pic node and sets up the mpic driver.
	380	*/
	381	static void __init chrp_find_openpic(void)
	382	{
	383	struct device_node np, root;
0ebfff14	384	int len, i, j;
bbd0abda	385	int isu_size, idu_size;
ae6b4101	386	const unsigned int iranges, opprop = NULL;
bbd0abda PM	387	int oplen = 0;
	388	unsigned long opaddr;
	389	int na = 1;
bbd0abda	390
0ebfff14	391	np = of_find_node_by_type(NULL, "open-pic");
bbd0abda PM	392	if (np == NULL)
bbd0abda PM	393	return;
0ebfff14	394	root = of_find_node_by_path("/");
bbd0abda	395	if (root) {
e2eb6392	396	opprop = of_get_property(root, "platform-open-pic", &oplen);
a8bda5dd	397	na = of_n_addr_cells(root);
bbd0abda PM	398	}
	399	if (opprop && oplen >= na * sizeof(unsigned int)) {
	400	opaddr = opprop[na-1]; /* assume 32-bit */
	401	oplen /= na * sizeof(unsigned int);
	402	} else {
575e3216	403	struct resource r;
0ebfff14 BH	404	if (of_address_to_resource(np, 0, &r)) {
	405	goto bail;
	406	}
575e3216	407	opaddr = r.start;
bbd0abda PM	408	oplen = 0;
	409	}
	410
	411	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
	412
e2eb6392	413	iranges = of_get_property(np, "interrupt-ranges", &len);
bbd0abda PM	414	if (iranges == NULL)
	415	len = 0; /* non-distributed mpic */
	416	else
	417	len /= 2 * sizeof(unsigned int);
	418
	419	/*
	420	* The first pair of cells in interrupt-ranges refers to the
	421	* IDU; subsequent pairs refer to the ISUs.
	422	*/
	423	if (oplen < len) {
	424	printk(KERN_ERR "Insufficient addresses for distributed"
575e3216	425	" OpenPIC (%d < %d)\n", oplen, len);
bbd0abda PM	426	len = oplen;
	427	}
	428
	429	isu_size = 0;
	430	idu_size = 0;
	431	if (len > 0 && iranges[1] != 0) {
	432	printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
	433	iranges[0], iranges[0] + iranges[1] - 1);
	434	idu_size = iranges[1];
	435	}
	436	if (len > 1)
	437	isu_size = iranges[3];
	438
e55d7f73 KM	439	chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
e55d7f73 KM	440	isu_size, 0, " MPIC ");
bbd0abda PM	441	if (chrp_mpic == NULL) {
bbd0abda PM	442	printk(KERN_ERR "Failed to allocate MPIC structure\n");
0ebfff14	443	goto bail;
bbd0abda	444	}
bbd0abda PM	445	j = na - 1;
	446	for (i = 1; i < len; ++i) {
	447	iranges += 2;
	448	j += na;
	449	printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
	450	iranges[0], iranges[0] + iranges[1] - 1,
	451	opprop[j]);
	452	mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
	453	}
	454
	455	mpic_init(chrp_mpic);
0ebfff14 BH	456	ppc_md.get_irq = mpic_get_irq;
	457	bail:
	458	of_node_put(root);
	459	of_node_put(np);
bbd0abda PM	460	}
bbd0abda PM	461
e85f008d	462	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
bbd0abda PM	463	static struct irqaction xmon_irqaction = {
bbd0abda PM	464	.handler = xmon_irq,
bbd0abda PM	465	.name = "XMON break",
	466	};
	467	#endif
	468
0ebfff14	469	static void __init chrp_find_8259(void)
bbd0abda	470	{
0ebfff14	471	struct device_node np, pic = NULL;
bbd0abda	472	unsigned long chrp_int_ack = 0;
0ebfff14	473	unsigned int cascade_irq;
bbd0abda	474
0ebfff14 BH	475	/* Look for cascade */
0ebfff14 BH	476	for_each_node_by_type(np, "interrupt-controller")
55b61fec	477	if (of_device_is_compatible(np, "chrp,iic")) {
0ebfff14 BH	478	pic = np;
	479	break;
	480	}
	481	/* Ok, 8259 wasn't found. We need to handle the case where
	482	* we have a pegasos that claims to be chrp but doesn't have
	483	* a proper interrupt tree
	484	*/
	485	if (pic == NULL && chrp_mpic != NULL) {
	486	printk(KERN_ERR "i8259: Not found in device-tree"
	487	" assuming no legacy interrupts\n");
	488	return;
	489	}
	490
	491	/* Look for intack. In a perfect world, we would look for it on
	492	* the ISA bus that holds the 8259 but heh... Works that way. If
	493	* we ever see a problem, we can try to re-use the pSeries code here.
	494	* Also, Pegasos-type platforms don't have a proper node to start
	495	* from anyway
	496	*/
30686ba6	497	for_each_node_by_name(np, "pci") {
e2eb6392	498	const unsigned int *addrp = of_get_property(np,
ae6b4101	499	"8259-interrupt-acknowledge", NULL);
bbd0abda PM	500
	501	if (addrp == NULL)
	502	continue;
a8bda5dd	503	chrp_int_ack = addrp[of_n_addr_cells(np)-1];
bbd0abda PM	504	break;
bbd0abda PM	505	}
30686ba6	506	of_node_put(np);
bbd0abda	507	if (np == NULL)
0ebfff14 BH	508	printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
	509	" address, polling\n");
	510
	511	i8259_init(pic, chrp_int_ack);
f4d4c354	512	if (ppc_md.get_irq == NULL) {
0ebfff14	513	ppc_md.get_irq = i8259_irq;
f4d4c354 BH	514	irq_set_default_host(i8259_get_host());
f4d4c354 BH	515	}
0ebfff14 BH	516	if (chrp_mpic != NULL) {
0ebfff14 BH	517	cascade_irq = irq_of_parse_and_map(pic, 0);
ef24ba70	518	if (!cascade_irq)
0ebfff14 BH	519	printk(KERN_ERR "i8259: failed to map cascade irq\n");
0ebfff14 BH	520	else
ec775d0e	521	irq_set_chained_handler(cascade_irq,
0ebfff14 BH	522	chrp_8259_cascade);
	523	}
	524	}
bbd0abda	525
0ebfff14 BH	526	void __init chrp_init_IRQ(void)
0ebfff14 BH	527	{
e85f008d	528	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
0ebfff14 BH	529	struct device_node *kbd;
0ebfff14 BH	530	#endif
bbd0abda	531	chrp_find_openpic();
0ebfff14	532	chrp_find_8259();
bbd0abda	533
1e031d65 BH	534	#ifdef CONFIG_SMP
	535	/* Pegasos has no MPIC, those ops would make it crash. It might be an
	536	* option to move setting them to after we probe the PIC though
	537	*/
	538	if (chrp_mpic != NULL)
	539	smp_ops = &chrp_smp_ops;
	540	#endif /* CONFIG_SMP */
	541
bbd0abda PM	542	if (_chrp_type == _CHRP_Pegasos)
bbd0abda PM	543	ppc_md.get_irq = i8259_irq;
bbd0abda	544
e85f008d	545	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
bbd0abda PM	546	/* see if there is a keyboard in the device tree
bbd0abda PM	547	with a parent of type "adb" */
30686ba6	548	for_each_node_by_name(kbd, "keyboard")
bbd0abda PM	549	if (kbd->parent && kbd->parent->type
	550	&& strcmp(kbd->parent->type, "adb") == 0)
	551	break;
30686ba6	552	of_node_put(kbd);
bbd0abda PM	553	if (kbd)
	554	setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
	555	#endif
	556	}
	557
	558	void __init
	559	chrp_init2(void)
	560	{
35e95e63 OH	561	#ifdef CONFIG_NVRAM
	562	chrp_nvram_init();
	563	#endif
	564
bbd0abda PM	565	request_region(0x20,0x20,"pic1");
	566	request_region(0xa0,0x20,"pic2");
	567	request_region(0x00,0x20,"dma1");
	568	request_region(0x40,0x20,"timer");
	569	request_region(0x80,0x10,"dma page reg");
	570	request_region(0xc0,0x20,"dma2");
	571
	572	if (ppc_md.progress)
	573	ppc_md.progress(" Have fun! ", 0x7777);
	574	}
	575
e8222502	576	static int __init chrp_probe(void)
bbd0abda	577	{
9d0c4dfe RH	578	const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
9d0c4dfe RH	579	"device_type", NULL);
e8222502 BH	580	if (dtype == NULL)
	581	return 0;
	582	if (strcmp(dtype, "chrp"))
	583	return 0;
	584
bbd0abda PM	585	ISA_DMA_THRESHOLD = ~0L;
	586	DMA_MODE_READ = 0x44;
	587	DMA_MODE_WRITE = 0x48;
bbd0abda	588
9178ba29 AG	589	pm_power_off = rtas_power_off;
9178ba29 AG	590
f2d57694 BH	591	chrp_init();
f2d57694 BH	592
b86756ae	593	return 1;
bbd0abda	594	}
b86756ae PM	595
	596	define_machine(chrp) {
	597	.name = "CHRP",
	598	.probe = chrp_probe,
	599	.setup_arch = chrp_setup_arch,
	600	.init = chrp_init2,
	601	.show_cpuinfo = chrp_show_cpuinfo,
	602	.init_IRQ = chrp_init_IRQ,
b86756ae	603	.restart = rtas_restart,
b86756ae PM	604	.halt = rtas_halt,
	605	.time_init = chrp_time_init,
	606	.set_rtc_time = chrp_set_rtc_time,
	607	.get_rtc_time = chrp_get_rtc_time,
	608	.calibrate_decr = generic_calibrate_decr,
	609	.phys_mem_access_prot = pci_phys_mem_access_prot,
	610	};