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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
9c21025c AH |
2 | /* |
3 | * arch/powerpc/platforms/embedded6xx/hlwd-pic.c | |
4 | * | |
5 | * Nintendo Wii "Hollywood" interrupt controller support. | |
6 | * Copyright (C) 2009 The GameCube Linux Team | |
7 | * Copyright (C) 2009 Albert Herranz | |
9c21025c AH |
8 | */ |
9 | #define DRV_MODULE_NAME "hlwd-pic" | |
10 | #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt | |
11 | ||
12 | #include <linux/kernel.h> | |
9c21025c AH |
13 | #include <linux/irq.h> |
14 | #include <linux/of.h> | |
26a2056e RH |
15 | #include <linux/of_address.h> |
16 | #include <linux/of_irq.h> | |
9c21025c AH |
17 | #include <asm/io.h> |
18 | ||
19 | #include "hlwd-pic.h" | |
20 | ||
21 | #define HLWD_NR_IRQS 32 | |
22 | ||
23 | /* | |
24 | * Each interrupt has a corresponding bit in both | |
25 | * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers. | |
26 | * | |
27 | * Enabling/disabling an interrupt line involves asserting/clearing | |
28 | * the corresponding bit in IMR. ACK'ing a request simply involves | |
29 | * asserting the corresponding bit in ICR. | |
30 | */ | |
31 | #define HW_BROADWAY_ICR 0x00 | |
32 | #define HW_BROADWAY_IMR 0x04 | |
9dcb3df4 JN |
33 | #define HW_STARLET_ICR 0x08 |
34 | #define HW_STARLET_IMR 0x0c | |
9c21025c AH |
35 | |
36 | ||
37 | /* | |
38 | * IRQ chip hooks. | |
39 | * | |
40 | */ | |
41 | ||
0bf8878e | 42 | static void hlwd_pic_mask_and_ack(struct irq_data *d) |
9c21025c | 43 | { |
476eb491 | 44 | int irq = irqd_to_hwirq(d); |
0bf8878e | 45 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
9c21025c AH |
46 | u32 mask = 1 << irq; |
47 | ||
48 | clrbits32(io_base + HW_BROADWAY_IMR, mask); | |
49 | out_be32(io_base + HW_BROADWAY_ICR, mask); | |
50 | } | |
51 | ||
0bf8878e | 52 | static void hlwd_pic_ack(struct irq_data *d) |
9c21025c | 53 | { |
476eb491 | 54 | int irq = irqd_to_hwirq(d); |
0bf8878e | 55 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
9c21025c AH |
56 | |
57 | out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); | |
58 | } | |
59 | ||
0bf8878e | 60 | static void hlwd_pic_mask(struct irq_data *d) |
9c21025c | 61 | { |
476eb491 | 62 | int irq = irqd_to_hwirq(d); |
0bf8878e | 63 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
9c21025c AH |
64 | |
65 | clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); | |
66 | } | |
67 | ||
0bf8878e | 68 | static void hlwd_pic_unmask(struct irq_data *d) |
9c21025c | 69 | { |
476eb491 | 70 | int irq = irqd_to_hwirq(d); |
0bf8878e | 71 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
9c21025c AH |
72 | |
73 | setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); | |
9dcb3df4 JN |
74 | |
75 | /* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */ | |
76 | clrbits32(io_base + HW_STARLET_IMR, 1 << irq); | |
9c21025c AH |
77 | } |
78 | ||
79 | ||
80 | static struct irq_chip hlwd_pic = { | |
81 | .name = "hlwd-pic", | |
0bf8878e LB |
82 | .irq_ack = hlwd_pic_ack, |
83 | .irq_mask_ack = hlwd_pic_mask_and_ack, | |
84 | .irq_mask = hlwd_pic_mask, | |
85 | .irq_unmask = hlwd_pic_unmask, | |
9c21025c AH |
86 | }; |
87 | ||
88 | /* | |
89 | * IRQ host hooks. | |
90 | * | |
91 | */ | |
92 | ||
bae1d8f1 | 93 | static struct irq_domain *hlwd_irq_host; |
9c21025c | 94 | |
bae1d8f1 | 95 | static int hlwd_pic_map(struct irq_domain *h, unsigned int virq, |
9c21025c AH |
96 | irq_hw_number_t hwirq) |
97 | { | |
ec775d0e | 98 | irq_set_chip_data(virq, h->host_data); |
98488db9 | 99 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e | 100 | irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq); |
9c21025c AH |
101 | return 0; |
102 | } | |
103 | ||
9f70b8eb | 104 | static const struct irq_domain_ops hlwd_irq_domain_ops = { |
9c21025c | 105 | .map = hlwd_pic_map, |
9c21025c AH |
106 | }; |
107 | ||
bae1d8f1 | 108 | static unsigned int __hlwd_pic_get_irq(struct irq_domain *h) |
9c21025c AH |
109 | { |
110 | void __iomem *io_base = h->host_data; | |
111 | int irq; | |
112 | u32 irq_status; | |
113 | ||
114 | irq_status = in_be32(io_base + HW_BROADWAY_ICR) & | |
115 | in_be32(io_base + HW_BROADWAY_IMR); | |
116 | if (irq_status == 0) | |
ef24ba70 | 117 | return 0; /* no more IRQs pending */ |
9c21025c AH |
118 | |
119 | irq = __ffs(irq_status); | |
120 | return irq_linear_revmap(h, irq); | |
121 | } | |
122 | ||
bd0b9ac4 | 123 | static void hlwd_pic_irq_cascade(struct irq_desc *desc) |
9c21025c | 124 | { |
ec775d0e | 125 | struct irq_chip *chip = irq_desc_get_chip(desc); |
c1231a78 | 126 | struct irq_domain *irq_domain = irq_desc_get_handler_data(desc); |
9c21025c AH |
127 | unsigned int virq; |
128 | ||
7ccec3e7 | 129 | raw_spin_lock(&desc->lock); |
0bf8878e | 130 | chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */ |
7ccec3e7 | 131 | raw_spin_unlock(&desc->lock); |
9c21025c | 132 | |
bae1d8f1 | 133 | virq = __hlwd_pic_get_irq(irq_domain); |
ef24ba70 | 134 | if (virq) |
9c21025c AH |
135 | generic_handle_irq(virq); |
136 | else | |
137 | pr_err("spurious interrupt!\n"); | |
138 | ||
7ccec3e7 | 139 | raw_spin_lock(&desc->lock); |
0bf8878e | 140 | chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ |
98488db9 | 141 | if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask) |
0bf8878e | 142 | chip->irq_unmask(&desc->irq_data); |
7ccec3e7 | 143 | raw_spin_unlock(&desc->lock); |
9c21025c AH |
144 | } |
145 | ||
146 | /* | |
147 | * Platform hooks. | |
148 | * | |
149 | */ | |
150 | ||
151 | static void __hlwd_quiesce(void __iomem *io_base) | |
152 | { | |
153 | /* mask and ack all IRQs */ | |
154 | out_be32(io_base + HW_BROADWAY_IMR, 0); | |
155 | out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff); | |
156 | } | |
157 | ||
eed6964b | 158 | static struct irq_domain *hlwd_pic_init(struct device_node *np) |
9c21025c | 159 | { |
bae1d8f1 | 160 | struct irq_domain *irq_domain; |
9c21025c AH |
161 | struct resource res; |
162 | void __iomem *io_base; | |
163 | int retval; | |
164 | ||
165 | retval = of_address_to_resource(np, 0, &res); | |
166 | if (retval) { | |
167 | pr_err("no io memory range found\n"); | |
168 | return NULL; | |
169 | } | |
170 | io_base = ioremap(res.start, resource_size(&res)); | |
171 | if (!io_base) { | |
172 | pr_err("ioremap failed\n"); | |
173 | return NULL; | |
174 | } | |
175 | ||
176 | pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); | |
177 | ||
178 | __hlwd_quiesce(io_base); | |
179 | ||
a8db8cf0 GL |
180 | irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS, |
181 | &hlwd_irq_domain_ops, io_base); | |
bae1d8f1 GL |
182 | if (!irq_domain) { |
183 | pr_err("failed to allocate irq_domain\n"); | |
8d7c0b52 | 184 | iounmap(io_base); |
9c21025c AH |
185 | return NULL; |
186 | } | |
9c21025c | 187 | |
bae1d8f1 | 188 | return irq_domain; |
9c21025c AH |
189 | } |
190 | ||
191 | unsigned int hlwd_pic_get_irq(void) | |
192 | { | |
6d166fec | 193 | return __hlwd_pic_get_irq(hlwd_irq_host); |
9c21025c AH |
194 | } |
195 | ||
196 | /* | |
197 | * Probe function. | |
198 | * | |
199 | */ | |
200 | ||
201 | void hlwd_pic_probe(void) | |
202 | { | |
bae1d8f1 | 203 | struct irq_domain *host; |
9c21025c AH |
204 | struct device_node *np; |
205 | const u32 *interrupts; | |
206 | int cascade_virq; | |
207 | ||
208 | for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") { | |
209 | interrupts = of_get_property(np, "interrupts", NULL); | |
210 | if (interrupts) { | |
211 | host = hlwd_pic_init(np); | |
212 | BUG_ON(!host); | |
213 | cascade_virq = irq_of_parse_and_map(np, 0); | |
ec775d0e TG |
214 | irq_set_handler_data(cascade_virq, host); |
215 | irq_set_chained_handler(cascade_virq, | |
9c21025c | 216 | hlwd_pic_irq_cascade); |
6d166fec | 217 | hlwd_irq_host = host; |
9c21025c AH |
218 | break; |
219 | } | |
220 | } | |
221 | } | |
222 | ||
223 | /** | |
224 | * hlwd_quiesce() - quiesce hollywood irq controller | |
225 | * | |
226 | * Mask and ack all interrupt sources. | |
227 | * | |
228 | */ | |
229 | void hlwd_quiesce(void) | |
230 | { | |
6d166fec | 231 | void __iomem *io_base = hlwd_irq_host->host_data; |
9c21025c AH |
232 | |
233 | __hlwd_quiesce(io_base); | |
234 | } | |
235 |