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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
3 | * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> | |
4 | * | |
1da177e4 LT |
5 | * Description: |
6 | * Architecture- / platform-specific boot-time initialization code for | |
7 | * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and | |
8 | * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek | |
9 | * <dan@net4x.com>. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #undef DEBUG | |
18 | ||
1da177e4 LT |
19 | #include <linux/init.h> |
20 | #include <linux/threads.h> | |
21 | #include <linux/smp.h> | |
22 | #include <linux/param.h> | |
23 | #include <linux/string.h> | |
1da177e4 LT |
24 | #include <linux/initrd.h> |
25 | #include <linux/seq_file.h> | |
26 | #include <linux/kdev_t.h> | |
27 | #include <linux/major.h> | |
28 | #include <linux/root_dev.h> | |
bec7c458 | 29 | #include <linux/kernel.h> |
1da177e4 LT |
30 | |
31 | #include <asm/processor.h> | |
32 | #include <asm/machdep.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/mmu.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/mmu_context.h> | |
37 | #include <asm/cputable.h> | |
38 | #include <asm/sections.h> | |
39 | #include <asm/iommu.h> | |
aed31351 | 40 | #include <asm/firmware.h> |
49b09853 | 41 | #include <asm/system.h> |
1da177e4 | 42 | #include <asm/time.h> |
1da177e4 LT |
43 | #include <asm/paca.h> |
44 | #include <asm/cache.h> | |
45 | #include <asm/sections.h> | |
0bc0ffd5 | 46 | #include <asm/abs_addr.h> |
15b17189 | 47 | #include <asm/iseries/hv_lp_config.h> |
c0a8d05c | 48 | #include <asm/iseries/hv_call_event.h> |
8021b8a7 | 49 | #include <asm/iseries/hv_call_xm.h> |
8875ccfb | 50 | #include <asm/iseries/it_lp_queue.h> |
bbc8b628 | 51 | #include <asm/iseries/mf.h> |
e45423ea | 52 | #include <asm/iseries/hv_lp_event.h> |
c43a55ff | 53 | #include <asm/iseries/lpar_map.h> |
bf6a7112 | 54 | #include <asm/udbg.h> |
7d01c880 | 55 | #include <asm/irq.h> |
1da177e4 | 56 | |
f11b7bd8 | 57 | #include "naca.h" |
c8b84976 | 58 | #include "setup.h" |
b08567cb SR |
59 | #include "irq.h" |
60 | #include "vpd_areas.h" | |
61 | #include "processor_vpd.h" | |
62 | #include "main_store.h" | |
63 | #include "call_sm.h" | |
0e29bb1a | 64 | #include "call_hpt.h" |
c8b84976 | 65 | |
1da177e4 | 66 | #ifdef DEBUG |
bf6a7112 | 67 | #define DBG(fmt...) udbg_printf(fmt) |
1da177e4 LT |
68 | #else |
69 | #define DBG(fmt...) | |
70 | #endif | |
71 | ||
72 | /* Function Prototypes */ | |
799d6046 | 73 | static unsigned long build_iSeries_Memory_Map(void); |
143a1dec PM |
74 | static void iseries_shared_idle(void); |
75 | static void iseries_dedicated_idle(void); | |
145d01e4 | 76 | #ifdef CONFIG_PCI |
1da177e4 | 77 | extern void iSeries_pci_final_fixup(void); |
145d01e4 SR |
78 | #else |
79 | static void iSeries_pci_final_fixup(void) { } | |
80 | #endif | |
1da177e4 | 81 | |
1da177e4 | 82 | extern int rd_size; /* Defined in drivers/block/rd.c */ |
1da177e4 LT |
83 | |
84 | extern unsigned long iSeries_recal_tb; | |
85 | extern unsigned long iSeries_recal_titan; | |
86 | ||
1da177e4 LT |
87 | struct MemoryBlock { |
88 | unsigned long absStart; | |
89 | unsigned long absEnd; | |
90 | unsigned long logicalStart; | |
91 | unsigned long logicalEnd; | |
92 | }; | |
93 | ||
94 | /* | |
95 | * Process the main store vpd to determine where the holes in memory are | |
96 | * and return the number of physical blocks and fill in the array of | |
97 | * block data. | |
98 | */ | |
99 | static unsigned long iSeries_process_Condor_mainstore_vpd( | |
100 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
101 | { | |
102 | unsigned long holeFirstChunk, holeSizeChunks; | |
103 | unsigned long numMemoryBlocks = 1; | |
104 | struct IoHriMainStoreSegment4 *msVpd = | |
105 | (struct IoHriMainStoreSegment4 *)xMsVpd; | |
106 | unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr; | |
107 | unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr; | |
108 | unsigned long holeSize = holeEnd - holeStart; | |
109 | ||
110 | printk("Mainstore_VPD: Condor\n"); | |
111 | /* | |
112 | * Determine if absolute memory has any | |
113 | * holes so that we can interpret the | |
114 | * access map we get back from the hypervisor | |
115 | * correctly. | |
116 | */ | |
117 | mb_array[0].logicalStart = 0; | |
118 | mb_array[0].logicalEnd = 0x100000000; | |
119 | mb_array[0].absStart = 0; | |
120 | mb_array[0].absEnd = 0x100000000; | |
121 | ||
122 | if (holeSize) { | |
123 | numMemoryBlocks = 2; | |
124 | holeStart = holeStart & 0x000fffffffffffff; | |
125 | holeStart = addr_to_chunk(holeStart); | |
126 | holeFirstChunk = holeStart; | |
127 | holeSize = addr_to_chunk(holeSize); | |
128 | holeSizeChunks = holeSize; | |
129 | printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n", | |
130 | holeFirstChunk, holeSizeChunks ); | |
131 | mb_array[0].logicalEnd = holeFirstChunk; | |
132 | mb_array[0].absEnd = holeFirstChunk; | |
133 | mb_array[1].logicalStart = holeFirstChunk; | |
134 | mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks; | |
135 | mb_array[1].absStart = holeFirstChunk + holeSizeChunks; | |
136 | mb_array[1].absEnd = 0x100000000; | |
137 | } | |
138 | return numMemoryBlocks; | |
139 | } | |
140 | ||
141 | #define MaxSegmentAreas 32 | |
142 | #define MaxSegmentAdrRangeBlocks 128 | |
143 | #define MaxAreaRangeBlocks 4 | |
144 | ||
145 | static unsigned long iSeries_process_Regatta_mainstore_vpd( | |
146 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
147 | { | |
148 | struct IoHriMainStoreSegment5 *msVpdP = | |
149 | (struct IoHriMainStoreSegment5 *)xMsVpd; | |
150 | unsigned long numSegmentBlocks = 0; | |
151 | u32 existsBits = msVpdP->msAreaExists; | |
152 | unsigned long area_num; | |
153 | ||
154 | printk("Mainstore_VPD: Regatta\n"); | |
155 | ||
156 | for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) { | |
157 | unsigned long numAreaBlocks; | |
158 | struct IoHriMainStoreArea4 *currentArea; | |
159 | ||
160 | if (existsBits & 0x80000000) { | |
161 | unsigned long block_num; | |
162 | ||
163 | currentArea = &msVpdP->msAreaArray[area_num]; | |
164 | numAreaBlocks = currentArea->numAdrRangeBlocks; | |
165 | printk("ms_vpd: processing area %2ld blocks=%ld", | |
166 | area_num, numAreaBlocks); | |
167 | for (block_num = 0; block_num < numAreaBlocks; | |
168 | ++block_num ) { | |
169 | /* Process an address range block */ | |
170 | struct MemoryBlock tempBlock; | |
171 | unsigned long i; | |
172 | ||
173 | tempBlock.absStart = | |
174 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart; | |
175 | tempBlock.absEnd = | |
176 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd; | |
177 | tempBlock.logicalStart = 0; | |
178 | tempBlock.logicalEnd = 0; | |
179 | printk("\n block %ld absStart=%016lx absEnd=%016lx", | |
180 | block_num, tempBlock.absStart, | |
181 | tempBlock.absEnd); | |
182 | ||
183 | for (i = 0; i < numSegmentBlocks; ++i) { | |
184 | if (mb_array[i].absStart == | |
185 | tempBlock.absStart) | |
186 | break; | |
187 | } | |
188 | if (i == numSegmentBlocks) { | |
189 | if (numSegmentBlocks == max_entries) | |
190 | panic("iSeries_process_mainstore_vpd: too many memory blocks"); | |
191 | mb_array[numSegmentBlocks] = tempBlock; | |
192 | ++numSegmentBlocks; | |
193 | } else | |
194 | printk(" (duplicate)"); | |
195 | } | |
196 | printk("\n"); | |
197 | } | |
198 | existsBits <<= 1; | |
199 | } | |
200 | /* Now sort the blocks found into ascending sequence */ | |
201 | if (numSegmentBlocks > 1) { | |
202 | unsigned long m, n; | |
203 | ||
204 | for (m = 0; m < numSegmentBlocks - 1; ++m) { | |
205 | for (n = numSegmentBlocks - 1; m < n; --n) { | |
206 | if (mb_array[n].absStart < | |
207 | mb_array[n-1].absStart) { | |
208 | struct MemoryBlock tempBlock; | |
209 | ||
210 | tempBlock = mb_array[n]; | |
211 | mb_array[n] = mb_array[n-1]; | |
212 | mb_array[n-1] = tempBlock; | |
213 | } | |
214 | } | |
215 | } | |
216 | } | |
217 | /* | |
218 | * Assign "logical" addresses to each block. These | |
219 | * addresses correspond to the hypervisor "bitmap" space. | |
220 | * Convert all addresses into units of 256K chunks. | |
221 | */ | |
222 | { | |
223 | unsigned long i, nextBitmapAddress; | |
224 | ||
225 | printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks); | |
226 | nextBitmapAddress = 0; | |
227 | for (i = 0; i < numSegmentBlocks; ++i) { | |
228 | unsigned long length = mb_array[i].absEnd - | |
229 | mb_array[i].absStart; | |
230 | ||
231 | mb_array[i].logicalStart = nextBitmapAddress; | |
232 | mb_array[i].logicalEnd = nextBitmapAddress + length; | |
233 | nextBitmapAddress += length; | |
234 | printk(" Bitmap range: %016lx - %016lx\n" | |
235 | " Absolute range: %016lx - %016lx\n", | |
236 | mb_array[i].logicalStart, | |
237 | mb_array[i].logicalEnd, | |
238 | mb_array[i].absStart, mb_array[i].absEnd); | |
239 | mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart & | |
240 | 0x000fffffffffffff); | |
241 | mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd & | |
242 | 0x000fffffffffffff); | |
243 | mb_array[i].logicalStart = | |
244 | addr_to_chunk(mb_array[i].logicalStart); | |
245 | mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd); | |
246 | } | |
247 | } | |
248 | ||
249 | return numSegmentBlocks; | |
250 | } | |
251 | ||
252 | static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array, | |
253 | unsigned long max_entries) | |
254 | { | |
255 | unsigned long i; | |
256 | unsigned long mem_blocks = 0; | |
257 | ||
258 | if (cpu_has_feature(CPU_FTR_SLB)) | |
259 | mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array, | |
260 | max_entries); | |
261 | else | |
262 | mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array, | |
263 | max_entries); | |
264 | ||
265 | printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks); | |
266 | for (i = 0; i < mem_blocks; ++i) { | |
267 | printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n" | |
268 | " abs chunks %016lx - %016lx\n", | |
269 | i, mb_array[i].logicalStart, mb_array[i].logicalEnd, | |
270 | mb_array[i].absStart, mb_array[i].absEnd); | |
271 | } | |
272 | return mem_blocks; | |
273 | } | |
274 | ||
275 | static void __init iSeries_get_cmdline(void) | |
276 | { | |
277 | char *p, *q; | |
278 | ||
279 | /* copy the command line parameter from the primary VSP */ | |
280 | HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256, | |
281 | HvLpDma_Direction_RemoteToLocal); | |
282 | ||
283 | p = cmd_line; | |
284 | q = cmd_line + 255; | |
285 | while(p < q) { | |
286 | if (!*p || *p == '\n') | |
287 | break; | |
288 | ++p; | |
289 | } | |
290 | *p = 0; | |
291 | } | |
292 | ||
293 | static void __init iSeries_init_early(void) | |
294 | { | |
1da177e4 LT |
295 | DBG(" -> iSeries_init_early()\n"); |
296 | ||
1da177e4 LT |
297 | #if defined(CONFIG_BLK_DEV_INITRD) |
298 | /* | |
299 | * If the init RAM disk has been configured and there is | |
300 | * a non-zero starting address for it, set it up | |
301 | */ | |
302 | if (naca.xRamDisk) { | |
303 | initrd_start = (unsigned long)__va(naca.xRamDisk); | |
3c726f8d | 304 | initrd_end = initrd_start + naca.xRamDiskSize * HW_PAGE_SIZE; |
1da177e4 LT |
305 | initrd_below_start_ok = 1; // ramdisk in kernel space |
306 | ROOT_DEV = Root_RAM0; | |
3c726f8d BH |
307 | if (((rd_size * 1024) / HW_PAGE_SIZE) < naca.xRamDiskSize) |
308 | rd_size = (naca.xRamDiskSize * HW_PAGE_SIZE) / 1024; | |
1da177e4 LT |
309 | } else |
310 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
311 | { | |
312 | /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */ | |
313 | } | |
314 | ||
315 | iSeries_recal_tb = get_tb(); | |
316 | iSeries_recal_titan = HvCallXm_loadTod(); | |
317 | ||
1da177e4 LT |
318 | /* |
319 | * Initialize the DMA/TCE management | |
320 | */ | |
321 | iommu_init_early_iSeries(); | |
322 | ||
1da177e4 LT |
323 | /* Initialize machine-dependency vectors */ |
324 | #ifdef CONFIG_SMP | |
325 | smp_init_iSeries(); | |
326 | #endif | |
1da177e4 LT |
327 | |
328 | /* Associate Lp Event Queue 0 with processor 0 */ | |
329 | HvCallEvent_setLpEventQueueInterruptProc(0, 0); | |
330 | ||
331 | mf_init(); | |
1da177e4 LT |
332 | |
333 | /* If we were passed an initrd, set the ROOT_DEV properly if the values | |
334 | * look sensible. If not, clear initrd reference. | |
335 | */ | |
336 | #ifdef CONFIG_BLK_DEV_INITRD | |
337 | if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE && | |
338 | initrd_end > initrd_start) | |
339 | ROOT_DEV = Root_RAM0; | |
340 | else | |
341 | initrd_start = initrd_end = 0; | |
342 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
343 | ||
344 | DBG(" <- iSeries_init_early()\n"); | |
345 | } | |
346 | ||
56e97b71 | 347 | struct mschunks_map mschunks_map = { |
34c8f696 ME |
348 | /* XXX We don't use these, but Piranha might need them. */ |
349 | .chunk_size = MSCHUNKS_CHUNK_SIZE, | |
350 | .chunk_shift = MSCHUNKS_CHUNK_SHIFT, | |
351 | .chunk_mask = MSCHUNKS_OFFSET_MASK, | |
352 | }; | |
56e97b71 | 353 | EXPORT_SYMBOL(mschunks_map); |
34c8f696 | 354 | |
56e97b71 | 355 | void mschunks_alloc(unsigned long num_chunks) |
34c8f696 ME |
356 | { |
357 | klimit = _ALIGN(klimit, sizeof(u32)); | |
56e97b71 | 358 | mschunks_map.mapping = (u32 *)klimit; |
34c8f696 | 359 | klimit += num_chunks * sizeof(u32); |
56e97b71 | 360 | mschunks_map.num_chunks = num_chunks; |
34c8f696 ME |
361 | } |
362 | ||
1da177e4 LT |
363 | /* |
364 | * The iSeries may have very large memories ( > 128 GB ) and a partition | |
365 | * may get memory in "chunks" that may be anywhere in the 2**52 real | |
366 | * address space. The chunks are 256K in size. To map this to the | |
367 | * memory model Linux expects, the AS/400 specific code builds a | |
368 | * translation table to translate what Linux thinks are "physical" | |
369 | * addresses to the actual real addresses. This allows us to make | |
370 | * it appear to Linux that we have contiguous memory starting at | |
371 | * physical address zero while in fact this could be far from the truth. | |
372 | * To avoid confusion, I'll let the words physical and/or real address | |
373 | * apply to the Linux addresses while I'll use "absolute address" to | |
374 | * refer to the actual hardware real address. | |
375 | * | |
376 | * build_iSeries_Memory_Map gets information from the Hypervisor and | |
377 | * looks at the Main Store VPD to determine the absolute addresses | |
378 | * of the memory that has been assigned to our partition and builds | |
379 | * a table used to translate Linux's physical addresses to these | |
380 | * absolute addresses. Absolute addresses are needed when | |
381 | * communicating with the hypervisor (e.g. to build HPT entries) | |
799d6046 PM |
382 | * |
383 | * Returns the physical memory size | |
1da177e4 LT |
384 | */ |
385 | ||
799d6046 | 386 | static unsigned long __init build_iSeries_Memory_Map(void) |
1da177e4 LT |
387 | { |
388 | u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize; | |
389 | u32 nextPhysChunk; | |
390 | u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages; | |
1da177e4 LT |
391 | u32 totalChunks,moreChunks; |
392 | u32 currChunk, thisChunk, absChunk; | |
393 | u32 currDword; | |
394 | u32 chunkBit; | |
395 | u64 map; | |
396 | struct MemoryBlock mb[32]; | |
397 | unsigned long numMemoryBlocks, curBlock; | |
398 | ||
399 | /* Chunk size on iSeries is 256K bytes */ | |
400 | totalChunks = (u32)HvLpConfig_getMsChunks(); | |
56e97b71 | 401 | mschunks_alloc(totalChunks); |
1da177e4 LT |
402 | |
403 | /* | |
404 | * Get absolute address of our load area | |
405 | * and map it to physical address 0 | |
406 | * This guarantees that the loadarea ends up at physical 0 | |
407 | * otherwise, it might not be returned by PLIC as the first | |
408 | * chunks | |
409 | */ | |
410 | ||
411 | loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr); | |
412 | loadAreaSize = itLpNaca.xLoadAreaChunks; | |
413 | ||
414 | /* | |
415 | * Only add the pages already mapped here. | |
416 | * Otherwise we might add the hpt pages | |
417 | * The rest of the pages of the load area | |
418 | * aren't in the HPT yet and can still | |
419 | * be assigned an arbitrary physical address | |
420 | */ | |
421 | if ((loadAreaSize * 64) > HvPagesToMap) | |
422 | loadAreaSize = HvPagesToMap / 64; | |
423 | ||
424 | loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1; | |
425 | ||
426 | /* | |
427 | * TODO Do we need to do something if the HPT is in the 64MB load area? | |
428 | * This would be required if the itLpNaca.xLoadAreaChunks includes | |
429 | * the HPT size | |
430 | */ | |
431 | ||
432 | printk("Mapping load area - physical addr = 0000000000000000\n" | |
433 | " absolute addr = %016lx\n", | |
434 | chunk_to_addr(loadAreaFirstChunk)); | |
435 | printk("Load area size %dK\n", loadAreaSize * 256); | |
436 | ||
437 | for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk) | |
56e97b71 | 438 | mschunks_map.mapping[nextPhysChunk] = |
1da177e4 LT |
439 | loadAreaFirstChunk + nextPhysChunk; |
440 | ||
441 | /* | |
442 | * Get absolute address of our HPT and remember it so | |
443 | * we won't map it to any physical address | |
444 | */ | |
445 | hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress()); | |
446 | hptSizePages = (u32)HvCallHpt_getHptPages(); | |
3c726f8d BH |
447 | hptSizeChunks = hptSizePages >> |
448 | (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT); | |
1da177e4 LT |
449 | hptLastChunk = hptFirstChunk + hptSizeChunks - 1; |
450 | ||
451 | printk("HPT absolute addr = %016lx, size = %dK\n", | |
452 | chunk_to_addr(hptFirstChunk), hptSizeChunks * 256); | |
453 | ||
1da177e4 LT |
454 | /* |
455 | * Determine if absolute memory has any | |
456 | * holes so that we can interpret the | |
457 | * access map we get back from the hypervisor | |
458 | * correctly. | |
459 | */ | |
460 | numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32); | |
461 | ||
462 | /* | |
463 | * Process the main store access map from the hypervisor | |
464 | * to build up our physical -> absolute translation table | |
465 | */ | |
466 | curBlock = 0; | |
467 | currChunk = 0; | |
468 | currDword = 0; | |
469 | moreChunks = totalChunks; | |
470 | ||
471 | while (moreChunks) { | |
472 | map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex, | |
473 | currDword); | |
474 | thisChunk = currChunk; | |
475 | while (map) { | |
476 | chunkBit = map >> 63; | |
477 | map <<= 1; | |
478 | if (chunkBit) { | |
479 | --moreChunks; | |
480 | while (thisChunk >= mb[curBlock].logicalEnd) { | |
481 | ++curBlock; | |
482 | if (curBlock >= numMemoryBlocks) | |
483 | panic("out of memory blocks"); | |
484 | } | |
485 | if (thisChunk < mb[curBlock].logicalStart) | |
486 | panic("memory block error"); | |
487 | ||
488 | absChunk = mb[curBlock].absStart + | |
489 | (thisChunk - mb[curBlock].logicalStart); | |
490 | if (((absChunk < hptFirstChunk) || | |
491 | (absChunk > hptLastChunk)) && | |
492 | ((absChunk < loadAreaFirstChunk) || | |
493 | (absChunk > loadAreaLastChunk))) { | |
56e97b71 ME |
494 | mschunks_map.mapping[nextPhysChunk] = |
495 | absChunk; | |
1da177e4 LT |
496 | ++nextPhysChunk; |
497 | } | |
498 | } | |
499 | ++thisChunk; | |
500 | } | |
501 | ++currDword; | |
502 | currChunk += 64; | |
503 | } | |
504 | ||
505 | /* | |
506 | * main store size (in chunks) is | |
507 | * totalChunks - hptSizeChunks | |
508 | * which should be equal to | |
509 | * nextPhysChunk | |
510 | */ | |
799d6046 | 511 | return chunk_to_addr(nextPhysChunk); |
1da177e4 LT |
512 | } |
513 | ||
1da177e4 LT |
514 | /* |
515 | * Document me. | |
516 | */ | |
517 | static void __init iSeries_setup_arch(void) | |
518 | { | |
3356bb9f | 519 | if (get_lppaca()->shared_proc) { |
9f497581 | 520 | ppc_md.idle_loop = iseries_shared_idle; |
4baaf0cf | 521 | printk(KERN_DEBUG "Using shared processor idle loop\n"); |
9f497581 ME |
522 | } else { |
523 | ppc_md.idle_loop = iseries_dedicated_idle; | |
4baaf0cf | 524 | printk(KERN_DEBUG "Using dedicated idle loop\n"); |
9f497581 ME |
525 | } |
526 | ||
1da177e4 | 527 | /* Setup the Lp Event Queue */ |
512d31d6 | 528 | setup_hvlpevent_queue(); |
1da177e4 | 529 | |
1da177e4 LT |
530 | printk("Max logical processors = %d\n", |
531 | itVpdAreas.xSlicMaxLogicalProcs); | |
532 | printk("Max physical processors = %d\n", | |
533 | itVpdAreas.xSlicMaxPhysicalProcs); | |
1da177e4 LT |
534 | } |
535 | ||
d8699e65 | 536 | static void iSeries_show_cpuinfo(struct seq_file *m) |
1da177e4 LT |
537 | { |
538 | seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n"); | |
539 | } | |
540 | ||
1da177e4 LT |
541 | static void __init iSeries_progress(char * st, unsigned short code) |
542 | { | |
543 | printk("Progress: [%04x] - %s\n", (unsigned)code, st); | |
260de22f | 544 | mf_display_progress(code); |
1da177e4 LT |
545 | } |
546 | ||
547 | static void __init iSeries_fixup_klimit(void) | |
548 | { | |
549 | /* | |
550 | * Change klimit to take into account any ram disk | |
551 | * that may be included | |
552 | */ | |
553 | if (naca.xRamDisk) | |
554 | klimit = KERNELBASE + (u64)naca.xRamDisk + | |
3c726f8d | 555 | (naca.xRamDiskSize * HW_PAGE_SIZE); |
1da177e4 LT |
556 | } |
557 | ||
558 | static int __init iSeries_src_init(void) | |
559 | { | |
560 | /* clear the progress line */ | |
561 | ppc_md.progress(" ", 0xffff); | |
562 | return 0; | |
563 | } | |
564 | ||
565 | late_initcall(iSeries_src_init); | |
566 | ||
d200903e ME |
567 | static inline void process_iSeries_events(void) |
568 | { | |
569 | asm volatile ("li 0,0x5555; sc" : : : "r0", "r3"); | |
570 | } | |
571 | ||
572 | static void yield_shared_processor(void) | |
573 | { | |
574 | unsigned long tb; | |
d200903e ME |
575 | |
576 | HvCall_setEnabledInterrupts(HvCall_MaskIPI | | |
577 | HvCall_MaskLpEvent | | |
578 | HvCall_MaskLpProd | | |
579 | HvCall_MaskTimeout); | |
580 | ||
581 | tb = get_tb(); | |
582 | /* Compute future tb value when yield should expire */ | |
583 | HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy); | |
584 | ||
d200903e ME |
585 | /* |
586 | * The decrementer stops during the yield. Force a fake decrementer | |
587 | * here and let the timer_interrupt code sort out the actual time. | |
588 | */ | |
3356bb9f | 589 | get_lppaca()->int_dword.fields.decr_int = 1; |
cb2c9b27 | 590 | ppc64_runlatch_on(); |
d200903e ME |
591 | process_iSeries_events(); |
592 | } | |
593 | ||
143a1dec | 594 | static void iseries_shared_idle(void) |
d200903e | 595 | { |
3c57bb9f AB |
596 | while (1) { |
597 | while (!need_resched() && !hvlpevent_is_pending()) { | |
598 | local_irq_disable(); | |
599 | ppc64_runlatch_off(); | |
600 | ||
601 | /* Recheck with irqs off */ | |
602 | if (!need_resched() && !hvlpevent_is_pending()) | |
603 | yield_shared_processor(); | |
d200903e | 604 | |
3c57bb9f AB |
605 | HMT_medium(); |
606 | local_irq_enable(); | |
607 | } | |
608 | ||
609 | ppc64_runlatch_on(); | |
d200903e | 610 | |
3c57bb9f AB |
611 | if (hvlpevent_is_pending()) |
612 | process_iSeries_events(); | |
613 | ||
5bfb5d69 | 614 | preempt_enable_no_resched(); |
3c57bb9f | 615 | schedule(); |
5bfb5d69 | 616 | preempt_disable(); |
3c57bb9f | 617 | } |
3c57bb9f AB |
618 | } |
619 | ||
143a1dec | 620 | static void iseries_dedicated_idle(void) |
3c57bb9f | 621 | { |
64c7c8f8 | 622 | set_thread_flag(TIF_POLLING_NRFLAG); |
d200903e ME |
623 | |
624 | while (1) { | |
64c7c8f8 | 625 | if (!need_resched()) { |
3c57bb9f AB |
626 | while (!need_resched()) { |
627 | ppc64_runlatch_off(); | |
628 | HMT_low(); | |
629 | ||
630 | if (hvlpevent_is_pending()) { | |
d200903e | 631 | HMT_medium(); |
3c57bb9f AB |
632 | ppc64_runlatch_on(); |
633 | process_iSeries_events(); | |
d200903e | 634 | } |
d200903e | 635 | } |
3c57bb9f AB |
636 | |
637 | HMT_medium(); | |
d200903e ME |
638 | } |
639 | ||
640 | ppc64_runlatch_on(); | |
5bfb5d69 | 641 | preempt_enable_no_resched(); |
d200903e | 642 | schedule(); |
5bfb5d69 | 643 | preempt_disable(); |
d200903e | 644 | } |
d200903e ME |
645 | } |
646 | ||
145d01e4 SR |
647 | #ifndef CONFIG_PCI |
648 | void __init iSeries_init_IRQ(void) { } | |
649 | #endif | |
650 | ||
e8222502 | 651 | static int __init iseries_probe(void) |
4762713a | 652 | { |
e8222502 BH |
653 | unsigned long root = of_get_flat_dt_root(); |
654 | if (!of_flat_dt_is_compatible(root, "IBM,iSeries")) | |
57cfb814 ME |
655 | return 0; |
656 | ||
d0160bf0 ME |
657 | powerpc_firmware_features |= FW_FEATURE_ISERIES; |
658 | powerpc_firmware_features |= FW_FEATURE_LPAR; | |
57cfb814 | 659 | |
7d0daae4 ME |
660 | hpte_init_iSeries(); |
661 | ||
57cfb814 | 662 | return 1; |
4762713a ME |
663 | } |
664 | ||
e8222502 BH |
665 | define_machine(iseries) { |
666 | .name = "iSeries", | |
9f497581 | 667 | .setup_arch = iSeries_setup_arch, |
d8699e65 | 668 | .show_cpuinfo = iSeries_show_cpuinfo, |
9f497581 ME |
669 | .init_IRQ = iSeries_init_IRQ, |
670 | .get_irq = iSeries_get_irq, | |
671 | .init_early = iSeries_init_early, | |
672 | .pcibios_fixup = iSeries_pci_final_fixup, | |
a9ea2101 ME |
673 | .restart = mf_reboot, |
674 | .power_off = mf_power_off, | |
675 | .halt = mf_power_off, | |
9f497581 ME |
676 | .get_boot_time = iSeries_get_boot_time, |
677 | .set_rtc_time = iSeries_set_rtc_time, | |
678 | .get_rtc_time = iSeries_get_rtc_time, | |
95b29380 | 679 | .calibrate_decr = generic_calibrate_decr, |
9f497581 | 680 | .progress = iSeries_progress, |
4762713a | 681 | .probe = iseries_probe, |
9f497581 ME |
682 | /* XXX Implement enable_pmcs for iSeries */ |
683 | }; | |
684 | ||
4762713a | 685 | void * __init iSeries_early_setup(void) |
1da177e4 | 686 | { |
799d6046 PM |
687 | unsigned long phys_mem_size; |
688 | ||
1da177e4 | 689 | iSeries_fixup_klimit(); |
c0a59491 | 690 | |
4762713a ME |
691 | /* |
692 | * Initialize the table which translate Linux physical addresses to | |
693 | * AS/400 absolute addresses | |
694 | */ | |
799d6046 | 695 | phys_mem_size = build_iSeries_Memory_Map(); |
4762713a | 696 | |
bec7c458 SR |
697 | iSeries_get_cmdline(); |
698 | ||
c81014f6 | 699 | return (void *) __pa(build_flat_dt(phys_mem_size)); |
1da177e4 | 700 | } |
bec7c458 | 701 | |
bf6a7112 ME |
702 | static void hvputc(char c) |
703 | { | |
704 | if (c == '\n') | |
705 | hvputc('\r'); | |
706 | ||
707 | HvCall_writeLogBuffer(&c, 1); | |
708 | } | |
709 | ||
710 | void __init udbg_init_iseries(void) | |
711 | { | |
712 | udbg_putc = hvputc; | |
713 | } |