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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
3 | * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> | |
4 | * | |
1da177e4 LT |
5 | * Description: |
6 | * Architecture- / platform-specific boot-time initialization code for | |
7 | * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and | |
8 | * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek | |
9 | * <dan@net4x.com>. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #undef DEBUG | |
18 | ||
19 | #include <linux/config.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/threads.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/param.h> | |
24 | #include <linux/string.h> | |
1da177e4 LT |
25 | #include <linux/initrd.h> |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/kdev_t.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/root_dev.h> | |
bec7c458 | 30 | #include <linux/kernel.h> |
1da177e4 LT |
31 | |
32 | #include <asm/processor.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/mmu.h> | |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/mmu_context.h> | |
38 | #include <asm/cputable.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/iommu.h> | |
aed31351 | 41 | #include <asm/firmware.h> |
49b09853 | 42 | #include <asm/system.h> |
1da177e4 | 43 | #include <asm/time.h> |
1da177e4 LT |
44 | #include <asm/paca.h> |
45 | #include <asm/cache.h> | |
46 | #include <asm/sections.h> | |
0bc0ffd5 | 47 | #include <asm/abs_addr.h> |
15b17189 | 48 | #include <asm/iseries/hv_lp_config.h> |
c0a8d05c | 49 | #include <asm/iseries/hv_call_event.h> |
8021b8a7 | 50 | #include <asm/iseries/hv_call_xm.h> |
8875ccfb | 51 | #include <asm/iseries/it_lp_queue.h> |
bbc8b628 | 52 | #include <asm/iseries/mf.h> |
e45423ea | 53 | #include <asm/iseries/hv_lp_event.h> |
c43a55ff | 54 | #include <asm/iseries/lpar_map.h> |
bf6a7112 | 55 | #include <asm/udbg.h> |
7d01c880 | 56 | #include <asm/irq.h> |
1da177e4 | 57 | |
f11b7bd8 | 58 | #include "naca.h" |
c8b84976 | 59 | #include "setup.h" |
b08567cb SR |
60 | #include "irq.h" |
61 | #include "vpd_areas.h" | |
62 | #include "processor_vpd.h" | |
63 | #include "main_store.h" | |
64 | #include "call_sm.h" | |
0e29bb1a | 65 | #include "call_hpt.h" |
c8b84976 | 66 | |
1da177e4 | 67 | #ifdef DEBUG |
bf6a7112 | 68 | #define DBG(fmt...) udbg_printf(fmt) |
1da177e4 LT |
69 | #else |
70 | #define DBG(fmt...) | |
71 | #endif | |
72 | ||
73 | /* Function Prototypes */ | |
799d6046 | 74 | static unsigned long build_iSeries_Memory_Map(void); |
143a1dec PM |
75 | static void iseries_shared_idle(void); |
76 | static void iseries_dedicated_idle(void); | |
145d01e4 | 77 | #ifdef CONFIG_PCI |
1da177e4 | 78 | extern void iSeries_pci_final_fixup(void); |
145d01e4 SR |
79 | #else |
80 | static void iSeries_pci_final_fixup(void) { } | |
81 | #endif | |
1da177e4 | 82 | |
1da177e4 | 83 | extern int rd_size; /* Defined in drivers/block/rd.c */ |
1da177e4 LT |
84 | |
85 | extern unsigned long iSeries_recal_tb; | |
86 | extern unsigned long iSeries_recal_titan; | |
87 | ||
1da177e4 LT |
88 | struct MemoryBlock { |
89 | unsigned long absStart; | |
90 | unsigned long absEnd; | |
91 | unsigned long logicalStart; | |
92 | unsigned long logicalEnd; | |
93 | }; | |
94 | ||
95 | /* | |
96 | * Process the main store vpd to determine where the holes in memory are | |
97 | * and return the number of physical blocks and fill in the array of | |
98 | * block data. | |
99 | */ | |
100 | static unsigned long iSeries_process_Condor_mainstore_vpd( | |
101 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
102 | { | |
103 | unsigned long holeFirstChunk, holeSizeChunks; | |
104 | unsigned long numMemoryBlocks = 1; | |
105 | struct IoHriMainStoreSegment4 *msVpd = | |
106 | (struct IoHriMainStoreSegment4 *)xMsVpd; | |
107 | unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr; | |
108 | unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr; | |
109 | unsigned long holeSize = holeEnd - holeStart; | |
110 | ||
111 | printk("Mainstore_VPD: Condor\n"); | |
112 | /* | |
113 | * Determine if absolute memory has any | |
114 | * holes so that we can interpret the | |
115 | * access map we get back from the hypervisor | |
116 | * correctly. | |
117 | */ | |
118 | mb_array[0].logicalStart = 0; | |
119 | mb_array[0].logicalEnd = 0x100000000; | |
120 | mb_array[0].absStart = 0; | |
121 | mb_array[0].absEnd = 0x100000000; | |
122 | ||
123 | if (holeSize) { | |
124 | numMemoryBlocks = 2; | |
125 | holeStart = holeStart & 0x000fffffffffffff; | |
126 | holeStart = addr_to_chunk(holeStart); | |
127 | holeFirstChunk = holeStart; | |
128 | holeSize = addr_to_chunk(holeSize); | |
129 | holeSizeChunks = holeSize; | |
130 | printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n", | |
131 | holeFirstChunk, holeSizeChunks ); | |
132 | mb_array[0].logicalEnd = holeFirstChunk; | |
133 | mb_array[0].absEnd = holeFirstChunk; | |
134 | mb_array[1].logicalStart = holeFirstChunk; | |
135 | mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks; | |
136 | mb_array[1].absStart = holeFirstChunk + holeSizeChunks; | |
137 | mb_array[1].absEnd = 0x100000000; | |
138 | } | |
139 | return numMemoryBlocks; | |
140 | } | |
141 | ||
142 | #define MaxSegmentAreas 32 | |
143 | #define MaxSegmentAdrRangeBlocks 128 | |
144 | #define MaxAreaRangeBlocks 4 | |
145 | ||
146 | static unsigned long iSeries_process_Regatta_mainstore_vpd( | |
147 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
148 | { | |
149 | struct IoHriMainStoreSegment5 *msVpdP = | |
150 | (struct IoHriMainStoreSegment5 *)xMsVpd; | |
151 | unsigned long numSegmentBlocks = 0; | |
152 | u32 existsBits = msVpdP->msAreaExists; | |
153 | unsigned long area_num; | |
154 | ||
155 | printk("Mainstore_VPD: Regatta\n"); | |
156 | ||
157 | for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) { | |
158 | unsigned long numAreaBlocks; | |
159 | struct IoHriMainStoreArea4 *currentArea; | |
160 | ||
161 | if (existsBits & 0x80000000) { | |
162 | unsigned long block_num; | |
163 | ||
164 | currentArea = &msVpdP->msAreaArray[area_num]; | |
165 | numAreaBlocks = currentArea->numAdrRangeBlocks; | |
166 | printk("ms_vpd: processing area %2ld blocks=%ld", | |
167 | area_num, numAreaBlocks); | |
168 | for (block_num = 0; block_num < numAreaBlocks; | |
169 | ++block_num ) { | |
170 | /* Process an address range block */ | |
171 | struct MemoryBlock tempBlock; | |
172 | unsigned long i; | |
173 | ||
174 | tempBlock.absStart = | |
175 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart; | |
176 | tempBlock.absEnd = | |
177 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd; | |
178 | tempBlock.logicalStart = 0; | |
179 | tempBlock.logicalEnd = 0; | |
180 | printk("\n block %ld absStart=%016lx absEnd=%016lx", | |
181 | block_num, tempBlock.absStart, | |
182 | tempBlock.absEnd); | |
183 | ||
184 | for (i = 0; i < numSegmentBlocks; ++i) { | |
185 | if (mb_array[i].absStart == | |
186 | tempBlock.absStart) | |
187 | break; | |
188 | } | |
189 | if (i == numSegmentBlocks) { | |
190 | if (numSegmentBlocks == max_entries) | |
191 | panic("iSeries_process_mainstore_vpd: too many memory blocks"); | |
192 | mb_array[numSegmentBlocks] = tempBlock; | |
193 | ++numSegmentBlocks; | |
194 | } else | |
195 | printk(" (duplicate)"); | |
196 | } | |
197 | printk("\n"); | |
198 | } | |
199 | existsBits <<= 1; | |
200 | } | |
201 | /* Now sort the blocks found into ascending sequence */ | |
202 | if (numSegmentBlocks > 1) { | |
203 | unsigned long m, n; | |
204 | ||
205 | for (m = 0; m < numSegmentBlocks - 1; ++m) { | |
206 | for (n = numSegmentBlocks - 1; m < n; --n) { | |
207 | if (mb_array[n].absStart < | |
208 | mb_array[n-1].absStart) { | |
209 | struct MemoryBlock tempBlock; | |
210 | ||
211 | tempBlock = mb_array[n]; | |
212 | mb_array[n] = mb_array[n-1]; | |
213 | mb_array[n-1] = tempBlock; | |
214 | } | |
215 | } | |
216 | } | |
217 | } | |
218 | /* | |
219 | * Assign "logical" addresses to each block. These | |
220 | * addresses correspond to the hypervisor "bitmap" space. | |
221 | * Convert all addresses into units of 256K chunks. | |
222 | */ | |
223 | { | |
224 | unsigned long i, nextBitmapAddress; | |
225 | ||
226 | printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks); | |
227 | nextBitmapAddress = 0; | |
228 | for (i = 0; i < numSegmentBlocks; ++i) { | |
229 | unsigned long length = mb_array[i].absEnd - | |
230 | mb_array[i].absStart; | |
231 | ||
232 | mb_array[i].logicalStart = nextBitmapAddress; | |
233 | mb_array[i].logicalEnd = nextBitmapAddress + length; | |
234 | nextBitmapAddress += length; | |
235 | printk(" Bitmap range: %016lx - %016lx\n" | |
236 | " Absolute range: %016lx - %016lx\n", | |
237 | mb_array[i].logicalStart, | |
238 | mb_array[i].logicalEnd, | |
239 | mb_array[i].absStart, mb_array[i].absEnd); | |
240 | mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart & | |
241 | 0x000fffffffffffff); | |
242 | mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd & | |
243 | 0x000fffffffffffff); | |
244 | mb_array[i].logicalStart = | |
245 | addr_to_chunk(mb_array[i].logicalStart); | |
246 | mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd); | |
247 | } | |
248 | } | |
249 | ||
250 | return numSegmentBlocks; | |
251 | } | |
252 | ||
253 | static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array, | |
254 | unsigned long max_entries) | |
255 | { | |
256 | unsigned long i; | |
257 | unsigned long mem_blocks = 0; | |
258 | ||
259 | if (cpu_has_feature(CPU_FTR_SLB)) | |
260 | mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array, | |
261 | max_entries); | |
262 | else | |
263 | mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array, | |
264 | max_entries); | |
265 | ||
266 | printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks); | |
267 | for (i = 0; i < mem_blocks; ++i) { | |
268 | printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n" | |
269 | " abs chunks %016lx - %016lx\n", | |
270 | i, mb_array[i].logicalStart, mb_array[i].logicalEnd, | |
271 | mb_array[i].absStart, mb_array[i].absEnd); | |
272 | } | |
273 | return mem_blocks; | |
274 | } | |
275 | ||
276 | static void __init iSeries_get_cmdline(void) | |
277 | { | |
278 | char *p, *q; | |
279 | ||
280 | /* copy the command line parameter from the primary VSP */ | |
281 | HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256, | |
282 | HvLpDma_Direction_RemoteToLocal); | |
283 | ||
284 | p = cmd_line; | |
285 | q = cmd_line + 255; | |
286 | while(p < q) { | |
287 | if (!*p || *p == '\n') | |
288 | break; | |
289 | ++p; | |
290 | } | |
291 | *p = 0; | |
292 | } | |
293 | ||
294 | static void __init iSeries_init_early(void) | |
295 | { | |
1da177e4 LT |
296 | DBG(" -> iSeries_init_early()\n"); |
297 | ||
ba293fff ME |
298 | ppc64_interrupt_controller = IC_ISERIES; |
299 | ||
1da177e4 LT |
300 | #if defined(CONFIG_BLK_DEV_INITRD) |
301 | /* | |
302 | * If the init RAM disk has been configured and there is | |
303 | * a non-zero starting address for it, set it up | |
304 | */ | |
305 | if (naca.xRamDisk) { | |
306 | initrd_start = (unsigned long)__va(naca.xRamDisk); | |
3c726f8d | 307 | initrd_end = initrd_start + naca.xRamDiskSize * HW_PAGE_SIZE; |
1da177e4 LT |
308 | initrd_below_start_ok = 1; // ramdisk in kernel space |
309 | ROOT_DEV = Root_RAM0; | |
3c726f8d BH |
310 | if (((rd_size * 1024) / HW_PAGE_SIZE) < naca.xRamDiskSize) |
311 | rd_size = (naca.xRamDiskSize * HW_PAGE_SIZE) / 1024; | |
1da177e4 LT |
312 | } else |
313 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
314 | { | |
315 | /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */ | |
316 | } | |
317 | ||
318 | iSeries_recal_tb = get_tb(); | |
319 | iSeries_recal_titan = HvCallXm_loadTod(); | |
320 | ||
1da177e4 LT |
321 | /* |
322 | * Initialize the DMA/TCE management | |
323 | */ | |
324 | iommu_init_early_iSeries(); | |
325 | ||
1da177e4 LT |
326 | /* Initialize machine-dependency vectors */ |
327 | #ifdef CONFIG_SMP | |
328 | smp_init_iSeries(); | |
329 | #endif | |
1da177e4 LT |
330 | |
331 | /* Associate Lp Event Queue 0 with processor 0 */ | |
332 | HvCallEvent_setLpEventQueueInterruptProc(0, 0); | |
333 | ||
334 | mf_init(); | |
1da177e4 LT |
335 | |
336 | /* If we were passed an initrd, set the ROOT_DEV properly if the values | |
337 | * look sensible. If not, clear initrd reference. | |
338 | */ | |
339 | #ifdef CONFIG_BLK_DEV_INITRD | |
340 | if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE && | |
341 | initrd_end > initrd_start) | |
342 | ROOT_DEV = Root_RAM0; | |
343 | else | |
344 | initrd_start = initrd_end = 0; | |
345 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
346 | ||
347 | DBG(" <- iSeries_init_early()\n"); | |
348 | } | |
349 | ||
56e97b71 | 350 | struct mschunks_map mschunks_map = { |
34c8f696 ME |
351 | /* XXX We don't use these, but Piranha might need them. */ |
352 | .chunk_size = MSCHUNKS_CHUNK_SIZE, | |
353 | .chunk_shift = MSCHUNKS_CHUNK_SHIFT, | |
354 | .chunk_mask = MSCHUNKS_OFFSET_MASK, | |
355 | }; | |
56e97b71 | 356 | EXPORT_SYMBOL(mschunks_map); |
34c8f696 | 357 | |
56e97b71 | 358 | void mschunks_alloc(unsigned long num_chunks) |
34c8f696 ME |
359 | { |
360 | klimit = _ALIGN(klimit, sizeof(u32)); | |
56e97b71 | 361 | mschunks_map.mapping = (u32 *)klimit; |
34c8f696 | 362 | klimit += num_chunks * sizeof(u32); |
56e97b71 | 363 | mschunks_map.num_chunks = num_chunks; |
34c8f696 ME |
364 | } |
365 | ||
1da177e4 LT |
366 | /* |
367 | * The iSeries may have very large memories ( > 128 GB ) and a partition | |
368 | * may get memory in "chunks" that may be anywhere in the 2**52 real | |
369 | * address space. The chunks are 256K in size. To map this to the | |
370 | * memory model Linux expects, the AS/400 specific code builds a | |
371 | * translation table to translate what Linux thinks are "physical" | |
372 | * addresses to the actual real addresses. This allows us to make | |
373 | * it appear to Linux that we have contiguous memory starting at | |
374 | * physical address zero while in fact this could be far from the truth. | |
375 | * To avoid confusion, I'll let the words physical and/or real address | |
376 | * apply to the Linux addresses while I'll use "absolute address" to | |
377 | * refer to the actual hardware real address. | |
378 | * | |
379 | * build_iSeries_Memory_Map gets information from the Hypervisor and | |
380 | * looks at the Main Store VPD to determine the absolute addresses | |
381 | * of the memory that has been assigned to our partition and builds | |
382 | * a table used to translate Linux's physical addresses to these | |
383 | * absolute addresses. Absolute addresses are needed when | |
384 | * communicating with the hypervisor (e.g. to build HPT entries) | |
799d6046 PM |
385 | * |
386 | * Returns the physical memory size | |
1da177e4 LT |
387 | */ |
388 | ||
799d6046 | 389 | static unsigned long __init build_iSeries_Memory_Map(void) |
1da177e4 LT |
390 | { |
391 | u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize; | |
392 | u32 nextPhysChunk; | |
393 | u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages; | |
1da177e4 LT |
394 | u32 totalChunks,moreChunks; |
395 | u32 currChunk, thisChunk, absChunk; | |
396 | u32 currDword; | |
397 | u32 chunkBit; | |
398 | u64 map; | |
399 | struct MemoryBlock mb[32]; | |
400 | unsigned long numMemoryBlocks, curBlock; | |
401 | ||
402 | /* Chunk size on iSeries is 256K bytes */ | |
403 | totalChunks = (u32)HvLpConfig_getMsChunks(); | |
56e97b71 | 404 | mschunks_alloc(totalChunks); |
1da177e4 LT |
405 | |
406 | /* | |
407 | * Get absolute address of our load area | |
408 | * and map it to physical address 0 | |
409 | * This guarantees that the loadarea ends up at physical 0 | |
410 | * otherwise, it might not be returned by PLIC as the first | |
411 | * chunks | |
412 | */ | |
413 | ||
414 | loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr); | |
415 | loadAreaSize = itLpNaca.xLoadAreaChunks; | |
416 | ||
417 | /* | |
418 | * Only add the pages already mapped here. | |
419 | * Otherwise we might add the hpt pages | |
420 | * The rest of the pages of the load area | |
421 | * aren't in the HPT yet and can still | |
422 | * be assigned an arbitrary physical address | |
423 | */ | |
424 | if ((loadAreaSize * 64) > HvPagesToMap) | |
425 | loadAreaSize = HvPagesToMap / 64; | |
426 | ||
427 | loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1; | |
428 | ||
429 | /* | |
430 | * TODO Do we need to do something if the HPT is in the 64MB load area? | |
431 | * This would be required if the itLpNaca.xLoadAreaChunks includes | |
432 | * the HPT size | |
433 | */ | |
434 | ||
435 | printk("Mapping load area - physical addr = 0000000000000000\n" | |
436 | " absolute addr = %016lx\n", | |
437 | chunk_to_addr(loadAreaFirstChunk)); | |
438 | printk("Load area size %dK\n", loadAreaSize * 256); | |
439 | ||
440 | for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk) | |
56e97b71 | 441 | mschunks_map.mapping[nextPhysChunk] = |
1da177e4 LT |
442 | loadAreaFirstChunk + nextPhysChunk; |
443 | ||
444 | /* | |
445 | * Get absolute address of our HPT and remember it so | |
446 | * we won't map it to any physical address | |
447 | */ | |
448 | hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress()); | |
449 | hptSizePages = (u32)HvCallHpt_getHptPages(); | |
3c726f8d BH |
450 | hptSizeChunks = hptSizePages >> |
451 | (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT); | |
1da177e4 LT |
452 | hptLastChunk = hptFirstChunk + hptSizeChunks - 1; |
453 | ||
454 | printk("HPT absolute addr = %016lx, size = %dK\n", | |
455 | chunk_to_addr(hptFirstChunk), hptSizeChunks * 256); | |
456 | ||
1da177e4 LT |
457 | /* |
458 | * Determine if absolute memory has any | |
459 | * holes so that we can interpret the | |
460 | * access map we get back from the hypervisor | |
461 | * correctly. | |
462 | */ | |
463 | numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32); | |
464 | ||
465 | /* | |
466 | * Process the main store access map from the hypervisor | |
467 | * to build up our physical -> absolute translation table | |
468 | */ | |
469 | curBlock = 0; | |
470 | currChunk = 0; | |
471 | currDword = 0; | |
472 | moreChunks = totalChunks; | |
473 | ||
474 | while (moreChunks) { | |
475 | map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex, | |
476 | currDword); | |
477 | thisChunk = currChunk; | |
478 | while (map) { | |
479 | chunkBit = map >> 63; | |
480 | map <<= 1; | |
481 | if (chunkBit) { | |
482 | --moreChunks; | |
483 | while (thisChunk >= mb[curBlock].logicalEnd) { | |
484 | ++curBlock; | |
485 | if (curBlock >= numMemoryBlocks) | |
486 | panic("out of memory blocks"); | |
487 | } | |
488 | if (thisChunk < mb[curBlock].logicalStart) | |
489 | panic("memory block error"); | |
490 | ||
491 | absChunk = mb[curBlock].absStart + | |
492 | (thisChunk - mb[curBlock].logicalStart); | |
493 | if (((absChunk < hptFirstChunk) || | |
494 | (absChunk > hptLastChunk)) && | |
495 | ((absChunk < loadAreaFirstChunk) || | |
496 | (absChunk > loadAreaLastChunk))) { | |
56e97b71 ME |
497 | mschunks_map.mapping[nextPhysChunk] = |
498 | absChunk; | |
1da177e4 LT |
499 | ++nextPhysChunk; |
500 | } | |
501 | } | |
502 | ++thisChunk; | |
503 | } | |
504 | ++currDword; | |
505 | currChunk += 64; | |
506 | } | |
507 | ||
508 | /* | |
509 | * main store size (in chunks) is | |
510 | * totalChunks - hptSizeChunks | |
511 | * which should be equal to | |
512 | * nextPhysChunk | |
513 | */ | |
799d6046 | 514 | return chunk_to_addr(nextPhysChunk); |
1da177e4 LT |
515 | } |
516 | ||
1da177e4 LT |
517 | /* |
518 | * Document me. | |
519 | */ | |
520 | static void __init iSeries_setup_arch(void) | |
521 | { | |
3356bb9f | 522 | if (get_lppaca()->shared_proc) { |
9f497581 | 523 | ppc_md.idle_loop = iseries_shared_idle; |
4baaf0cf | 524 | printk(KERN_DEBUG "Using shared processor idle loop\n"); |
9f497581 ME |
525 | } else { |
526 | ppc_md.idle_loop = iseries_dedicated_idle; | |
4baaf0cf | 527 | printk(KERN_DEBUG "Using dedicated idle loop\n"); |
9f497581 ME |
528 | } |
529 | ||
1da177e4 | 530 | /* Setup the Lp Event Queue */ |
512d31d6 | 531 | setup_hvlpevent_queue(); |
1da177e4 | 532 | |
1da177e4 LT |
533 | printk("Max logical processors = %d\n", |
534 | itVpdAreas.xSlicMaxLogicalProcs); | |
535 | printk("Max physical processors = %d\n", | |
536 | itVpdAreas.xSlicMaxPhysicalProcs); | |
1da177e4 LT |
537 | } |
538 | ||
d8699e65 | 539 | static void iSeries_show_cpuinfo(struct seq_file *m) |
1da177e4 LT |
540 | { |
541 | seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n"); | |
542 | } | |
543 | ||
1da177e4 LT |
544 | static void __init iSeries_progress(char * st, unsigned short code) |
545 | { | |
546 | printk("Progress: [%04x] - %s\n", (unsigned)code, st); | |
260de22f | 547 | mf_display_progress(code); |
1da177e4 LT |
548 | } |
549 | ||
550 | static void __init iSeries_fixup_klimit(void) | |
551 | { | |
552 | /* | |
553 | * Change klimit to take into account any ram disk | |
554 | * that may be included | |
555 | */ | |
556 | if (naca.xRamDisk) | |
557 | klimit = KERNELBASE + (u64)naca.xRamDisk + | |
3c726f8d | 558 | (naca.xRamDiskSize * HW_PAGE_SIZE); |
1da177e4 LT |
559 | } |
560 | ||
561 | static int __init iSeries_src_init(void) | |
562 | { | |
563 | /* clear the progress line */ | |
564 | ppc_md.progress(" ", 0xffff); | |
565 | return 0; | |
566 | } | |
567 | ||
568 | late_initcall(iSeries_src_init); | |
569 | ||
d200903e ME |
570 | static inline void process_iSeries_events(void) |
571 | { | |
572 | asm volatile ("li 0,0x5555; sc" : : : "r0", "r3"); | |
573 | } | |
574 | ||
575 | static void yield_shared_processor(void) | |
576 | { | |
577 | unsigned long tb; | |
d200903e ME |
578 | |
579 | HvCall_setEnabledInterrupts(HvCall_MaskIPI | | |
580 | HvCall_MaskLpEvent | | |
581 | HvCall_MaskLpProd | | |
582 | HvCall_MaskTimeout); | |
583 | ||
584 | tb = get_tb(); | |
585 | /* Compute future tb value when yield should expire */ | |
586 | HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy); | |
587 | ||
d200903e ME |
588 | /* |
589 | * The decrementer stops during the yield. Force a fake decrementer | |
590 | * here and let the timer_interrupt code sort out the actual time. | |
591 | */ | |
3356bb9f | 592 | get_lppaca()->int_dword.fields.decr_int = 1; |
cb2c9b27 | 593 | ppc64_runlatch_on(); |
d200903e ME |
594 | process_iSeries_events(); |
595 | } | |
596 | ||
143a1dec | 597 | static void iseries_shared_idle(void) |
d200903e | 598 | { |
3c57bb9f AB |
599 | while (1) { |
600 | while (!need_resched() && !hvlpevent_is_pending()) { | |
601 | local_irq_disable(); | |
602 | ppc64_runlatch_off(); | |
603 | ||
604 | /* Recheck with irqs off */ | |
605 | if (!need_resched() && !hvlpevent_is_pending()) | |
606 | yield_shared_processor(); | |
d200903e | 607 | |
3c57bb9f AB |
608 | HMT_medium(); |
609 | local_irq_enable(); | |
610 | } | |
611 | ||
612 | ppc64_runlatch_on(); | |
d200903e | 613 | |
3c57bb9f AB |
614 | if (hvlpevent_is_pending()) |
615 | process_iSeries_events(); | |
616 | ||
5bfb5d69 | 617 | preempt_enable_no_resched(); |
3c57bb9f | 618 | schedule(); |
5bfb5d69 | 619 | preempt_disable(); |
3c57bb9f | 620 | } |
3c57bb9f AB |
621 | } |
622 | ||
143a1dec | 623 | static void iseries_dedicated_idle(void) |
3c57bb9f | 624 | { |
64c7c8f8 | 625 | set_thread_flag(TIF_POLLING_NRFLAG); |
d200903e ME |
626 | |
627 | while (1) { | |
64c7c8f8 | 628 | if (!need_resched()) { |
3c57bb9f AB |
629 | while (!need_resched()) { |
630 | ppc64_runlatch_off(); | |
631 | HMT_low(); | |
632 | ||
633 | if (hvlpevent_is_pending()) { | |
d200903e | 634 | HMT_medium(); |
3c57bb9f AB |
635 | ppc64_runlatch_on(); |
636 | process_iSeries_events(); | |
d200903e | 637 | } |
d200903e | 638 | } |
3c57bb9f AB |
639 | |
640 | HMT_medium(); | |
d200903e ME |
641 | } |
642 | ||
643 | ppc64_runlatch_on(); | |
5bfb5d69 | 644 | preempt_enable_no_resched(); |
d200903e | 645 | schedule(); |
5bfb5d69 | 646 | preempt_disable(); |
d200903e | 647 | } |
d200903e ME |
648 | } |
649 | ||
145d01e4 SR |
650 | #ifndef CONFIG_PCI |
651 | void __init iSeries_init_IRQ(void) { } | |
652 | #endif | |
653 | ||
e8222502 | 654 | static int __init iseries_probe(void) |
4762713a | 655 | { |
e8222502 BH |
656 | unsigned long root = of_get_flat_dt_root(); |
657 | if (!of_flat_dt_is_compatible(root, "IBM,iSeries")) | |
57cfb814 ME |
658 | return 0; |
659 | ||
d0160bf0 ME |
660 | powerpc_firmware_features |= FW_FEATURE_ISERIES; |
661 | powerpc_firmware_features |= FW_FEATURE_LPAR; | |
57cfb814 | 662 | |
7d01c880 SR |
663 | /* |
664 | * The Hypervisor only allows us up to 256 interrupt | |
665 | * sources (the irq number is passed in a u8). | |
666 | */ | |
667 | virt_irq_max = 255; | |
668 | ||
7d0daae4 ME |
669 | hpte_init_iSeries(); |
670 | ||
57cfb814 | 671 | return 1; |
4762713a ME |
672 | } |
673 | ||
e8222502 BH |
674 | define_machine(iseries) { |
675 | .name = "iSeries", | |
9f497581 | 676 | .setup_arch = iSeries_setup_arch, |
d8699e65 | 677 | .show_cpuinfo = iSeries_show_cpuinfo, |
9f497581 ME |
678 | .init_IRQ = iSeries_init_IRQ, |
679 | .get_irq = iSeries_get_irq, | |
680 | .init_early = iSeries_init_early, | |
681 | .pcibios_fixup = iSeries_pci_final_fixup, | |
a9ea2101 ME |
682 | .restart = mf_reboot, |
683 | .power_off = mf_power_off, | |
684 | .halt = mf_power_off, | |
9f497581 ME |
685 | .get_boot_time = iSeries_get_boot_time, |
686 | .set_rtc_time = iSeries_set_rtc_time, | |
687 | .get_rtc_time = iSeries_get_rtc_time, | |
95b29380 | 688 | .calibrate_decr = generic_calibrate_decr, |
9f497581 | 689 | .progress = iSeries_progress, |
4762713a | 690 | .probe = iseries_probe, |
9f497581 ME |
691 | /* XXX Implement enable_pmcs for iSeries */ |
692 | }; | |
693 | ||
4762713a | 694 | void * __init iSeries_early_setup(void) |
1da177e4 | 695 | { |
799d6046 PM |
696 | unsigned long phys_mem_size; |
697 | ||
1da177e4 | 698 | iSeries_fixup_klimit(); |
c0a59491 | 699 | |
4762713a ME |
700 | /* |
701 | * Initialize the table which translate Linux physical addresses to | |
702 | * AS/400 absolute addresses | |
703 | */ | |
799d6046 | 704 | phys_mem_size = build_iSeries_Memory_Map(); |
4762713a | 705 | |
bec7c458 SR |
706 | iSeries_get_cmdline(); |
707 | ||
c81014f6 | 708 | return (void *) __pa(build_flat_dt(phys_mem_size)); |
1da177e4 | 709 | } |
bec7c458 | 710 | |
bf6a7112 ME |
711 | static void hvputc(char c) |
712 | { | |
713 | if (c == '\n') | |
714 | hvputc('\r'); | |
715 | ||
716 | HvCall_writeLogBuffer(&c, 1); | |
717 | } | |
718 | ||
719 | void __init udbg_init_iseries(void) | |
720 | { | |
721 | udbg_putc = hvputc; | |
722 | } |