]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), | |
3 | * IBM Corp. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
c10af8c3 | 11 | #undef DEBUG |
1da177e4 LT |
12 | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/bootmem.h> | |
c10af8c3 | 19 | #include <linux/irq.h> |
1da177e4 LT |
20 | |
21 | #include <asm/sections.h> | |
22 | #include <asm/io.h> | |
23 | #include <asm/prom.h> | |
24 | #include <asm/pci-bridge.h> | |
25 | #include <asm/machdep.h> | |
26 | #include <asm/iommu.h> | |
d387899f | 27 | #include <asm/ppc-pci.h> |
1da177e4 | 28 | |
0cb7b2af PM |
29 | #include "maple.h" |
30 | ||
1da177e4 LT |
31 | #ifdef DEBUG |
32 | #define DBG(x...) printk(x) | |
33 | #else | |
34 | #define DBG(x...) | |
35 | #endif | |
36 | ||
c10af8c3 | 37 | static struct pci_controller *u3_agp, *u3_ht, *u4_pcie; |
1da177e4 LT |
38 | |
39 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) | |
40 | { | |
41 | for (; node != 0;node = node->sibling) { | |
eeb2b723 JK |
42 | const int *bus_range; |
43 | const unsigned int *class_code; | |
1da177e4 LT |
44 | int len; |
45 | ||
46 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
e2eb6392 | 47 | class_code = of_get_property(node, "class-code", NULL); |
1da177e4 LT |
48 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
49 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
50 | continue; | |
e2eb6392 | 51 | bus_range = of_get_property(node, "bus-range", &len); |
1da177e4 LT |
52 | if (bus_range != NULL && len > 2 * sizeof(int)) { |
53 | if (bus_range[1] > higher) | |
54 | higher = bus_range[1]; | |
55 | } | |
56 | higher = fixup_one_level_bus_range(node->child, higher); | |
57 | } | |
58 | return higher; | |
59 | } | |
60 | ||
61 | /* This routine fixes the "bus-range" property of all bridges in the | |
62 | * system since they tend to have their "last" member wrong on macs | |
63 | * | |
64 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
65 | * are not Linux bus numbers. | |
66 | */ | |
67 | static void __init fixup_bus_range(struct device_node *bridge) | |
68 | { | |
eeb2b723 JK |
69 | int *bus_range; |
70 | struct property *prop; | |
1da177e4 LT |
71 | int len; |
72 | ||
73 | /* Lookup the "bus-range" property for the hose */ | |
eeb2b723 JK |
74 | prop = of_find_property(bridge, "bus-range", &len); |
75 | if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) { | |
1da177e4 LT |
76 | printk(KERN_WARNING "Can't get bus-range for %s\n", |
77 | bridge->full_name); | |
78 | return; | |
79 | } | |
1a38147e | 80 | bus_range = prop->value; |
1da177e4 LT |
81 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); |
82 | } | |
83 | ||
84 | ||
cc9881ce NL |
85 | static unsigned long u3_agp_cfa0(u8 devfn, u8 off) |
86 | { | |
87 | return (1 << (unsigned long)PCI_SLOT(devfn)) | | |
88 | ((unsigned long)PCI_FUNC(devfn) << 8) | | |
89 | ((unsigned long)off & 0xFCUL); | |
90 | } | |
1da177e4 | 91 | |
cc9881ce NL |
92 | static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off) |
93 | { | |
94 | return ((unsigned long)bus << 16) | | |
95 | ((unsigned long)devfn << 8) | | |
96 | ((unsigned long)off & 0xFCUL) | | |
97 | 1UL; | |
98 | } | |
1da177e4 | 99 | |
8c42ec2c | 100 | static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose, |
1da177e4 LT |
101 | u8 bus, u8 dev_fn, u8 offset) |
102 | { | |
103 | unsigned int caddr; | |
104 | ||
105 | if (bus == hose->first_busno) { | |
106 | if (dev_fn < (11 << 3)) | |
8c42ec2c | 107 | return NULL; |
cc9881ce | 108 | caddr = u3_agp_cfa0(dev_fn, offset); |
1da177e4 | 109 | } else |
cc9881ce | 110 | caddr = u3_agp_cfa1(bus, dev_fn, offset); |
1da177e4 LT |
111 | |
112 | /* Uninorth will return garbage if we don't read back the value ! */ | |
113 | do { | |
114 | out_le32(hose->cfg_addr, caddr); | |
115 | } while (in_le32(hose->cfg_addr) != caddr); | |
116 | ||
117 | offset &= 0x07; | |
8c42ec2c | 118 | return hose->cfg_data + offset; |
1da177e4 LT |
119 | } |
120 | ||
121 | static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, | |
122 | int offset, int len, u32 *val) | |
123 | { | |
124 | struct pci_controller *hose; | |
8c42ec2c | 125 | volatile void __iomem *addr; |
1da177e4 LT |
126 | |
127 | hose = pci_bus_to_host(bus); | |
128 | if (hose == NULL) | |
129 | return PCIBIOS_DEVICE_NOT_FOUND; | |
130 | ||
131 | addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); | |
132 | if (!addr) | |
133 | return PCIBIOS_DEVICE_NOT_FOUND; | |
134 | /* | |
135 | * Note: the caller has already checked that offset is | |
136 | * suitably aligned and that len is 1, 2 or 4. | |
137 | */ | |
138 | switch (len) { | |
139 | case 1: | |
8c42ec2c | 140 | *val = in_8(addr); |
1da177e4 LT |
141 | break; |
142 | case 2: | |
8c42ec2c | 143 | *val = in_le16(addr); |
1da177e4 LT |
144 | break; |
145 | default: | |
8c42ec2c | 146 | *val = in_le32(addr); |
1da177e4 LT |
147 | break; |
148 | } | |
149 | return PCIBIOS_SUCCESSFUL; | |
150 | } | |
151 | ||
152 | static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, | |
153 | int offset, int len, u32 val) | |
154 | { | |
155 | struct pci_controller *hose; | |
8c42ec2c | 156 | volatile void __iomem *addr; |
1da177e4 LT |
157 | |
158 | hose = pci_bus_to_host(bus); | |
159 | if (hose == NULL) | |
160 | return PCIBIOS_DEVICE_NOT_FOUND; | |
161 | ||
162 | addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); | |
163 | if (!addr) | |
164 | return PCIBIOS_DEVICE_NOT_FOUND; | |
165 | /* | |
166 | * Note: the caller has already checked that offset is | |
167 | * suitably aligned and that len is 1, 2 or 4. | |
168 | */ | |
169 | switch (len) { | |
170 | case 1: | |
8c42ec2c AV |
171 | out_8(addr, val); |
172 | (void) in_8(addr); | |
1da177e4 LT |
173 | break; |
174 | case 2: | |
8c42ec2c AV |
175 | out_le16(addr, val); |
176 | (void) in_le16(addr); | |
1da177e4 LT |
177 | break; |
178 | default: | |
8c42ec2c AV |
179 | out_le32(addr, val); |
180 | (void) in_le32(addr); | |
1da177e4 LT |
181 | break; |
182 | } | |
183 | return PCIBIOS_SUCCESSFUL; | |
184 | } | |
185 | ||
186 | static struct pci_ops u3_agp_pci_ops = | |
187 | { | |
188 | u3_agp_read_config, | |
189 | u3_agp_write_config | |
190 | }; | |
191 | ||
cc9881ce NL |
192 | static unsigned long u3_ht_cfa0(u8 devfn, u8 off) |
193 | { | |
194 | return (devfn << 8) | off; | |
195 | } | |
1da177e4 | 196 | |
cc9881ce NL |
197 | static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off) |
198 | { | |
199 | return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL; | |
200 | } | |
1da177e4 | 201 | |
8c42ec2c | 202 | static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, |
1da177e4 LT |
203 | u8 bus, u8 devfn, u8 offset) |
204 | { | |
205 | if (bus == hose->first_busno) { | |
206 | if (PCI_SLOT(devfn) == 0) | |
8c42ec2c AV |
207 | return NULL; |
208 | return hose->cfg_data + u3_ht_cfa0(devfn, offset); | |
1da177e4 | 209 | } else |
8c42ec2c | 210 | return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset); |
1da177e4 LT |
211 | } |
212 | ||
213 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, | |
214 | int offset, int len, u32 *val) | |
215 | { | |
216 | struct pci_controller *hose; | |
8c42ec2c | 217 | volatile void __iomem *addr; |
1da177e4 LT |
218 | |
219 | hose = pci_bus_to_host(bus); | |
220 | if (hose == NULL) | |
221 | return PCIBIOS_DEVICE_NOT_FOUND; | |
222 | ||
d608df5c NL |
223 | if (offset > 0xff) |
224 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
225 | ||
1da177e4 LT |
226 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
227 | if (!addr) | |
228 | return PCIBIOS_DEVICE_NOT_FOUND; | |
229 | ||
230 | /* | |
231 | * Note: the caller has already checked that offset is | |
232 | * suitably aligned and that len is 1, 2 or 4. | |
233 | */ | |
234 | switch (len) { | |
235 | case 1: | |
8c42ec2c | 236 | *val = in_8(addr); |
1da177e4 LT |
237 | break; |
238 | case 2: | |
8c42ec2c | 239 | *val = in_le16(addr); |
1da177e4 LT |
240 | break; |
241 | default: | |
8c42ec2c | 242 | *val = in_le32(addr); |
1da177e4 LT |
243 | break; |
244 | } | |
245 | return PCIBIOS_SUCCESSFUL; | |
246 | } | |
247 | ||
248 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, | |
249 | int offset, int len, u32 val) | |
250 | { | |
251 | struct pci_controller *hose; | |
8c42ec2c | 252 | volatile void __iomem *addr; |
1da177e4 LT |
253 | |
254 | hose = pci_bus_to_host(bus); | |
255 | if (hose == NULL) | |
256 | return PCIBIOS_DEVICE_NOT_FOUND; | |
257 | ||
d608df5c NL |
258 | if (offset > 0xff) |
259 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
260 | ||
1da177e4 LT |
261 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
262 | if (!addr) | |
263 | return PCIBIOS_DEVICE_NOT_FOUND; | |
264 | /* | |
265 | * Note: the caller has already checked that offset is | |
266 | * suitably aligned and that len is 1, 2 or 4. | |
267 | */ | |
268 | switch (len) { | |
269 | case 1: | |
8c42ec2c AV |
270 | out_8(addr, val); |
271 | (void) in_8(addr); | |
1da177e4 LT |
272 | break; |
273 | case 2: | |
8c42ec2c AV |
274 | out_le16(addr, val); |
275 | (void) in_le16(addr); | |
1da177e4 LT |
276 | break; |
277 | default: | |
8c42ec2c AV |
278 | out_le32(addr, val); |
279 | (void) in_le32(addr); | |
1da177e4 LT |
280 | break; |
281 | } | |
282 | return PCIBIOS_SUCCESSFUL; | |
283 | } | |
284 | ||
285 | static struct pci_ops u3_ht_pci_ops = | |
286 | { | |
287 | u3_ht_read_config, | |
288 | u3_ht_write_config | |
289 | }; | |
290 | ||
c10af8c3 BH |
291 | static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off) |
292 | { | |
293 | return (1 << PCI_SLOT(devfn)) | | |
294 | (PCI_FUNC(devfn) << 8) | | |
295 | ((off >> 8) << 28) | | |
296 | (off & 0xfcu); | |
297 | } | |
298 | ||
299 | static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn, | |
300 | unsigned int off) | |
301 | { | |
302 | return (bus << 16) | | |
303 | (devfn << 8) | | |
304 | ((off >> 8) << 28) | | |
305 | (off & 0xfcu) | 1u; | |
306 | } | |
307 | ||
308 | static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, | |
309 | u8 bus, u8 dev_fn, int offset) | |
310 | { | |
311 | unsigned int caddr; | |
312 | ||
313 | if (bus == hose->first_busno) | |
314 | caddr = u4_pcie_cfa0(dev_fn, offset); | |
315 | else | |
316 | caddr = u4_pcie_cfa1(bus, dev_fn, offset); | |
317 | ||
318 | /* Uninorth will return garbage if we don't read back the value ! */ | |
319 | do { | |
320 | out_le32(hose->cfg_addr, caddr); | |
321 | } while (in_le32(hose->cfg_addr) != caddr); | |
322 | ||
323 | offset &= 0x03; | |
324 | return hose->cfg_data + offset; | |
325 | } | |
326 | ||
327 | static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, | |
328 | int offset, int len, u32 *val) | |
329 | { | |
330 | struct pci_controller *hose; | |
331 | volatile void __iomem *addr; | |
332 | ||
333 | hose = pci_bus_to_host(bus); | |
334 | if (hose == NULL) | |
335 | return PCIBIOS_DEVICE_NOT_FOUND; | |
336 | if (offset >= 0x1000) | |
337 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
338 | addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); | |
339 | if (!addr) | |
340 | return PCIBIOS_DEVICE_NOT_FOUND; | |
341 | /* | |
342 | * Note: the caller has already checked that offset is | |
343 | * suitably aligned and that len is 1, 2 or 4. | |
344 | */ | |
345 | switch (len) { | |
346 | case 1: | |
347 | *val = in_8(addr); | |
348 | break; | |
349 | case 2: | |
350 | *val = in_le16(addr); | |
351 | break; | |
352 | default: | |
353 | *val = in_le32(addr); | |
354 | break; | |
355 | } | |
356 | return PCIBIOS_SUCCESSFUL; | |
357 | } | |
358 | static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, | |
359 | int offset, int len, u32 val) | |
360 | { | |
361 | struct pci_controller *hose; | |
362 | volatile void __iomem *addr; | |
363 | ||
364 | hose = pci_bus_to_host(bus); | |
365 | if (hose == NULL) | |
366 | return PCIBIOS_DEVICE_NOT_FOUND; | |
367 | if (offset >= 0x1000) | |
368 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
369 | addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); | |
370 | if (!addr) | |
371 | return PCIBIOS_DEVICE_NOT_FOUND; | |
372 | /* | |
373 | * Note: the caller has already checked that offset is | |
374 | * suitably aligned and that len is 1, 2 or 4. | |
375 | */ | |
376 | switch (len) { | |
377 | case 1: | |
378 | out_8(addr, val); | |
379 | (void) in_8(addr); | |
380 | break; | |
381 | case 2: | |
382 | out_le16(addr, val); | |
383 | (void) in_le16(addr); | |
384 | break; | |
385 | default: | |
386 | out_le32(addr, val); | |
387 | (void) in_le32(addr); | |
388 | break; | |
389 | } | |
390 | return PCIBIOS_SUCCESSFUL; | |
391 | } | |
392 | ||
393 | static struct pci_ops u4_pcie_pci_ops = | |
394 | { | |
395 | u4_pcie_read_config, | |
396 | u4_pcie_write_config | |
397 | }; | |
398 | ||
1da177e4 LT |
399 | static void __init setup_u3_agp(struct pci_controller* hose) |
400 | { | |
401 | /* On G5, we move AGP up to high bus number so we don't need | |
402 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
399fe2bd | 403 | * on AGP, we'll have to move pci_assign_all_buses to the |
1da177e4 LT |
404 | * pci_controller structure so we enable it for AGP and not for |
405 | * HT childs. | |
406 | * We hard code the address because of the different size of | |
407 | * the reg address cell, we shall fix that by killing struct | |
408 | * reg_property and using some accessor functions instead | |
409 | */ | |
3238e9c9 | 410 | hose->first_busno = 0xf0; |
1da177e4 LT |
411 | hose->last_busno = 0xff; |
412 | hose->ops = &u3_agp_pci_ops; | |
413 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
414 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
415 | ||
416 | u3_agp = hose; | |
417 | } | |
418 | ||
c10af8c3 BH |
419 | static void __init setup_u4_pcie(struct pci_controller* hose) |
420 | { | |
421 | /* We currently only implement the "non-atomic" config space, to | |
422 | * be optimised later. | |
423 | */ | |
424 | hose->ops = &u4_pcie_pci_ops; | |
425 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
426 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
427 | ||
c10af8c3 BH |
428 | u4_pcie = hose; |
429 | } | |
430 | ||
1da177e4 LT |
431 | static void __init setup_u3_ht(struct pci_controller* hose) |
432 | { | |
433 | hose->ops = &u3_ht_pci_ops; | |
434 | ||
435 | /* We hard code the address because of the different size of | |
436 | * the reg address cell, we shall fix that by killing struct | |
437 | * reg_property and using some accessor functions instead | |
438 | */ | |
8c42ec2c | 439 | hose->cfg_data = ioremap(0xf2000000, 0x02000000); |
1da177e4 LT |
440 | |
441 | hose->first_busno = 0; | |
442 | hose->last_busno = 0xef; | |
443 | ||
444 | u3_ht = hose; | |
445 | } | |
446 | ||
447 | static int __init add_bridge(struct device_node *dev) | |
448 | { | |
449 | int len; | |
450 | struct pci_controller *hose; | |
451 | char* disp_name; | |
eeb2b723 | 452 | const int *bus_range; |
1da177e4 | 453 | int primary = 1; |
1da177e4 LT |
454 | |
455 | DBG("Adding PCI host bridge %s\n", dev->full_name); | |
456 | ||
e2eb6392 | 457 | bus_range = of_get_property(dev, "bus-range", &len); |
3238e9c9 AB |
458 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
459 | printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", | |
460 | dev->full_name); | |
461 | } | |
1da177e4 | 462 | |
b5166cc2 | 463 | hose = pcibios_alloc_controller(dev); |
1da177e4 LT |
464 | if (hose == NULL) |
465 | return -ENOMEM; | |
3238e9c9 AB |
466 | hose->first_busno = bus_range ? bus_range[0] : 0; |
467 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
1da177e4 | 468 | |
1da177e4 | 469 | disp_name = NULL; |
55b61fec | 470 | if (of_device_is_compatible(dev, "u3-agp")) { |
3238e9c9 AB |
471 | setup_u3_agp(hose); |
472 | disp_name = "U3-AGP"; | |
473 | primary = 0; | |
55b61fec | 474 | } else if (of_device_is_compatible(dev, "u3-ht")) { |
3238e9c9 AB |
475 | setup_u3_ht(hose); |
476 | disp_name = "U3-HT"; | |
477 | primary = 1; | |
55b61fec | 478 | } else if (of_device_is_compatible(dev, "u4-pcie")) { |
c10af8c3 BH |
479 | setup_u4_pcie(hose); |
480 | disp_name = "U4-PCIE"; | |
481 | primary = 0; | |
3238e9c9 AB |
482 | } |
483 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", | |
484 | disp_name, hose->first_busno, hose->last_busno); | |
485 | ||
486 | /* Interpret the "ranges" property */ | |
487 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
f7abbc19 | 488 | pci_process_bridge_OF_ranges(hose, dev, primary); |
1da177e4 | 489 | |
3238e9c9 AB |
490 | /* Fixup "bus-range" OF property */ |
491 | fixup_bus_range(dev); | |
1da177e4 LT |
492 | |
493 | return 0; | |
494 | } | |
495 | ||
496 | ||
f90bb153 | 497 | void __devinit maple_pci_irq_fixup(struct pci_dev *dev) |
1da177e4 | 498 | { |
f90bb153 BH |
499 | DBG(" -> maple_pci_irq_fixup\n"); |
500 | ||
501 | /* Fixup IRQ for PCIe host */ | |
502 | if (u4_pcie != NULL && dev->bus->number == 0 && | |
503 | pci_bus_to_host(dev->bus) == u4_pcie) { | |
504 | printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); | |
505 | dev->irq = irq_create_mapping(NULL, 1); | |
506 | if (dev->irq != NO_IRQ) | |
507 | set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); | |
508 | } | |
1e1b20a1 | 509 | |
f90bb153 BH |
510 | /* Hide AMD8111 IDE interrupt when in legacy mode so |
511 | * the driver calls pci_get_legacy_ide_irq() | |
512 | */ | |
513 | if (dev->vendor == PCI_VENDOR_ID_AMD && | |
514 | dev->device == PCI_DEVICE_ID_AMD_8111_IDE && | |
515 | (dev->class & 5) != 5) { | |
516 | dev->irq = NO_IRQ; | |
c10af8c3 | 517 | } |
1da177e4 | 518 | |
f90bb153 | 519 | DBG(" <- maple_pci_irq_fixup\n"); |
1da177e4 LT |
520 | } |
521 | ||
522 | static void __init maple_fixup_phb_resources(void) | |
523 | { | |
524 | struct pci_controller *hose, *tmp; | |
525 | ||
526 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
527 | unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
c10af8c3 | 528 | |
1da177e4 LT |
529 | hose->io_resource.start += offset; |
530 | hose->io_resource.end += offset; | |
c10af8c3 | 531 | |
685143ac | 532 | printk(KERN_INFO "PCI Host %d, io start: %llx; io end: %llx\n", |
1da177e4 | 533 | hose->global_number, |
685143ac GKH |
534 | (unsigned long long)hose->io_resource.start, |
535 | (unsigned long long)hose->io_resource.end); | |
1da177e4 LT |
536 | } |
537 | } | |
538 | ||
539 | void __init maple_pci_init(void) | |
540 | { | |
541 | struct device_node *np, *root; | |
542 | struct device_node *ht = NULL; | |
543 | ||
544 | /* Probe root PCI hosts, that is on U3 the AGP host and the | |
545 | * HyperTransport host. That one is actually "kept" around | |
546 | * and actually added last as it's resource management relies | |
547 | * on the AGP resources to have been setup first | |
548 | */ | |
549 | root = of_find_node_by_path("/"); | |
550 | if (root == NULL) { | |
551 | printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n"); | |
552 | return; | |
553 | } | |
554 | for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { | |
f1f00333 | 555 | if (!np->type) |
1da177e4 | 556 | continue; |
f1f00333 NL |
557 | if (strcmp(np->type, "pci") && strcmp(np->type, "ht")) |
558 | continue; | |
55b61fec SR |
559 | if ((of_device_is_compatible(np, "u4-pcie") || |
560 | of_device_is_compatible(np, "u3-agp")) && | |
f1f00333 NL |
561 | add_bridge(np) == 0) |
562 | of_node_get(np); | |
563 | ||
55b61fec | 564 | if (of_device_is_compatible(np, "u3-ht")) { |
1da177e4 LT |
565 | of_node_get(np); |
566 | ht = np; | |
567 | } | |
568 | } | |
569 | of_node_put(root); | |
570 | ||
571 | /* Now setup the HyperTransport host if we found any | |
572 | */ | |
573 | if (ht && add_bridge(ht) != 0) | |
574 | of_node_put(ht); | |
575 | ||
c10af8c3 BH |
576 | /* |
577 | * We need to call pci_setup_phb_io for the HT bridge first | |
578 | * so it gets the I/O port numbers starting at 0, and we | |
579 | * need to call it for the AGP bridge after that so it gets | |
580 | * small positive I/O port numbers. | |
581 | */ | |
582 | if (u3_ht) | |
583 | pci_setup_phb_io(u3_ht, 1); | |
584 | if (u3_agp) | |
585 | pci_setup_phb_io(u3_agp, 0); | |
586 | if (u4_pcie) | |
587 | pci_setup_phb_io(u4_pcie, 0); | |
588 | ||
1da177e4 LT |
589 | /* Fixup the IO resources on our host bridges as the common code |
590 | * does it only for childs of the host bridges | |
591 | */ | |
592 | maple_fixup_phb_resources(); | |
593 | ||
594 | /* Setup the linkage between OF nodes and PHBs */ | |
595 | pci_devs_phb_init(); | |
596 | ||
597 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We | |
598 | * assume there is no P2P bridge on the AGP bus, which should be a | |
599 | * safe assumptions hopefully. | |
600 | */ | |
601 | if (u3_agp) { | |
602 | struct device_node *np = u3_agp->arch_data; | |
1635317f | 603 | PCI_DN(np)->busno = 0xf0; |
1da177e4 | 604 | for (np = np->child; np; np = np->sibling) |
1635317f | 605 | PCI_DN(np)->busno = 0xf0; |
1da177e4 LT |
606 | } |
607 | ||
4558f417 SB |
608 | /* Tell pci.c to not change any resource allocations. */ |
609 | pci_probe_only = 1; | |
1da177e4 LT |
610 | } |
611 | ||
612 | int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel) | |
613 | { | |
614 | struct device_node *np; | |
0ebfff14 BH |
615 | unsigned int defirq = channel ? 15 : 14; |
616 | unsigned int irq; | |
1da177e4 LT |
617 | |
618 | if (pdev->vendor != PCI_VENDOR_ID_AMD || | |
619 | pdev->device != PCI_DEVICE_ID_AMD_8111_IDE) | |
0ebfff14 | 620 | return defirq; |
1da177e4 LT |
621 | |
622 | np = pci_device_to_OF_node(pdev); | |
c10af8c3 BH |
623 | if (np == NULL) { |
624 | printk("Failed to locate OF node for IDE %s\n", | |
625 | pci_name(pdev)); | |
0ebfff14 | 626 | return defirq; |
c10af8c3 | 627 | } |
0ebfff14 BH |
628 | irq = irq_of_parse_and_map(np, channel & 0x1); |
629 | if (irq == NO_IRQ) { | |
630 | printk("Failed to map onboard IDE interrupt for channel %d\n", | |
631 | channel); | |
632 | return defirq; | |
633 | } | |
634 | return irq; | |
1da177e4 LT |
635 | } |
636 | ||
637 | /* XXX: To remove once all firmwares are ok */ | |
638 | static void fixup_maple_ide(struct pci_dev* dev) | |
639 | { | |
c10af8c3 BH |
640 | if (!machine_is(maple)) |
641 | return; | |
642 | ||
1da177e4 LT |
643 | #if 0 /* Enable this to enable IDE port 0 */ |
644 | { | |
645 | u8 v; | |
646 | ||
647 | pci_read_config_byte(dev, 0x40, &v); | |
648 | v |= 2; | |
649 | pci_write_config_byte(dev, 0x40, v); | |
650 | } | |
651 | #endif | |
652 | #if 0 /* fix bus master base */ | |
653 | pci_write_config_dword(dev, 0x20, 0xcc01); | |
654 | printk("old ide resource: %lx -> %lx \n", | |
655 | dev->resource[4].start, dev->resource[4].end); | |
656 | dev->resource[4].start = 0xcc00; | |
657 | dev->resource[4].end = 0xcc10; | |
658 | #endif | |
c10af8c3 | 659 | #if 0 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */ |
1da177e4 LT |
660 | { |
661 | struct pci_dev *apicdev; | |
662 | u32 v; | |
663 | ||
664 | apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0)); | |
665 | if (apicdev == NULL) | |
666 | printk("IDE Fixup IRQ: Can't find IO-APIC !\n"); | |
667 | else { | |
668 | pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14); | |
669 | pci_read_config_dword(apicdev, 0xf4, &v); | |
670 | v &= ~0x00000022; | |
671 | pci_write_config_dword(apicdev, 0xf4, v); | |
672 | pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15); | |
673 | pci_read_config_dword(apicdev, 0xf4, &v); | |
674 | v &= ~0x00000022; | |
675 | pci_write_config_dword(apicdev, 0xf4, v); | |
676 | pci_dev_put(apicdev); | |
677 | } | |
678 | } | |
679 | #endif | |
680 | } | |
681 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, | |
682 | fixup_maple_ide); |