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1/*
2 * Copyright 2007, Olof Johansson, PA Semi
3 *
4 * Based on arch/powerpc/sysdev/mpic_u3msi.c:
5 *
6 * Copyright 2006, Segher Boessenkool, IBM Corporation.
7 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 */
15
38958dd9 16#include <linux/irq.h>
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17#include <linux/msi.h>
18#include <asm/mpic.h>
19#include <asm/prom.h>
20#include <asm/hw_irq.h>
21#include <asm/ppc-pci.h>
25235f71 22#include <asm/msi_bitmap.h>
38958dd9 23
5af7a6f3 24#include <sysdev/mpic.h>
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25
26/* Allocate 16 interrupts per device, to give an alignment of 16,
27 * since that's the size of the grouping w.r.t. affinity. If someone
28 * needs more than 32 MSI's down the road we'll have to rethink this,
29 * but it should be OK for now.
30 */
31#define ALLOC_CHUNK 16
32
33#define PASEMI_MSI_ADDR 0xfc080000
34
35/* A bit ugly, can we get this from the pci_dev somehow? */
36static struct mpic *msi_mpic;
37
38
1c9db525 39static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
38958dd9 40{
1c9db525 41 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
280510f1 42 pci_msi_mask_irq(data);
835c0553 43 mpic_mask_irq(data);
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44}
45
1c9db525 46static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
38958dd9 47{
1c9db525 48 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
835c0553 49 mpic_unmask_irq(data);
280510f1 50 pci_msi_unmask_irq(data);
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51}
52
53static struct irq_chip mpic_pasemi_msi_chip = {
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54 .irq_shutdown = mpic_pasemi_msi_mask_irq,
55 .irq_mask = mpic_pasemi_msi_mask_irq,
56 .irq_unmask = mpic_pasemi_msi_unmask_irq,
57 .irq_eoi = mpic_end_irq,
58 .irq_set_type = mpic_set_irq_type,
59 .irq_set_affinity = mpic_set_affinity,
60 .name = "PASEMI-MSI",
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61};
62
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63static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
64{
65 struct msi_desc *entry;
e297c939 66 irq_hw_number_t hwirq;
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67
68 pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
69
2921d179 70 for_each_pci_msi_entry(entry, pdev) {
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71 if (entry->irq == NO_IRQ)
72 continue;
73
e297c939 74 hwirq = virq_to_hw(entry->irq);
ec775d0e 75 irq_set_msi_desc(entry->irq, NULL);
38958dd9 76 irq_dispose_mapping(entry->irq);
e297c939 77 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK);
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78 }
79
80 return;
81}
82
83static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
84{
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85 unsigned int virq;
86 struct msi_desc *entry;
87 struct msi_msg msg;
25235f71 88 int hwirq;
38958dd9 89
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90 if (type == PCI_CAP_ID_MSIX)
91 pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
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92 pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
93 pdev, nvec, type);
94
95 msg.address_hi = 0;
96 msg.address_lo = PASEMI_MSI_ADDR;
97
2921d179 98 for_each_pci_msi_entry(entry, pdev) {
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99 /* Allocate 16 interrupts for now, since that's the grouping for
100 * affinity. This can be changed later if it turns out 32 is too
101 * few MSIs for someone, but restrictions will apply to how the
102 * sources can be changed independently.
103 */
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104 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
105 ALLOC_CHUNK);
106 if (hwirq < 0) {
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107 pr_debug("pasemi_msi: failed allocating hwirq\n");
108 return hwirq;
109 }
110
111 virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
112 if (virq == NO_IRQ) {
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113 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
114 hwirq);
115 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
116 ALLOC_CHUNK);
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117 return -ENOSPC;
118 }
119
120 /* Vector on MSI is really an offset, the hardware adds
121 * it to the value written at the magic address. So set
122 * it to 0 to remain sane.
123 */
124 mpic_set_vector(virq, 0);
125
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126 irq_set_msi_desc(virq, entry);
127 irq_set_chip(virq, &mpic_pasemi_msi_chip);
128 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
38958dd9 129
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130 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
131 "addr 0x%x\n", virq, hwirq, msg.address_lo);
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132
133 /* Likewise, the device writes [0...511] into the target
134 * register to generate MSI [512...1023]
135 */
136 msg.data = hwirq-0x200;
83a18912 137 pci_write_msi_msg(virq, &msg);
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138 }
139
140 return 0;
141}
142
143int mpic_pasemi_msi_init(struct mpic *mpic)
144{
145 int rc;
83922966 146 struct pci_controller *phb;
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147
148 if (!mpic->irqhost->of_node ||
149 !of_device_is_compatible(mpic->irqhost->of_node,
150 "pasemi,pwrficient-openpic"))
151 return -ENODEV;
152
153 rc = mpic_msi_init_allocator(mpic);
154 if (rc) {
155 pr_debug("pasemi_msi: Error allocating bitmap!\n");
156 return rc;
157 }
158
159 pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
160
161 msi_mpic = mpic;
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162 list_for_each_entry(phb, &hose_list, list_node) {
163 WARN_ON(phb->controller_ops.setup_msi_irqs);
164 phb->controller_ops.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
165 phb->controller_ops.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
166 }
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167
168 return 0;
169}