[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / platforms / powermac / nvram.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 *  Todo: - add support for the OF persistent properties
 */
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/nvram.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/adb.h>
#include <linux/pmu.h>
#include <linux/memblock.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/nvram.h>

#include "pmac.h"

#define DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define NVRAM_SIZE		0x2000	/* 8kB of non-volatile RAM */

#define CORE99_SIGNATURE	0x5a
#define CORE99_ADLER_START	0x14

/* On Core99, nvram is either a sharp, a micron or an AMD flash */
#define SM_FLASH_STATUS_DONE	0x80
#define SM_FLASH_STATUS_ERR	0x38

#define SM_FLASH_CMD_ERASE_CONFIRM	0xd0
#define SM_FLASH_CMD_ERASE_SETUP	0x20
#define SM_FLASH_CMD_RESET		0xff
#define SM_FLASH_CMD_WRITE_SETUP	0x40
#define SM_FLASH_CMD_CLEAR_STATUS	0x50
#define SM_FLASH_CMD_READ_STATUS	0x70

/* CHRP NVRAM header */
struct chrp_header {
  u8		signature;
  u8		cksum;
  u16		len;
  char          name[12];
  u8		data[0];
};

struct core99_header {
  struct chrp_header	hdr;
  u32			adler;
  u32			generation;
  u32			reserved[2];
};

/*
 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
 */
static int nvram_naddrs;
static volatile unsigned char __iomem *nvram_data;
static int is_core_99;
static int core99_bank = 0;
static int nvram_partitions[3];
// XXX Turn that into a sem
static DEFINE_RAW_SPINLOCK(nv_lock);

static int (*core99_write_bank)(int bank, u8* datas);
static int (*core99_erase_bank)(int bank);

static char *nvram_image;


static unsigned char core99_nvram_read_byte(int addr)
{
	if (nvram_image == NULL)
		return 0xff;
	return nvram_image[addr];
}

static void core99_nvram_write_byte(int addr, unsigned char val)
{
	if (nvram_image == NULL)
		return;
	nvram_image[addr] = val;
}

static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
{
	int i;

	if (nvram_image == NULL)
		return -ENODEV;
	if (*index > NVRAM_SIZE)
		return 0;

	i = *index;
	if (i + count > NVRAM_SIZE)
		count = NVRAM_SIZE - i;

	memcpy(buf, &nvram_image[i], count);
	*index = i + count;
	return count;
}

static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
{
	int i;

	if (nvram_image == NULL)
		return -ENODEV;
	if (*index > NVRAM_SIZE)
		return 0;

	i = *index;
	if (i + count > NVRAM_SIZE)
		count = NVRAM_SIZE - i;

	memcpy(&nvram_image[i], buf, count);
	*index = i + count;
	return count;
}

static ssize_t core99_nvram_size(void)
{
	if (nvram_image == NULL)
		return -ENODEV;
	return NVRAM_SIZE;
}

#ifdef CONFIG_PPC32
static volatile unsigned char __iomem *nvram_addr;
static int nvram_mult;

static ssize_t ppc32_nvram_size(void)
{
	return NVRAM_SIZE;
}

static unsigned char direct_nvram_read_byte(int addr)
{
	return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
}

static void direct_nvram_write_byte(int addr, unsigned char val)
{
	out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
}


static unsigned char indirect_nvram_read_byte(int addr)
{
	unsigned char val;
	unsigned long flags;

	raw_spin_lock_irqsave(&nv_lock, flags);
	out_8(nvram_addr, addr >> 5);
	val = in_8(&nvram_data[(addr & 0x1f) << 4]);
	raw_spin_unlock_irqrestore(&nv_lock, flags);

	return val;
}

static void indirect_nvram_write_byte(int addr, unsigned char val)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&nv_lock, flags);
	out_8(nvram_addr, addr >> 5);
	out_8(&nvram_data[(addr & 0x1f) << 4], val);
	raw_spin_unlock_irqrestore(&nv_lock, flags);
}


#ifdef CONFIG_ADB_PMU

static void pmu_nvram_complete(struct adb_request *req)
{
	if (req->arg)
		complete((struct completion *)req->arg);
}

static unsigned char pmu_nvram_read_byte(int addr)
{
	struct adb_request req;
	DECLARE_COMPLETION_ONSTACK(req_complete);
	
	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
			(addr >> 8) & 0xff, addr & 0xff))
		return 0xff;
	if (system_state == SYSTEM_RUNNING)
		wait_for_completion(&req_complete);
	while (!req.complete)
		pmu_poll();
	return req.reply[0];
}

static void pmu_nvram_write_byte(int addr, unsigned char val)
{
	struct adb_request req;
	DECLARE_COMPLETION_ONSTACK(req_complete);
	
	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
			(addr >> 8) & 0xff, addr & 0xff, val))
		return;
	if (system_state == SYSTEM_RUNNING)
		wait_for_completion(&req_complete);
	while (!req.complete)
		pmu_poll();
}

#endif /* CONFIG_ADB_PMU */
#endif /* CONFIG_PPC32 */

static u8 chrp_checksum(struct chrp_header* hdr)
{
	u8 *ptr;
	u16 sum = hdr->signature;
	for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
		sum += *ptr;
	while (sum > 0xFF)
		sum = (sum & 0xFF) + (sum>>8);
	return sum;
}

static u32 core99_calc_adler(u8 *buffer)
{
	int cnt;
	u32 low, high;

   	buffer += CORE99_ADLER_START;
	low = 1;
	high = 0;
	for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
		if ((cnt % 5000) == 0) {
			high  %= 65521UL;
			high %= 65521UL;
		}
		low += buffer[cnt];
		high += low;
	}
	low  %= 65521UL;
	high %= 65521UL;

	return (high << 16) | low;
}

static u32 core99_check(u8* datas)
{
	struct core99_header* hdr99 = (struct core99_header*)datas;

	if (hdr99->hdr.signature != CORE99_SIGNATURE) {
		DBG("Invalid signature\n");
		return 0;
	}
	if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
		DBG("Invalid checksum\n");
		return 0;
	}
	if (hdr99->adler != core99_calc_adler(datas)) {
		DBG("Invalid adler\n");
		return 0;
	}
	return hdr99->generation;
}

static int sm_erase_bank(int bank)
{
	int stat;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);

	out_8(base, SM_FLASH_CMD_ERASE_SETUP);
	out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
	timeout = 0;
	do {
		if (++timeout > 1000000) {
			printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
			break;
		}
		out_8(base, SM_FLASH_CMD_READ_STATUS);
		stat = in_8(base);
	} while (!(stat & SM_FLASH_STATUS_DONE));

	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	out_8(base, SM_FLASH_CMD_RESET);

	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
		return -ENXIO;
	}
	return 0;
}

static int sm_write_bank(int bank, u8* datas)
{
	int i, stat = 0;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);

	for (i=0; i<NVRAM_SIZE; i++) {
		out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
		udelay(1);
		out_8(base+i, datas[i]);
		timeout = 0;
		do {
			if (++timeout > 1000000) {
				printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
				break;
			}
			out_8(base, SM_FLASH_CMD_READ_STATUS);
			stat = in_8(base);
		} while (!(stat & SM_FLASH_STATUS_DONE));
		if (!(stat & SM_FLASH_STATUS_DONE))
			break;
	}
	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	out_8(base, SM_FLASH_CMD_RESET);
	if (memcmp(base, datas, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
		return -ENXIO;
	}
	return 0;
}

static int amd_erase_bank(int bank)
{
	int stat = 0;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: AMD Erasing bank %d...\n", bank);

	/* Unlock 1 */
	out_8(base+0x555, 0xaa);
	udelay(1);
	/* Unlock 2 */
	out_8(base+0x2aa, 0x55);
	udelay(1);

	/* Sector-Erase */
	out_8(base+0x555, 0x80);
	udelay(1);
	out_8(base+0x555, 0xaa);
	udelay(1);
	out_8(base+0x2aa, 0x55);
	udelay(1);
	out_8(base, 0x30);
	udelay(1);

	timeout = 0;
	do {
		if (++timeout > 1000000) {
			printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
			break;
		}
		stat = in_8(base) ^ in_8(base);
	} while (stat != 0);
	
	/* Reset */
	out_8(base, 0xf0);
	udelay(1);

	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: AMD flash erase failed !\n");
		return -ENXIO;
	}
	return 0;
}

static int amd_write_bank(int bank, u8* datas)
{
	int i, stat = 0;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: AMD Writing bank %d...\n", bank);

	for (i=0; i<NVRAM_SIZE; i++) {
		/* Unlock 1 */
		out_8(base+0x555, 0xaa);
		udelay(1);
		/* Unlock 2 */
		out_8(base+0x2aa, 0x55);
		udelay(1);

		/* Write single word */
		out_8(base+0x555, 0xa0);
		udelay(1);
		out_8(base+i, datas[i]);
		
		timeout = 0;
		do {
			if (++timeout > 1000000) {
				printk(KERN_ERR "nvram: AMD flash write timeout !\n");
				break;
			}
			stat = in_8(base) ^ in_8(base);
		} while (stat != 0);
		if (stat != 0)
			break;
	}

	/* Reset */
	out_8(base, 0xf0);
	udelay(1);

	if (memcmp(base, datas, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: AMD flash write failed !\n");
		return -ENXIO;
	}
	return 0;
}

static void __init lookup_partitions(void)
{
	u8 buffer[17];
	int i, offset;
	struct chrp_header* hdr;

	if (pmac_newworld) {
		nvram_partitions[pmac_nvram_OF] = -1;
		nvram_partitions[pmac_nvram_XPRAM] = -1;
		nvram_partitions[pmac_nvram_NR] = -1;
		hdr = (struct chrp_header *)buffer;

		offset = 0;
		buffer[16] = 0;
		do {
			for (i=0;i<16;i++)
				buffer[i] = ppc_md.nvram_read_val(offset+i);
			if (!strcmp(hdr->name, "common"))
				nvram_partitions[pmac_nvram_OF] = offset + 0x10;
			if (!strcmp(hdr->name, "APL,MacOS75")) {
				nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
				nvram_partitions[pmac_nvram_NR] = offset + 0x110;
			}
			offset += (hdr->len * 0x10);
		} while(offset < NVRAM_SIZE);
	} else {
		nvram_partitions[pmac_nvram_OF] = 0x1800;
		nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
		nvram_partitions[pmac_nvram_NR] = 0x1400;
	}
	DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
	DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
	DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
}

static void core99_nvram_sync(void)
{
	struct core99_header* hdr99;
	unsigned long flags;

	if (!is_core_99 || !nvram_data || !nvram_image)
		return;

	raw_spin_lock_irqsave(&nv_lock, flags);
	if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
		NVRAM_SIZE))
		goto bail;

	DBG("Updating nvram...\n");

	hdr99 = (struct core99_header*)nvram_image;
	hdr99->generation++;
	hdr99->hdr.signature = CORE99_SIGNATURE;
	hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
	hdr99->adler = core99_calc_adler(nvram_image);
	core99_bank = core99_bank ? 0 : 1;
	if (core99_erase_bank)
		if (core99_erase_bank(core99_bank)) {
			printk("nvram: Error erasing bank %d\n", core99_bank);
			goto bail;
		}
	if (core99_write_bank)
		if (core99_write_bank(core99_bank, nvram_image))
			printk("nvram: Error writing bank %d\n", core99_bank);
 bail:
	raw_spin_unlock_irqrestore(&nv_lock, flags);

#ifdef DEBUG
       	mdelay(2000);
#endif
}

static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
{
	int i;
	u32 gen_bank0, gen_bank1;

	if (nvram_naddrs < 1) {
		printk(KERN_ERR "nvram: no address\n");
		return -EINVAL;
	}
	nvram_image = memblock_alloc(NVRAM_SIZE, SMP_CACHE_BYTES);
	if (!nvram_image)
		panic("%s: Failed to allocate %u bytes\n", __func__,
		      NVRAM_SIZE);
	nvram_data = ioremap(addr, NVRAM_SIZE*2);
	nvram_naddrs = 1; /* Make sure we get the correct case */

	DBG("nvram: Checking bank 0...\n");

	gen_bank0 = core99_check((u8 *)nvram_data);
	gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
	core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;

	DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
	DBG("nvram: Active bank is: %d\n", core99_bank);

	for (i=0; i<NVRAM_SIZE; i++)
		nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];

	ppc_md.nvram_read_val	= core99_nvram_read_byte;
	ppc_md.nvram_write_val	= core99_nvram_write_byte;
	ppc_md.nvram_read	= core99_nvram_read;
	ppc_md.nvram_write	= core99_nvram_write;
	ppc_md.nvram_size	= core99_nvram_size;
	ppc_md.nvram_sync	= core99_nvram_sync;
	ppc_md.machine_shutdown	= core99_nvram_sync;
	/* 
	 * Maybe we could be smarter here though making an exclusive list
	 * of known flash chips is a bit nasty as older OF didn't provide us
	 * with a useful "compatible" entry. A solution would be to really
	 * identify the chip using flash id commands and base ourselves on
	 * a list of known chips IDs
	 */
	if (of_device_is_compatible(dp, "amd-0137")) {
		core99_erase_bank = amd_erase_bank;
		core99_write_bank = amd_write_bank;
	} else {
		core99_erase_bank = sm_erase_bank;
		core99_write_bank = sm_write_bank;
	}
	return 0;
}

int __init pmac_nvram_init(void)
{
	struct device_node *dp;
	struct resource r1, r2;
	unsigned int s1 = 0, s2 = 0;
	int err = 0;

	nvram_naddrs = 0;

	dp = of_find_node_by_name(NULL, "nvram");
	if (dp == NULL) {
		printk(KERN_ERR "Can't find NVRAM device\n");
		return -ENODEV;
	}

	/* Try to obtain an address */
	if (of_address_to_resource(dp, 0, &r1) == 0) {
		nvram_naddrs = 1;
		s1 = resource_size(&r1);
		if (of_address_to_resource(dp, 1, &r2) == 0) {
			nvram_naddrs = 2;
			s2 = resource_size(&r2);
		}
	}

	is_core_99 = of_device_is_compatible(dp, "nvram,flash");
	if (is_core_99) {
		err = core99_nvram_setup(dp, r1.start);
		goto bail;
	}

#ifdef CONFIG_PPC32
	if (machine_is(chrp) && nvram_naddrs == 1) {
		nvram_data = ioremap(r1.start, s1);
		nvram_mult = 1;
		ppc_md.nvram_read_val	= direct_nvram_read_byte;
		ppc_md.nvram_write_val	= direct_nvram_write_byte;
		ppc_md.nvram_size	= ppc32_nvram_size;
	} else if (nvram_naddrs == 1) {
		nvram_data = ioremap(r1.start, s1);
		nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
		ppc_md.nvram_read_val	= direct_nvram_read_byte;
		ppc_md.nvram_write_val	= direct_nvram_write_byte;
		ppc_md.nvram_size	= ppc32_nvram_size;
	} else if (nvram_naddrs == 2) {
		nvram_addr = ioremap(r1.start, s1);
		nvram_data = ioremap(r2.start, s2);
		ppc_md.nvram_read_val	= indirect_nvram_read_byte;
		ppc_md.nvram_write_val	= indirect_nvram_write_byte;
		ppc_md.nvram_size	= ppc32_nvram_size;
	} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
#ifdef CONFIG_ADB_PMU
		nvram_naddrs = -1;
		ppc_md.nvram_read_val	= pmu_nvram_read_byte;
		ppc_md.nvram_write_val	= pmu_nvram_write_byte;
		ppc_md.nvram_size	= ppc32_nvram_size;
#endif /* CONFIG_ADB_PMU */
	} else {
		printk(KERN_ERR "Incompatible type of NVRAM\n");
		err = -ENXIO;
	}
#endif /* CONFIG_PPC32 */
bail:
	of_node_put(dp);
	if (err == 0)
		lookup_partitions();
	return err;
}

int pmac_get_partition(int partition)
{
	return nvram_partitions[partition];
}

u8 pmac_xpram_read(int xpaddr)
{
	int offset = pmac_get_partition(pmac_nvram_XPRAM);

	if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
		return 0xff;

	return ppc_md.nvram_read_val(xpaddr + offset);
}

void pmac_xpram_write(int xpaddr, u8 data)
{
	int offset = pmac_get_partition(pmac_nvram_XPRAM);

	if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
		return;

	ppc_md.nvram_write_val(xpaddr + offset, data);
}

EXPORT_SYMBOL(pmac_get_partition);
EXPORT_SYMBOL(pmac_xpram_read);
EXPORT_SYMBOL(pmac_xpram_write);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
14cf11af	2	/*
14cf11af PM	3	* Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
14cf11af PM	4	*
14cf11af PM	5	* Todo: - add support for the OF persistent properties
14cf11af PM	6	*/
4b16f8e2	7	#include <linux/export.h>
14cf11af PM	8	#include <linux/kernel.h>
	9	#include <linux/stddef.h>
	10	#include <linux/string.h>
	11	#include <linux/nvram.h>
	12	#include <linux/init.h>
14cf11af PM	13	#include <linux/delay.h>
	14	#include <linux/errno.h>
	15	#include <linux/adb.h>
	16	#include <linux/pmu.h>
57c8a661	17	#include <linux/memblock.h>
14cf11af PM	18	#include <linux/completion.h>
	19	#include <linux/spinlock.h>
	20	#include <asm/sections.h>
	21	#include <asm/io.h>
14cf11af PM	22	#include <asm/prom.h>
	23	#include <asm/machdep.h>
	24	#include <asm/nvram.h>
	25
0ebfff14 BH	26	#include "pmac.h"
0ebfff14 BH	27
14cf11af PM	28	#define DEBUG
	29
	30	#ifdef DEBUG
	31	#define DBG(x...) printk(x)
	32	#else
	33	#define DBG(x...)
	34	#endif
	35
	36	#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
	37
	38	#define CORE99_SIGNATURE 0x5a
	39	#define CORE99_ADLER_START 0x14
	40
	41	/* On Core99, nvram is either a sharp, a micron or an AMD flash */
	42	#define SM_FLASH_STATUS_DONE 0x80
35499c01 PM	43	#define SM_FLASH_STATUS_ERR 0x38
35499c01 PM	44
14cf11af PM	45	#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
	46	#define SM_FLASH_CMD_ERASE_SETUP 0x20
	47	#define SM_FLASH_CMD_RESET 0xff
	48	#define SM_FLASH_CMD_WRITE_SETUP 0x40
	49	#define SM_FLASH_CMD_CLEAR_STATUS 0x50
	50	#define SM_FLASH_CMD_READ_STATUS 0x70
	51
	52	/* CHRP NVRAM header */
	53	struct chrp_header {
	54	u8 signature;
	55	u8 cksum;
	56	u16 len;
	57	char name[12];
	58	u8 data[0];
	59	};
	60
	61	struct core99_header {
	62	struct chrp_header hdr;
	63	u32 adler;
	64	u32 generation;
	65	u32 reserved[2];
	66	};
	67
	68	/*
	69	* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
	70	*/
	71	static int nvram_naddrs;
af308377	72	static volatile unsigned char __iomem *nvram_data;
35499c01	73	static int is_core_99;
14cf11af PM	74	static int core99_bank = 0;
14cf11af PM	75	static int nvram_partitions[3];
35499c01	76	// XXX Turn that into a sem
7d725bdc	77	static DEFINE_RAW_SPINLOCK(nv_lock);
14cf11af	78
14cf11af PM	79	static int (core99_write_bank)(int bank, u8 datas);
	80	static int (*core99_erase_bank)(int bank);
	81
	82	static char *nvram_image;
	83
	84
	85	static unsigned char core99_nvram_read_byte(int addr)
	86	{
	87	if (nvram_image == NULL)
	88	return 0xff;
	89	return nvram_image[addr];
	90	}
	91
	92	static void core99_nvram_write_byte(int addr, unsigned char val)
	93	{
	94	if (nvram_image == NULL)
	95	return;
	96	nvram_image[addr] = val;
	97	}
	98
35499c01 PM	99	static ssize_t core99_nvram_read(char buf, size_t count, loff_t index)
	100	{
	101	int i;
	102
	103	if (nvram_image == NULL)
	104	return -ENODEV;
	105	if (*index > NVRAM_SIZE)
	106	return 0;
	107
	108	i = *index;
	109	if (i + count > NVRAM_SIZE)
	110	count = NVRAM_SIZE - i;
	111
	112	memcpy(buf, &nvram_image[i], count);
	113	*index = i + count;
	114	return count;
	115	}
	116
	117	static ssize_t core99_nvram_write(char buf, size_t count, loff_t index)
	118	{
	119	int i;
	120
	121	if (nvram_image == NULL)
	122	return -ENODEV;
	123	if (*index > NVRAM_SIZE)
	124	return 0;
	125
	126	i = *index;
	127	if (i + count > NVRAM_SIZE)
	128	count = NVRAM_SIZE - i;
	129
	130	memcpy(&nvram_image[i], buf, count);
	131	*index = i + count;
	132	return count;
	133	}
	134
	135	static ssize_t core99_nvram_size(void)
	136	{
	137	if (nvram_image == NULL)
	138	return -ENODEV;
	139	return NVRAM_SIZE;
	140	}
	141
	142	#ifdef CONFIG_PPC32
af308377	143	static volatile unsigned char __iomem *nvram_addr;
35499c01	144	static int nvram_mult;
14cf11af	145
ebcebc7f FT	146	static ssize_t ppc32_nvram_size(void)
	147	{
	148	return NVRAM_SIZE;
	149	}
	150
14cf11af PM	151	static unsigned char direct_nvram_read_byte(int addr)
	152	{
	153	return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
	154	}
	155
	156	static void direct_nvram_write_byte(int addr, unsigned char val)
	157	{
	158	out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
	159	}
	160
	161
	162	static unsigned char indirect_nvram_read_byte(int addr)
	163	{
	164	unsigned char val;
	165	unsigned long flags;
	166
7d725bdc	167	raw_spin_lock_irqsave(&nv_lock, flags);
14cf11af PM	168	out_8(nvram_addr, addr >> 5);
14cf11af PM	169	val = in_8(&nvram_data[(addr & 0x1f) << 4]);
7d725bdc	170	raw_spin_unlock_irqrestore(&nv_lock, flags);
14cf11af PM	171
	172	return val;
	173	}
	174
	175	static void indirect_nvram_write_byte(int addr, unsigned char val)
	176	{
	177	unsigned long flags;
	178
7d725bdc	179	raw_spin_lock_irqsave(&nv_lock, flags);
14cf11af PM	180	out_8(nvram_addr, addr >> 5);
14cf11af PM	181	out_8(&nvram_data[(addr & 0x1f) << 4], val);
7d725bdc	182	raw_spin_unlock_irqrestore(&nv_lock, flags);
14cf11af PM	183	}
	184
	185
	186	#ifdef CONFIG_ADB_PMU
	187
	188	static void pmu_nvram_complete(struct adb_request *req)
	189	{
	190	if (req->arg)
	191	complete((struct completion *)req->arg);
	192	}
	193
	194	static unsigned char pmu_nvram_read_byte(int addr)
	195	{
	196	struct adb_request req;
6e9a4738	197	DECLARE_COMPLETION_ONSTACK(req_complete);
14cf11af PM	198
	199	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	200	if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
	201	(addr >> 8) & 0xff, addr & 0xff))
	202	return 0xff;
	203	if (system_state == SYSTEM_RUNNING)
	204	wait_for_completion(&req_complete);
	205	while (!req.complete)
	206	pmu_poll();
	207	return req.reply[0];
	208	}
	209
	210	static void pmu_nvram_write_byte(int addr, unsigned char val)
	211	{
	212	struct adb_request req;
6e9a4738	213	DECLARE_COMPLETION_ONSTACK(req_complete);
14cf11af PM	214
	215	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	216	if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
	217	(addr >> 8) & 0xff, addr & 0xff, val))
	218	return;
	219	if (system_state == SYSTEM_RUNNING)
	220	wait_for_completion(&req_complete);
	221	while (!req.complete)
	222	pmu_poll();
	223	}
	224
	225	#endif /* CONFIG_ADB_PMU */
35499c01	226	#endif /* CONFIG_PPC32 */
14cf11af PM	227
	228	static u8 chrp_checksum(struct chrp_header* hdr)
	229	{
	230	u8 *ptr;
	231	u16 sum = hdr->signature;
	232	for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
	233	sum += *ptr;
	234	while (sum > 0xFF)
	235	sum = (sum & 0xFF) + (sum>>8);
	236	return sum;
	237	}
	238
	239	static u32 core99_calc_adler(u8 *buffer)
	240	{
	241	int cnt;
	242	u32 low, high;
	243
	244	buffer += CORE99_ADLER_START;
	245	low = 1;
	246	high = 0;
	247	for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
	248	if ((cnt % 5000) == 0) {
	249	high %= 65521UL;
	250	high %= 65521UL;
	251	}
	252	low += buffer[cnt];
	253	high += low;
	254	}
	255	low %= 65521UL;
	256	high %= 65521UL;
	257
	258	return (high << 16) \| low;
	259	}
	260
	261	static u32 core99_check(u8* datas)
	262	{
	263	struct core99_header* hdr99 = (struct core99_header*)datas;
	264
	265	if (hdr99->hdr.signature != CORE99_SIGNATURE) {
	266	DBG("Invalid signature\n");
	267	return 0;
	268	}
	269	if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
	270	DBG("Invalid checksum\n");
	271	return 0;
	272	}
	273	if (hdr99->adler != core99_calc_adler(datas)) {
	274	DBG("Invalid adler\n");
	275	return 0;
	276	}
	277	return hdr99->generation;
	278	}
	279
	280	static int sm_erase_bank(int bank)
	281	{
2d4b9712	282	int stat;
14cf11af PM	283	unsigned long timeout;
14cf11af PM	284
af308377	285	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	286
	287	DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
	288
	289	out_8(base, SM_FLASH_CMD_ERASE_SETUP);
	290	out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
	291	timeout = 0;
	292	do {
	293	if (++timeout > 1000000) {
35499c01	294	printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
14cf11af PM	295	break;
	296	}
	297	out_8(base, SM_FLASH_CMD_READ_STATUS);
	298	stat = in_8(base);
	299	} while (!(stat & SM_FLASH_STATUS_DONE));
	300
	301	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	302	out_8(base, SM_FLASH_CMD_RESET);
	303
2d4b9712 AM	304	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
	305	printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
	306	return -ENXIO;
	307	}
14cf11af PM	308	return 0;
	309	}
	310
	311	static int sm_write_bank(int bank, u8* datas)
	312	{
	313	int i, stat = 0;
	314	unsigned long timeout;
	315
af308377	316	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	317
	318	DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
	319
	320	for (i=0; i<NVRAM_SIZE; i++) {
	321	out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
	322	udelay(1);
	323	out_8(base+i, datas[i]);
	324	timeout = 0;
	325	do {
	326	if (++timeout > 1000000) {
	327	printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
	328	break;
	329	}
	330	out_8(base, SM_FLASH_CMD_READ_STATUS);
	331	stat = in_8(base);
	332	} while (!(stat & SM_FLASH_STATUS_DONE));
	333	if (!(stat & SM_FLASH_STATUS_DONE))
	334	break;
	335	}
	336	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	337	out_8(base, SM_FLASH_CMD_RESET);
2d4b9712 AM	338	if (memcmp(base, datas, NVRAM_SIZE)) {
	339	printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
	340	return -ENXIO;
	341	}
14cf11af PM	342	return 0;
	343	}
	344
	345	static int amd_erase_bank(int bank)
	346	{
2d4b9712	347	int stat = 0;
14cf11af PM	348	unsigned long timeout;
14cf11af PM	349
af308377	350	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	351
	352	DBG("nvram: AMD Erasing bank %d...\n", bank);
	353
	354	/* Unlock 1 */
	355	out_8(base+0x555, 0xaa);
	356	udelay(1);
	357	/* Unlock 2 */
	358	out_8(base+0x2aa, 0x55);
	359	udelay(1);
	360
	361	/* Sector-Erase */
	362	out_8(base+0x555, 0x80);
	363	udelay(1);
	364	out_8(base+0x555, 0xaa);
	365	udelay(1);
	366	out_8(base+0x2aa, 0x55);
	367	udelay(1);
	368	out_8(base, 0x30);
	369	udelay(1);
	370
	371	timeout = 0;
	372	do {
	373	if (++timeout > 1000000) {
	374	printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
	375	break;
	376	}
	377	stat = in_8(base) ^ in_8(base);
	378	} while (stat != 0);
	379
	380	/* Reset */
	381	out_8(base, 0xf0);
	382	udelay(1);
2d4b9712 AM	383
	384	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
	385	printk(KERN_ERR "nvram: AMD flash erase failed !\n");
	386	return -ENXIO;
	387	}
14cf11af PM	388	return 0;
	389	}
	390
	391	static int amd_write_bank(int bank, u8* datas)
	392	{
	393	int i, stat = 0;
	394	unsigned long timeout;
	395
af308377	396	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	397
	398	DBG("nvram: AMD Writing bank %d...\n", bank);
	399
	400	for (i=0; i<NVRAM_SIZE; i++) {
	401	/* Unlock 1 */
	402	out_8(base+0x555, 0xaa);
	403	udelay(1);
	404	/* Unlock 2 */
	405	out_8(base+0x2aa, 0x55);
	406	udelay(1);
	407
	408	/* Write single word */
	409	out_8(base+0x555, 0xa0);
	410	udelay(1);
	411	out_8(base+i, datas[i]);
	412
	413	timeout = 0;
	414	do {
	415	if (++timeout > 1000000) {
	416	printk(KERN_ERR "nvram: AMD flash write timeout !\n");
	417	break;
	418	}
	419	stat = in_8(base) ^ in_8(base);
	420	} while (stat != 0);
	421	if (stat != 0)
	422	break;
	423	}
	424
	425	/* Reset */
	426	out_8(base, 0xf0);
	427	udelay(1);
	428
2d4b9712 AM	429	if (memcmp(base, datas, NVRAM_SIZE)) {
	430	printk(KERN_ERR "nvram: AMD flash write failed !\n");
	431	return -ENXIO;
	432	}
14cf11af PM	433	return 0;
	434	}
	435
	436	static void __init lookup_partitions(void)
	437	{
	438	u8 buffer[17];
	439	int i, offset;
	440	struct chrp_header* hdr;
	441
	442	if (pmac_newworld) {
	443	nvram_partitions[pmac_nvram_OF] = -1;
	444	nvram_partitions[pmac_nvram_XPRAM] = -1;
	445	nvram_partitions[pmac_nvram_NR] = -1;
	446	hdr = (struct chrp_header *)buffer;
	447
	448	offset = 0;
	449	buffer[16] = 0;
	450	do {
	451	for (i=0;i<16;i++)
35499c01	452	buffer[i] = ppc_md.nvram_read_val(offset+i);
14cf11af PM	453	if (!strcmp(hdr->name, "common"))
	454	nvram_partitions[pmac_nvram_OF] = offset + 0x10;
	455	if (!strcmp(hdr->name, "APL,MacOS75")) {
	456	nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
	457	nvram_partitions[pmac_nvram_NR] = offset + 0x110;
	458	}
	459	offset += (hdr->len * 0x10);
	460	} while(offset < NVRAM_SIZE);
	461	} else {
	462	nvram_partitions[pmac_nvram_OF] = 0x1800;
	463	nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
	464	nvram_partitions[pmac_nvram_NR] = 0x1400;
	465	}
	466	DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
	467	DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
	468	DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
	469	}
	470
	471	static void core99_nvram_sync(void)
	472	{
	473	struct core99_header* hdr99;
	474	unsigned long flags;
	475
	476	if (!is_core_99 \|\| !nvram_data \|\| !nvram_image)
	477	return;
	478
7d725bdc	479	raw_spin_lock_irqsave(&nv_lock, flags);
14cf11af PM	480	if (!memcmp(nvram_image, (u8)nvram_data + core99_bankNVRAM_SIZE,
	481	NVRAM_SIZE))
	482	goto bail;
	483
	484	DBG("Updating nvram...\n");
	485
	486	hdr99 = (struct core99_header*)nvram_image;
	487	hdr99->generation++;
	488	hdr99->hdr.signature = CORE99_SIGNATURE;
	489	hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
	490	hdr99->adler = core99_calc_adler(nvram_image);
	491	core99_bank = core99_bank ? 0 : 1;
	492	if (core99_erase_bank)
	493	if (core99_erase_bank(core99_bank)) {
	494	printk("nvram: Error erasing bank %d\n", core99_bank);
	495	goto bail;
	496	}
	497	if (core99_write_bank)
	498	if (core99_write_bank(core99_bank, nvram_image))
	499	printk("nvram: Error writing bank %d\n", core99_bank);
	500	bail:
7d725bdc	501	raw_spin_unlock_irqrestore(&nv_lock, flags);
14cf11af PM	502
	503	#ifdef DEBUG
	504	mdelay(2000);
	505	#endif
	506	}
	507
cc5d0189	508	static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
35499c01 PM	509	{
	510	int i;
	511	u32 gen_bank0, gen_bank1;
	512
	513	if (nvram_naddrs < 1) {
	514	printk(KERN_ERR "nvram: no address\n");
	515	return -EINVAL;
	516	}
7e1c4e27	517	nvram_image = memblock_alloc(NVRAM_SIZE, SMP_CACHE_BYTES);
8a7f97b9 MR	518	if (!nvram_image)
	519	panic("%s: Failed to allocate %u bytes\n", __func__,
	520	NVRAM_SIZE);
cc5d0189	521	nvram_data = ioremap(addr, NVRAM_SIZE*2);
35499c01 PM	522	nvram_naddrs = 1; /* Make sure we get the correct case */
	523
	524	DBG("nvram: Checking bank 0...\n");
	525
	526	gen_bank0 = core99_check((u8 *)nvram_data);
	527	gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
	528	core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
	529
	530	DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
	531	DBG("nvram: Active bank is: %d\n", core99_bank);
	532
	533	for (i=0; i<NVRAM_SIZE; i++)
	534	nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
	535
	536	ppc_md.nvram_read_val = core99_nvram_read_byte;
	537	ppc_md.nvram_write_val = core99_nvram_write_byte;
	538	ppc_md.nvram_read = core99_nvram_read;
	539	ppc_md.nvram_write = core99_nvram_write;
	540	ppc_md.nvram_size = core99_nvram_size;
	541	ppc_md.nvram_sync = core99_nvram_sync;
3d1229d6	542	ppc_md.machine_shutdown = core99_nvram_sync;
35499c01 PM	543	/*
	544	* Maybe we could be smarter here though making an exclusive list
	545	* of known flash chips is a bit nasty as older OF didn't provide us
	546	* with a useful "compatible" entry. A solution would be to really
	547	* identify the chip using flash id commands and base ourselves on
	548	* a list of known chips IDs
	549	*/
55b61fec	550	if (of_device_is_compatible(dp, "amd-0137")) {
35499c01 PM	551	core99_erase_bank = amd_erase_bank;
	552	core99_write_bank = amd_write_bank;
	553	} else {
	554	core99_erase_bank = sm_erase_bank;
	555	core99_write_bank = sm_write_bank;
	556	}
	557	return 0;
	558	}
	559
	560	int __init pmac_nvram_init(void)
14cf11af PM	561	{
14cf11af PM	562	struct device_node *dp;
cc5d0189 BH	563	struct resource r1, r2;
cc5d0189 BH	564	unsigned int s1 = 0, s2 = 0;
35499c01	565	int err = 0;
14cf11af PM	566
	567	nvram_naddrs = 0;
	568
cc5d0189	569	dp = of_find_node_by_name(NULL, "nvram");
14cf11af PM	570	if (dp == NULL) {
14cf11af PM	571	printk(KERN_ERR "Can't find NVRAM device\n");
35499c01	572	return -ENODEV;
14cf11af	573	}
cc5d0189 BH	574
	575	/* Try to obtain an address */
	576	if (of_address_to_resource(dp, 0, &r1) == 0) {
	577	nvram_naddrs = 1;
28f65c11	578	s1 = resource_size(&r1);
cc5d0189 BH	579	if (of_address_to_resource(dp, 1, &r2) == 0) {
cc5d0189 BH	580	nvram_naddrs = 2;
28f65c11	581	s2 = resource_size(&r2);
cc5d0189 BH	582	}
	583	}
	584
55b61fec	585	is_core_99 = of_device_is_compatible(dp, "nvram,flash");
cc5d0189 BH	586	if (is_core_99) {
	587	err = core99_nvram_setup(dp, r1.start);
	588	goto bail;
	589	}
	590
35499c01	591	#ifdef CONFIG_PPC32
e8222502	592	if (machine_is(chrp) && nvram_naddrs == 1) {
cc5d0189	593	nvram_data = ioremap(r1.start, s1);
14cf11af PM	594	nvram_mult = 1;
	595	ppc_md.nvram_read_val = direct_nvram_read_byte;
	596	ppc_md.nvram_write_val = direct_nvram_write_byte;
ebcebc7f	597	ppc_md.nvram_size = ppc32_nvram_size;
14cf11af	598	} else if (nvram_naddrs == 1) {
cc5d0189 BH	599	nvram_data = ioremap(r1.start, s1);
cc5d0189 BH	600	nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
14cf11af PM	601	ppc_md.nvram_read_val = direct_nvram_read_byte;
14cf11af PM	602	ppc_md.nvram_write_val = direct_nvram_write_byte;
ebcebc7f	603	ppc_md.nvram_size = ppc32_nvram_size;
14cf11af	604	} else if (nvram_naddrs == 2) {
cc5d0189 BH	605	nvram_addr = ioremap(r1.start, s1);
cc5d0189 BH	606	nvram_data = ioremap(r2.start, s2);
14cf11af PM	607	ppc_md.nvram_read_val = indirect_nvram_read_byte;
14cf11af PM	608	ppc_md.nvram_write_val = indirect_nvram_write_byte;
ebcebc7f	609	ppc_md.nvram_size = ppc32_nvram_size;
14cf11af PM	610	} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
	611	#ifdef CONFIG_ADB_PMU
	612	nvram_naddrs = -1;
	613	ppc_md.nvram_read_val = pmu_nvram_read_byte;
	614	ppc_md.nvram_write_val = pmu_nvram_write_byte;
ebcebc7f	615	ppc_md.nvram_size = ppc32_nvram_size;
14cf11af	616	#endif /* CONFIG_ADB_PMU */
cc5d0189	617	} else {
35499c01	618	printk(KERN_ERR "Incompatible type of NVRAM\n");
cc5d0189	619	err = -ENXIO;
14cf11af	620	}
cc5d0189 BH	621	#endif /* CONFIG_PPC32 */
	622	bail:
	623	of_node_put(dp);
	624	if (err == 0)
	625	lookup_partitions();
35499c01	626	return err;
14cf11af PM	627	}
	628
	629	int pmac_get_partition(int partition)
	630	{
	631	return nvram_partitions[partition];
	632	}
	633
	634	u8 pmac_xpram_read(int xpaddr)
	635	{
35499c01	636	int offset = pmac_get_partition(pmac_nvram_XPRAM);
14cf11af	637
35499c01	638	if (offset < 0 \|\| xpaddr < 0 \|\| xpaddr > 0x100)
14cf11af PM	639	return 0xff;
	640
	641	return ppc_md.nvram_read_val(xpaddr + offset);
	642	}
	643
	644	void pmac_xpram_write(int xpaddr, u8 data)
	645	{
35499c01	646	int offset = pmac_get_partition(pmac_nvram_XPRAM);
14cf11af	647
35499c01	648	if (offset < 0 \|\| xpaddr < 0 \|\| xpaddr > 0x100)
14cf11af PM	649	return;
	650
	651	ppc_md.nvram_write_val(xpaddr + offset, data);
	652	}
	653
	654	EXPORT_SYMBOL(pmac_get_partition);
	655	EXPORT_SYMBOL(pmac_xpram_read);
	656	EXPORT_SYMBOL(pmac_xpram_write);