[mirror_ubuntu-focal-kernel.git] / arch / powerpc / platforms / powermac / pfunc_base.c

#include <linux/config.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>

#include <asm/pmac_feature.h>
#include <asm/pmac_pfunc.h>

#define DBG(fmt...)	printk(fmt)

static irqreturn_t macio_gpio_irq(int irq, void *data, struct pt_regs *regs)
{
	pmf_do_irq(data);

	return IRQ_HANDLED;
}

static int macio_do_gpio_irq_enable(struct pmf_function *func)
{
	if (func->node->n_intrs < 1)
		return -EINVAL;

	return request_irq(func->node->intrs[0].line, macio_gpio_irq, 0,
			   func->node->name, func);
}

static int macio_do_gpio_irq_disable(struct pmf_function *func)
{
	if (func->node->n_intrs < 1)
		return -EINVAL;

	free_irq(func->node->intrs[0].line, func);
	return 0;
}

static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask)
{
	u8 __iomem *addr = (u8 __iomem *)func->driver_data;
	unsigned long flags;
	u8 tmp;

	/* Check polarity */
	if (args && args->count && !args->u[0].v)
		value = ~value;

	/* Toggle the GPIO */
	spin_lock_irqsave(&feature_lock, flags);
	tmp = readb(addr);
	tmp = (tmp & ~mask) | (value & mask);
	DBG("Do write 0x%02x to GPIO %s (%p)\n",
	    tmp, func->node->full_name, addr);
	writeb(tmp, addr);
	spin_unlock_irqrestore(&feature_lock, flags);

	return 0;
}

static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor)
{
	u8 __iomem *addr = (u8 __iomem *)func->driver_data;
	u32 value;

	/* Check if we have room for reply */
	if (args == NULL || args->count == 0 || args->u[0].p == NULL)
		return -EINVAL;

	value = readb(addr);
	*args->u[0].p = ((value & mask) >> rshift) ^ xor;

	return 0;
}

static int macio_do_delay(PMF_STD_ARGS, u32 duration)
{
	/* assume we can sleep ! */
	msleep((duration + 999) / 1000);
	return 0;
}

static struct pmf_handlers macio_gpio_handlers = {
	.irq_enable	= macio_do_gpio_irq_enable,
	.irq_disable	= macio_do_gpio_irq_disable,
	.write_gpio	= macio_do_gpio_write,
	.read_gpio	= macio_do_gpio_read,
	.delay		= macio_do_delay,
};

static void macio_gpio_init_one(struct macio_chip *macio)
{
	struct device_node *gparent, *gp;

	/*
	 * Find the "gpio" parent node
	 */

	for (gparent = NULL;
	     (gparent = of_get_next_child(macio->of_node, gparent)) != NULL;)
		if (strcmp(gparent->name, "gpio") == 0)
			break;
	if (gparent == NULL)
		return;

	DBG("Installing GPIO functions for macio %s\n",
	    macio->of_node->full_name);

	/*
	 * Ok, got one, we dont need anything special to track them down, so
	 * we just create them all
	 */
	for (gp = NULL; (gp = of_get_next_child(gparent, gp)) != NULL;) {
		u32 *reg = (u32 *)get_property(gp, "reg", NULL);
		unsigned long offset;
		if (reg == NULL)
			continue;
		offset = *reg;
		/* Deal with old style device-tree. We can safely hard code the
		 * offset for now too even if it's a bit gross ...
		 */
		if (offset < 0x50)
			offset += 0x50;
		offset += (unsigned long)macio->base;
		pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset);
	}

	DBG("Calling initial GPIO functions for macio %s\n",
	    macio->of_node->full_name);

	/* And now we run all the init ones */
	for (gp = NULL; (gp = of_get_next_child(gparent, gp)) != NULL;)
		pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL);

	/* Note: We do not at this point implement the "at sleep" or "at wake"
	 * functions. I yet to find any for GPIOs anyway
	 */
}

static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
{
	struct macio_chip *macio = func->driver_data;
	unsigned long flags;

	spin_lock_irqsave(&feature_lock, flags);
	MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask));
	spin_unlock_irqrestore(&feature_lock, flags);
	return 0;
}

static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset)
{
	struct macio_chip *macio = func->driver_data;

	/* Check if we have room for reply */
	if (args == NULL || args->count == 0 || args->u[0].p == NULL)
		return -EINVAL;

	*args->u[0].p = MACIO_IN32(offset);
	return 0;
}

static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask)
{
	struct macio_chip *macio = func->driver_data;
	unsigned long flags;

	spin_lock_irqsave(&feature_lock, flags);
	MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask));
	spin_unlock_irqrestore(&feature_lock, flags);
	return 0;
}

static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset)
{
	struct macio_chip *macio = func->driver_data;

	/* Check if we have room for reply */
	if (args == NULL || args->count == 0 || args->u[0].p == NULL)
		return -EINVAL;

	*((u8 *)(args->u[0].p)) = MACIO_IN8(offset);
	return 0;
}

static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
				    u32 shift, u32 xor)
{
	struct macio_chip *macio = func->driver_data;

	/* Check if we have room for reply */
	if (args == NULL || args->count == 0 || args->u[0].p == NULL)
		return -EINVAL;

	*args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor;
	return 0;
}

static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
				   u32 shift, u32 xor)
{
	struct macio_chip *macio = func->driver_data;

	/* Check if we have room for reply */
	if (args == NULL || args->count == 0 || args->u[0].p == NULL)
		return -EINVAL;

	*((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor;
	return 0;
}

static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift,
				    u32 mask)
{
	struct macio_chip *macio = func->driver_data;
	unsigned long flags;
	u32 tmp, val;

	/* Check args */
	if (args == NULL || args->count == 0)
		return -EINVAL;

	spin_lock_irqsave(&feature_lock, flags);
	tmp = MACIO_IN32(offset);
	val = args->u[0].v << shift;
	tmp = (tmp & ~mask) | (val & mask);
	MACIO_OUT32(offset, tmp);
	spin_unlock_irqrestore(&feature_lock, flags);
	return 0;
}

static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift,
				   u32 mask)
{
	struct macio_chip *macio = func->driver_data;
	unsigned long flags;
	u32 tmp, val;

	/* Check args */
	if (args == NULL || args->count == 0)
		return -EINVAL;

	spin_lock_irqsave(&feature_lock, flags);
	tmp = MACIO_IN8(offset);
	val = args->u[0].v << shift;
	tmp = (tmp & ~mask) | (val & mask);
	MACIO_OUT8(offset, tmp);
	spin_unlock_irqrestore(&feature_lock, flags);
	return 0;
}

static struct pmf_handlers macio_mmio_handlers = {
	.write_reg32		= macio_do_write_reg32,
	.read_reg32		= macio_do_read_reg32,
	.write_reg8		= macio_do_write_reg8,
	.read_reg32		= macio_do_read_reg8,
	.read_reg32_msrx	= macio_do_read_reg32_msrx,
	.read_reg8_msrx		= macio_do_read_reg8_msrx,
	.write_reg32_slm	= macio_do_write_reg32_slm,
	.write_reg8_slm		= macio_do_write_reg8_slm,
	.delay			= macio_do_delay,
};

static void macio_mmio_init_one(struct macio_chip *macio)
{
	DBG("Installing MMIO functions for macio %s\n",
	    macio->of_node->full_name);

	pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio);
}

static struct device_node *unin_hwclock;

static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
{
	unsigned long flags;

	spin_lock_irqsave(&feature_lock, flags);
	/* This is fairly bogus in darwin, but it should work for our needs
	 * implemeted that way:
	 */
	UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask));
	spin_unlock_irqrestore(&feature_lock, flags);
	return 0;
}


static struct pmf_handlers unin_mmio_handlers = {
	.write_reg32		= unin_do_write_reg32,
	.delay			= macio_do_delay,
};

static void uninorth_install_pfunc(void)
{
	struct device_node *np;

	DBG("Installing functions for UniN %s\n",
	    uninorth_node->full_name);

	/*
	 * Install handlers for the bridge itself
	 */
	pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL);
	pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL);


	/*
	 * Install handlers for the hwclock child if any
	 */
	for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;)
		if (strcmp(np->name, "hw-clock") == 0) {
			unin_hwclock = np;
			break;
		}
	if (unin_hwclock) {
		DBG("Installing functions for UniN clock %s\n",
		    unin_hwclock->full_name);
		pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL);
		pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT,
				 NULL);
	}
}

/* We export this as the SMP code might init us early */
int __init pmac_pfunc_base_install(void)
{
	static int pfbase_inited;
	int i;

	if (pfbase_inited)
		return 0;
	pfbase_inited = 1;


	DBG("Installing base platform functions...\n");

	/*
	 * Locate mac-io chips and install handlers
	 */
	for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
		if (macio_chips[i].of_node) {
			macio_mmio_init_one(&macio_chips[i]);
			macio_gpio_init_one(&macio_chips[i]);
		}
	}

	/*
	 * Install handlers for northbridge and direct mapped hwclock
	 * if any. We do not implement the config space access callback
	 * which is only ever used for functions that we do not call in
	 * the current driver (enabling/disabling cells in U2, mostly used
	 * to restore the PCI settings, we do that differently)
	 */
	if (uninorth_node && uninorth_base)
		uninorth_install_pfunc();

	DBG("All base functions installed\n");

	return 0;
}

arch_initcall(pmac_pfunc_base_install);

#ifdef CONFIG_PM

/* Those can be called by pmac_feature. Ultimately, I should use a sysdev
 * or a device, but for now, that's good enough until I sort out some
 * ordering issues. Also, we do not bother with GPIOs, as so far I yet have
 * to see a case where a GPIO function has the on-suspend or on-resume bit
 */
void pmac_pfunc_base_suspend(void)
{
	int i;

	for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
		if (macio_chips[i].of_node)
			pmf_do_functions(macio_chips[i].of_node, NULL, 0,
					 PMF_FLAGS_ON_SLEEP, NULL);
	}
	if (uninorth_node)
		pmf_do_functions(uninorth_node, NULL, 0,
				 PMF_FLAGS_ON_SLEEP, NULL);
	if (unin_hwclock)
		pmf_do_functions(unin_hwclock, NULL, 0,
				 PMF_FLAGS_ON_SLEEP, NULL);
}

void pmac_pfunc_base_resume(void)
{
	int i;

	if (unin_hwclock)
		pmf_do_functions(unin_hwclock, NULL, 0,
				 PMF_FLAGS_ON_WAKE, NULL);
	if (uninorth_node)
		pmf_do_functions(uninorth_node, NULL, 0,
				 PMF_FLAGS_ON_WAKE, NULL);
	for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
		if (macio_chips[i].of_node)
			pmf_do_functions(macio_chips[i].of_node, NULL, 0,
					 PMF_FLAGS_ON_WAKE, NULL);
	}
}

#endif /* CONFIG_PM */
Commit	Line	Data
5b9ca526 BH	1	#include <linux/config.h>
	2	#include <linux/types.h>
	3	#include <linux/init.h>
	4	#include <linux/delay.h>
	5	#include <linux/kernel.h>
	6	#include <linux/interrupt.h>
	7	#include <linux/spinlock.h>
	8
	9	#include <asm/pmac_feature.h>
	10	#include <asm/pmac_pfunc.h>
	11
	12	#define DBG(fmt...) printk(fmt)
	13
	14	static irqreturn_t macio_gpio_irq(int irq, void data, struct pt_regs regs)
	15	{
	16	pmf_do_irq(data);
	17
	18	return IRQ_HANDLED;
	19	}
	20
	21	static int macio_do_gpio_irq_enable(struct pmf_function *func)
	22	{
	23	if (func->node->n_intrs < 1)
	24	return -EINVAL;
	25
	26	return request_irq(func->node->intrs[0].line, macio_gpio_irq, 0,
	27	func->node->name, func);
	28	}
	29
	30	static int macio_do_gpio_irq_disable(struct pmf_function *func)
	31	{
	32	if (func->node->n_intrs < 1)
	33	return -EINVAL;
	34
	35	free_irq(func->node->intrs[0].line, func);
	36	return 0;
	37	}
	38
	39	static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask)
	40	{
	41	u8 __iomem addr = (u8 __iomem )func->driver_data;
	42	unsigned long flags;
	43	u8 tmp;
	44
	45	/* Check polarity */
	46	if (args && args->count && !args->u[0].v)
	47	value = ~value;
	48
	49	/* Toggle the GPIO */
	50	spin_lock_irqsave(&feature_lock, flags);
	51	tmp = readb(addr);
	52	tmp = (tmp & ~mask) \| (value & mask);
	53	DBG("Do write 0x%02x to GPIO %s (%p)\n",
	54	tmp, func->node->full_name, addr);
	55	writeb(tmp, addr);
	56	spin_unlock_irqrestore(&feature_lock, flags);
	57
	58	return 0;
	59	}
	60
	61	static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor)
	62	{
	63	u8 __iomem addr = (u8 __iomem )func->driver_data;
	64	u32 value;
65
66	/* Check if we have room for reply */
67	if (args == NULL \|\| args->count == 0 \|\| args->u[0].p == NULL)
68	return -EINVAL;
69
70	value = readb(addr);
71	*args->u[0].p = ((value & mask) >> rshift) ^ xor;
72
73	return 0;
74	}
75
76	static int macio_do_delay(PMF_STD_ARGS, u32 duration)
77	{
78	/* assume we can sleep ! */
79	msleep((duration + 999) / 1000);
80	return 0;
81	}
82
83	static struct pmf_handlers macio_gpio_handlers = {
84	.irq_enable = macio_do_gpio_irq_enable,
85	.irq_disable = macio_do_gpio_irq_disable,
86	.write_gpio = macio_do_gpio_write,
87	.read_gpio = macio_do_gpio_read,
88	.delay = macio_do_delay,
89	};
90
91	static void macio_gpio_init_one(struct macio_chip *macio)
92	{
93	struct device_node gparent, gp;
94
95	/*
96	* Find the "gpio" parent node
97	*/
98
99	for (gparent = NULL;
100	(gparent = of_get_next_child(macio->of_node, gparent)) != NULL;)
101	if (strcmp(gparent->name, "gpio") == 0)
102	break;
103	if (gparent == NULL)
104	return;
105
106	DBG("Installing GPIO functions for macio %s\n",
107	macio->of_node->full_name);
108
109	/*
110	* Ok, got one, we dont need anything special to track them down, so
111	* we just create them all
112	*/
113	for (gp = NULL; (gp = of_get_next_child(gparent, gp)) != NULL;) {
114	u32 reg = (u32 )get_property(gp, "reg", NULL);
115	unsigned long offset;
116	if (reg == NULL)
117	continue;
118	offset = *reg;
119	/* Deal with old style device-tree. We can safely hard code the
120	* offset for now too even if it's a bit gross ...
121	*/
122	if (offset < 0x50)
123	offset += 0x50;
124	offset += (unsigned long)macio->base;
125	pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset);
126	}
127
128	DBG("Calling initial GPIO functions for macio %s\n",
129	macio->of_node->full_name);
130
131	/* And now we run all the init ones */
132	for (gp = NULL; (gp = of_get_next_child(gparent, gp)) != NULL;)
133	pmf_do_functions(gp, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
134
135	/* Note: We do not at this point implement the "at sleep" or "at wake"
136	* functions. I yet to find any for GPIOs anyway
137	*/
138	}
139
140	static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
141	{
142	struct macio_chip *macio = func->driver_data;
143	unsigned long flags;
144
145	spin_lock_irqsave(&feature_lock, flags);
146	MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) \| (value & mask));
147	spin_unlock_irqrestore(&feature_lock, flags);
148	return 0;
149	}
150
151	static int macio_do_read_reg32(PMF_STD_ARGS, u32 offset)
152	{
153	struct macio_chip *macio = func->driver_data;
154
155	/* Check if we have room for reply */
156	if (args == NULL \|\| args->count == 0 \|\| args->u[0].p == NULL)
157	return -EINVAL;
158
159	*args->u[0].p = MACIO_IN32(offset);
160	return 0;
161	}
162
163	static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask)
164	{
165	struct macio_chip *macio = func->driver_data;
166	unsigned long flags;
167
168	spin_lock_irqsave(&feature_lock, flags);
169	MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) \| (value & mask));
170	spin_unlock_irqrestore(&feature_lock, flags);
171	return 0;
172	}
173
174	static int macio_do_read_reg8(PMF_STD_ARGS, u32 offset)
175	{
176	struct macio_chip *macio = func->driver_data;
177
178	/* Check if we have room for reply */
179	if (args == NULL \|\| args->count == 0 \|\| args->u[0].p == NULL)
180	return -EINVAL;
181
182	((u8 )(args->u[0].p)) = MACIO_IN8(offset);
183	return 0;
184	}
185
186	static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
187	u32 shift, u32 xor)
188	{
189	struct macio_chip *macio = func->driver_data;
190
191	/* Check if we have room for reply */
192	if (args == NULL \|\| args->count == 0 \|\| args->u[0].p == NULL)
193	return -EINVAL;
194
195	*args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor;
196	return 0;
197	}
198
199	static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask,
200	u32 shift, u32 xor)
201	{
202	struct macio_chip *macio = func->driver_data;
203
204	/* Check if we have room for reply */
205	if (args == NULL \|\| args->count == 0 \|\| args->u[0].p == NULL)
206	return -EINVAL;
207
208	((u8 )(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor;
209	return 0;
210	}
211
212	static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift,
213	u32 mask)
214	{
215	struct macio_chip *macio = func->driver_data;
216	unsigned long flags;
217	u32 tmp, val;
218
219	/* Check args */
220	if (args == NULL \|\| args->count == 0)
221	return -EINVAL;
222
223	spin_lock_irqsave(&feature_lock, flags);
224	tmp = MACIO_IN32(offset);
225	val = args->u[0].v << shift;
226	tmp = (tmp & ~mask) \| (val & mask);
227	MACIO_OUT32(offset, tmp);
228	spin_unlock_irqrestore(&feature_lock, flags);
229	return 0;
230	}
231
232	static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift,
233	u32 mask)
234	{
235	struct macio_chip *macio = func->driver_data;
236	unsigned long flags;
237	u32 tmp, val;
238
239	/* Check args */
240	if (args == NULL \|\| args->count == 0)
241	return -EINVAL;
242
243	spin_lock_irqsave(&feature_lock, flags);
244	tmp = MACIO_IN8(offset);
245	val = args->u[0].v << shift;
246	tmp = (tmp & ~mask) \| (val & mask);
247	MACIO_OUT8(offset, tmp);
248	spin_unlock_irqrestore(&feature_lock, flags);
249	return 0;
250	}
251
252	static struct pmf_handlers macio_mmio_handlers = {
253	.write_reg32 = macio_do_write_reg32,
254	.read_reg32 = macio_do_read_reg32,
255	.write_reg8 = macio_do_write_reg8,
256	.read_reg32 = macio_do_read_reg8,
257	.read_reg32_msrx = macio_do_read_reg32_msrx,
258	.read_reg8_msrx = macio_do_read_reg8_msrx,
259	.write_reg32_slm = macio_do_write_reg32_slm,
260	.write_reg8_slm = macio_do_write_reg8_slm,
261	.delay = macio_do_delay,
262	};
263
264	static void macio_mmio_init_one(struct macio_chip *macio)
265	{
266	DBG("Installing MMIO functions for macio %s\n",
267	macio->of_node->full_name);
268
269	pmf_register_driver(macio->of_node, &macio_mmio_handlers, macio);
270	}
271
272	static struct device_node *unin_hwclock;
273
274	static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
275	{
276	unsigned long flags;
277
278	spin_lock_irqsave(&feature_lock, flags);
279	/* This is fairly bogus in darwin, but it should work for our needs
280	* implemeted that way:
281	*/
282	UN_OUT(offset, (UN_IN(offset) & ~mask) \| (value & mask));
283	spin_unlock_irqrestore(&feature_lock, flags);
284	return 0;
285	}
286
287
288	static struct pmf_handlers unin_mmio_handlers = {
289	.write_reg32 = unin_do_write_reg32,
290	.delay = macio_do_delay,
291	};
292
293	static void uninorth_install_pfunc(void)
294	{
295	struct device_node *np;
296
297	DBG("Installing functions for UniN %s\n",
298	uninorth_node->full_name);
299
300	/*
301	* Install handlers for the bridge itself
302	*/
303	pmf_register_driver(uninorth_node, &unin_mmio_handlers, NULL);
304	pmf_do_functions(uninorth_node, NULL, 0, PMF_FLAGS_ON_INIT, NULL);
305
306
307	/*
308	* Install handlers for the hwclock child if any
309	*/
310	for (np = NULL; (np = of_get_next_child(uninorth_node, np)) != NULL;)
311	if (strcmp(np->name, "hw-clock") == 0) {
312	unin_hwclock = np;
313	break;
314	}
315	if (unin_hwclock) {
316	DBG("Installing functions for UniN clock %s\n",
317	unin_hwclock->full_name);
318	pmf_register_driver(unin_hwclock, &unin_mmio_handlers, NULL);
319	pmf_do_functions(unin_hwclock, NULL, 0, PMF_FLAGS_ON_INIT,
320	NULL);
321	}
322	}
323
324	/* We export this as the SMP code might init us early */
325	int __init pmac_pfunc_base_install(void)
326	{
327	static int pfbase_inited;
328	int i;
329
330	if (pfbase_inited)
331	return 0;
332	pfbase_inited = 1;
333
334
335	DBG("Installing base platform functions...\n");
336
337	/*
338	* Locate mac-io chips and install handlers
339	*/
340	for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
341	if (macio_chips[i].of_node) {
342	macio_mmio_init_one(&macio_chips[i]);
343	macio_gpio_init_one(&macio_chips[i]);
344	}
345	}
346
347	/*
348	* Install handlers for northbridge and direct mapped hwclock
349	* if any. We do not implement the config space access callback
350	* which is only ever used for functions that we do not call in
351	* the current driver (enabling/disabling cells in U2, mostly used
352	* to restore the PCI settings, we do that differently)
353	*/
354	if (uninorth_node && uninorth_base)
355	uninorth_install_pfunc();
356
357	DBG("All base functions installed\n");
358
359	return 0;
360	}
361
362	arch_initcall(pmac_pfunc_base_install);
363
364	#ifdef CONFIG_PM
365
366	/* Those can be called by pmac_feature. Ultimately, I should use a sysdev
367	* or a device, but for now, that's good enough until I sort out some
368	* ordering issues. Also, we do not bother with GPIOs, as so far I yet have
369	* to see a case where a GPIO function has the on-suspend or on-resume bit
370	*/
371	void pmac_pfunc_base_suspend(void)
372	{
373	int i;
374
375	for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
376	if (macio_chips[i].of_node)
377	pmf_do_functions(macio_chips[i].of_node, NULL, 0,
378	PMF_FLAGS_ON_SLEEP, NULL);
379	}
380	if (uninorth_node)
381	pmf_do_functions(uninorth_node, NULL, 0,
382	PMF_FLAGS_ON_SLEEP, NULL);
383	if (unin_hwclock)
384	pmf_do_functions(unin_hwclock, NULL, 0,
385	PMF_FLAGS_ON_SLEEP, NULL);
386	}
387
388	void pmac_pfunc_base_resume(void)
389	{
390	int i;
391
392	if (unin_hwclock)
393	pmf_do_functions(unin_hwclock, NULL, 0,
394	PMF_FLAGS_ON_WAKE, NULL);
395	if (uninorth_node)
396	pmf_do_functions(uninorth_node, NULL, 0,
397	PMF_FLAGS_ON_WAKE, NULL);
398	for (i = 0 ; i < MAX_MACIO_CHIPS; i++) {
399	if (macio_chips[i].of_node)
400	pmf_do_functions(macio_chips[i].of_node, NULL, 0,
401	PMF_FLAGS_ON_WAKE, NULL);
402	}
403	}
404
405	#endif /* CONFIG_PM */