]>
Commit | Line | Data |
---|---|---|
14cf11af PM |
1 | /* |
2 | * Support for the interrupt controllers found on Power Macintosh, | |
3 | * currently Apple's "Grand Central" interrupt controller in all | |
4 | * it's incarnations. OpenPIC support used on newer machines is | |
5 | * in a separate file | |
6 | * | |
7 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) | |
cc5d0189 BH |
8 | * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
9 | * IBM, Corp. | |
14cf11af PM |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/stddef.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/signal.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sysdev.h> | |
25 | #include <linux/adb.h> | |
26 | #include <linux/pmu.h> | |
3c3f42d6 | 27 | #include <linux/module.h> |
14cf11af PM |
28 | |
29 | #include <asm/sections.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/pci-bridge.h> | |
34 | #include <asm/time.h> | |
14cf11af PM |
35 | #include <asm/pmac_feature.h> |
36 | #include <asm/mpic.h> | |
37 | ||
3c3f42d6 | 38 | #include "pmac.h" |
14cf11af PM |
39 | |
40 | /* | |
41 | * XXX this should be in xmon.h, but putting it there means xmon.h | |
42 | * has to include <linux/interrupt.h> (to get irqreturn_t), which | |
43 | * causes all sorts of problems. -- paulus | |
44 | */ | |
45 | extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); | |
46 | ||
3c3f42d6 | 47 | #ifdef CONFIG_PPC32 |
14cf11af PM |
48 | struct pmac_irq_hw { |
49 | unsigned int event; | |
50 | unsigned int enable; | |
51 | unsigned int ack; | |
52 | unsigned int level; | |
53 | }; | |
54 | ||
55 | /* Default addresses */ | |
cc5d0189 | 56 | static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; |
14cf11af PM |
57 | |
58 | #define GC_LEVEL_MASK 0x3ff00000 | |
59 | #define OHARE_LEVEL_MASK 0x1ff00000 | |
60 | #define HEATHROW_LEVEL_MASK 0x1ff00000 | |
61 | ||
62 | static int max_irqs; | |
63 | static int max_real_irqs; | |
64 | static u32 level_mask[4]; | |
65 | ||
66 | static DEFINE_SPINLOCK(pmac_pic_lock); | |
67 | ||
756e7104 SR |
68 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) |
69 | static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; | |
b9e5b4e6 BH |
70 | static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; |
71 | static int pmac_irq_cascade = -1; | |
0ebfff14 | 72 | static struct irq_host *pmac_pic_host; |
756e7104 | 73 | |
b9e5b4e6 | 74 | static void __pmac_retrigger(unsigned int irq_nr) |
14cf11af | 75 | { |
b9e5b4e6 BH |
76 | if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { |
77 | __set_bit(irq_nr, ppc_lost_interrupts); | |
78 | irq_nr = pmac_irq_cascade; | |
79 | mb(); | |
80 | } | |
81 | if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { | |
14cf11af | 82 | atomic_inc(&ppc_n_lost_interrupts); |
b9e5b4e6 | 83 | set_dec(1); |
14cf11af PM |
84 | } |
85 | } | |
86 | ||
0ebfff14 | 87 | static void pmac_mask_and_ack_irq(unsigned int virq) |
14cf11af | 88 | { |
0ebfff14 BH |
89 | unsigned int src = irq_map[virq].hwirq; |
90 | unsigned long bit = 1UL << (virq & 0x1f); | |
91 | int i = virq >> 5; | |
14cf11af PM |
92 | unsigned long flags; |
93 | ||
14cf11af | 94 | spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
95 | __clear_bit(src, ppc_cached_irq_mask); |
96 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) | |
b9e5b4e6 | 97 | atomic_dec(&ppc_n_lost_interrupts); |
14cf11af PM |
98 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); |
99 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
100 | do { | |
101 | /* make sure ack gets to controller before we enable | |
102 | interrupts */ | |
103 | mb(); | |
104 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
105 | != (ppc_cached_irq_mask[i] & bit)); | |
106 | spin_unlock_irqrestore(&pmac_pic_lock, flags); | |
107 | } | |
108 | ||
0ebfff14 | 109 | static void pmac_ack_irq(unsigned int virq) |
14cf11af | 110 | { |
0ebfff14 BH |
111 | unsigned int src = irq_map[virq].hwirq; |
112 | unsigned long bit = 1UL << (src & 0x1f); | |
113 | int i = src >> 5; | |
14cf11af PM |
114 | unsigned long flags; |
115 | ||
b9e5b4e6 | 116 | spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 117 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) |
b9e5b4e6 BH |
118 | atomic_dec(&ppc_n_lost_interrupts); |
119 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
120 | (void)in_le32(&pmac_irq_hw[i]->ack); | |
121 | spin_unlock_irqrestore(&pmac_pic_lock, flags); | |
122 | } | |
123 | ||
124 | static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |
125 | { | |
126 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
127 | int i = irq_nr >> 5; | |
128 | ||
129 | if ((unsigned)irq_nr >= max_irqs) | |
130 | return; | |
131 | ||
14cf11af PM |
132 | /* enable unmasked interrupts */ |
133 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
134 | ||
135 | do { | |
136 | /* make sure mask gets to controller before we | |
137 | return to user */ | |
138 | mb(); | |
139 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
140 | != (ppc_cached_irq_mask[i] & bit)); | |
141 | ||
142 | /* | |
143 | * Unfortunately, setting the bit in the enable register | |
144 | * when the device interrupt is already on *doesn't* set | |
145 | * the bit in the flag register or request another interrupt. | |
146 | */ | |
147 | if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) | |
b9e5b4e6 | 148 | __pmac_retrigger(irq_nr); |
14cf11af PM |
149 | } |
150 | ||
151 | /* When an irq gets requested for the first client, if it's an | |
152 | * edge interrupt, we clear any previous one on the controller | |
153 | */ | |
0ebfff14 | 154 | static unsigned int pmac_startup_irq(unsigned int virq) |
14cf11af | 155 | { |
b9e5b4e6 | 156 | unsigned long flags; |
0ebfff14 BH |
157 | unsigned int src = irq_map[virq].hwirq; |
158 | unsigned long bit = 1UL << (src & 0x1f); | |
159 | int i = src >> 5; | |
14cf11af | 160 | |
b9e5b4e6 | 161 | spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 162 | if ((irq_desc[virq].status & IRQ_LEVEL) == 0) |
14cf11af | 163 | out_le32(&pmac_irq_hw[i]->ack, bit); |
0ebfff14 BH |
164 | __set_bit(src, ppc_cached_irq_mask); |
165 | __pmac_set_irq_mask(src, 0); | |
b9e5b4e6 | 166 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
167 | |
168 | return 0; | |
169 | } | |
170 | ||
0ebfff14 | 171 | static void pmac_mask_irq(unsigned int virq) |
14cf11af | 172 | { |
b9e5b4e6 | 173 | unsigned long flags; |
0ebfff14 | 174 | unsigned int src = irq_map[virq].hwirq; |
b9e5b4e6 BH |
175 | |
176 | spin_lock_irqsave(&pmac_pic_lock, flags); | |
0ebfff14 BH |
177 | __clear_bit(src, ppc_cached_irq_mask); |
178 | __pmac_set_irq_mask(src, 0); | |
b9e5b4e6 | 179 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
180 | } |
181 | ||
0ebfff14 | 182 | static void pmac_unmask_irq(unsigned int virq) |
14cf11af | 183 | { |
b9e5b4e6 | 184 | unsigned long flags; |
0ebfff14 | 185 | unsigned int src = irq_map[virq].hwirq; |
b9e5b4e6 BH |
186 | |
187 | spin_lock_irqsave(&pmac_pic_lock, flags); | |
0ebfff14 BH |
188 | __set_bit(src, ppc_cached_irq_mask); |
189 | __pmac_set_irq_mask(src, 0); | |
b9e5b4e6 | 190 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
191 | } |
192 | ||
0ebfff14 | 193 | static int pmac_retrigger(unsigned int virq) |
14cf11af | 194 | { |
b9e5b4e6 | 195 | unsigned long flags; |
14cf11af | 196 | |
b9e5b4e6 | 197 | spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 198 | __pmac_retrigger(irq_map[virq].hwirq); |
b9e5b4e6 BH |
199 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
200 | return 1; | |
201 | } | |
14cf11af | 202 | |
b9e5b4e6 | 203 | static struct irq_chip pmac_pic = { |
14cf11af PM |
204 | .typename = " PMAC-PIC ", |
205 | .startup = pmac_startup_irq, | |
b9e5b4e6 BH |
206 | .mask = pmac_mask_irq, |
207 | .ack = pmac_ack_irq, | |
208 | .mask_ack = pmac_mask_and_ack_irq, | |
209 | .unmask = pmac_unmask_irq, | |
210 | .retrigger = pmac_retrigger, | |
14cf11af PM |
211 | }; |
212 | ||
213 | static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs) | |
214 | { | |
b9e5b4e6 | 215 | unsigned long flags; |
14cf11af | 216 | int irq, bits; |
b9e5b4e6 | 217 | int rc = IRQ_NONE; |
14cf11af | 218 | |
b9e5b4e6 | 219 | spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
220 | for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { |
221 | int i = irq >> 5; | |
222 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
223 | /* We must read level interrupts from the level register */ | |
224 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
225 | bits &= ppc_cached_irq_mask[i]; | |
226 | if (bits == 0) | |
227 | continue; | |
228 | irq += __ilog2(bits); | |
b9e5b4e6 | 229 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af | 230 | __do_IRQ(irq, regs); |
b9e5b4e6 BH |
231 | spin_lock_irqsave(&pmac_pic_lock, flags); |
232 | rc = IRQ_HANDLED; | |
14cf11af | 233 | } |
b9e5b4e6 BH |
234 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
235 | return rc; | |
14cf11af PM |
236 | } |
237 | ||
0ebfff14 | 238 | static unsigned int pmac_pic_get_irq(struct pt_regs *regs) |
14cf11af PM |
239 | { |
240 | int irq; | |
241 | unsigned long bits = 0; | |
b9e5b4e6 | 242 | unsigned long flags; |
14cf11af PM |
243 | |
244 | #ifdef CONFIG_SMP | |
245 | void psurge_smp_message_recv(struct pt_regs *); | |
246 | ||
247 | /* IPI's are a hack on the powersurge -- Cort */ | |
248 | if ( smp_processor_id() != 0 ) { | |
249 | psurge_smp_message_recv(regs); | |
0ebfff14 | 250 | return NO_IRQ_IGNORE; /* ignore, already handled */ |
14cf11af PM |
251 | } |
252 | #endif /* CONFIG_SMP */ | |
b9e5b4e6 | 253 | spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
254 | for (irq = max_real_irqs; (irq -= 32) >= 0; ) { |
255 | int i = irq >> 5; | |
256 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
257 | /* We must read level interrupts from the level register */ | |
258 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
259 | bits &= ppc_cached_irq_mask[i]; | |
260 | if (bits == 0) | |
261 | continue; | |
262 | irq += __ilog2(bits); | |
263 | break; | |
264 | } | |
b9e5b4e6 | 265 | spin_unlock_irqrestore(&pmac_pic_lock, flags); |
0ebfff14 BH |
266 | if (unlikely(irq < 0)) |
267 | return NO_IRQ; | |
268 | return irq_linear_revmap(pmac_pic_host, irq); | |
14cf11af PM |
269 | } |
270 | ||
14cf11af PM |
271 | #ifdef CONFIG_XMON |
272 | static struct irqaction xmon_action = { | |
273 | .handler = xmon_irq, | |
274 | .flags = 0, | |
275 | .mask = CPU_MASK_NONE, | |
276 | .name = "NMI - XMON" | |
277 | }; | |
278 | #endif | |
279 | ||
280 | static struct irqaction gatwick_cascade_action = { | |
281 | .handler = gatwick_action, | |
6714465e | 282 | .flags = IRQF_DISABLED, |
14cf11af PM |
283 | .mask = CPU_MASK_NONE, |
284 | .name = "cascade", | |
285 | }; | |
3c3f42d6 | 286 | |
0ebfff14 BH |
287 | static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) |
288 | { | |
289 | /* We match all, we don't always have a node anyway */ | |
290 | return 1; | |
291 | } | |
292 | ||
293 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | |
294 | irq_hw_number_t hw, unsigned int flags) | |
295 | { | |
296 | struct irq_desc *desc = get_irq_desc(virq); | |
297 | int level; | |
298 | ||
299 | if (hw >= max_irqs) | |
300 | return -EINVAL; | |
301 | ||
302 | /* Mark level interrupts, set delayed disable for edge ones and set | |
303 | * handlers | |
304 | */ | |
305 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); | |
306 | if (level) | |
307 | desc->status |= IRQ_LEVEL; | |
308 | else | |
309 | desc->status |= IRQ_DELAYED_DISABLE; | |
310 | set_irq_chip_and_handler(virq, &pmac_pic, level ? | |
311 | handle_level_irq : handle_edge_irq); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct, | |
316 | u32 *intspec, unsigned int intsize, | |
317 | irq_hw_number_t *out_hwirq, | |
318 | unsigned int *out_flags) | |
319 | ||
320 | { | |
321 | *out_hwirq = *intspec; | |
322 | return 0; | |
323 | } | |
324 | ||
325 | static struct irq_host_ops pmac_pic_host_ops = { | |
326 | .match = pmac_pic_host_match, | |
327 | .map = pmac_pic_host_map, | |
328 | .xlate = pmac_pic_host_xlate, | |
329 | }; | |
330 | ||
cc5d0189 | 331 | static void __init pmac_pic_probe_oldstyle(void) |
3c3f42d6 | 332 | { |
3c3f42d6 | 333 | int i; |
cc5d0189 BH |
334 | struct device_node *master = NULL; |
335 | struct device_node *slave = NULL; | |
336 | u8 __iomem *addr; | |
337 | struct resource r; | |
14cf11af | 338 | |
cc5d0189 | 339 | /* Set our get_irq function */ |
0ebfff14 | 340 | ppc_md.get_irq = pmac_pic_get_irq; |
14cf11af | 341 | |
cc5d0189 BH |
342 | /* |
343 | * Find the interrupt controller type & node | |
14cf11af | 344 | */ |
cc5d0189 BH |
345 | |
346 | if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { | |
347 | max_irqs = max_real_irqs = 32; | |
14cf11af | 348 | level_mask[0] = GC_LEVEL_MASK; |
cc5d0189 BH |
349 | } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { |
350 | max_irqs = max_real_irqs = 32; | |
14cf11af | 351 | level_mask[0] = OHARE_LEVEL_MASK; |
cc5d0189 | 352 | |
14cf11af | 353 | /* We might have a second cascaded ohare */ |
cc5d0189 BH |
354 | slave = of_find_node_by_name(NULL, "pci106b,7"); |
355 | if (slave) { | |
356 | max_irqs = 64; | |
357 | level_mask[1] = OHARE_LEVEL_MASK; | |
cc5d0189 BH |
358 | } |
359 | } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { | |
360 | max_irqs = max_real_irqs = 64; | |
14cf11af PM |
361 | level_mask[0] = HEATHROW_LEVEL_MASK; |
362 | level_mask[1] = 0; | |
cc5d0189 | 363 | |
14cf11af | 364 | /* We might have a second cascaded heathrow */ |
cc5d0189 BH |
365 | slave = of_find_node_by_name(master, "mac-io"); |
366 | ||
367 | /* Check ordering of master & slave */ | |
368 | if (device_is_compatible(master, "gatwick")) { | |
369 | struct device_node *tmp; | |
370 | BUG_ON(slave == NULL); | |
371 | tmp = master; | |
372 | master = slave; | |
373 | slave = tmp; | |
374 | } | |
14cf11af | 375 | |
cc5d0189 BH |
376 | /* We found a slave */ |
377 | if (slave) { | |
14cf11af | 378 | max_irqs = 128; |
cc5d0189 BH |
379 | level_mask[2] = HEATHROW_LEVEL_MASK; |
380 | level_mask[3] = 0; | |
cc5d0189 | 381 | } |
14cf11af | 382 | } |
cc5d0189 BH |
383 | BUG_ON(master == NULL); |
384 | ||
0ebfff14 BH |
385 | /* |
386 | * Allocate an irq host | |
387 | */ | |
388 | pmac_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, max_irqs, | |
389 | &pmac_pic_host_ops, | |
390 | max_irqs); | |
391 | BUG_ON(pmac_pic_host == NULL); | |
392 | irq_set_default_host(pmac_pic_host); | |
14cf11af | 393 | |
cc5d0189 BH |
394 | /* Get addresses of first controller if we have a node for it */ |
395 | BUG_ON(of_address_to_resource(master, 0, &r)); | |
396 | ||
397 | /* Map interrupts of primary controller */ | |
398 | addr = (u8 __iomem *) ioremap(r.start, 0x40); | |
399 | i = 0; | |
400 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
401 | (addr + 0x20); | |
402 | if (max_real_irqs > 32) | |
403 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
404 | (addr + 0x10); | |
405 | of_node_put(master); | |
406 | ||
407 | printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", | |
408 | master->full_name, max_real_irqs); | |
409 | ||
410 | /* Map interrupts of cascaded controller */ | |
411 | if (slave && !of_address_to_resource(slave, 0, &r)) { | |
412 | addr = (u8 __iomem *)ioremap(r.start, 0x40); | |
413 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
414 | (addr + 0x20); | |
415 | if (max_irqs > 64) | |
416 | pmac_irq_hw[i++] = | |
417 | (volatile struct pmac_irq_hw __iomem *) | |
418 | (addr + 0x10); | |
0ebfff14 | 419 | pmac_irq_cascade = irq_of_parse_and_map(slave, 0); |
cc5d0189 BH |
420 | |
421 | printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" | |
422 | " cascade: %d\n", slave->full_name, | |
b9e5b4e6 | 423 | max_irqs - max_real_irqs, pmac_irq_cascade); |
14cf11af | 424 | } |
cc5d0189 | 425 | of_node_put(slave); |
14cf11af | 426 | |
b9e5b4e6 | 427 | /* Disable all interrupts in all controllers */ |
14cf11af PM |
428 | for (i = 0; i * 32 < max_irqs; ++i) |
429 | out_le32(&pmac_irq_hw[i]->enable, 0); | |
cc5d0189 | 430 | |
b9e5b4e6 | 431 | /* Hookup cascade irq */ |
0ebfff14 | 432 | if (slave && pmac_irq_cascade != NO_IRQ) |
b9e5b4e6 | 433 | setup_irq(pmac_irq_cascade, &gatwick_cascade_action); |
14cf11af | 434 | |
cc5d0189 | 435 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
14cf11af | 436 | #ifdef CONFIG_XMON |
0ebfff14 | 437 | setup_irq(irq_create_mapping(NULL, 20, 0), &xmon_action); |
cc5d0189 BH |
438 | #endif |
439 | } | |
440 | #endif /* CONFIG_PPC32 */ | |
441 | ||
b9e5b4e6 BH |
442 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc, |
443 | struct pt_regs *regs) | |
cc5d0189 | 444 | { |
b9e5b4e6 | 445 | struct mpic *mpic = desc->handler_data; |
b9e5b4e6 | 446 | |
0ebfff14 BH |
447 | unsigned int cascade_irq = mpic_get_one_irq(mpic, regs); |
448 | if (cascade_irq != NO_IRQ) | |
b9e5b4e6 | 449 | generic_handle_irq(cascade_irq, regs); |
0ebfff14 | 450 | desc->chip->eoi(irq); |
cc5d0189 BH |
451 | } |
452 | ||
453 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) | |
454 | { | |
455 | #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) | |
456 | struct device_node* pswitch; | |
457 | int nmi_irq; | |
458 | ||
459 | pswitch = of_find_node_by_name(NULL, "programmer-switch"); | |
0ebfff14 BH |
460 | if (pswitch) { |
461 | nmi_irq = irq_of_parse_and_map(pswitch, 0); | |
462 | if (nmi_irq != NO_IRQ) { | |
463 | mpic_irq_set_priority(nmi_irq, 9); | |
464 | setup_irq(nmi_irq, &xmon_action); | |
465 | } | |
466 | of_node_put(pswitch); | |
cc5d0189 | 467 | } |
cc5d0189 BH |
468 | #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ |
469 | } | |
470 | ||
1beb6a7d BH |
471 | static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, |
472 | int master) | |
473 | { | |
1beb6a7d BH |
474 | const char *name = master ? " MPIC 1 " : " MPIC 2 "; |
475 | struct resource r; | |
476 | struct mpic *mpic; | |
477 | unsigned int flags = master ? MPIC_PRIMARY : 0; | |
478 | int rc; | |
479 | ||
480 | rc = of_address_to_resource(np, 0, &r); | |
481 | if (rc) | |
482 | return NULL; | |
483 | ||
484 | pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); | |
485 | ||
1beb6a7d BH |
486 | flags |= MPIC_WANTS_RESET; |
487 | if (get_property(np, "big-endian", NULL)) | |
488 | flags |= MPIC_BIG_ENDIAN; | |
489 | ||
490 | /* Primary Big Endian means HT interrupts. This is quite dodgy | |
491 | * but works until I find a better way | |
492 | */ | |
493 | if (master && (flags & MPIC_BIG_ENDIAN)) | |
494 | flags |= MPIC_BROKEN_U3; | |
495 | ||
0ebfff14 | 496 | mpic = mpic_alloc(np, r.start, flags, 0, 0, name); |
1beb6a7d BH |
497 | if (mpic == NULL) |
498 | return NULL; | |
499 | ||
500 | mpic_init(mpic); | |
501 | ||
502 | return mpic; | |
503 | } | |
504 | ||
cc5d0189 BH |
505 | static int __init pmac_pic_probe_mpic(void) |
506 | { | |
507 | struct mpic *mpic1, *mpic2; | |
508 | struct device_node *np, *master = NULL, *slave = NULL; | |
0ebfff14 | 509 | unsigned int cascade; |
cc5d0189 BH |
510 | |
511 | /* We can have up to 2 MPICs cascaded */ | |
512 | for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) | |
513 | != NULL;) { | |
514 | if (master == NULL && | |
1beb6a7d | 515 | get_property(np, "interrupts", NULL) == NULL) |
cc5d0189 BH |
516 | master = of_node_get(np); |
517 | else if (slave == NULL) | |
518 | slave = of_node_get(np); | |
519 | if (master && slave) | |
520 | break; | |
521 | } | |
522 | ||
523 | /* Check for bogus setups */ | |
524 | if (master == NULL && slave != NULL) { | |
525 | master = slave; | |
526 | slave = NULL; | |
527 | } | |
528 | ||
529 | /* Not found, default to good old pmac pic */ | |
530 | if (master == NULL) | |
531 | return -ENODEV; | |
532 | ||
533 | /* Set master handler */ | |
534 | ppc_md.get_irq = mpic_get_irq; | |
535 | ||
536 | /* Setup master */ | |
1beb6a7d | 537 | mpic1 = pmac_setup_one_mpic(master, 1); |
cc5d0189 | 538 | BUG_ON(mpic1 == NULL); |
cc5d0189 BH |
539 | |
540 | /* Install NMI if any */ | |
541 | pmac_pic_setup_mpic_nmi(mpic1); | |
542 | ||
543 | of_node_put(master); | |
544 | ||
545 | /* No slave, let's go out */ | |
0ebfff14 BH |
546 | if (slave == NULL) |
547 | return 0; | |
548 | ||
549 | /* Get/Map slave interrupt */ | |
550 | cascade = irq_of_parse_and_map(slave, 0); | |
551 | if (cascade == NO_IRQ) { | |
552 | printk(KERN_ERR "Failed to map cascade IRQ\n"); | |
cc5d0189 | 553 | return 0; |
0ebfff14 | 554 | } |
cc5d0189 | 555 | |
1beb6a7d | 556 | mpic2 = pmac_setup_one_mpic(slave, 0); |
cc5d0189 | 557 | if (mpic2 == NULL) { |
1beb6a7d BH |
558 | printk(KERN_ERR "Failed to setup slave MPIC\n"); |
559 | of_node_put(slave); | |
cc5d0189 BH |
560 | return 0; |
561 | } | |
0ebfff14 BH |
562 | set_irq_data(cascade, mpic2); |
563 | set_irq_chained_handler(cascade, pmac_u3_cascade); | |
cc5d0189 BH |
564 | |
565 | of_node_put(slave); | |
566 | return 0; | |
567 | } | |
568 | ||
569 | ||
570 | void __init pmac_pic_init(void) | |
571 | { | |
0ebfff14 BH |
572 | unsigned int flags = 0; |
573 | ||
574 | /* We configure the OF parsing based on our oldworld vs. newworld | |
575 | * platform type and wether we were booted by BootX. | |
576 | */ | |
577 | #ifdef CONFIG_PPC32 | |
578 | if (!pmac_newworld) | |
579 | flags |= OF_IMAP_OLDWORLD_MAC; | |
580 | if (get_property(of_chosen, "linux,bootx", NULL) != NULL) | |
581 | flags |= OF_IMAP_NO_PHANDLE; | |
582 | of_irq_map_init(flags); | |
583 | #endif /* CONFIG_PPC_32 */ | |
584 | ||
cc5d0189 BH |
585 | /* We first try to detect Apple's new Core99 chipset, since mac-io |
586 | * is quite different on those machines and contains an IBM MPIC2. | |
587 | */ | |
588 | if (pmac_pic_probe_mpic() == 0) | |
589 | return; | |
590 | ||
591 | #ifdef CONFIG_PPC32 | |
592 | pmac_pic_probe_oldstyle(); | |
593 | #endif | |
14cf11af PM |
594 | } |
595 | ||
a0005034 | 596 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
597 | /* |
598 | * These procedures are used in implementing sleep on the powerbooks. | |
599 | * sleep_save_intrs() saves the states of all interrupt enables | |
600 | * and disables all interrupts except for the nominated one. | |
601 | * sleep_restore_intrs() restores the states of all interrupt enables. | |
602 | */ | |
603 | unsigned long sleep_save_mask[2]; | |
604 | ||
605 | /* This used to be passed by the PMU driver but that link got | |
606 | * broken with the new driver model. We use this tweak for now... | |
0ebfff14 | 607 | * We really want to do things differently though... |
14cf11af PM |
608 | */ |
609 | static int pmacpic_find_viaint(void) | |
610 | { | |
611 | int viaint = -1; | |
612 | ||
613 | #ifdef CONFIG_ADB_PMU | |
614 | struct device_node *np; | |
615 | ||
616 | if (pmu_get_model() != PMU_OHARE_BASED) | |
617 | goto not_found; | |
618 | np = of_find_node_by_name(NULL, "via-pmu"); | |
619 | if (np == NULL) | |
620 | goto not_found; | |
0ebfff14 | 621 | viaint = irq_of_parse_and_map(np, 0);; |
14cf11af PM |
622 | #endif /* CONFIG_ADB_PMU */ |
623 | ||
624 | not_found: | |
625 | return viaint; | |
626 | } | |
627 | ||
628 | static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) | |
629 | { | |
630 | int viaint = pmacpic_find_viaint(); | |
631 | ||
632 | sleep_save_mask[0] = ppc_cached_irq_mask[0]; | |
633 | sleep_save_mask[1] = ppc_cached_irq_mask[1]; | |
634 | ppc_cached_irq_mask[0] = 0; | |
635 | ppc_cached_irq_mask[1] = 0; | |
636 | if (viaint > 0) | |
637 | set_bit(viaint, ppc_cached_irq_mask); | |
638 | out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); | |
639 | if (max_real_irqs > 32) | |
640 | out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); | |
641 | (void)in_le32(&pmac_irq_hw[0]->event); | |
642 | /* make sure mask gets to controller before we return to caller */ | |
643 | mb(); | |
644 | (void)in_le32(&pmac_irq_hw[0]->enable); | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | static int pmacpic_resume(struct sys_device *sysdev) | |
650 | { | |
651 | int i; | |
652 | ||
653 | out_le32(&pmac_irq_hw[0]->enable, 0); | |
654 | if (max_real_irqs > 32) | |
655 | out_le32(&pmac_irq_hw[1]->enable, 0); | |
656 | mb(); | |
657 | for (i = 0; i < max_real_irqs; ++i) | |
658 | if (test_bit(i, sleep_save_mask)) | |
659 | pmac_unmask_irq(i); | |
660 | ||
661 | return 0; | |
662 | } | |
663 | ||
a0005034 | 664 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |
14cf11af PM |
665 | |
666 | static struct sysdev_class pmacpic_sysclass = { | |
667 | set_kset_name("pmac_pic"), | |
668 | }; | |
669 | ||
670 | static struct sys_device device_pmacpic = { | |
671 | .id = 0, | |
672 | .cls = &pmacpic_sysclass, | |
673 | }; | |
674 | ||
675 | static struct sysdev_driver driver_pmacpic = { | |
a0005034 | 676 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
677 | .suspend = &pmacpic_suspend, |
678 | .resume = &pmacpic_resume, | |
a0005034 | 679 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |
14cf11af PM |
680 | }; |
681 | ||
682 | static int __init init_pmacpic_sysfs(void) | |
683 | { | |
3c3f42d6 | 684 | #ifdef CONFIG_PPC32 |
14cf11af PM |
685 | if (max_irqs == 0) |
686 | return -ENODEV; | |
3c3f42d6 | 687 | #endif |
14cf11af PM |
688 | printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); |
689 | sysdev_class_register(&pmacpic_sysclass); | |
690 | sysdev_register(&device_pmacpic); | |
691 | sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); | |
692 | return 0; | |
693 | } | |
694 | ||
695 | subsys_initcall(init_pmacpic_sysfs); | |
696 |