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14cf11af PM |
1 | /* |
2 | * Support for the interrupt controllers found on Power Macintosh, | |
3 | * currently Apple's "Grand Central" interrupt controller in all | |
4 | * it's incarnations. OpenPIC support used on newer machines is | |
5 | * in a separate file | |
6 | * | |
7 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) | |
cc5d0189 BH |
8 | * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
9 | * IBM, Corp. | |
14cf11af PM |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/stddef.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/signal.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/sysdev.h> | |
25 | #include <linux/adb.h> | |
26 | #include <linux/pmu.h> | |
3c3f42d6 | 27 | #include <linux/module.h> |
14cf11af PM |
28 | |
29 | #include <asm/sections.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/pci-bridge.h> | |
34 | #include <asm/time.h> | |
14cf11af PM |
35 | #include <asm/pmac_feature.h> |
36 | #include <asm/mpic.h> | |
af3b74df | 37 | #include <asm/xmon.h> |
14cf11af | 38 | |
3c3f42d6 | 39 | #include "pmac.h" |
14cf11af | 40 | |
3c3f42d6 | 41 | #ifdef CONFIG_PPC32 |
14cf11af PM |
42 | struct pmac_irq_hw { |
43 | unsigned int event; | |
44 | unsigned int enable; | |
45 | unsigned int ack; | |
46 | unsigned int level; | |
47 | }; | |
48 | ||
b83da291 GL |
49 | /* Workaround flags for 32bit powermac machines */ |
50 | unsigned int of_irq_workarounds; | |
51 | struct device_node *of_irq_dflt_pic; | |
52 | ||
14cf11af | 53 | /* Default addresses */ |
cc5d0189 | 54 | static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; |
14cf11af PM |
55 | |
56 | #define GC_LEVEL_MASK 0x3ff00000 | |
57 | #define OHARE_LEVEL_MASK 0x1ff00000 | |
58 | #define HEATHROW_LEVEL_MASK 0x1ff00000 | |
59 | ||
60 | static int max_irqs; | |
61 | static int max_real_irqs; | |
62 | static u32 level_mask[4]; | |
63 | ||
d0eab3eb | 64 | static DEFINE_RAW_SPINLOCK(pmac_pic_lock); |
14cf11af | 65 | |
756e7104 SR |
66 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) |
67 | static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; | |
b9e5b4e6 BH |
68 | static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; |
69 | static int pmac_irq_cascade = -1; | |
0ebfff14 | 70 | static struct irq_host *pmac_pic_host; |
756e7104 | 71 | |
b9e5b4e6 | 72 | static void __pmac_retrigger(unsigned int irq_nr) |
14cf11af | 73 | { |
b9e5b4e6 BH |
74 | if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { |
75 | __set_bit(irq_nr, ppc_lost_interrupts); | |
76 | irq_nr = pmac_irq_cascade; | |
77 | mb(); | |
78 | } | |
79 | if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { | |
14cf11af | 80 | atomic_inc(&ppc_n_lost_interrupts); |
b9e5b4e6 | 81 | set_dec(1); |
14cf11af PM |
82 | } |
83 | } | |
84 | ||
d8c94aca | 85 | static void pmac_mask_and_ack_irq(struct irq_data *d) |
14cf11af | 86 | { |
476eb491 | 87 | unsigned int src = irqd_to_hwirq(d); |
ca72945d BH |
88 | unsigned long bit = 1UL << (src & 0x1f); |
89 | int i = src >> 5; | |
14cf11af PM |
90 | unsigned long flags; |
91 | ||
d0eab3eb | 92 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
93 | __clear_bit(src, ppc_cached_irq_mask); |
94 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) | |
b9e5b4e6 | 95 | atomic_dec(&ppc_n_lost_interrupts); |
14cf11af PM |
96 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); |
97 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
98 | do { | |
99 | /* make sure ack gets to controller before we enable | |
100 | interrupts */ | |
101 | mb(); | |
102 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
103 | != (ppc_cached_irq_mask[i] & bit)); | |
d0eab3eb | 104 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
105 | } |
106 | ||
d8c94aca | 107 | static void pmac_ack_irq(struct irq_data *d) |
14cf11af | 108 | { |
476eb491 | 109 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
110 | unsigned long bit = 1UL << (src & 0x1f); |
111 | int i = src >> 5; | |
14cf11af PM |
112 | unsigned long flags; |
113 | ||
d0eab3eb | 114 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 115 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) |
b9e5b4e6 BH |
116 | atomic_dec(&ppc_n_lost_interrupts); |
117 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
118 | (void)in_le32(&pmac_irq_hw[i]->ack); | |
d0eab3eb | 119 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
120 | } |
121 | ||
122 | static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |
123 | { | |
124 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
125 | int i = irq_nr >> 5; | |
126 | ||
127 | if ((unsigned)irq_nr >= max_irqs) | |
128 | return; | |
129 | ||
14cf11af PM |
130 | /* enable unmasked interrupts */ |
131 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
132 | ||
133 | do { | |
134 | /* make sure mask gets to controller before we | |
135 | return to user */ | |
136 | mb(); | |
137 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
138 | != (ppc_cached_irq_mask[i] & bit)); | |
139 | ||
140 | /* | |
141 | * Unfortunately, setting the bit in the enable register | |
142 | * when the device interrupt is already on *doesn't* set | |
143 | * the bit in the flag register or request another interrupt. | |
144 | */ | |
145 | if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) | |
b9e5b4e6 | 146 | __pmac_retrigger(irq_nr); |
14cf11af PM |
147 | } |
148 | ||
149 | /* When an irq gets requested for the first client, if it's an | |
150 | * edge interrupt, we clear any previous one on the controller | |
151 | */ | |
d8c94aca | 152 | static unsigned int pmac_startup_irq(struct irq_data *d) |
14cf11af | 153 | { |
b9e5b4e6 | 154 | unsigned long flags; |
476eb491 | 155 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
156 | unsigned long bit = 1UL << (src & 0x1f); |
157 | int i = src >> 5; | |
14cf11af | 158 | |
d0eab3eb | 159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
8c99f561 | 160 | if (!irqd_is_level_type(d)) |
14cf11af | 161 | out_le32(&pmac_irq_hw[i]->ack, bit); |
0ebfff14 BH |
162 | __set_bit(src, ppc_cached_irq_mask); |
163 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 164 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
165 | |
166 | return 0; | |
167 | } | |
168 | ||
d8c94aca | 169 | static void pmac_mask_irq(struct irq_data *d) |
14cf11af | 170 | { |
b9e5b4e6 | 171 | unsigned long flags; |
476eb491 | 172 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 173 | |
d0eab3eb | 174 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 175 | __clear_bit(src, ppc_cached_irq_mask); |
ca72945d | 176 | __pmac_set_irq_mask(src, 1); |
d0eab3eb | 177 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
178 | } |
179 | ||
d8c94aca | 180 | static void pmac_unmask_irq(struct irq_data *d) |
14cf11af | 181 | { |
b9e5b4e6 | 182 | unsigned long flags; |
476eb491 | 183 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 184 | |
d0eab3eb | 185 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
186 | __set_bit(src, ppc_cached_irq_mask); |
187 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 188 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
189 | } |
190 | ||
d8c94aca | 191 | static int pmac_retrigger(struct irq_data *d) |
14cf11af | 192 | { |
b9e5b4e6 | 193 | unsigned long flags; |
14cf11af | 194 | |
d0eab3eb | 195 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
476eb491 | 196 | __pmac_retrigger(irqd_to_hwirq(d)); |
d0eab3eb | 197 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
198 | return 1; |
199 | } | |
14cf11af | 200 | |
b9e5b4e6 | 201 | static struct irq_chip pmac_pic = { |
fc380c0c | 202 | .name = "PMAC-PIC", |
d8c94aca LB |
203 | .irq_startup = pmac_startup_irq, |
204 | .irq_mask = pmac_mask_irq, | |
205 | .irq_ack = pmac_ack_irq, | |
206 | .irq_mask_ack = pmac_mask_and_ack_irq, | |
207 | .irq_unmask = pmac_unmask_irq, | |
208 | .irq_retrigger = pmac_retrigger, | |
14cf11af PM |
209 | }; |
210 | ||
35a84c2f | 211 | static irqreturn_t gatwick_action(int cpl, void *dev_id) |
14cf11af | 212 | { |
b9e5b4e6 | 213 | unsigned long flags; |
14cf11af | 214 | int irq, bits; |
b9e5b4e6 | 215 | int rc = IRQ_NONE; |
14cf11af | 216 | |
d0eab3eb | 217 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
218 | for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { |
219 | int i = irq >> 5; | |
220 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
221 | /* We must read level interrupts from the level register */ | |
222 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
223 | bits &= ppc_cached_irq_mask[i]; | |
224 | if (bits == 0) | |
225 | continue; | |
226 | irq += __ilog2(bits); | |
d0eab3eb | 227 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
f11f76d4 | 228 | generic_handle_irq(irq); |
d0eab3eb | 229 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
b9e5b4e6 | 230 | rc = IRQ_HANDLED; |
14cf11af | 231 | } |
d0eab3eb | 232 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 | 233 | return rc; |
14cf11af PM |
234 | } |
235 | ||
35a84c2f | 236 | static unsigned int pmac_pic_get_irq(void) |
14cf11af PM |
237 | { |
238 | int irq; | |
239 | unsigned long bits = 0; | |
b9e5b4e6 | 240 | unsigned long flags; |
14cf11af | 241 | |
1ece355b | 242 | #ifdef CONFIG_PPC_PMAC32_PSURGE |
35a84c2f | 243 | void psurge_smp_message_recv(void); |
14cf11af PM |
244 | |
245 | /* IPI's are a hack on the powersurge -- Cort */ | |
246 | if ( smp_processor_id() != 0 ) { | |
35a84c2f | 247 | psurge_smp_message_recv(); |
0ebfff14 | 248 | return NO_IRQ_IGNORE; /* ignore, already handled */ |
14cf11af | 249 | } |
1ece355b | 250 | #endif /* CONFIG_PPC_PMAC32_PSURGE */ |
d0eab3eb | 251 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
252 | for (irq = max_real_irqs; (irq -= 32) >= 0; ) { |
253 | int i = irq >> 5; | |
254 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
255 | /* We must read level interrupts from the level register */ | |
256 | bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); | |
257 | bits &= ppc_cached_irq_mask[i]; | |
258 | if (bits == 0) | |
259 | continue; | |
260 | irq += __ilog2(bits); | |
261 | break; | |
262 | } | |
d0eab3eb | 263 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
0ebfff14 BH |
264 | if (unlikely(irq < 0)) |
265 | return NO_IRQ; | |
266 | return irq_linear_revmap(pmac_pic_host, irq); | |
14cf11af PM |
267 | } |
268 | ||
14cf11af PM |
269 | #ifdef CONFIG_XMON |
270 | static struct irqaction xmon_action = { | |
271 | .handler = xmon_irq, | |
272 | .flags = 0, | |
14cf11af PM |
273 | .name = "NMI - XMON" |
274 | }; | |
275 | #endif | |
276 | ||
277 | static struct irqaction gatwick_cascade_action = { | |
278 | .handler = gatwick_action, | |
6714465e | 279 | .flags = IRQF_DISABLED, |
14cf11af PM |
280 | .name = "cascade", |
281 | }; | |
3c3f42d6 | 282 | |
0ebfff14 BH |
283 | static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) |
284 | { | |
285 | /* We match all, we don't always have a node anyway */ | |
286 | return 1; | |
287 | } | |
288 | ||
289 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | |
6e99e458 | 290 | irq_hw_number_t hw) |
0ebfff14 | 291 | { |
0ebfff14 BH |
292 | int level; |
293 | ||
294 | if (hw >= max_irqs) | |
295 | return -EINVAL; | |
296 | ||
297 | /* Mark level interrupts, set delayed disable for edge ones and set | |
298 | * handlers | |
299 | */ | |
300 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); | |
301 | if (level) | |
98488db9 | 302 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e TG |
303 | irq_set_chip_and_handler(virq, &pmac_pic, |
304 | level ? handle_level_irq : handle_edge_irq); | |
0ebfff14 BH |
305 | return 0; |
306 | } | |
307 | ||
308 | static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 309 | const u32 *intspec, unsigned int intsize, |
0ebfff14 BH |
310 | irq_hw_number_t *out_hwirq, |
311 | unsigned int *out_flags) | |
312 | ||
313 | { | |
6e99e458 | 314 | *out_flags = IRQ_TYPE_NONE; |
0ebfff14 BH |
315 | *out_hwirq = *intspec; |
316 | return 0; | |
317 | } | |
318 | ||
319 | static struct irq_host_ops pmac_pic_host_ops = { | |
320 | .match = pmac_pic_host_match, | |
321 | .map = pmac_pic_host_map, | |
322 | .xlate = pmac_pic_host_xlate, | |
323 | }; | |
324 | ||
cc5d0189 | 325 | static void __init pmac_pic_probe_oldstyle(void) |
3c3f42d6 | 326 | { |
3c3f42d6 | 327 | int i; |
cc5d0189 BH |
328 | struct device_node *master = NULL; |
329 | struct device_node *slave = NULL; | |
330 | u8 __iomem *addr; | |
331 | struct resource r; | |
14cf11af | 332 | |
cc5d0189 | 333 | /* Set our get_irq function */ |
0ebfff14 | 334 | ppc_md.get_irq = pmac_pic_get_irq; |
14cf11af | 335 | |
cc5d0189 BH |
336 | /* |
337 | * Find the interrupt controller type & node | |
14cf11af | 338 | */ |
cc5d0189 BH |
339 | |
340 | if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { | |
341 | max_irqs = max_real_irqs = 32; | |
14cf11af | 342 | level_mask[0] = GC_LEVEL_MASK; |
cc5d0189 BH |
343 | } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { |
344 | max_irqs = max_real_irqs = 32; | |
14cf11af | 345 | level_mask[0] = OHARE_LEVEL_MASK; |
cc5d0189 | 346 | |
14cf11af | 347 | /* We might have a second cascaded ohare */ |
cc5d0189 BH |
348 | slave = of_find_node_by_name(NULL, "pci106b,7"); |
349 | if (slave) { | |
350 | max_irqs = 64; | |
351 | level_mask[1] = OHARE_LEVEL_MASK; | |
cc5d0189 BH |
352 | } |
353 | } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { | |
354 | max_irqs = max_real_irqs = 64; | |
14cf11af PM |
355 | level_mask[0] = HEATHROW_LEVEL_MASK; |
356 | level_mask[1] = 0; | |
cc5d0189 | 357 | |
14cf11af | 358 | /* We might have a second cascaded heathrow */ |
cc5d0189 BH |
359 | slave = of_find_node_by_name(master, "mac-io"); |
360 | ||
361 | /* Check ordering of master & slave */ | |
55b61fec | 362 | if (of_device_is_compatible(master, "gatwick")) { |
cc5d0189 BH |
363 | struct device_node *tmp; |
364 | BUG_ON(slave == NULL); | |
365 | tmp = master; | |
366 | master = slave; | |
367 | slave = tmp; | |
368 | } | |
14cf11af | 369 | |
cc5d0189 BH |
370 | /* We found a slave */ |
371 | if (slave) { | |
14cf11af | 372 | max_irqs = 128; |
cc5d0189 BH |
373 | level_mask[2] = HEATHROW_LEVEL_MASK; |
374 | level_mask[3] = 0; | |
cc5d0189 | 375 | } |
14cf11af | 376 | } |
cc5d0189 BH |
377 | BUG_ON(master == NULL); |
378 | ||
0ebfff14 BH |
379 | /* |
380 | * Allocate an irq host | |
381 | */ | |
52964f87 | 382 | pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs, |
0ebfff14 BH |
383 | &pmac_pic_host_ops, |
384 | max_irqs); | |
385 | BUG_ON(pmac_pic_host == NULL); | |
386 | irq_set_default_host(pmac_pic_host); | |
14cf11af | 387 | |
cc5d0189 BH |
388 | /* Get addresses of first controller if we have a node for it */ |
389 | BUG_ON(of_address_to_resource(master, 0, &r)); | |
390 | ||
391 | /* Map interrupts of primary controller */ | |
392 | addr = (u8 __iomem *) ioremap(r.start, 0x40); | |
393 | i = 0; | |
394 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
395 | (addr + 0x20); | |
396 | if (max_real_irqs > 32) | |
397 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
398 | (addr + 0x10); | |
399 | of_node_put(master); | |
400 | ||
401 | printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", | |
402 | master->full_name, max_real_irqs); | |
403 | ||
404 | /* Map interrupts of cascaded controller */ | |
405 | if (slave && !of_address_to_resource(slave, 0, &r)) { | |
406 | addr = (u8 __iomem *)ioremap(r.start, 0x40); | |
407 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
408 | (addr + 0x20); | |
409 | if (max_irqs > 64) | |
410 | pmac_irq_hw[i++] = | |
411 | (volatile struct pmac_irq_hw __iomem *) | |
412 | (addr + 0x10); | |
0ebfff14 | 413 | pmac_irq_cascade = irq_of_parse_and_map(slave, 0); |
cc5d0189 BH |
414 | |
415 | printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" | |
416 | " cascade: %d\n", slave->full_name, | |
b9e5b4e6 | 417 | max_irqs - max_real_irqs, pmac_irq_cascade); |
14cf11af | 418 | } |
cc5d0189 | 419 | of_node_put(slave); |
14cf11af | 420 | |
b9e5b4e6 | 421 | /* Disable all interrupts in all controllers */ |
14cf11af PM |
422 | for (i = 0; i * 32 < max_irqs; ++i) |
423 | out_le32(&pmac_irq_hw[i]->enable, 0); | |
cc5d0189 | 424 | |
b9e5b4e6 | 425 | /* Hookup cascade irq */ |
0ebfff14 | 426 | if (slave && pmac_irq_cascade != NO_IRQ) |
b9e5b4e6 | 427 | setup_irq(pmac_irq_cascade, &gatwick_cascade_action); |
14cf11af | 428 | |
cc5d0189 | 429 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
14cf11af | 430 | #ifdef CONFIG_XMON |
6e99e458 | 431 | setup_irq(irq_create_mapping(NULL, 20), &xmon_action); |
cc5d0189 BH |
432 | #endif |
433 | } | |
b83da291 GL |
434 | |
435 | int of_irq_map_oldworld(struct device_node *device, int index, | |
436 | struct of_irq *out_irq) | |
437 | { | |
438 | const u32 *ints = NULL; | |
439 | int intlen; | |
440 | ||
441 | /* | |
442 | * Old machines just have a list of interrupt numbers | |
443 | * and no interrupt-controller nodes. We also have dodgy | |
444 | * cases where the APPL,interrupts property is completely | |
445 | * missing behind pci-pci bridges and we have to get it | |
446 | * from the parent (the bridge itself, as apple just wired | |
447 | * everything together on these) | |
448 | */ | |
449 | while (device) { | |
450 | ints = of_get_property(device, "AAPL,interrupts", &intlen); | |
451 | if (ints != NULL) | |
452 | break; | |
453 | device = device->parent; | |
454 | if (device && strcmp(device->type, "pci") != 0) | |
455 | break; | |
456 | } | |
457 | if (ints == NULL) | |
458 | return -EINVAL; | |
459 | intlen /= sizeof(u32); | |
460 | ||
461 | if (index >= intlen) | |
462 | return -EINVAL; | |
463 | ||
464 | out_irq->controller = NULL; | |
465 | out_irq->specifier[0] = ints[index]; | |
466 | out_irq->size = 1; | |
467 | ||
468 | return 0; | |
469 | } | |
cc5d0189 BH |
470 | #endif /* CONFIG_PPC32 */ |
471 | ||
7d12e780 | 472 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) |
cc5d0189 | 473 | { |
ec775d0e TG |
474 | struct irq_chip *chip = irq_desc_get_chip(desc); |
475 | struct mpic *mpic = irq_desc_get_handler_data(desc); | |
35a84c2f | 476 | unsigned int cascade_irq = mpic_get_one_irq(mpic); |
d8c94aca | 477 | |
0ebfff14 | 478 | if (cascade_irq != NO_IRQ) |
7d12e780 | 479 | generic_handle_irq(cascade_irq); |
d8c94aca LB |
480 | |
481 | chip->irq_eoi(&desc->irq_data); | |
cc5d0189 BH |
482 | } |
483 | ||
484 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) | |
485 | { | |
486 | #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) | |
487 | struct device_node* pswitch; | |
488 | int nmi_irq; | |
489 | ||
490 | pswitch = of_find_node_by_name(NULL, "programmer-switch"); | |
0ebfff14 BH |
491 | if (pswitch) { |
492 | nmi_irq = irq_of_parse_and_map(pswitch, 0); | |
493 | if (nmi_irq != NO_IRQ) { | |
494 | mpic_irq_set_priority(nmi_irq, 9); | |
495 | setup_irq(nmi_irq, &xmon_action); | |
496 | } | |
497 | of_node_put(pswitch); | |
cc5d0189 | 498 | } |
cc5d0189 BH |
499 | #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ |
500 | } | |
501 | ||
1beb6a7d BH |
502 | static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, |
503 | int master) | |
504 | { | |
1beb6a7d BH |
505 | const char *name = master ? " MPIC 1 " : " MPIC 2 "; |
506 | struct resource r; | |
507 | struct mpic *mpic; | |
508 | unsigned int flags = master ? MPIC_PRIMARY : 0; | |
509 | int rc; | |
510 | ||
511 | rc = of_address_to_resource(np, 0, &r); | |
512 | if (rc) | |
513 | return NULL; | |
514 | ||
515 | pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); | |
516 | ||
1beb6a7d | 517 | flags |= MPIC_WANTS_RESET; |
e2eb6392 | 518 | if (of_get_property(np, "big-endian", NULL)) |
1beb6a7d BH |
519 | flags |= MPIC_BIG_ENDIAN; |
520 | ||
521 | /* Primary Big Endian means HT interrupts. This is quite dodgy | |
522 | * but works until I find a better way | |
523 | */ | |
524 | if (master && (flags & MPIC_BIG_ENDIAN)) | |
6cfef5b2 | 525 | flags |= MPIC_U3_HT_IRQS; |
1beb6a7d | 526 | |
0ebfff14 | 527 | mpic = mpic_alloc(np, r.start, flags, 0, 0, name); |
1beb6a7d BH |
528 | if (mpic == NULL) |
529 | return NULL; | |
530 | ||
531 | mpic_init(mpic); | |
532 | ||
533 | return mpic; | |
534 | } | |
535 | ||
cc5d0189 BH |
536 | static int __init pmac_pic_probe_mpic(void) |
537 | { | |
538 | struct mpic *mpic1, *mpic2; | |
539 | struct device_node *np, *master = NULL, *slave = NULL; | |
0ebfff14 | 540 | unsigned int cascade; |
cc5d0189 BH |
541 | |
542 | /* We can have up to 2 MPICs cascaded */ | |
543 | for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) | |
544 | != NULL;) { | |
545 | if (master == NULL && | |
e2eb6392 | 546 | of_get_property(np, "interrupts", NULL) == NULL) |
cc5d0189 BH |
547 | master = of_node_get(np); |
548 | else if (slave == NULL) | |
549 | slave = of_node_get(np); | |
550 | if (master && slave) | |
551 | break; | |
552 | } | |
553 | ||
554 | /* Check for bogus setups */ | |
555 | if (master == NULL && slave != NULL) { | |
556 | master = slave; | |
557 | slave = NULL; | |
558 | } | |
559 | ||
560 | /* Not found, default to good old pmac pic */ | |
561 | if (master == NULL) | |
562 | return -ENODEV; | |
563 | ||
564 | /* Set master handler */ | |
565 | ppc_md.get_irq = mpic_get_irq; | |
566 | ||
567 | /* Setup master */ | |
1beb6a7d | 568 | mpic1 = pmac_setup_one_mpic(master, 1); |
cc5d0189 | 569 | BUG_ON(mpic1 == NULL); |
cc5d0189 BH |
570 | |
571 | /* Install NMI if any */ | |
572 | pmac_pic_setup_mpic_nmi(mpic1); | |
573 | ||
574 | of_node_put(master); | |
575 | ||
576 | /* No slave, let's go out */ | |
0ebfff14 BH |
577 | if (slave == NULL) |
578 | return 0; | |
579 | ||
580 | /* Get/Map slave interrupt */ | |
581 | cascade = irq_of_parse_and_map(slave, 0); | |
582 | if (cascade == NO_IRQ) { | |
583 | printk(KERN_ERR "Failed to map cascade IRQ\n"); | |
cc5d0189 | 584 | return 0; |
0ebfff14 | 585 | } |
cc5d0189 | 586 | |
1beb6a7d | 587 | mpic2 = pmac_setup_one_mpic(slave, 0); |
cc5d0189 | 588 | if (mpic2 == NULL) { |
1beb6a7d BH |
589 | printk(KERN_ERR "Failed to setup slave MPIC\n"); |
590 | of_node_put(slave); | |
cc5d0189 BH |
591 | return 0; |
592 | } | |
ec775d0e TG |
593 | irq_set_handler_data(cascade, mpic2); |
594 | irq_set_chained_handler(cascade, pmac_u3_cascade); | |
cc5d0189 BH |
595 | |
596 | of_node_put(slave); | |
597 | return 0; | |
598 | } | |
599 | ||
600 | ||
601 | void __init pmac_pic_init(void) | |
602 | { | |
0ebfff14 BH |
603 | /* We configure the OF parsing based on our oldworld vs. newworld |
604 | * platform type and wether we were booted by BootX. | |
605 | */ | |
606 | #ifdef CONFIG_PPC32 | |
607 | if (!pmac_newworld) | |
b83da291 | 608 | of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC; |
e2eb6392 | 609 | if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL) |
b83da291 | 610 | of_irq_workarounds |= OF_IMAP_NO_PHANDLE; |
0ebfff14 | 611 | |
b83da291 GL |
612 | /* If we don't have phandles on a newworld, then try to locate a |
613 | * default interrupt controller (happens when booting with BootX). | |
614 | * We do a first match here, hopefully, that only ever happens on | |
615 | * machines with one controller. | |
616 | */ | |
617 | if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) { | |
618 | struct device_node *np; | |
619 | ||
620 | for_each_node_with_property(np, "interrupt-controller") { | |
621 | /* Skip /chosen/interrupt-controller */ | |
622 | if (strcmp(np->name, "chosen") == 0) | |
623 | continue; | |
624 | /* It seems like at least one person wants | |
625 | * to use BootX on a machine with an AppleKiwi | |
626 | * controller which happens to pretend to be an | |
627 | * interrupt controller too. */ | |
628 | if (strcmp(np->name, "AppleKiwi") == 0) | |
629 | continue; | |
630 | /* I think we found one ! */ | |
631 | of_irq_dflt_pic = np; | |
632 | break; | |
633 | } | |
634 | } | |
635 | #endif /* CONFIG_PPC32 */ | |
6e99e458 | 636 | |
cc5d0189 BH |
637 | /* We first try to detect Apple's new Core99 chipset, since mac-io |
638 | * is quite different on those machines and contains an IBM MPIC2. | |
639 | */ | |
640 | if (pmac_pic_probe_mpic() == 0) | |
641 | return; | |
642 | ||
643 | #ifdef CONFIG_PPC32 | |
644 | pmac_pic_probe_oldstyle(); | |
645 | #endif | |
14cf11af PM |
646 | } |
647 | ||
a0005034 | 648 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
649 | /* |
650 | * These procedures are used in implementing sleep on the powerbooks. | |
651 | * sleep_save_intrs() saves the states of all interrupt enables | |
652 | * and disables all interrupts except for the nominated one. | |
653 | * sleep_restore_intrs() restores the states of all interrupt enables. | |
654 | */ | |
655 | unsigned long sleep_save_mask[2]; | |
656 | ||
657 | /* This used to be passed by the PMU driver but that link got | |
658 | * broken with the new driver model. We use this tweak for now... | |
0ebfff14 | 659 | * We really want to do things differently though... |
14cf11af PM |
660 | */ |
661 | static int pmacpic_find_viaint(void) | |
662 | { | |
663 | int viaint = -1; | |
664 | ||
665 | #ifdef CONFIG_ADB_PMU | |
666 | struct device_node *np; | |
667 | ||
668 | if (pmu_get_model() != PMU_OHARE_BASED) | |
669 | goto not_found; | |
670 | np = of_find_node_by_name(NULL, "via-pmu"); | |
671 | if (np == NULL) | |
672 | goto not_found; | |
d258e64e | 673 | viaint = irq_of_parse_and_map(np, 0); |
14cf11af PM |
674 | |
675 | not_found: | |
98cddbfb | 676 | #endif /* CONFIG_ADB_PMU */ |
14cf11af PM |
677 | return viaint; |
678 | } | |
679 | ||
680 | static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) | |
681 | { | |
682 | int viaint = pmacpic_find_viaint(); | |
683 | ||
684 | sleep_save_mask[0] = ppc_cached_irq_mask[0]; | |
685 | sleep_save_mask[1] = ppc_cached_irq_mask[1]; | |
686 | ppc_cached_irq_mask[0] = 0; | |
687 | ppc_cached_irq_mask[1] = 0; | |
688 | if (viaint > 0) | |
689 | set_bit(viaint, ppc_cached_irq_mask); | |
690 | out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); | |
691 | if (max_real_irqs > 32) | |
692 | out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); | |
693 | (void)in_le32(&pmac_irq_hw[0]->event); | |
694 | /* make sure mask gets to controller before we return to caller */ | |
695 | mb(); | |
696 | (void)in_le32(&pmac_irq_hw[0]->enable); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | static int pmacpic_resume(struct sys_device *sysdev) | |
702 | { | |
703 | int i; | |
704 | ||
705 | out_le32(&pmac_irq_hw[0]->enable, 0); | |
706 | if (max_real_irqs > 32) | |
707 | out_le32(&pmac_irq_hw[1]->enable, 0); | |
708 | mb(); | |
709 | for (i = 0; i < max_real_irqs; ++i) | |
710 | if (test_bit(i, sleep_save_mask)) | |
d8c94aca | 711 | pmac_unmask_irq(irq_get_irq_data(i)); |
14cf11af PM |
712 | |
713 | return 0; | |
714 | } | |
715 | ||
a0005034 | 716 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |
14cf11af PM |
717 | |
718 | static struct sysdev_class pmacpic_sysclass = { | |
af5ca3f4 | 719 | .name = "pmac_pic", |
14cf11af PM |
720 | }; |
721 | ||
722 | static struct sys_device device_pmacpic = { | |
723 | .id = 0, | |
724 | .cls = &pmacpic_sysclass, | |
725 | }; | |
726 | ||
727 | static struct sysdev_driver driver_pmacpic = { | |
a0005034 | 728 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
729 | .suspend = &pmacpic_suspend, |
730 | .resume = &pmacpic_resume, | |
a0005034 | 731 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |
14cf11af PM |
732 | }; |
733 | ||
734 | static int __init init_pmacpic_sysfs(void) | |
735 | { | |
3c3f42d6 | 736 | #ifdef CONFIG_PPC32 |
14cf11af PM |
737 | if (max_irqs == 0) |
738 | return -ENODEV; | |
3c3f42d6 | 739 | #endif |
14cf11af PM |
740 | printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); |
741 | sysdev_class_register(&pmacpic_sysclass); | |
742 | sysdev_register(&device_pmacpic); | |
743 | sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); | |
744 | return 0; | |
745 | } | |
d518b717 | 746 | machine_subsys_initcall(powermac, init_pmacpic_sysfs); |
14cf11af | 747 |