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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * SMP support for power macintosh. | |
3 | * | |
4 | * We support both the old "powersurge" SMP architecture | |
5 | * and the current Core99 (G4 PowerMac) machines. | |
6 | * | |
7 | * Note that we don't support the very first rev. of | |
8 | * Apple/DayStar 2 CPUs board, the one with the funky | |
9 | * watchdog. Hopefully, none of these should be there except | |
10 | * maybe internally to Apple. I should probably still add some | |
11 | * code to detect this card though and disable SMP. --BenH. | |
12 | * | |
13 | * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) | |
14 | * and Ben Herrenschmidt <benh@kernel.crashing.org>. | |
15 | * | |
16 | * Support for DayStar quad CPU cards | |
17 | * Copyright (C) XLR8, Inc. 1994-2000 | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
14cf11af PM |
24 | #include <linux/kernel.h> |
25 | #include <linux/sched.h> | |
26 | #include <linux/smp.h> | |
27 | #include <linux/smp_lock.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/kernel_stat.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/hardirq.h> | |
35 | #include <linux/cpu.h> | |
54c4e6b5 | 36 | #include <linux/compiler.h> |
14cf11af PM |
37 | |
38 | #include <asm/ptrace.h> | |
39 | #include <asm/atomic.h> | |
40 | #include <asm/irq.h> | |
41 | #include <asm/page.h> | |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/sections.h> | |
44 | #include <asm/io.h> | |
45 | #include <asm/prom.h> | |
46 | #include <asm/smp.h> | |
14cf11af PM |
47 | #include <asm/machdep.h> |
48 | #include <asm/pmac_feature.h> | |
49 | #include <asm/time.h> | |
c0c0d996 | 50 | #include <asm/mpic.h> |
14cf11af PM |
51 | #include <asm/cacheflush.h> |
52 | #include <asm/keylargo.h> | |
35499c01 | 53 | #include <asm/pmac_low_i2c.h> |
5b9ca526 | 54 | #include <asm/pmac_pfunc.h> |
35499c01 | 55 | |
5b9ca526 | 56 | #define DEBUG |
35499c01 PM |
57 | |
58 | #ifdef DEBUG | |
59 | #define DBG(fmt...) udbg_printf(fmt) | |
60 | #else | |
61 | #define DBG(fmt...) | |
62 | #endif | |
63 | ||
64 | extern void __secondary_start_pmac_0(void); | |
5b9ca526 | 65 | extern int pmac_pfunc_base_install(void); |
35499c01 PM |
66 | |
67 | #ifdef CONFIG_PPC32 | |
68 | ||
69 | /* Sync flag for HW tb sync */ | |
70 | static volatile int sec_tb_reset = 0; | |
14cf11af PM |
71 | |
72 | /* | |
73 | * Powersurge (old powermac SMP) support. | |
74 | */ | |
75 | ||
14cf11af PM |
76 | /* Addresses for powersurge registers */ |
77 | #define HAMMERHEAD_BASE 0xf8000000 | |
78 | #define HHEAD_CONFIG 0x90 | |
79 | #define HHEAD_SEC_INTR 0xc0 | |
80 | ||
81 | /* register for interrupting the primary processor on the powersurge */ | |
82 | /* N.B. this is actually the ethernet ROM! */ | |
83 | #define PSURGE_PRI_INTR 0xf3019000 | |
84 | ||
85 | /* register for storing the start address for the secondary processor */ | |
86 | /* N.B. this is the PCI config space address register for the 1st bridge */ | |
87 | #define PSURGE_START 0xf2800000 | |
88 | ||
89 | /* Daystar/XLR8 4-CPU card */ | |
90 | #define PSURGE_QUAD_REG_ADDR 0xf8800000 | |
91 | ||
92 | #define PSURGE_QUAD_IRQ_SET 0 | |
93 | #define PSURGE_QUAD_IRQ_CLR 1 | |
94 | #define PSURGE_QUAD_IRQ_PRIMARY 2 | |
95 | #define PSURGE_QUAD_CKSTOP_CTL 3 | |
96 | #define PSURGE_QUAD_PRIMARY_ARB 4 | |
97 | #define PSURGE_QUAD_BOARD_ID 6 | |
98 | #define PSURGE_QUAD_WHICH_CPU 7 | |
99 | #define PSURGE_QUAD_CKSTOP_RDBK 8 | |
100 | #define PSURGE_QUAD_RESET_CTL 11 | |
101 | ||
102 | #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) | |
103 | #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) | |
104 | #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) | |
105 | #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) | |
106 | ||
107 | /* virtual addresses for the above */ | |
108 | static volatile u8 __iomem *hhead_base; | |
109 | static volatile u8 __iomem *quad_base; | |
110 | static volatile u32 __iomem *psurge_pri_intr; | |
111 | static volatile u8 __iomem *psurge_sec_intr; | |
112 | static volatile u32 __iomem *psurge_start; | |
113 | ||
114 | /* values for psurge_type */ | |
115 | #define PSURGE_NONE -1 | |
116 | #define PSURGE_DUAL 0 | |
117 | #define PSURGE_QUAD_OKEE 1 | |
118 | #define PSURGE_QUAD_COTTON 2 | |
119 | #define PSURGE_QUAD_ICEGRASS 3 | |
120 | ||
121 | /* what sort of powersurge board we have */ | |
122 | static int psurge_type = PSURGE_NONE; | |
123 | ||
14cf11af PM |
124 | /* |
125 | * Set and clear IPIs for powersurge. | |
126 | */ | |
127 | static inline void psurge_set_ipi(int cpu) | |
128 | { | |
129 | if (psurge_type == PSURGE_NONE) | |
130 | return; | |
131 | if (cpu == 0) | |
132 | in_be32(psurge_pri_intr); | |
133 | else if (psurge_type == PSURGE_DUAL) | |
134 | out_8(psurge_sec_intr, 0); | |
135 | else | |
136 | PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); | |
137 | } | |
138 | ||
139 | static inline void psurge_clr_ipi(int cpu) | |
140 | { | |
141 | if (cpu > 0) { | |
142 | switch(psurge_type) { | |
143 | case PSURGE_DUAL: | |
144 | out_8(psurge_sec_intr, ~0); | |
145 | case PSURGE_NONE: | |
146 | break; | |
147 | default: | |
148 | PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); | |
149 | } | |
150 | } | |
151 | } | |
152 | ||
153 | /* | |
154 | * On powersurge (old SMP powermac architecture) we don't have | |
155 | * separate IPIs for separate messages like openpic does. Instead | |
156 | * we have a bitmap for each processor, where a 1 bit means that | |
157 | * the corresponding message is pending for that processor. | |
158 | * Ideally each cpu's entry would be in a different cache line. | |
159 | * -- paulus. | |
160 | */ | |
161 | static unsigned long psurge_smp_message[NR_CPUS]; | |
162 | ||
35a84c2f | 163 | void psurge_smp_message_recv(void) |
14cf11af PM |
164 | { |
165 | int cpu = smp_processor_id(); | |
166 | int msg; | |
167 | ||
168 | /* clear interrupt */ | |
169 | psurge_clr_ipi(cpu); | |
170 | ||
171 | if (num_online_cpus() < 2) | |
172 | return; | |
173 | ||
174 | /* make sure there is a message there */ | |
175 | for (msg = 0; msg < 4; msg++) | |
176 | if (test_and_clear_bit(msg, &psurge_smp_message[cpu])) | |
35a84c2f | 177 | smp_message_recv(msg); |
14cf11af PM |
178 | } |
179 | ||
35a84c2f | 180 | irqreturn_t psurge_primary_intr(int irq, void *d) |
14cf11af | 181 | { |
35a84c2f | 182 | psurge_smp_message_recv(); |
14cf11af PM |
183 | return IRQ_HANDLED; |
184 | } | |
185 | ||
7ed476d1 | 186 | static void smp_psurge_message_pass(int target, int msg) |
14cf11af PM |
187 | { |
188 | int i; | |
189 | ||
190 | if (num_online_cpus() < 2) | |
191 | return; | |
192 | ||
394e3902 | 193 | for_each_online_cpu(i) { |
14cf11af PM |
194 | if (target == MSG_ALL |
195 | || (target == MSG_ALL_BUT_SELF && i != smp_processor_id()) | |
196 | || target == i) { | |
197 | set_bit(msg, &psurge_smp_message[i]); | |
198 | psurge_set_ipi(i); | |
199 | } | |
200 | } | |
201 | } | |
202 | ||
203 | /* | |
204 | * Determine a quad card presence. We read the board ID register, we | |
205 | * force the data bus to change to something else, and we read it again. | |
206 | * It it's stable, then the register probably exist (ugh !) | |
207 | */ | |
208 | static int __init psurge_quad_probe(void) | |
209 | { | |
210 | int type; | |
211 | unsigned int i; | |
212 | ||
213 | type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); | |
214 | if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS | |
215 | || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) | |
216 | return PSURGE_DUAL; | |
217 | ||
218 | /* looks OK, try a slightly more rigorous test */ | |
219 | /* bogus is not necessarily cacheline-aligned, | |
220 | though I don't suppose that really matters. -- paulus */ | |
221 | for (i = 0; i < 100; i++) { | |
222 | volatile u32 bogus[8]; | |
223 | bogus[(0+i)%8] = 0x00000000; | |
224 | bogus[(1+i)%8] = 0x55555555; | |
225 | bogus[(2+i)%8] = 0xFFFFFFFF; | |
226 | bogus[(3+i)%8] = 0xAAAAAAAA; | |
227 | bogus[(4+i)%8] = 0x33333333; | |
228 | bogus[(5+i)%8] = 0xCCCCCCCC; | |
229 | bogus[(6+i)%8] = 0xCCCCCCCC; | |
230 | bogus[(7+i)%8] = 0x33333333; | |
231 | wmb(); | |
232 | asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); | |
233 | mb(); | |
234 | if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) | |
235 | return PSURGE_DUAL; | |
236 | } | |
237 | return type; | |
238 | } | |
239 | ||
240 | static void __init psurge_quad_init(void) | |
241 | { | |
242 | int procbits; | |
243 | ||
244 | if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); | |
245 | procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); | |
246 | if (psurge_type == PSURGE_QUAD_ICEGRASS) | |
247 | PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); | |
248 | else | |
249 | PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); | |
250 | mdelay(33); | |
251 | out_8(psurge_sec_intr, ~0); | |
252 | PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); | |
253 | PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); | |
254 | if (psurge_type != PSURGE_QUAD_ICEGRASS) | |
255 | PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); | |
256 | PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); | |
257 | mdelay(33); | |
258 | PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); | |
259 | mdelay(33); | |
260 | PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); | |
261 | mdelay(33); | |
262 | } | |
263 | ||
264 | static int __init smp_psurge_probe(void) | |
265 | { | |
266 | int i, ncpus; | |
267 | ||
268 | /* We don't do SMP on the PPC601 -- paulus */ | |
269 | if (PVR_VER(mfspr(SPRN_PVR)) == 1) | |
270 | return 1; | |
271 | ||
272 | /* | |
273 | * The powersurge cpu board can be used in the generation | |
274 | * of powermacs that have a socket for an upgradeable cpu card, | |
275 | * including the 7500, 8500, 9500, 9600. | |
276 | * The device tree doesn't tell you if you have 2 cpus because | |
277 | * OF doesn't know anything about the 2nd processor. | |
278 | * Instead we look for magic bits in magic registers, | |
279 | * in the hammerhead memory controller in the case of the | |
280 | * dual-cpu powersurge board. -- paulus. | |
281 | */ | |
282 | if (find_devices("hammerhead") == NULL) | |
283 | return 1; | |
284 | ||
285 | hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); | |
286 | quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); | |
287 | psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; | |
288 | ||
289 | psurge_type = psurge_quad_probe(); | |
290 | if (psurge_type != PSURGE_DUAL) { | |
291 | psurge_quad_init(); | |
292 | /* All released cards using this HW design have 4 CPUs */ | |
293 | ncpus = 4; | |
294 | } else { | |
295 | iounmap(quad_base); | |
296 | if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { | |
297 | /* not a dual-cpu card */ | |
298 | iounmap(hhead_base); | |
299 | psurge_type = PSURGE_NONE; | |
300 | return 1; | |
301 | } | |
302 | ncpus = 2; | |
303 | } | |
304 | ||
305 | psurge_start = ioremap(PSURGE_START, 4); | |
306 | psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); | |
307 | ||
094fe2e7 PM |
308 | /* |
309 | * This is necessary because OF doesn't know about the | |
310 | * secondary cpu(s), and thus there aren't nodes in the | |
311 | * device tree for them, and smp_setup_cpu_maps hasn't | |
312 | * set their bits in cpu_possible_map and cpu_present_map. | |
313 | */ | |
314 | if (ncpus > NR_CPUS) | |
315 | ncpus = NR_CPUS; | |
316 | for (i = 1; i < ncpus ; ++i) { | |
317 | cpu_set(i, cpu_present_map); | |
318 | cpu_set(i, cpu_possible_map); | |
319 | set_hard_smp_processor_id(i, i); | |
320 | } | |
14cf11af PM |
321 | |
322 | if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); | |
323 | ||
324 | return ncpus; | |
325 | } | |
326 | ||
327 | static void __init smp_psurge_kick_cpu(int nr) | |
328 | { | |
329 | unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; | |
330 | unsigned long a; | |
d6a29252 | 331 | int i; |
14cf11af PM |
332 | |
333 | /* may need to flush here if secondary bats aren't setup */ | |
334 | for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) | |
335 | asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); | |
336 | asm volatile("sync"); | |
337 | ||
338 | if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); | |
339 | ||
340 | out_be32(psurge_start, start); | |
341 | mb(); | |
342 | ||
343 | psurge_set_ipi(nr); | |
d6a29252 PM |
344 | /* |
345 | * We can't use udelay here because the timebase is now frozen. | |
346 | */ | |
347 | for (i = 0; i < 2000; ++i) | |
348 | barrier(); | |
14cf11af PM |
349 | psurge_clr_ipi(nr); |
350 | ||
351 | if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); | |
352 | } | |
353 | ||
354 | /* | |
355 | * With the dual-cpu powersurge board, the decrementers and timebases | |
356 | * of both cpus are frozen after the secondary cpu is started up, | |
357 | * until we give the secondary cpu another interrupt. This routine | |
358 | * uses this to get the timebases synchronized. | |
359 | * -- paulus. | |
360 | */ | |
361 | static void __init psurge_dual_sync_tb(int cpu_nr) | |
362 | { | |
363 | int t; | |
364 | ||
365 | set_dec(tb_ticks_per_jiffy); | |
094fe2e7 | 366 | /* XXX fixme */ |
14cf11af | 367 | set_tb(0, 0); |
14cf11af PM |
368 | |
369 | if (cpu_nr > 0) { | |
370 | mb(); | |
371 | sec_tb_reset = 1; | |
372 | return; | |
373 | } | |
374 | ||
375 | /* wait for the secondary to have reset its TB before proceeding */ | |
376 | for (t = 10000000; t > 0 && !sec_tb_reset; --t) | |
377 | ; | |
378 | ||
379 | /* now interrupt the secondary, starting both TBs */ | |
380 | psurge_set_ipi(1); | |
14cf11af PM |
381 | } |
382 | ||
383 | static struct irqaction psurge_irqaction = { | |
384 | .handler = psurge_primary_intr, | |
6714465e | 385 | .flags = IRQF_DISABLED, |
14cf11af PM |
386 | .mask = CPU_MASK_NONE, |
387 | .name = "primary IPI", | |
388 | }; | |
389 | ||
390 | static void __init smp_psurge_setup_cpu(int cpu_nr) | |
391 | { | |
392 | ||
393 | if (cpu_nr == 0) { | |
394 | /* If we failed to start the second CPU, we should still | |
395 | * send it an IPI to start the timebase & DEC or we might | |
396 | * have them stuck. | |
397 | */ | |
398 | if (num_online_cpus() < 2) { | |
399 | if (psurge_type == PSURGE_DUAL) | |
400 | psurge_set_ipi(1); | |
401 | return; | |
402 | } | |
403 | /* reset the entry point so if we get another intr we won't | |
404 | * try to startup again */ | |
405 | out_be32(psurge_start, 0x100); | |
406 | if (setup_irq(30, &psurge_irqaction)) | |
407 | printk(KERN_ERR "Couldn't get primary IPI interrupt"); | |
408 | } | |
409 | ||
410 | if (psurge_type == PSURGE_DUAL) | |
411 | psurge_dual_sync_tb(cpu_nr); | |
412 | } | |
413 | ||
414 | void __init smp_psurge_take_timebase(void) | |
415 | { | |
416 | /* Dummy implementation */ | |
417 | } | |
418 | ||
419 | void __init smp_psurge_give_timebase(void) | |
420 | { | |
421 | /* Dummy implementation */ | |
422 | } | |
423 | ||
35499c01 PM |
424 | /* PowerSurge-style Macs */ |
425 | struct smp_ops_t psurge_smp_ops = { | |
426 | .message_pass = smp_psurge_message_pass, | |
427 | .probe = smp_psurge_probe, | |
428 | .kick_cpu = smp_psurge_kick_cpu, | |
429 | .setup_cpu = smp_psurge_setup_cpu, | |
430 | .give_timebase = smp_psurge_give_timebase, | |
431 | .take_timebase = smp_psurge_take_timebase, | |
432 | }; | |
433 | #endif /* CONFIG_PPC32 - actually powersurge support */ | |
14cf11af | 434 | |
1beb6a7d BH |
435 | /* |
436 | * Core 99 and later support | |
437 | */ | |
438 | ||
439 | static void (*pmac_tb_freeze)(int freeze); | |
0c2aca88 | 440 | static u64 timebase; |
1beb6a7d BH |
441 | static int tb_req; |
442 | ||
443 | static void smp_core99_give_timebase(void) | |
444 | { | |
445 | unsigned long flags; | |
446 | ||
447 | local_irq_save(flags); | |
448 | ||
449 | while(!tb_req) | |
450 | barrier(); | |
451 | tb_req = 0; | |
452 | (*pmac_tb_freeze)(1); | |
453 | mb(); | |
454 | timebase = get_tb(); | |
455 | mb(); | |
456 | while (timebase) | |
457 | barrier(); | |
458 | mb(); | |
459 | (*pmac_tb_freeze)(0); | |
460 | mb(); | |
461 | ||
462 | local_irq_restore(flags); | |
463 | } | |
464 | ||
465 | ||
466 | static void __devinit smp_core99_take_timebase(void) | |
467 | { | |
468 | unsigned long flags; | |
469 | ||
470 | local_irq_save(flags); | |
471 | ||
472 | tb_req = 1; | |
473 | mb(); | |
474 | while (!timebase) | |
475 | barrier(); | |
476 | mb(); | |
477 | set_tb(timebase >> 32, timebase & 0xffffffff); | |
478 | timebase = 0; | |
479 | mb(); | |
480 | set_dec(tb_ticks_per_jiffy/2); | |
481 | ||
482 | local_irq_restore(flags); | |
483 | } | |
484 | ||
35499c01 PM |
485 | #ifdef CONFIG_PPC64 |
486 | /* | |
487 | * G5s enable/disable the timebase via an i2c-connected clock chip. | |
488 | */ | |
730745a5 | 489 | static struct pmac_i2c_bus *pmac_tb_clock_chip_host; |
35499c01 | 490 | static u8 pmac_tb_pulsar_addr; |
14cf11af | 491 | |
35499c01 PM |
492 | static void smp_core99_cypress_tb_freeze(int freeze) |
493 | { | |
494 | u8 data; | |
495 | int rc; | |
14cf11af | 496 | |
35499c01 PM |
497 | /* Strangely, the device-tree says address is 0xd2, but darwin |
498 | * accesses 0xd0 ... | |
499 | */ | |
730745a5 BH |
500 | pmac_i2c_setmode(pmac_tb_clock_chip_host, |
501 | pmac_i2c_mode_combined); | |
502 | rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, | |
503 | 0xd0 | pmac_i2c_read, | |
504 | 1, 0x81, &data, 1); | |
35499c01 PM |
505 | if (rc != 0) |
506 | goto bail; | |
507 | ||
508 | data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); | |
509 | ||
730745a5 BH |
510 | pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); |
511 | rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, | |
512 | 0xd0 | pmac_i2c_write, | |
513 | 1, 0x81, &data, 1); | |
35499c01 PM |
514 | |
515 | bail: | |
516 | if (rc != 0) { | |
517 | printk("Cypress Timebase %s rc: %d\n", | |
518 | freeze ? "freeze" : "unfreeze", rc); | |
519 | panic("Timebase freeze failed !\n"); | |
14cf11af | 520 | } |
14cf11af PM |
521 | } |
522 | ||
14cf11af | 523 | |
35499c01 PM |
524 | static void smp_core99_pulsar_tb_freeze(int freeze) |
525 | { | |
526 | u8 data; | |
527 | int rc; | |
528 | ||
730745a5 BH |
529 | pmac_i2c_setmode(pmac_tb_clock_chip_host, |
530 | pmac_i2c_mode_combined); | |
531 | rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, | |
532 | pmac_tb_pulsar_addr | pmac_i2c_read, | |
533 | 1, 0x2e, &data, 1); | |
35499c01 PM |
534 | if (rc != 0) |
535 | goto bail; | |
536 | ||
537 | data = (data & 0x88) | (freeze ? 0x11 : 0x22); | |
538 | ||
730745a5 BH |
539 | pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); |
540 | rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, | |
541 | pmac_tb_pulsar_addr | pmac_i2c_write, | |
542 | 1, 0x2e, &data, 1); | |
35499c01 PM |
543 | bail: |
544 | if (rc != 0) { | |
545 | printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", | |
546 | freeze ? "freeze" : "unfreeze", rc); | |
547 | panic("Timebase freeze failed !\n"); | |
548 | } | |
549 | } | |
14cf11af | 550 | |
1beb6a7d | 551 | static void __init smp_core99_setup_i2c_hwsync(int ncpus) |
14cf11af | 552 | { |
35499c01 PM |
553 | struct device_node *cc = NULL; |
554 | struct device_node *p; | |
1beb6a7d | 555 | const char *name = NULL; |
018a3d1d | 556 | const u32 *reg; |
35499c01 PM |
557 | int ok; |
558 | ||
35499c01 PM |
559 | /* Look for the clock chip */ |
560 | while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) { | |
561 | p = of_get_parent(cc); | |
562 | ok = p && device_is_compatible(p, "uni-n-i2c"); | |
563 | of_node_put(p); | |
564 | if (!ok) | |
565 | continue; | |
14cf11af | 566 | |
730745a5 BH |
567 | pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); |
568 | if (pmac_tb_clock_chip_host == NULL) | |
569 | continue; | |
e2eb6392 | 570 | reg = of_get_property(cc, "reg", NULL); |
35499c01 PM |
571 | if (reg == NULL) |
572 | continue; | |
35499c01 PM |
573 | switch (*reg) { |
574 | case 0xd2: | |
730745a5 | 575 | if (device_is_compatible(cc,"pulsar-legacy-slewing")) { |
35499c01 PM |
576 | pmac_tb_freeze = smp_core99_pulsar_tb_freeze; |
577 | pmac_tb_pulsar_addr = 0xd2; | |
1beb6a7d | 578 | name = "Pulsar"; |
35499c01 PM |
579 | } else if (device_is_compatible(cc, "cy28508")) { |
580 | pmac_tb_freeze = smp_core99_cypress_tb_freeze; | |
1beb6a7d | 581 | name = "Cypress"; |
35499c01 PM |
582 | } |
583 | break; | |
584 | case 0xd4: | |
585 | pmac_tb_freeze = smp_core99_pulsar_tb_freeze; | |
586 | pmac_tb_pulsar_addr = 0xd4; | |
1beb6a7d | 587 | name = "Pulsar"; |
35499c01 PM |
588 | break; |
589 | } | |
1beb6a7d | 590 | if (pmac_tb_freeze != NULL) |
35499c01 | 591 | break; |
35499c01 | 592 | } |
1beb6a7d | 593 | if (pmac_tb_freeze != NULL) { |
1beb6a7d | 594 | /* Open i2c bus for synchronous access */ |
730745a5 BH |
595 | if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { |
596 | printk(KERN_ERR "Failed top open i2c bus for clock" | |
597 | " sync, fallback to software sync !\n"); | |
1beb6a7d BH |
598 | goto no_i2c_sync; |
599 | } | |
1beb6a7d BH |
600 | printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", |
601 | name); | |
602 | return; | |
14cf11af | 603 | } |
1beb6a7d BH |
604 | no_i2c_sync: |
605 | pmac_tb_freeze = NULL; | |
730745a5 | 606 | pmac_tb_clock_chip_host = NULL; |
14cf11af PM |
607 | } |
608 | ||
14cf11af | 609 | |
14cf11af | 610 | |
35499c01 | 611 | /* |
5b9ca526 BH |
612 | * Newer G5s uses a platform function |
613 | */ | |
614 | ||
615 | static void smp_core99_pfunc_tb_freeze(int freeze) | |
616 | { | |
617 | struct device_node *cpus; | |
618 | struct pmf_args args; | |
619 | ||
620 | cpus = of_find_node_by_path("/cpus"); | |
621 | BUG_ON(cpus == NULL); | |
622 | args.count = 1; | |
623 | args.u[0].v = !freeze; | |
624 | pmf_call_function(cpus, "cpu-timebase", &args); | |
625 | of_node_put(cpus); | |
626 | } | |
627 | ||
628 | #else /* CONFIG_PPC64 */ | |
629 | ||
630 | /* | |
631 | * SMP G4 use a GPIO to enable/disable the timebase. | |
35499c01 | 632 | */ |
14cf11af | 633 | |
35499c01 | 634 | static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ |
14cf11af | 635 | |
1beb6a7d | 636 | static void smp_core99_gpio_tb_freeze(int freeze) |
14cf11af | 637 | { |
1beb6a7d BH |
638 | if (freeze) |
639 | pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); | |
640 | else | |
641 | pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); | |
14cf11af | 642 | pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); |
35499c01 PM |
643 | } |
644 | ||
5b9ca526 BH |
645 | |
646 | #endif /* !CONFIG_PPC64 */ | |
647 | ||
35499c01 PM |
648 | /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ |
649 | volatile static long int core99_l2_cache; | |
650 | volatile static long int core99_l3_cache; | |
651 | ||
652 | static void __devinit core99_init_caches(int cpu) | |
14cf11af | 653 | { |
1beb6a7d | 654 | #ifndef CONFIG_PPC64 |
35499c01 | 655 | if (!cpu_has_feature(CPU_FTR_L2CR)) |
14cf11af | 656 | return; |
35499c01 PM |
657 | |
658 | if (cpu == 0) { | |
659 | core99_l2_cache = _get_L2CR(); | |
660 | printk("CPU0: L2CR is %lx\n", core99_l2_cache); | |
661 | } else { | |
662 | printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); | |
663 | _set_L2CR(0); | |
664 | _set_L2CR(core99_l2_cache); | |
665 | printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); | |
14cf11af | 666 | } |
35499c01 PM |
667 | |
668 | if (!cpu_has_feature(CPU_FTR_L3CR)) | |
669 | return; | |
670 | ||
671 | if (cpu == 0){ | |
672 | core99_l3_cache = _get_L3CR(); | |
673 | printk("CPU0: L3CR is %lx\n", core99_l3_cache); | |
674 | } else { | |
675 | printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); | |
676 | _set_L3CR(0); | |
677 | _set_L3CR(core99_l3_cache); | |
678 | printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); | |
14cf11af | 679 | } |
1beb6a7d | 680 | #endif /* !CONFIG_PPC64 */ |
14cf11af PM |
681 | } |
682 | ||
35499c01 PM |
683 | static void __init smp_core99_setup(int ncpus) |
684 | { | |
1beb6a7d | 685 | #ifdef CONFIG_PPC64 |
35499c01 | 686 | |
1beb6a7d BH |
687 | /* i2c based HW sync on some G5s */ |
688 | if (machine_is_compatible("PowerMac7,2") || | |
689 | machine_is_compatible("PowerMac7,3") || | |
690 | machine_is_compatible("RackMac3,1")) | |
691 | smp_core99_setup_i2c_hwsync(ncpus); | |
692 | ||
5b9ca526 | 693 | /* pfunc based HW sync on recent G5s */ |
1beb6a7d | 694 | if (pmac_tb_freeze == NULL) { |
5b9ca526 BH |
695 | struct device_node *cpus = |
696 | of_find_node_by_path("/cpus"); | |
697 | if (cpus && | |
e2eb6392 | 698 | of_get_property(cpus, "platform-cpu-timebase", NULL)) { |
5b9ca526 | 699 | pmac_tb_freeze = smp_core99_pfunc_tb_freeze; |
1beb6a7d | 700 | printk(KERN_INFO "Processor timebase sync using" |
5b9ca526 | 701 | " platform function\n"); |
1beb6a7d | 702 | } |
35499c01 PM |
703 | } |
704 | ||
1beb6a7d BH |
705 | #else /* CONFIG_PPC64 */ |
706 | ||
707 | /* GPIO based HW sync on ppc32 Core99 */ | |
708 | if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) { | |
709 | struct device_node *cpu; | |
13b5aecc | 710 | const u32 *tbprop = NULL; |
1beb6a7d BH |
711 | |
712 | core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ | |
713 | cpu = of_find_node_by_type(NULL, "cpu"); | |
714 | if (cpu != NULL) { | |
e2eb6392 | 715 | tbprop = of_get_property(cpu, "timebase-enable", NULL); |
1beb6a7d BH |
716 | if (tbprop) |
717 | core99_tb_gpio = *tbprop; | |
718 | of_node_put(cpu); | |
719 | } | |
720 | pmac_tb_freeze = smp_core99_gpio_tb_freeze; | |
721 | printk(KERN_INFO "Processor timebase sync using" | |
722 | " GPIO 0x%02x\n", core99_tb_gpio); | |
723 | } | |
724 | ||
725 | #endif /* CONFIG_PPC64 */ | |
726 | ||
727 | /* No timebase sync, fallback to software */ | |
728 | if (pmac_tb_freeze == NULL) { | |
729 | smp_ops->give_timebase = smp_generic_give_timebase; | |
730 | smp_ops->take_timebase = smp_generic_take_timebase; | |
731 | printk(KERN_INFO "Processor timebase sync using software\n"); | |
732 | } | |
733 | ||
734 | #ifndef CONFIG_PPC64 | |
735 | { | |
736 | int i; | |
737 | ||
738 | /* XXX should get this from reg properties */ | |
739 | for (i = 1; i < ncpus; ++i) | |
740 | smp_hw_index[i] = i; | |
741 | } | |
35499c01 PM |
742 | #endif |
743 | ||
1beb6a7d BH |
744 | /* 32 bits SMP can't NAP */ |
745 | if (!machine_is_compatible("MacRISC4")) | |
746 | powersave_nap = 0; | |
747 | } | |
748 | ||
35499c01 PM |
749 | static int __init smp_core99_probe(void) |
750 | { | |
751 | struct device_node *cpus; | |
752 | int ncpus = 0; | |
753 | ||
754 | if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); | |
755 | ||
756 | /* Count CPUs in the device-tree */ | |
757 | for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;) | |
758 | ++ncpus; | |
759 | ||
760 | printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); | |
761 | ||
762 | /* Nothing more to do if less than 2 of them */ | |
763 | if (ncpus <= 1) | |
764 | return 1; | |
765 | ||
730745a5 BH |
766 | /* We need to perform some early initialisations before we can start |
767 | * setting up SMP as we are running before initcalls | |
768 | */ | |
5b9ca526 | 769 | pmac_pfunc_base_install(); |
730745a5 BH |
770 | pmac_i2c_init(); |
771 | ||
772 | /* Setup various bits like timebase sync method, ability to nap, ... */ | |
35499c01 | 773 | smp_core99_setup(ncpus); |
730745a5 BH |
774 | |
775 | /* Install IPIs */ | |
35499c01 | 776 | mpic_request_ipis(); |
730745a5 BH |
777 | |
778 | /* Collect l2cr and l3cr values from CPU 0 */ | |
35499c01 PM |
779 | core99_init_caches(0); |
780 | ||
781 | return ncpus; | |
782 | } | |
783 | ||
784 | static void __devinit smp_core99_kick_cpu(int nr) | |
785 | { | |
786 | unsigned int save_vector; | |
758438a7 | 787 | unsigned long target, flags; |
35499c01 PM |
788 | volatile unsigned int *vector |
789 | = ((volatile unsigned int *)(KERNELBASE+0x100)); | |
790 | ||
791 | if (nr < 0 || nr > 3) | |
792 | return; | |
758438a7 ME |
793 | |
794 | if (ppc_md.progress) | |
795 | ppc_md.progress("smp_core99_kick_cpu", 0x346); | |
35499c01 PM |
796 | |
797 | local_irq_save(flags); | |
35499c01 PM |
798 | |
799 | /* Save reset vector */ | |
800 | save_vector = *vector; | |
801 | ||
758438a7 | 802 | /* Setup fake reset vector that does |
35499c01 PM |
803 | * b __secondary_start_pmac_0 + nr*8 - KERNELBASE |
804 | */ | |
758438a7 ME |
805 | target = (unsigned long) __secondary_start_pmac_0 + nr * 8; |
806 | create_branch((unsigned long)vector, target, BRANCH_SET_LINK); | |
35499c01 PM |
807 | |
808 | /* Put some life in our friend */ | |
809 | pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); | |
810 | ||
811 | /* FIXME: We wait a bit for the CPU to take the exception, I should | |
812 | * instead wait for the entry code to set something for me. Well, | |
813 | * ideally, all that crap will be done in prom.c and the CPU left | |
814 | * in a RAM-based wait loop like CHRP. | |
815 | */ | |
816 | mdelay(1); | |
817 | ||
818 | /* Restore our exception vector */ | |
819 | *vector = save_vector; | |
820 | flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); | |
821 | ||
822 | local_irq_restore(flags); | |
823 | if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); | |
824 | } | |
825 | ||
826 | static void __devinit smp_core99_setup_cpu(int cpu_nr) | |
827 | { | |
828 | /* Setup L2/L3 */ | |
829 | if (cpu_nr != 0) | |
830 | core99_init_caches(cpu_nr); | |
831 | ||
832 | /* Setup openpic */ | |
833 | mpic_setup_this_cpu(); | |
834 | ||
835 | if (cpu_nr == 0) { | |
1beb6a7d | 836 | #ifdef CONFIG_PPC64 |
35499c01 PM |
837 | extern void g5_phy_disable_cpu1(void); |
838 | ||
1beb6a7d BH |
839 | /* Close i2c bus if it was used for tb sync */ |
840 | if (pmac_tb_clock_chip_host) { | |
730745a5 | 841 | pmac_i2c_close(pmac_tb_clock_chip_host); |
1beb6a7d BH |
842 | pmac_tb_clock_chip_host = NULL; |
843 | } | |
844 | ||
35499c01 PM |
845 | /* If we didn't start the second CPU, we must take |
846 | * it off the bus | |
847 | */ | |
848 | if (machine_is_compatible("MacRISC4") && | |
849 | num_online_cpus() < 2) | |
850 | g5_phy_disable_cpu1(); | |
1beb6a7d BH |
851 | #endif /* CONFIG_PPC64 */ |
852 | ||
853 | if (ppc_md.progress) | |
854 | ppc_md.progress("core99_setup_cpu 0 done", 0x349); | |
35499c01 PM |
855 | } |
856 | } | |
14cf11af | 857 | |
14cf11af | 858 | |
35499c01 | 859 | #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) |
14cf11af | 860 | |
094fe2e7 | 861 | int smp_core99_cpu_disable(void) |
14cf11af PM |
862 | { |
863 | cpu_clear(smp_processor_id(), cpu_online_map); | |
864 | ||
865 | /* XXX reset cpu affinity here */ | |
c0c0d996 | 866 | mpic_cpu_set_priority(0xf); |
14cf11af PM |
867 | asm volatile("mtdec %0" : : "r" (0x7fffffff)); |
868 | mb(); | |
869 | udelay(20); | |
870 | asm volatile("mtdec %0" : : "r" (0x7fffffff)); | |
871 | return 0; | |
872 | } | |
873 | ||
35499c01 | 874 | extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */ |
14cf11af PM |
875 | static int cpu_dead[NR_CPUS]; |
876 | ||
877 | void cpu_die(void) | |
878 | { | |
879 | local_irq_disable(); | |
880 | cpu_dead[smp_processor_id()] = 1; | |
881 | mb(); | |
882 | low_cpu_die(); | |
883 | } | |
884 | ||
094fe2e7 | 885 | void smp_core99_cpu_die(unsigned int cpu) |
14cf11af PM |
886 | { |
887 | int timeout; | |
888 | ||
889 | timeout = 1000; | |
890 | while (!cpu_dead[cpu]) { | |
891 | if (--timeout == 0) { | |
892 | printk("CPU %u refused to die!\n", cpu); | |
893 | break; | |
894 | } | |
895 | msleep(1); | |
896 | } | |
14cf11af PM |
897 | cpu_dead[cpu] = 0; |
898 | } | |
899 | ||
900 | #endif | |
094fe2e7 PM |
901 | |
902 | /* Core99 Macs (dual G4s and G5s) */ | |
903 | struct smp_ops_t core99_smp_ops = { | |
904 | .message_pass = smp_mpic_message_pass, | |
905 | .probe = smp_core99_probe, | |
906 | .kick_cpu = smp_core99_kick_cpu, | |
907 | .setup_cpu = smp_core99_setup_cpu, | |
908 | .give_timebase = smp_core99_give_timebase, | |
909 | .take_timebase = smp_core99_take_timebase, | |
910 | #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) | |
911 | .cpu_disable = smp_core99_cpu_disable, | |
912 | .cpu_die = smp_core99_cpu_die, | |
913 | #endif | |
914 | }; |