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Commit | Line | Data |
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8747f363 GS |
1 | /* |
2 | * The file intends to implement the functions needed by EEH, which is | |
3 | * built on IODA compliant chip. Actually, lots of functions related | |
4 | * to EEH would be built based on the OPAL APIs. | |
5 | * | |
6 | * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/bootmem.h> | |
8998897b | 15 | #include <linux/debugfs.h> |
8747f363 | 16 | #include <linux/delay.h> |
8747f363 GS |
17 | #include <linux/io.h> |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/msi.h> | |
7cb9d93d | 21 | #include <linux/notifier.h> |
8747f363 GS |
22 | #include <linux/pci.h> |
23 | #include <linux/string.h> | |
24 | ||
25 | #include <asm/eeh.h> | |
26 | #include <asm/eeh_event.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/iommu.h> | |
29 | #include <asm/msi_bitmap.h> | |
30 | #include <asm/opal.h> | |
31 | #include <asm/pci-bridge.h> | |
32 | #include <asm/ppc-pci.h> | |
33 | #include <asm/tce.h> | |
34 | ||
35 | #include "powernv.h" | |
36 | #include "pci.h" | |
37 | ||
7cb9d93d GS |
38 | static int ioda_eeh_nb_init = 0; |
39 | ||
40 | static int ioda_eeh_event(struct notifier_block *nb, | |
41 | unsigned long events, void *change) | |
42 | { | |
43 | uint64_t changed_evts = (uint64_t)change; | |
44 | ||
7f52a526 GS |
45 | /* |
46 | * We simply send special EEH event if EEH has | |
47 | * been enabled, or clear pending events in | |
48 | * case that we enable EEH soon | |
49 | */ | |
50 | if (!(changed_evts & OPAL_EVENT_PCI_ERROR) || | |
51 | !(events & OPAL_EVENT_PCI_ERROR)) | |
52 | return 0; | |
53 | ||
54 | if (eeh_enabled()) | |
7cb9d93d | 55 | eeh_send_failure_event(NULL); |
7f52a526 GS |
56 | else |
57 | opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul); | |
7cb9d93d GS |
58 | |
59 | return 0; | |
60 | } | |
61 | ||
62 | static struct notifier_block ioda_eeh_nb = { | |
63 | .notifier_call = ioda_eeh_event, | |
64 | .next = NULL, | |
65 | .priority = 0 | |
66 | }; | |
70f942db | 67 | |
8998897b | 68 | #ifdef CONFIG_DEBUG_FS |
ff6bdcd9 | 69 | static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val) |
8998897b GS |
70 | { |
71 | struct pci_controller *hose = data; | |
72 | struct pnv_phb *phb = hose->private_data; | |
73 | ||
ff6bdcd9 | 74 | out_be64(phb->regs + offset, val); |
8998897b GS |
75 | return 0; |
76 | } | |
77 | ||
ff6bdcd9 | 78 | static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val) |
8998897b GS |
79 | { |
80 | struct pci_controller *hose = data; | |
81 | struct pnv_phb *phb = hose->private_data; | |
82 | ||
ff6bdcd9 | 83 | *val = in_be64(phb->regs + offset); |
8998897b GS |
84 | return 0; |
85 | } | |
86 | ||
ff6bdcd9 GS |
87 | static int ioda_eeh_outb_dbgfs_set(void *data, u64 val) |
88 | { | |
89 | return ioda_eeh_dbgfs_set(data, 0xD10, val); | |
90 | } | |
91 | ||
92 | static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val) | |
93 | { | |
94 | return ioda_eeh_dbgfs_get(data, 0xD10, val); | |
95 | } | |
96 | ||
97 | static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val) | |
98 | { | |
99 | return ioda_eeh_dbgfs_set(data, 0xD90, val); | |
100 | } | |
101 | ||
102 | static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val) | |
103 | { | |
104 | return ioda_eeh_dbgfs_get(data, 0xD90, val); | |
105 | } | |
106 | ||
107 | static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val) | |
108 | { | |
109 | return ioda_eeh_dbgfs_set(data, 0xE10, val); | |
110 | } | |
111 | ||
112 | static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val) | |
113 | { | |
114 | return ioda_eeh_dbgfs_get(data, 0xE10, val); | |
115 | } | |
116 | ||
117 | DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get, | |
118 | ioda_eeh_outb_dbgfs_set, "0x%llx\n"); | |
119 | DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get, | |
120 | ioda_eeh_inbA_dbgfs_set, "0x%llx\n"); | |
121 | DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get, | |
122 | ioda_eeh_inbB_dbgfs_set, "0x%llx\n"); | |
8998897b GS |
123 | #endif /* CONFIG_DEBUG_FS */ |
124 | ||
94716604 | 125 | |
73370c66 GS |
126 | /** |
127 | * ioda_eeh_post_init - Chip dependent post initialization | |
128 | * @hose: PCI controller | |
129 | * | |
130 | * The function will be called after eeh PEs and devices | |
131 | * have been built. That means the EEH is ready to supply | |
132 | * service with I/O cache. | |
133 | */ | |
134 | static int ioda_eeh_post_init(struct pci_controller *hose) | |
135 | { | |
136 | struct pnv_phb *phb = hose->private_data; | |
7cb9d93d GS |
137 | int ret; |
138 | ||
139 | /* Register OPAL event notifier */ | |
140 | if (!ioda_eeh_nb_init) { | |
141 | ret = opal_notifier_register(&ioda_eeh_nb); | |
142 | if (ret) { | |
143 | pr_err("%s: Can't register OPAL event notifier (%d)\n", | |
144 | __func__, ret); | |
145 | return ret; | |
146 | } | |
147 | ||
148 | ioda_eeh_nb_init = 1; | |
149 | } | |
73370c66 | 150 | |
8998897b | 151 | #ifdef CONFIG_DEBUG_FS |
7f52a526 GS |
152 | if (!phb->has_dbgfs && phb->dbgfs) { |
153 | phb->has_dbgfs = 1; | |
154 | ||
ff6bdcd9 GS |
155 | debugfs_create_file("err_injct_outbound", 0600, |
156 | phb->dbgfs, hose, | |
157 | &ioda_eeh_outb_dbgfs_ops); | |
158 | debugfs_create_file("err_injct_inboundA", 0600, | |
20bb842b | 159 | phb->dbgfs, hose, |
ff6bdcd9 GS |
160 | &ioda_eeh_inbA_dbgfs_ops); |
161 | debugfs_create_file("err_injct_inboundB", 0600, | |
162 | phb->dbgfs, hose, | |
163 | &ioda_eeh_inbB_dbgfs_ops); | |
164 | } | |
8998897b GS |
165 | #endif |
166 | ||
7f52a526 GS |
167 | /* If EEH is enabled, we're going to rely on that. |
168 | * Otherwise, we restore to conventional mechanism | |
169 | * to clear frozen PE during PCI config access. | |
170 | */ | |
171 | if (eeh_enabled()) | |
172 | phb->flags |= PNV_PHB_FLAG_EEH; | |
173 | else | |
174 | phb->flags &= ~PNV_PHB_FLAG_EEH; | |
73370c66 GS |
175 | |
176 | return 0; | |
177 | } | |
178 | ||
eb005983 GS |
179 | /** |
180 | * ioda_eeh_set_option - Set EEH operation or I/O setting | |
181 | * @pe: EEH PE | |
182 | * @option: options | |
183 | * | |
184 | * Enable or disable EEH option for the indicated PE. The | |
185 | * function also can be used to enable I/O or DMA for the | |
186 | * PE. | |
187 | */ | |
188 | static int ioda_eeh_set_option(struct eeh_pe *pe, int option) | |
189 | { | |
eb005983 GS |
190 | struct pci_controller *hose = pe->phb; |
191 | struct pnv_phb *phb = hose->private_data; | |
0d5ee520 | 192 | bool freeze_pe = false; |
58287909 GS |
193 | int enable, ret = 0; |
194 | s64 rc; | |
eb005983 GS |
195 | |
196 | /* Check on PE number */ | |
197 | if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) { | |
198 | pr_err("%s: PE address %x out of range [0, %x] " | |
199 | "on PHB#%x\n", | |
200 | __func__, pe->addr, phb->ioda.total_pe, | |
201 | hose->global_number); | |
202 | return -EINVAL; | |
203 | } | |
204 | ||
eb005983 GS |
205 | switch (option) { |
206 | case EEH_OPT_DISABLE: | |
58287909 | 207 | return -EPERM; |
eb005983 | 208 | case EEH_OPT_ENABLE: |
58287909 | 209 | return 0; |
eb005983 | 210 | case EEH_OPT_THAW_MMIO: |
58287909 | 211 | enable = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; |
eb005983 GS |
212 | break; |
213 | case EEH_OPT_THAW_DMA: | |
58287909 | 214 | enable = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; |
eb005983 | 215 | break; |
0d5ee520 GS |
216 | case EEH_OPT_FREEZE_PE: |
217 | freeze_pe = true; | |
218 | enable = OPAL_EEH_ACTION_SET_FREEZE_ALL; | |
219 | break; | |
eb005983 | 220 | default: |
58287909 GS |
221 | pr_warn("%s: Invalid option %d\n", |
222 | __func__, option); | |
eb005983 GS |
223 | return -EINVAL; |
224 | } | |
225 | ||
58287909 | 226 | /* If PHB supports compound PE, to handle it */ |
0d5ee520 GS |
227 | if (freeze_pe) { |
228 | if (phb->freeze_pe) { | |
229 | phb->freeze_pe(phb, pe->addr); | |
230 | } else { | |
231 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
232 | pe->addr, | |
233 | enable); | |
234 | if (rc != OPAL_SUCCESS) { | |
235 | pr_warn("%s: Failure %lld freezing " | |
236 | "PHB#%x-PE#%x\n", | |
237 | __func__, rc, | |
238 | phb->hose->global_number, pe->addr); | |
239 | ret = -EIO; | |
240 | } | |
241 | } | |
58287909 | 242 | } else { |
0d5ee520 GS |
243 | if (phb->unfreeze_pe) { |
244 | ret = phb->unfreeze_pe(phb, pe->addr, enable); | |
245 | } else { | |
246 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
247 | pe->addr, | |
248 | enable); | |
249 | if (rc != OPAL_SUCCESS) { | |
250 | pr_warn("%s: Failure %lld enable %d " | |
251 | "for PHB#%x-PE#%x\n", | |
252 | __func__, rc, option, | |
253 | phb->hose->global_number, pe->addr); | |
254 | ret = -EIO; | |
255 | } | |
58287909 GS |
256 | } |
257 | } | |
258 | ||
eb005983 GS |
259 | return ret; |
260 | } | |
261 | ||
bb593c00 | 262 | static void ioda_eeh_phb_diag(struct eeh_pe *pe) |
94716604 | 263 | { |
bb593c00 | 264 | struct pnv_phb *phb = pe->phb->private_data; |
94716604 GS |
265 | long rc; |
266 | ||
bb593c00 | 267 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, |
94716604 | 268 | PNV_PCI_DIAG_BUF_SIZE); |
bb593c00 | 269 | if (rc != OPAL_SUCCESS) |
0dae2743 | 270 | pr_warn("%s: Failed to get diag-data for PHB#%x (%ld)\n", |
bb593c00 | 271 | __func__, pe->phb->global_number, rc); |
94716604 GS |
272 | } |
273 | ||
c979c70e | 274 | static int ioda_eeh_get_phb_state(struct eeh_pe *pe) |
8c41a7f3 | 275 | { |
c979c70e | 276 | struct pnv_phb *phb = pe->phb->private_data; |
8c41a7f3 | 277 | u8 fstate; |
ddf0322a | 278 | __be16 pcierr; |
c979c70e GS |
279 | s64 rc; |
280 | int result = 0; | |
281 | ||
282 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
283 | pe->addr, | |
284 | &fstate, | |
285 | &pcierr, | |
286 | NULL); | |
287 | if (rc != OPAL_SUCCESS) { | |
288 | pr_warn("%s: Failure %lld getting PHB#%x state\n", | |
289 | __func__, rc, phb->hose->global_number); | |
290 | return EEH_STATE_NOT_SUPPORT; | |
291 | } | |
8c41a7f3 GS |
292 | |
293 | /* | |
c979c70e GS |
294 | * Check PHB state. If the PHB is frozen for the |
295 | * first time, to dump the PHB diag-data. | |
8c41a7f3 | 296 | */ |
c979c70e GS |
297 | if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { |
298 | result = (EEH_STATE_MMIO_ACTIVE | | |
299 | EEH_STATE_DMA_ACTIVE | | |
300 | EEH_STATE_MMIO_ENABLED | | |
301 | EEH_STATE_DMA_ENABLED); | |
302 | } else if (!(pe->state & EEH_PE_ISOLATED)) { | |
303 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); | |
304 | ioda_eeh_phb_diag(pe); | |
8c41a7f3 GS |
305 | } |
306 | ||
c979c70e GS |
307 | return result; |
308 | } | |
309 | ||
310 | static int ioda_eeh_get_pe_state(struct eeh_pe *pe) | |
311 | { | |
312 | struct pnv_phb *phb = pe->phb->private_data; | |
313 | u8 fstate; | |
314 | __be16 pcierr; | |
315 | s64 rc; | |
316 | int result; | |
317 | ||
78954700 | 318 | /* |
c979c70e GS |
319 | * We don't clobber hardware frozen state until PE |
320 | * reset is completed. In order to keep EEH core | |
321 | * moving forward, we have to return operational | |
322 | * state during PE reset. | |
78954700 | 323 | */ |
c979c70e GS |
324 | if (pe->state & EEH_PE_RESET) { |
325 | result = (EEH_STATE_MMIO_ACTIVE | | |
326 | EEH_STATE_DMA_ACTIVE | | |
78954700 GS |
327 | EEH_STATE_MMIO_ENABLED | |
328 | EEH_STATE_DMA_ENABLED); | |
329 | return result; | |
330 | } | |
331 | ||
58287909 GS |
332 | /* |
333 | * Fetch PE state from hardware. If the PHB | |
334 | * supports compound PE, let it handle that. | |
335 | */ | |
336 | if (phb->get_pe_state) { | |
337 | fstate = phb->get_pe_state(phb, pe->addr); | |
338 | } else { | |
339 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
340 | pe->addr, | |
341 | &fstate, | |
342 | &pcierr, | |
343 | NULL); | |
344 | if (rc != OPAL_SUCCESS) { | |
345 | pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", | |
346 | __func__, rc, phb->hose->global_number, pe->addr); | |
347 | return EEH_STATE_NOT_SUPPORT; | |
348 | } | |
8c41a7f3 GS |
349 | } |
350 | ||
c979c70e | 351 | /* Figure out state */ |
8c41a7f3 GS |
352 | switch (fstate) { |
353 | case OPAL_EEH_STOPPED_NOT_FROZEN: | |
c979c70e GS |
354 | result = (EEH_STATE_MMIO_ACTIVE | |
355 | EEH_STATE_DMA_ACTIVE | | |
356 | EEH_STATE_MMIO_ENABLED | | |
357 | EEH_STATE_DMA_ENABLED); | |
8c41a7f3 GS |
358 | break; |
359 | case OPAL_EEH_STOPPED_MMIO_FREEZE: | |
c979c70e GS |
360 | result = (EEH_STATE_DMA_ACTIVE | |
361 | EEH_STATE_DMA_ENABLED); | |
8c41a7f3 GS |
362 | break; |
363 | case OPAL_EEH_STOPPED_DMA_FREEZE: | |
c979c70e GS |
364 | result = (EEH_STATE_MMIO_ACTIVE | |
365 | EEH_STATE_MMIO_ENABLED); | |
8c41a7f3 GS |
366 | break; |
367 | case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: | |
c979c70e | 368 | result = 0; |
8c41a7f3 GS |
369 | break; |
370 | case OPAL_EEH_STOPPED_RESET: | |
c979c70e | 371 | result = EEH_STATE_RESET_ACTIVE; |
8c41a7f3 GS |
372 | break; |
373 | case OPAL_EEH_STOPPED_TEMP_UNAVAIL: | |
c979c70e | 374 | result = EEH_STATE_UNAVAILABLE; |
8c41a7f3 GS |
375 | break; |
376 | case OPAL_EEH_STOPPED_PERM_UNAVAIL: | |
c979c70e | 377 | result = EEH_STATE_NOT_SUPPORT; |
8c41a7f3 GS |
378 | break; |
379 | default: | |
c979c70e GS |
380 | result = EEH_STATE_NOT_SUPPORT; |
381 | pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", | |
382 | __func__, phb->hose->global_number, | |
383 | pe->addr, fstate); | |
8c41a7f3 GS |
384 | } |
385 | ||
c979c70e | 386 | /* |
58287909 GS |
387 | * If PHB supports compound PE, to freeze all |
388 | * slave PEs for consistency. | |
389 | * | |
c979c70e GS |
390 | * If the PE is switching to frozen state for the |
391 | * first time, to dump the PHB diag-data. | |
392 | */ | |
393 | if (!(result & EEH_STATE_NOT_SUPPORT) && | |
394 | !(result & EEH_STATE_UNAVAILABLE) && | |
395 | !(result & EEH_STATE_MMIO_ACTIVE) && | |
396 | !(result & EEH_STATE_DMA_ACTIVE) && | |
94716604 | 397 | !(pe->state & EEH_PE_ISOLATED)) { |
58287909 GS |
398 | if (phb->freeze_pe) |
399 | phb->freeze_pe(phb, pe->addr); | |
400 | ||
94716604 | 401 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
bb593c00 | 402 | ioda_eeh_phb_diag(pe); |
94716604 GS |
403 | } |
404 | ||
8c41a7f3 GS |
405 | return result; |
406 | } | |
407 | ||
c979c70e GS |
408 | /** |
409 | * ioda_eeh_get_state - Retrieve the state of PE | |
410 | * @pe: EEH PE | |
411 | * | |
412 | * The PE's state should be retrieved from the PEEV, PEST | |
413 | * IODA tables. Since the OPAL has exported the function | |
414 | * to do it, it'd better to use that. | |
415 | */ | |
416 | static int ioda_eeh_get_state(struct eeh_pe *pe) | |
417 | { | |
418 | struct pnv_phb *phb = pe->phb->private_data; | |
419 | ||
420 | /* Sanity check on PE number. PHB PE should have 0 */ | |
421 | if (pe->addr < 0 || | |
422 | pe->addr >= phb->ioda.total_pe) { | |
423 | pr_warn("%s: PHB#%x-PE#%x out of range [0, %x]\n", | |
424 | __func__, phb->hose->global_number, | |
425 | pe->addr, phb->ioda.total_pe); | |
426 | return EEH_STATE_NOT_SUPPORT; | |
427 | } | |
428 | ||
429 | if (pe->type & EEH_PE_PHB) | |
430 | return ioda_eeh_get_phb_state(pe); | |
431 | ||
432 | return ioda_eeh_get_pe_state(pe); | |
433 | } | |
434 | ||
9d5cab00 GS |
435 | static s64 ioda_eeh_phb_poll(struct pnv_phb *phb) |
436 | { | |
437 | s64 rc = OPAL_HARDWARE; | |
438 | ||
439 | while (1) { | |
440 | rc = opal_pci_poll(phb->opal_id); | |
441 | if (rc <= 0) | |
442 | break; | |
443 | ||
361f2a2a GS |
444 | if (system_state < SYSTEM_RUNNING) |
445 | udelay(1000 * rc); | |
446 | else | |
447 | msleep(rc); | |
9d5cab00 GS |
448 | } |
449 | ||
450 | return rc; | |
451 | } | |
452 | ||
361f2a2a | 453 | int ioda_eeh_phb_reset(struct pci_controller *hose, int option) |
9d5cab00 GS |
454 | { |
455 | struct pnv_phb *phb = hose->private_data; | |
456 | s64 rc = OPAL_HARDWARE; | |
457 | ||
458 | pr_debug("%s: Reset PHB#%x, option=%d\n", | |
459 | __func__, hose->global_number, option); | |
460 | ||
461 | /* Issue PHB complete reset request */ | |
462 | if (option == EEH_RESET_FUNDAMENTAL || | |
463 | option == EEH_RESET_HOT) | |
464 | rc = opal_pci_reset(phb->opal_id, | |
465 | OPAL_PHB_COMPLETE, | |
466 | OPAL_ASSERT_RESET); | |
467 | else if (option == EEH_RESET_DEACTIVATE) | |
468 | rc = opal_pci_reset(phb->opal_id, | |
469 | OPAL_PHB_COMPLETE, | |
470 | OPAL_DEASSERT_RESET); | |
471 | if (rc < 0) | |
472 | goto out; | |
473 | ||
474 | /* | |
475 | * Poll state of the PHB until the request is done | |
26833a50 GS |
476 | * successfully. The PHB reset is usually PHB complete |
477 | * reset followed by hot reset on root bus. So we also | |
478 | * need the PCI bus settlement delay. | |
9d5cab00 GS |
479 | */ |
480 | rc = ioda_eeh_phb_poll(phb); | |
361f2a2a GS |
481 | if (option == EEH_RESET_DEACTIVATE) { |
482 | if (system_state < SYSTEM_RUNNING) | |
483 | udelay(1000 * EEH_PE_RST_SETTLE_TIME); | |
484 | else | |
485 | msleep(EEH_PE_RST_SETTLE_TIME); | |
486 | } | |
9d5cab00 GS |
487 | out: |
488 | if (rc != OPAL_SUCCESS) | |
489 | return -EIO; | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | static int ioda_eeh_root_reset(struct pci_controller *hose, int option) | |
495 | { | |
496 | struct pnv_phb *phb = hose->private_data; | |
497 | s64 rc = OPAL_SUCCESS; | |
498 | ||
499 | pr_debug("%s: Reset PHB#%x, option=%d\n", | |
500 | __func__, hose->global_number, option); | |
501 | ||
502 | /* | |
503 | * During the reset deassert time, we needn't care | |
504 | * the reset scope because the firmware does nothing | |
505 | * for fundamental or hot reset during deassert phase. | |
506 | */ | |
507 | if (option == EEH_RESET_FUNDAMENTAL) | |
508 | rc = opal_pci_reset(phb->opal_id, | |
509 | OPAL_PCI_FUNDAMENTAL_RESET, | |
510 | OPAL_ASSERT_RESET); | |
511 | else if (option == EEH_RESET_HOT) | |
512 | rc = opal_pci_reset(phb->opal_id, | |
513 | OPAL_PCI_HOT_RESET, | |
514 | OPAL_ASSERT_RESET); | |
515 | else if (option == EEH_RESET_DEACTIVATE) | |
516 | rc = opal_pci_reset(phb->opal_id, | |
517 | OPAL_PCI_HOT_RESET, | |
518 | OPAL_DEASSERT_RESET); | |
519 | if (rc < 0) | |
520 | goto out; | |
521 | ||
522 | /* Poll state of the PHB until the request is done */ | |
523 | rc = ioda_eeh_phb_poll(phb); | |
26833a50 GS |
524 | if (option == EEH_RESET_DEACTIVATE) |
525 | msleep(EEH_PE_RST_SETTLE_TIME); | |
9d5cab00 GS |
526 | out: |
527 | if (rc != OPAL_SUCCESS) | |
528 | return -EIO; | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
1d9a5446 GS |
533 | static int ioda_eeh_bridge_reset(struct pci_dev *dev, int option) |
534 | ||
9d5cab00 | 535 | { |
1d9a5446 | 536 | struct device_node *dn = pci_device_to_OF_node(dev); |
d92a208d GS |
537 | struct eeh_dev *edev = of_node_to_eeh_dev(dn); |
538 | int aer = edev ? edev->aer_cap : 0; | |
965b5608 | 539 | u32 ctrl; |
9d5cab00 | 540 | |
1d9a5446 GS |
541 | pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", |
542 | __func__, pci_domain_nr(dev->bus), | |
543 | dev->bus->number, option); | |
9d5cab00 GS |
544 | |
545 | switch (option) { | |
546 | case EEH_RESET_FUNDAMENTAL: | |
547 | case EEH_RESET_HOT: | |
965b5608 | 548 | /* Don't report linkDown event */ |
d92a208d GS |
549 | if (aer) { |
550 | eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK, | |
965b5608 BH |
551 | 4, &ctrl); |
552 | ctrl |= PCI_ERR_UNC_SURPDN; | |
d92a208d | 553 | eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK, |
965b5608 BH |
554 | 4, ctrl); |
555 | } | |
d92a208d | 556 | |
965b5608 BH |
557 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl); |
558 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
559 | eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl); | |
26833a50 | 560 | msleep(EEH_PE_RST_HOLD_TIME); |
d92a208d | 561 | |
9d5cab00 GS |
562 | break; |
563 | case EEH_RESET_DEACTIVATE: | |
965b5608 BH |
564 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl); |
565 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
566 | eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl); | |
26833a50 | 567 | msleep(EEH_PE_RST_SETTLE_TIME); |
d92a208d | 568 | |
965b5608 | 569 | /* Continue reporting linkDown event */ |
d92a208d GS |
570 | if (aer) { |
571 | eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK, | |
965b5608 BH |
572 | 4, &ctrl); |
573 | ctrl &= ~PCI_ERR_UNC_SURPDN; | |
d92a208d | 574 | eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK, |
965b5608 | 575 | 4, ctrl); |
d92a208d GS |
576 | } |
577 | ||
9d5cab00 GS |
578 | break; |
579 | } | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
d92a208d GS |
584 | void pnv_pci_reset_secondary_bus(struct pci_dev *dev) |
585 | { | |
586 | struct pci_controller *hose; | |
587 | ||
588 | if (pci_is_root_bus(dev->bus)) { | |
589 | hose = pci_bus_to_host(dev->bus); | |
590 | ioda_eeh_root_reset(hose, EEH_RESET_HOT); | |
591 | ioda_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); | |
592 | } else { | |
593 | ioda_eeh_bridge_reset(dev, EEH_RESET_HOT); | |
594 | ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); | |
595 | } | |
596 | } | |
597 | ||
9d5cab00 GS |
598 | /** |
599 | * ioda_eeh_reset - Reset the indicated PE | |
600 | * @pe: EEH PE | |
601 | * @option: reset option | |
602 | * | |
603 | * Do reset on the indicated PE. For PCI bus sensitive PE, | |
604 | * we need to reset the parent p2p bridge. The PHB has to | |
605 | * be reinitialized if the p2p bridge is root bridge. For | |
606 | * PCI device sensitive PE, we will try to reset the device | |
607 | * through FLR. For now, we don't have OPAL APIs to do HARD | |
608 | * reset yet, so all reset would be SOFT (HOT) reset. | |
609 | */ | |
610 | static int ioda_eeh_reset(struct eeh_pe *pe, int option) | |
611 | { | |
612 | struct pci_controller *hose = pe->phb; | |
5b2e198e | 613 | struct pci_bus *bus; |
9d5cab00 GS |
614 | int ret; |
615 | ||
9d5cab00 | 616 | /* |
fd5cee7c GS |
617 | * For PHB reset, we always have complete reset. For those PEs whose |
618 | * primary bus derived from root complex (root bus) or root port | |
619 | * (usually bus#1), we apply hot or fundamental reset on the root port. | |
620 | * For other PEs, we always have hot reset on the PE primary bus. | |
78954700 GS |
621 | * |
622 | * Here, we have different design to pHyp, which always clear the | |
623 | * frozen state during PE reset. However, the good idea here from | |
624 | * benh is to keep frozen state before we get PE reset done completely | |
625 | * (until BAR restore). With the frozen state, HW drops illegal IO | |
626 | * or MMIO access, which can incur recrusive frozen PE during PE | |
627 | * reset. The side effect is that EEH core has to clear the frozen | |
628 | * state explicitly after BAR restore. | |
9d5cab00 GS |
629 | */ |
630 | if (pe->type & EEH_PE_PHB) { | |
631 | ret = ioda_eeh_phb_reset(hose, option); | |
632 | } else { | |
5b2e198e | 633 | bus = eeh_pe_bus_get(pe); |
fd5cee7c GS |
634 | if (pci_is_root_bus(bus) || |
635 | pci_is_root_bus(bus->parent)) | |
9d5cab00 GS |
636 | ret = ioda_eeh_root_reset(hose, option); |
637 | else | |
1d9a5446 | 638 | ret = ioda_eeh_bridge_reset(bus->self, option); |
9d5cab00 GS |
639 | } |
640 | ||
641 | return ret; | |
642 | } | |
643 | ||
bb593c00 GS |
644 | /** |
645 | * ioda_eeh_get_log - Retrieve error log | |
646 | * @pe: frozen PE | |
647 | * @severity: permanent or temporary error | |
648 | * @drv_log: device driver log | |
649 | * @len: length of device driver log | |
650 | * | |
651 | * Retrieve error log, which contains log from device driver | |
652 | * and firmware. | |
653 | */ | |
e51df2c1 AB |
654 | static int ioda_eeh_get_log(struct eeh_pe *pe, int severity, |
655 | char *drv_log, unsigned long len) | |
bb593c00 GS |
656 | { |
657 | pnv_pci_dump_phb_diag_data(pe->phb, pe->data); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
bf90dfea GS |
662 | /** |
663 | * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE | |
664 | * @pe: EEH PE | |
665 | * | |
666 | * For particular PE, it might have included PCI bridges. In order | |
667 | * to make the PE work properly, those PCI bridges should be configured | |
668 | * correctly. However, we need do nothing on P7IOC since the reset | |
669 | * function will do everything that should be covered by the function. | |
670 | */ | |
671 | static int ioda_eeh_configure_bridge(struct eeh_pe *pe) | |
672 | { | |
673 | return 0; | |
674 | } | |
675 | ||
131c123a GS |
676 | static int ioda_eeh_err_inject(struct eeh_pe *pe, int type, int func, |
677 | unsigned long addr, unsigned long mask) | |
678 | { | |
679 | struct pci_controller *hose = pe->phb; | |
680 | struct pnv_phb *phb = hose->private_data; | |
681 | s64 ret; | |
682 | ||
683 | /* Sanity check on error type */ | |
684 | if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && | |
685 | type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { | |
686 | pr_warn("%s: Invalid error type %d\n", | |
687 | __func__, type); | |
688 | return -ERANGE; | |
689 | } | |
690 | ||
691 | if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || | |
692 | func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { | |
693 | pr_warn("%s: Invalid error function %d\n", | |
694 | __func__, func); | |
695 | return -ERANGE; | |
696 | } | |
697 | ||
698 | /* Firmware supports error injection ? */ | |
699 | if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { | |
700 | pr_warn("%s: Firmware doesn't support error injection\n", | |
701 | __func__); | |
702 | return -ENXIO; | |
703 | } | |
704 | ||
705 | /* Do error injection */ | |
706 | ret = opal_pci_err_inject(phb->opal_id, pe->addr, | |
707 | type, func, addr, mask); | |
708 | if (ret != OPAL_SUCCESS) { | |
709 | pr_warn("%s: Failure %lld injecting error " | |
710 | "%d-%d to PHB#%x-PE#%x\n", | |
711 | __func__, ret, type, func, | |
712 | hose->global_number, pe->addr); | |
713 | return -EIO; | |
714 | } | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
70f942db GS |
719 | static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data) |
720 | { | |
721 | /* GEM */ | |
f18440fb GS |
722 | if (data->gemXfir || data->gemRfir || |
723 | data->gemRirqfir || data->gemMask || data->gemRwof) | |
724 | pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", | |
725 | be64_to_cpu(data->gemXfir), | |
726 | be64_to_cpu(data->gemRfir), | |
727 | be64_to_cpu(data->gemRirqfir), | |
728 | be64_to_cpu(data->gemMask), | |
729 | be64_to_cpu(data->gemRwof)); | |
70f942db GS |
730 | |
731 | /* LEM */ | |
f18440fb GS |
732 | if (data->lemFir || data->lemErrMask || |
733 | data->lemAction0 || data->lemAction1 || data->lemWof) | |
734 | pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", | |
735 | be64_to_cpu(data->lemFir), | |
736 | be64_to_cpu(data->lemErrMask), | |
737 | be64_to_cpu(data->lemAction0), | |
738 | be64_to_cpu(data->lemAction1), | |
739 | be64_to_cpu(data->lemWof)); | |
70f942db GS |
740 | } |
741 | ||
742 | static void ioda_eeh_hub_diag(struct pci_controller *hose) | |
743 | { | |
744 | struct pnv_phb *phb = hose->private_data; | |
ca1de5de | 745 | struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; |
70f942db GS |
746 | long rc; |
747 | ||
ca1de5de | 748 | rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); |
70f942db | 749 | if (rc != OPAL_SUCCESS) { |
0dae2743 GS |
750 | pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", |
751 | __func__, phb->hub_id, rc); | |
70f942db GS |
752 | return; |
753 | } | |
754 | ||
755 | switch (data->type) { | |
756 | case OPAL_P7IOC_DIAG_TYPE_RGC: | |
757 | pr_info("P7IOC diag-data for RGC\n\n"); | |
758 | ioda_eeh_hub_diag_common(data); | |
f18440fb GS |
759 | if (data->rgc.rgcStatus || data->rgc.rgcLdcp) |
760 | pr_info(" RGC: %016llx %016llx\n", | |
761 | be64_to_cpu(data->rgc.rgcStatus), | |
762 | be64_to_cpu(data->rgc.rgcLdcp)); | |
70f942db GS |
763 | break; |
764 | case OPAL_P7IOC_DIAG_TYPE_BI: | |
765 | pr_info("P7IOC diag-data for BI %s\n\n", | |
766 | data->bi.biDownbound ? "Downbound" : "Upbound"); | |
767 | ioda_eeh_hub_diag_common(data); | |
f18440fb GS |
768 | if (data->bi.biLdcp0 || data->bi.biLdcp1 || |
769 | data->bi.biLdcp2 || data->bi.biFenceStatus) | |
770 | pr_info(" BI: %016llx %016llx %016llx %016llx\n", | |
771 | be64_to_cpu(data->bi.biLdcp0), | |
772 | be64_to_cpu(data->bi.biLdcp1), | |
773 | be64_to_cpu(data->bi.biLdcp2), | |
774 | be64_to_cpu(data->bi.biFenceStatus)); | |
70f942db GS |
775 | break; |
776 | case OPAL_P7IOC_DIAG_TYPE_CI: | |
f18440fb | 777 | pr_info("P7IOC diag-data for CI Port %d\n\n", |
70f942db GS |
778 | data->ci.ciPort); |
779 | ioda_eeh_hub_diag_common(data); | |
f18440fb GS |
780 | if (data->ci.ciPortStatus || data->ci.ciPortLdcp) |
781 | pr_info(" CI: %016llx %016llx\n", | |
782 | be64_to_cpu(data->ci.ciPortStatus), | |
783 | be64_to_cpu(data->ci.ciPortLdcp)); | |
70f942db GS |
784 | break; |
785 | case OPAL_P7IOC_DIAG_TYPE_MISC: | |
786 | pr_info("P7IOC diag-data for MISC\n\n"); | |
787 | ioda_eeh_hub_diag_common(data); | |
788 | break; | |
789 | case OPAL_P7IOC_DIAG_TYPE_I2C: | |
790 | pr_info("P7IOC diag-data for I2C\n\n"); | |
791 | ioda_eeh_hub_diag_common(data); | |
792 | break; | |
793 | default: | |
0dae2743 GS |
794 | pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", |
795 | __func__, phb->hub_id, data->type); | |
70f942db GS |
796 | } |
797 | } | |
798 | ||
70f942db GS |
799 | static int ioda_eeh_get_pe(struct pci_controller *hose, |
800 | u16 pe_no, struct eeh_pe **pe) | |
801 | { | |
58287909 GS |
802 | struct pnv_phb *phb = hose->private_data; |
803 | struct pnv_ioda_pe *pnv_pe; | |
804 | struct eeh_pe *dev_pe; | |
805 | struct eeh_dev edev; | |
70f942db | 806 | |
58287909 GS |
807 | /* |
808 | * If PHB supports compound PE, to fetch | |
809 | * the master PE because slave PE is invisible | |
810 | * to EEH core. | |
811 | */ | |
812 | if (phb->get_pe_state) { | |
813 | pnv_pe = &phb->ioda.pe_array[pe_no]; | |
814 | if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { | |
815 | pnv_pe = pnv_pe->master; | |
816 | WARN_ON(!pnv_pe || | |
817 | !(pnv_pe->flags & PNV_IODA_PE_MASTER)); | |
818 | pe_no = pnv_pe->pe_number; | |
819 | } | |
820 | } | |
70f942db GS |
821 | |
822 | /* Find the PE according to PE# */ | |
58287909 GS |
823 | memset(&edev, 0, sizeof(struct eeh_dev)); |
824 | edev.phb = hose; | |
825 | edev.pe_config_addr = pe_no; | |
826 | dev_pe = eeh_pe_get(&edev); | |
827 | if (!dev_pe) | |
828 | return -EEXIST; | |
70f942db | 829 | |
58287909 GS |
830 | /* |
831 | * At this point, we're sure the compound PE should | |
832 | * be put into frozen state. | |
833 | */ | |
70f942db | 834 | *pe = dev_pe; |
58287909 GS |
835 | if (phb->freeze_pe && |
836 | !(dev_pe->state & EEH_PE_ISOLATED)) | |
837 | phb->freeze_pe(phb, pe_no); | |
838 | ||
70f942db GS |
839 | return 0; |
840 | } | |
841 | ||
842 | /** | |
843 | * ioda_eeh_next_error - Retrieve next error for EEH core to handle | |
844 | * @pe: The affected PE | |
845 | * | |
846 | * The function is expected to be called by EEH core while it gets | |
847 | * special EEH event (without binding PE). The function calls to | |
848 | * OPAL APIs for next error to handle. The informational error is | |
849 | * handled internally by platform. However, the dead IOC, dead PHB, | |
850 | * fenced PHB and frozen PE should be handled by EEH core eventually. | |
851 | */ | |
852 | static int ioda_eeh_next_error(struct eeh_pe **pe) | |
853 | { | |
7e4e7867 | 854 | struct pci_controller *hose; |
70f942db | 855 | struct pnv_phb *phb; |
1ad7a72c | 856 | struct eeh_pe *phb_pe, *parent_pe; |
ddf0322a GC |
857 | __be64 frozen_pe_no; |
858 | __be16 err_type, severity; | |
1ad7a72c | 859 | int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
70f942db | 860 | long rc; |
1ad7a72c | 861 | int state, ret = EEH_NEXT_ERR_NONE; |
70f942db | 862 | |
7cb9d93d GS |
863 | /* |
864 | * While running here, it's safe to purge the event queue. | |
865 | * And we should keep the cached OPAL notifier event sychronized | |
866 | * between the kernel and firmware. | |
867 | */ | |
5c7a35e3 | 868 | eeh_remove_event(NULL, false); |
7cb9d93d | 869 | opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul); |
70f942db | 870 | |
7e4e7867 | 871 | list_for_each_entry(hose, &hose_list, list_node) { |
70f942db GS |
872 | /* |
873 | * If the subordinate PCI buses of the PHB has been | |
467f79a9 GS |
874 | * removed or is exactly under error recovery, we |
875 | * needn't take care of it any more. | |
70f942db GS |
876 | */ |
877 | phb = hose->private_data; | |
467f79a9 GS |
878 | phb_pe = eeh_phb_pe_get(hose); |
879 | if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) | |
70f942db GS |
880 | continue; |
881 | ||
882 | rc = opal_pci_next_error(phb->opal_id, | |
883 | &frozen_pe_no, &err_type, &severity); | |
884 | ||
885 | /* If OPAL API returns error, we needn't proceed */ | |
886 | if (rc != OPAL_SUCCESS) { | |
20212703 MQ |
887 | pr_devel("%s: Invalid return value on " |
888 | "PHB#%x (0x%lx) from opal_pci_next_error", | |
889 | __func__, hose->global_number, rc); | |
70f942db GS |
890 | continue; |
891 | } | |
892 | ||
893 | /* If the PHB doesn't have error, stop processing */ | |
ddf0322a GC |
894 | if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || |
895 | be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { | |
20212703 MQ |
896 | pr_devel("%s: No error found on PHB#%x\n", |
897 | __func__, hose->global_number); | |
70f942db GS |
898 | continue; |
899 | } | |
900 | ||
901 | /* | |
902 | * Processing the error. We're expecting the error with | |
903 | * highest priority reported upon multiple errors on the | |
904 | * specific PHB. | |
905 | */ | |
20212703 | 906 | pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", |
ddf0322a GC |
907 | __func__, be16_to_cpu(err_type), be16_to_cpu(severity), |
908 | be64_to_cpu(frozen_pe_no), hose->global_number); | |
909 | switch (be16_to_cpu(err_type)) { | |
70f942db | 910 | case OPAL_EEH_IOC_ERROR: |
ddf0322a | 911 | if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { |
56ca4fde | 912 | pr_err("EEH: dead IOC detected\n"); |
7e4e7867 | 913 | ret = EEH_NEXT_ERR_DEAD_IOC; |
ddf0322a | 914 | } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { |
56ca4fde GS |
915 | pr_info("EEH: IOC informative error " |
916 | "detected\n"); | |
70f942db | 917 | ioda_eeh_hub_diag(hose); |
7e4e7867 | 918 | ret = EEH_NEXT_ERR_NONE; |
56ca4fde | 919 | } |
70f942db GS |
920 | |
921 | break; | |
922 | case OPAL_EEH_PHB_ERROR: | |
ddf0322a | 923 | if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { |
467f79a9 | 924 | *pe = phb_pe; |
357b2f3d GS |
925 | pr_err("EEH: dead PHB#%x detected, " |
926 | "location: %s\n", | |
927 | hose->global_number, | |
928 | eeh_pe_loc_get(phb_pe)); | |
7e4e7867 | 929 | ret = EEH_NEXT_ERR_DEAD_PHB; |
ddf0322a GC |
930 | } else if (be16_to_cpu(severity) == |
931 | OPAL_EEH_SEV_PHB_FENCED) { | |
467f79a9 | 932 | *pe = phb_pe; |
357b2f3d GS |
933 | pr_err("EEH: Fenced PHB#%x detected, " |
934 | "location: %s\n", | |
935 | hose->global_number, | |
936 | eeh_pe_loc_get(phb_pe)); | |
7e4e7867 | 937 | ret = EEH_NEXT_ERR_FENCED_PHB; |
ddf0322a | 938 | } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { |
56ca4fde | 939 | pr_info("EEH: PHB#%x informative error " |
357b2f3d GS |
940 | "detected, location: %s\n", |
941 | hose->global_number, | |
942 | eeh_pe_loc_get(phb_pe)); | |
bb593c00 GS |
943 | ioda_eeh_phb_diag(phb_pe); |
944 | pnv_pci_dump_phb_diag_data(hose, phb_pe->data); | |
7e4e7867 | 945 | ret = EEH_NEXT_ERR_NONE; |
56ca4fde | 946 | } |
70f942db GS |
947 | |
948 | break; | |
949 | case OPAL_EEH_PE_ERROR: | |
cb5b242c | 950 | /* |
71b540ad GS |
951 | * If we can't find the corresponding PE, we |
952 | * just try to unfreeze. | |
cb5b242c | 953 | */ |
ddf0322a | 954 | if (ioda_eeh_get_pe(hose, |
71b540ad GS |
955 | be64_to_cpu(frozen_pe_no), pe)) { |
956 | /* Try best to clear it */ | |
957 | pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", | |
958 | hose->global_number, frozen_pe_no); | |
357b2f3d GS |
959 | pr_info("EEH: PHB location: %s\n", |
960 | eeh_pe_loc_get(phb_pe)); | |
71b540ad GS |
961 | opal_pci_eeh_freeze_clear(phb->opal_id, frozen_pe_no, |
962 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
963 | ret = EEH_NEXT_ERR_NONE; | |
05ec424e GS |
964 | } else if ((*pe)->state & EEH_PE_ISOLATED || |
965 | eeh_pe_passed(*pe)) { | |
63796558 | 966 | ret = EEH_NEXT_ERR_NONE; |
cb5b242c GS |
967 | } else { |
968 | pr_err("EEH: Frozen PE#%x on PHB#%x detected\n", | |
969 | (*pe)->addr, (*pe)->phb->global_number); | |
357b2f3d GS |
970 | pr_err("EEH: PE location: %s, PHB location: %s\n", |
971 | eeh_pe_loc_get(*pe), eeh_pe_loc_get(phb_pe)); | |
cb5b242c GS |
972 | ret = EEH_NEXT_ERR_FROZEN_PE; |
973 | } | |
70f942db | 974 | |
7e4e7867 GS |
975 | break; |
976 | default: | |
977 | pr_warn("%s: Unexpected error type %d\n", | |
ddf0322a | 978 | __func__, be16_to_cpu(err_type)); |
70f942db | 979 | } |
7e4e7867 | 980 | |
94716604 GS |
981 | /* |
982 | * EEH core will try recover from fenced PHB or | |
983 | * frozen PE. In the time for frozen PE, EEH core | |
984 | * enable IO path for that before collecting logs, | |
985 | * but it ruins the site. So we have to dump the | |
986 | * log in advance here. | |
987 | */ | |
988 | if ((ret == EEH_NEXT_ERR_FROZEN_PE || | |
989 | ret == EEH_NEXT_ERR_FENCED_PHB) && | |
990 | !((*pe)->state & EEH_PE_ISOLATED)) { | |
991 | eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); | |
bb593c00 | 992 | ioda_eeh_phb_diag(*pe); |
94716604 GS |
993 | } |
994 | ||
1ad7a72c GS |
995 | /* |
996 | * We probably have the frozen parent PE out there and | |
997 | * we need have to handle frozen parent PE firstly. | |
998 | */ | |
999 | if (ret == EEH_NEXT_ERR_FROZEN_PE) { | |
1000 | parent_pe = (*pe)->parent; | |
1001 | while (parent_pe) { | |
1002 | /* Hit the ceiling ? */ | |
1003 | if (parent_pe->type & EEH_PE_PHB) | |
1004 | break; | |
1005 | ||
1006 | /* Frozen parent PE ? */ | |
1007 | state = ioda_eeh_get_state(parent_pe); | |
1008 | if (state > 0 && | |
1009 | (state & active_flags) != active_flags) | |
1010 | *pe = parent_pe; | |
1011 | ||
1012 | /* Next parent level */ | |
1013 | parent_pe = parent_pe->parent; | |
1014 | } | |
1015 | ||
1016 | /* We possibly migrate to another PE */ | |
1017 | eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); | |
1018 | } | |
1019 | ||
7e4e7867 GS |
1020 | /* |
1021 | * If we have no errors on the specific PHB or only | |
1022 | * informative error there, we continue poking it. | |
1023 | * Otherwise, we need actions to be taken by upper | |
1024 | * layer. | |
1025 | */ | |
1026 | if (ret > EEH_NEXT_ERR_INF) | |
1027 | break; | |
70f942db GS |
1028 | } |
1029 | ||
70f942db GS |
1030 | return ret; |
1031 | } | |
1032 | ||
8747f363 | 1033 | struct pnv_eeh_ops ioda_eeh_ops = { |
73370c66 | 1034 | .post_init = ioda_eeh_post_init, |
eb005983 | 1035 | .set_option = ioda_eeh_set_option, |
8c41a7f3 | 1036 | .get_state = ioda_eeh_get_state, |
9d5cab00 | 1037 | .reset = ioda_eeh_reset, |
bb593c00 | 1038 | .get_log = ioda_eeh_get_log, |
bf90dfea | 1039 | .configure_bridge = ioda_eeh_configure_bridge, |
131c123a | 1040 | .err_inject = ioda_eeh_err_inject, |
70f942db | 1041 | .next_error = ioda_eeh_next_error |
8747f363 | 1042 | }; |