]>
Commit | Line | Data |
---|---|---|
184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
361f2a2a | 16 | #include <linux/crash_dump.h> |
37c367f2 | 17 | #include <linux/debugfs.h> |
184cd4a3 BH |
18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/msi.h> | |
cd15b048 | 25 | #include <linux/memblock.h> |
ac9a5889 | 26 | #include <linux/iommu.h> |
e57080f1 | 27 | #include <linux/rculist.h> |
4793d65d | 28 | #include <linux/sizes.h> |
184cd4a3 BH |
29 | |
30 | #include <asm/sections.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/pci-bridge.h> | |
34 | #include <asm/machdep.h> | |
fb1b55d6 | 35 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
36 | #include <asm/ppc-pci.h> |
37 | #include <asm/opal.h> | |
38 | #include <asm/iommu.h> | |
39 | #include <asm/tce.h> | |
137436c9 | 40 | #include <asm/xics.h> |
37c367f2 | 41 | #include <asm/debug.h> |
262af557 | 42 | #include <asm/firmware.h> |
80c49c7e | 43 | #include <asm/pnv-pci.h> |
aca6913f | 44 | #include <asm/mmzone.h> |
80c49c7e | 45 | |
ec249dd8 | 46 | #include <misc/cxl-base.h> |
184cd4a3 BH |
47 | |
48 | #include "powernv.h" | |
49 | #include "pci.h" | |
50 | ||
99451551 GS |
51 | #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ |
52 | #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ | |
acce971c | 53 | #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 |
781a868f | 54 | |
bbb845c4 AK |
55 | #define POWERNV_IOMMU_DEFAULT_LEVELS 1 |
56 | #define POWERNV_IOMMU_MAX_LEVELS 5 | |
57 | ||
9497a1c1 | 58 | static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; |
aca6913f AK |
59 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); |
60 | ||
7d623e42 | 61 | void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
6d31c2fa JP |
62 | const char *fmt, ...) |
63 | { | |
64 | struct va_format vaf; | |
65 | va_list args; | |
66 | char pfix[32]; | |
67 | ||
68 | va_start(args, fmt); | |
69 | ||
70 | vaf.fmt = fmt; | |
71 | vaf.va = &args; | |
72 | ||
781a868f | 73 | if (pe->flags & PNV_IODA_PE_DEV) |
6d31c2fa | 74 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
781a868f | 75 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
6d31c2fa JP |
76 | sprintf(pfix, "%04x:%02x ", |
77 | pci_domain_nr(pe->pbus), pe->pbus->number); | |
781a868f WY |
78 | #ifdef CONFIG_PCI_IOV |
79 | else if (pe->flags & PNV_IODA_PE_VF) | |
80 | sprintf(pfix, "%04x:%02x:%2x.%d", | |
81 | pci_domain_nr(pe->parent_dev->bus), | |
82 | (pe->rid & 0xff00) >> 8, | |
83 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); | |
84 | #endif /* CONFIG_PCI_IOV*/ | |
6d31c2fa | 85 | |
1f52f176 | 86 | printk("%spci %s: [PE# %.2x] %pV", |
6d31c2fa JP |
87 | level, pfix, pe->pe_number, &vaf); |
88 | ||
89 | va_end(args); | |
90 | } | |
184cd4a3 | 91 | |
4e287840 TLSC |
92 | static bool pnv_iommu_bypass_disabled __read_mostly; |
93 | ||
94 | static int __init iommu_setup(char *str) | |
95 | { | |
96 | if (!str) | |
97 | return -EINVAL; | |
98 | ||
99 | while (*str) { | |
100 | if (!strncmp(str, "nobypass", 8)) { | |
101 | pnv_iommu_bypass_disabled = true; | |
102 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); | |
103 | break; | |
104 | } | |
105 | str += strcspn(str, ","); | |
106 | if (*str == ',') | |
107 | str++; | |
108 | } | |
109 | ||
110 | return 0; | |
111 | } | |
112 | early_param("iommu", iommu_setup); | |
113 | ||
5958d19a | 114 | static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) |
262af557 | 115 | { |
5958d19a BH |
116 | /* |
117 | * WARNING: We cannot rely on the resource flags. The Linux PCI | |
118 | * allocation code sometimes decides to put a 64-bit prefetchable | |
119 | * BAR in the 32-bit window, so we have to compare the addresses. | |
120 | * | |
121 | * For simplicity we only test resource start. | |
122 | */ | |
123 | return (r->start >= phb->ioda.m64_base && | |
124 | r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); | |
262af557 GC |
125 | } |
126 | ||
b79331a5 RC |
127 | static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) |
128 | { | |
129 | unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
130 | ||
131 | return (resource_flags & flags) == flags; | |
132 | } | |
133 | ||
1e916772 GS |
134 | static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) |
135 | { | |
313483dd GS |
136 | s64 rc; |
137 | ||
1e916772 GS |
138 | phb->ioda.pe_array[pe_no].phb = phb; |
139 | phb->ioda.pe_array[pe_no].pe_number = pe_no; | |
140 | ||
313483dd GS |
141 | /* |
142 | * Clear the PE frozen state as it might be put into frozen state | |
143 | * in the last PCI remove path. It's not harmful to do so when the | |
144 | * PE is already in unfrozen state. | |
145 | */ | |
146 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, | |
147 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
d4791db5 | 148 | if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) |
1f52f176 | 149 | pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", |
313483dd GS |
150 | __func__, rc, phb->hose->global_number, pe_no); |
151 | ||
1e916772 GS |
152 | return &phb->ioda.pe_array[pe_no]; |
153 | } | |
154 | ||
4b82ab18 GS |
155 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
156 | { | |
92b8f137 | 157 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { |
1f52f176 | 158 | pr_warn("%s: Invalid PE %x on PHB#%x\n", |
4b82ab18 GS |
159 | __func__, pe_no, phb->hose->global_number); |
160 | return; | |
161 | } | |
162 | ||
e9dc4d7f | 163 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) |
1f52f176 | 164 | pr_debug("%s: PE %x was reserved on PHB#%x\n", |
e9dc4d7f | 165 | __func__, pe_no, phb->hose->global_number); |
4b82ab18 | 166 | |
1e916772 | 167 | pnv_ioda_init_pe(phb, pe_no); |
4b82ab18 GS |
168 | } |
169 | ||
1e916772 | 170 | static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 | 171 | { |
60964816 | 172 | long pe; |
184cd4a3 | 173 | |
9fcd6f4a GS |
174 | for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { |
175 | if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) | |
176 | return pnv_ioda_init_pe(phb, pe); | |
177 | } | |
184cd4a3 | 178 | |
9fcd6f4a | 179 | return NULL; |
184cd4a3 BH |
180 | } |
181 | ||
1e916772 | 182 | static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) |
184cd4a3 | 183 | { |
1e916772 | 184 | struct pnv_phb *phb = pe->phb; |
caa58f80 | 185 | unsigned int pe_num = pe->pe_number; |
1e916772 GS |
186 | |
187 | WARN_ON(pe->pdev); | |
184cd4a3 | 188 | |
1e916772 | 189 | memset(pe, 0, sizeof(struct pnv_ioda_pe)); |
caa58f80 | 190 | clear_bit(pe_num, phb->ioda.pe_alloc); |
184cd4a3 BH |
191 | } |
192 | ||
262af557 GC |
193 | /* The default M64 BAR is shared by all PEs */ |
194 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) | |
195 | { | |
196 | const char *desc; | |
197 | struct resource *r; | |
198 | s64 rc; | |
199 | ||
200 | /* Configure the default M64 BAR */ | |
201 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
202 | OPAL_M64_WINDOW_TYPE, | |
203 | phb->ioda.m64_bar_idx, | |
204 | phb->ioda.m64_base, | |
205 | 0, /* unused */ | |
206 | phb->ioda.m64_size); | |
207 | if (rc != OPAL_SUCCESS) { | |
208 | desc = "configuring"; | |
209 | goto fail; | |
210 | } | |
211 | ||
212 | /* Enable the default M64 BAR */ | |
213 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
214 | OPAL_M64_WINDOW_TYPE, | |
215 | phb->ioda.m64_bar_idx, | |
216 | OPAL_ENABLE_M64_SPLIT); | |
217 | if (rc != OPAL_SUCCESS) { | |
218 | desc = "enabling"; | |
219 | goto fail; | |
220 | } | |
221 | ||
262af557 | 222 | /* |
63803c39 GS |
223 | * Exclude the segments for reserved and root bus PE, which |
224 | * are first or last two PEs. | |
262af557 GC |
225 | */ |
226 | r = &phb->hose->mem_resources[1]; | |
92b8f137 | 227 | if (phb->ioda.reserved_pe_idx == 0) |
63803c39 | 228 | r->start += (2 * phb->ioda.m64_segsize); |
92b8f137 | 229 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
63803c39 | 230 | r->end -= (2 * phb->ioda.m64_segsize); |
262af557 | 231 | else |
1f52f176 | 232 | pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", |
92b8f137 | 233 | phb->ioda.reserved_pe_idx); |
262af557 GC |
234 | |
235 | return 0; | |
236 | ||
237 | fail: | |
238 | pr_warn(" Failure %lld %s M64 BAR#%d\n", | |
239 | rc, desc, phb->ioda.m64_bar_idx); | |
240 | opal_pci_phb_mmio_enable(phb->opal_id, | |
241 | OPAL_M64_WINDOW_TYPE, | |
242 | phb->ioda.m64_bar_idx, | |
243 | OPAL_DISABLE_M64); | |
244 | return -EIO; | |
245 | } | |
246 | ||
c430670a | 247 | static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, |
96a2f92b | 248 | unsigned long *pe_bitmap) |
262af557 | 249 | { |
96a2f92b GS |
250 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
251 | struct pnv_phb *phb = hose->private_data; | |
262af557 | 252 | struct resource *r; |
96a2f92b GS |
253 | resource_size_t base, sgsz, start, end; |
254 | int segno, i; | |
255 | ||
256 | base = phb->ioda.m64_base; | |
257 | sgsz = phb->ioda.m64_segsize; | |
258 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
259 | r = &pdev->resource[i]; | |
5958d19a | 260 | if (!r->parent || !pnv_pci_is_m64(phb, r)) |
96a2f92b | 261 | continue; |
262af557 | 262 | |
96a2f92b GS |
263 | start = _ALIGN_DOWN(r->start - base, sgsz); |
264 | end = _ALIGN_UP(r->end - base, sgsz); | |
265 | for (segno = start / sgsz; segno < end / sgsz; segno++) { | |
266 | if (pe_bitmap) | |
267 | set_bit(segno, pe_bitmap); | |
268 | else | |
269 | pnv_ioda_reserve_pe(phb, segno); | |
262af557 GC |
270 | } |
271 | } | |
272 | } | |
273 | ||
99451551 GS |
274 | static int pnv_ioda1_init_m64(struct pnv_phb *phb) |
275 | { | |
276 | struct resource *r; | |
277 | int index; | |
278 | ||
279 | /* | |
280 | * There are 16 M64 BARs, each of which has 8 segments. So | |
281 | * there are as many M64 segments as the maximum number of | |
282 | * PEs, which is 128. | |
283 | */ | |
284 | for (index = 0; index < PNV_IODA1_M64_NUM; index++) { | |
285 | unsigned long base, segsz = phb->ioda.m64_segsize; | |
286 | int64_t rc; | |
287 | ||
288 | base = phb->ioda.m64_base + | |
289 | index * PNV_IODA1_M64_SEGS * segsz; | |
290 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
291 | OPAL_M64_WINDOW_TYPE, index, base, 0, | |
292 | PNV_IODA1_M64_SEGS * segsz); | |
293 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 294 | pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", |
99451551 GS |
295 | rc, phb->hose->global_number, index); |
296 | goto fail; | |
297 | } | |
298 | ||
299 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
300 | OPAL_M64_WINDOW_TYPE, index, | |
301 | OPAL_ENABLE_M64_SPLIT); | |
302 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 303 | pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", |
99451551 GS |
304 | rc, phb->hose->global_number, index); |
305 | goto fail; | |
306 | } | |
307 | } | |
308 | ||
309 | /* | |
63803c39 GS |
310 | * Exclude the segments for reserved and root bus PE, which |
311 | * are first or last two PEs. | |
99451551 GS |
312 | */ |
313 | r = &phb->hose->mem_resources[1]; | |
314 | if (phb->ioda.reserved_pe_idx == 0) | |
63803c39 | 315 | r->start += (2 * phb->ioda.m64_segsize); |
99451551 | 316 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
63803c39 | 317 | r->end -= (2 * phb->ioda.m64_segsize); |
99451551 | 318 | else |
1f52f176 | 319 | WARN(1, "Wrong reserved PE#%x on PHB#%x\n", |
99451551 GS |
320 | phb->ioda.reserved_pe_idx, phb->hose->global_number); |
321 | ||
322 | return 0; | |
323 | ||
324 | fail: | |
325 | for ( ; index >= 0; index--) | |
326 | opal_pci_phb_mmio_enable(phb->opal_id, | |
327 | OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); | |
328 | ||
329 | return -EIO; | |
330 | } | |
331 | ||
c430670a GS |
332 | static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, |
333 | unsigned long *pe_bitmap, | |
334 | bool all) | |
262af557 | 335 | { |
262af557 | 336 | struct pci_dev *pdev; |
96a2f92b GS |
337 | |
338 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
c430670a | 339 | pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); |
96a2f92b GS |
340 | |
341 | if (all && pdev->subordinate) | |
c430670a GS |
342 | pnv_ioda_reserve_m64_pe(pdev->subordinate, |
343 | pe_bitmap, all); | |
96a2f92b GS |
344 | } |
345 | } | |
346 | ||
1e916772 | 347 | static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) |
262af557 | 348 | { |
26ba248d GS |
349 | struct pci_controller *hose = pci_bus_to_host(bus); |
350 | struct pnv_phb *phb = hose->private_data; | |
262af557 GC |
351 | struct pnv_ioda_pe *master_pe, *pe; |
352 | unsigned long size, *pe_alloc; | |
26ba248d | 353 | int i; |
262af557 GC |
354 | |
355 | /* Root bus shouldn't use M64 */ | |
356 | if (pci_is_root_bus(bus)) | |
1e916772 | 357 | return NULL; |
262af557 | 358 | |
262af557 | 359 | /* Allocate bitmap */ |
92b8f137 | 360 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
262af557 GC |
361 | pe_alloc = kzalloc(size, GFP_KERNEL); |
362 | if (!pe_alloc) { | |
363 | pr_warn("%s: Out of memory !\n", | |
364 | __func__); | |
1e916772 | 365 | return NULL; |
262af557 GC |
366 | } |
367 | ||
26ba248d | 368 | /* Figure out reserved PE numbers by the PE */ |
c430670a | 369 | pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); |
262af557 GC |
370 | |
371 | /* | |
372 | * the current bus might not own M64 window and that's all | |
373 | * contributed by its child buses. For the case, we needn't | |
374 | * pick M64 dependent PE#. | |
375 | */ | |
92b8f137 | 376 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { |
262af557 | 377 | kfree(pe_alloc); |
1e916772 | 378 | return NULL; |
262af557 GC |
379 | } |
380 | ||
381 | /* | |
382 | * Figure out the master PE and put all slave PEs to master | |
383 | * PE's list to form compound PE. | |
384 | */ | |
262af557 GC |
385 | master_pe = NULL; |
386 | i = -1; | |
92b8f137 GS |
387 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < |
388 | phb->ioda.total_pe_num) { | |
262af557 | 389 | pe = &phb->ioda.pe_array[i]; |
262af557 | 390 | |
93289d8c | 391 | phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; |
262af557 GC |
392 | if (!master_pe) { |
393 | pe->flags |= PNV_IODA_PE_MASTER; | |
394 | INIT_LIST_HEAD(&pe->slaves); | |
395 | master_pe = pe; | |
396 | } else { | |
397 | pe->flags |= PNV_IODA_PE_SLAVE; | |
398 | pe->master = master_pe; | |
399 | list_add_tail(&pe->list, &master_pe->slaves); | |
400 | } | |
99451551 GS |
401 | |
402 | /* | |
403 | * P7IOC supports M64DT, which helps mapping M64 segment | |
404 | * to one particular PE#. However, PHB3 has fixed mapping | |
405 | * between M64 segment and PE#. In order to have same logic | |
406 | * for P7IOC and PHB3, we enforce fixed mapping between M64 | |
407 | * segment and PE# on P7IOC. | |
408 | */ | |
409 | if (phb->type == PNV_PHB_IODA1) { | |
410 | int64_t rc; | |
411 | ||
412 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
413 | pe->pe_number, OPAL_M64_WINDOW_TYPE, | |
414 | pe->pe_number / PNV_IODA1_M64_SEGS, | |
415 | pe->pe_number % PNV_IODA1_M64_SEGS); | |
416 | if (rc != OPAL_SUCCESS) | |
1f52f176 | 417 | pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", |
99451551 GS |
418 | __func__, rc, phb->hose->global_number, |
419 | pe->pe_number); | |
420 | } | |
262af557 GC |
421 | } |
422 | ||
423 | kfree(pe_alloc); | |
1e916772 | 424 | return master_pe; |
262af557 GC |
425 | } |
426 | ||
427 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) | |
428 | { | |
429 | struct pci_controller *hose = phb->hose; | |
430 | struct device_node *dn = hose->dn; | |
431 | struct resource *res; | |
a1339faf | 432 | u32 m64_range[2], i; |
0e7736c6 | 433 | const __be32 *r; |
262af557 GC |
434 | u64 pci_addr; |
435 | ||
99451551 | 436 | if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { |
1665c4a8 GS |
437 | pr_info(" Not support M64 window\n"); |
438 | return; | |
439 | } | |
440 | ||
e4d54f71 | 441 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
262af557 GC |
442 | pr_info(" Firmware too old to support M64 window\n"); |
443 | return; | |
444 | } | |
445 | ||
446 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); | |
447 | if (!r) { | |
448 | pr_info(" No <ibm,opal-m64-window> on %s\n", | |
449 | dn->full_name); | |
450 | return; | |
451 | } | |
452 | ||
a1339faf BH |
453 | /* |
454 | * Find the available M64 BAR range and pickup the last one for | |
455 | * covering the whole 64-bits space. We support only one range. | |
456 | */ | |
457 | if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", | |
458 | m64_range, 2)) { | |
459 | /* In absence of the property, assume 0..15 */ | |
460 | m64_range[0] = 0; | |
461 | m64_range[1] = 16; | |
462 | } | |
463 | /* We only support 64 bits in our allocator */ | |
464 | if (m64_range[1] > 63) { | |
465 | pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", | |
466 | __func__, m64_range[1], phb->hose->global_number); | |
467 | m64_range[1] = 63; | |
468 | } | |
469 | /* Empty range, no m64 */ | |
470 | if (m64_range[1] <= m64_range[0]) { | |
471 | pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", | |
472 | __func__, phb->hose->global_number); | |
473 | return; | |
474 | } | |
475 | ||
476 | /* Configure M64 informations */ | |
262af557 | 477 | res = &hose->mem_resources[1]; |
e80c4e7c | 478 | res->name = dn->full_name; |
262af557 GC |
479 | res->start = of_translate_address(dn, r + 2); |
480 | res->end = res->start + of_read_number(r + 4, 2) - 1; | |
481 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
482 | pci_addr = of_read_number(r, 2); | |
483 | hose->mem_offset[1] = res->start - pci_addr; | |
484 | ||
485 | phb->ioda.m64_size = resource_size(res); | |
92b8f137 | 486 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; |
262af557 GC |
487 | phb->ioda.m64_base = pci_addr; |
488 | ||
a1339faf BH |
489 | /* This lines up nicely with the display from processing OF ranges */ |
490 | pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", | |
491 | res->start, res->end, pci_addr, m64_range[0], | |
492 | m64_range[0] + m64_range[1] - 1); | |
493 | ||
494 | /* Mark all M64 used up by default */ | |
495 | phb->ioda.m64_bar_alloc = (unsigned long)-1; | |
e9863e68 | 496 | |
262af557 | 497 | /* Use last M64 BAR to cover M64 window */ |
a1339faf BH |
498 | m64_range[1]--; |
499 | phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; | |
500 | ||
501 | pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); | |
502 | ||
503 | /* Mark remaining ones free */ | |
504 | for (i = m64_range[0]; i < m64_range[1]; i++) | |
505 | clear_bit(i, &phb->ioda.m64_bar_alloc); | |
506 | ||
507 | /* | |
508 | * Setup init functions for M64 based on IODA version, IODA3 uses | |
509 | * the IODA2 code. | |
510 | */ | |
99451551 GS |
511 | if (phb->type == PNV_PHB_IODA1) |
512 | phb->init_m64 = pnv_ioda1_init_m64; | |
513 | else | |
514 | phb->init_m64 = pnv_ioda2_init_m64; | |
c430670a GS |
515 | phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; |
516 | phb->pick_m64_pe = pnv_ioda_pick_m64_pe; | |
262af557 GC |
517 | } |
518 | ||
49dec922 GS |
519 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
520 | { | |
521 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; | |
522 | struct pnv_ioda_pe *slave; | |
523 | s64 rc; | |
524 | ||
525 | /* Fetch master PE */ | |
526 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
527 | pe = pe->master; | |
ec8e4e9d GS |
528 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
529 | return; | |
530 | ||
49dec922 GS |
531 | pe_no = pe->pe_number; |
532 | } | |
533 | ||
534 | /* Freeze master PE */ | |
535 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
536 | pe_no, | |
537 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
538 | if (rc != OPAL_SUCCESS) { | |
539 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
540 | __func__, rc, phb->hose->global_number, pe_no); | |
541 | return; | |
542 | } | |
543 | ||
544 | /* Freeze slave PEs */ | |
545 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
546 | return; | |
547 | ||
548 | list_for_each_entry(slave, &pe->slaves, list) { | |
549 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
550 | slave->pe_number, | |
551 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
552 | if (rc != OPAL_SUCCESS) | |
553 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
554 | __func__, rc, phb->hose->global_number, | |
555 | slave->pe_number); | |
556 | } | |
557 | } | |
558 | ||
e51df2c1 | 559 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
49dec922 GS |
560 | { |
561 | struct pnv_ioda_pe *pe, *slave; | |
562 | s64 rc; | |
563 | ||
564 | /* Find master PE */ | |
565 | pe = &phb->ioda.pe_array[pe_no]; | |
566 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
567 | pe = pe->master; | |
568 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
569 | pe_no = pe->pe_number; | |
570 | } | |
571 | ||
572 | /* Clear frozen state for master PE */ | |
573 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); | |
574 | if (rc != OPAL_SUCCESS) { | |
575 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
576 | __func__, rc, opt, phb->hose->global_number, pe_no); | |
577 | return -EIO; | |
578 | } | |
579 | ||
580 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
581 | return 0; | |
582 | ||
583 | /* Clear frozen state for slave PEs */ | |
584 | list_for_each_entry(slave, &pe->slaves, list) { | |
585 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
586 | slave->pe_number, | |
587 | opt); | |
588 | if (rc != OPAL_SUCCESS) { | |
589 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
590 | __func__, rc, opt, phb->hose->global_number, | |
591 | slave->pe_number); | |
592 | return -EIO; | |
593 | } | |
594 | } | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) | |
600 | { | |
601 | struct pnv_ioda_pe *slave, *pe; | |
602 | u8 fstate, state; | |
603 | __be16 pcierr; | |
604 | s64 rc; | |
605 | ||
606 | /* Sanity check on PE number */ | |
92b8f137 | 607 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) |
49dec922 GS |
608 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; |
609 | ||
610 | /* | |
611 | * Fetch the master PE and the PE instance might be | |
612 | * not initialized yet. | |
613 | */ | |
614 | pe = &phb->ioda.pe_array[pe_no]; | |
615 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
616 | pe = pe->master; | |
617 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
618 | pe_no = pe->pe_number; | |
619 | } | |
620 | ||
621 | /* Check the master PE */ | |
622 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, | |
623 | &state, &pcierr, NULL); | |
624 | if (rc != OPAL_SUCCESS) { | |
625 | pr_warn("%s: Failure %lld getting " | |
626 | "PHB#%x-PE#%x state\n", | |
627 | __func__, rc, | |
628 | phb->hose->global_number, pe_no); | |
629 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
630 | } | |
631 | ||
632 | /* Check the slave PE */ | |
633 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
634 | return state; | |
635 | ||
636 | list_for_each_entry(slave, &pe->slaves, list) { | |
637 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
638 | slave->pe_number, | |
639 | &fstate, | |
640 | &pcierr, | |
641 | NULL); | |
642 | if (rc != OPAL_SUCCESS) { | |
643 | pr_warn("%s: Failure %lld getting " | |
644 | "PHB#%x-PE#%x state\n", | |
645 | __func__, rc, | |
646 | phb->hose->global_number, slave->pe_number); | |
647 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
648 | } | |
649 | ||
650 | /* | |
651 | * Override the result based on the ascending | |
652 | * priority. | |
653 | */ | |
654 | if (fstate > state) | |
655 | state = fstate; | |
656 | } | |
657 | ||
658 | return state; | |
659 | } | |
660 | ||
184cd4a3 BH |
661 | /* Currently those 2 are only used when MSIs are enabled, this will change |
662 | * but in the meantime, we need to protect them to avoid warnings | |
663 | */ | |
664 | #ifdef CONFIG_PCI_MSI | |
f456834a | 665 | struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
666 | { |
667 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
668 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 669 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
670 | |
671 | if (!pdn) | |
672 | return NULL; | |
673 | if (pdn->pe_number == IODA_INVALID_PE) | |
674 | return NULL; | |
675 | return &phb->ioda.pe_array[pdn->pe_number]; | |
676 | } | |
184cd4a3 BH |
677 | #endif /* CONFIG_PCI_MSI */ |
678 | ||
b131a842 GS |
679 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
680 | struct pnv_ioda_pe *parent, | |
681 | struct pnv_ioda_pe *child, | |
682 | bool is_add) | |
683 | { | |
684 | const char *desc = is_add ? "adding" : "removing"; | |
685 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : | |
686 | OPAL_REMOVE_PE_FROM_DOMAIN; | |
687 | struct pnv_ioda_pe *slave; | |
688 | long rc; | |
689 | ||
690 | /* Parent PE affects child PE */ | |
691 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
692 | child->pe_number, op); | |
693 | if (rc != OPAL_SUCCESS) { | |
694 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", | |
695 | rc, desc); | |
696 | return -ENXIO; | |
697 | } | |
698 | ||
699 | if (!(child->flags & PNV_IODA_PE_MASTER)) | |
700 | return 0; | |
701 | ||
702 | /* Compound case: parent PE affects slave PEs */ | |
703 | list_for_each_entry(slave, &child->slaves, list) { | |
704 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
705 | slave->pe_number, op); | |
706 | if (rc != OPAL_SUCCESS) { | |
707 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", | |
708 | rc, desc); | |
709 | return -ENXIO; | |
710 | } | |
711 | } | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |
717 | struct pnv_ioda_pe *pe, | |
718 | bool is_add) | |
719 | { | |
720 | struct pnv_ioda_pe *slave; | |
781a868f | 721 | struct pci_dev *pdev = NULL; |
b131a842 GS |
722 | int ret; |
723 | ||
724 | /* | |
725 | * Clear PE frozen state. If it's master PE, we need | |
726 | * clear slave PE frozen state as well. | |
727 | */ | |
728 | if (is_add) { | |
729 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, | |
730 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
731 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
732 | list_for_each_entry(slave, &pe->slaves, list) | |
733 | opal_pci_eeh_freeze_clear(phb->opal_id, | |
734 | slave->pe_number, | |
735 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
736 | } | |
737 | } | |
738 | ||
739 | /* | |
740 | * Associate PE in PELT. We need add the PE into the | |
741 | * corresponding PELT-V as well. Otherwise, the error | |
742 | * originated from the PE might contribute to other | |
743 | * PEs. | |
744 | */ | |
745 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); | |
746 | if (ret) | |
747 | return ret; | |
748 | ||
749 | /* For compound PEs, any one affects all of them */ | |
750 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
751 | list_for_each_entry(slave, &pe->slaves, list) { | |
752 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); | |
753 | if (ret) | |
754 | return ret; | |
755 | } | |
756 | } | |
757 | ||
758 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) | |
759 | pdev = pe->pbus->self; | |
781a868f | 760 | else if (pe->flags & PNV_IODA_PE_DEV) |
b131a842 | 761 | pdev = pe->pdev->bus->self; |
781a868f WY |
762 | #ifdef CONFIG_PCI_IOV |
763 | else if (pe->flags & PNV_IODA_PE_VF) | |
283e2d8a | 764 | pdev = pe->parent_dev; |
781a868f | 765 | #endif /* CONFIG_PCI_IOV */ |
b131a842 GS |
766 | while (pdev) { |
767 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
768 | struct pnv_ioda_pe *parent; | |
769 | ||
770 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
771 | parent = &phb->ioda.pe_array[pdn->pe_number]; | |
772 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); | |
773 | if (ret) | |
774 | return ret; | |
775 | } | |
776 | ||
777 | pdev = pdev->bus->self; | |
778 | } | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
781a868f WY |
783 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
784 | { | |
785 | struct pci_dev *parent; | |
786 | uint8_t bcomp, dcomp, fcomp; | |
787 | int64_t rc; | |
788 | long rid_end, rid; | |
789 | ||
790 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ | |
791 | if (pe->pbus) { | |
792 | int count; | |
793 | ||
794 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
795 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
796 | parent = pe->pbus->self; | |
797 | if (pe->flags & PNV_IODA_PE_BUS_ALL) | |
798 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
799 | else | |
800 | count = 1; | |
801 | ||
802 | switch(count) { | |
803 | case 1: bcomp = OpalPciBusAll; break; | |
804 | case 2: bcomp = OpalPciBus7Bits; break; | |
805 | case 4: bcomp = OpalPciBus6Bits; break; | |
806 | case 8: bcomp = OpalPciBus5Bits; break; | |
807 | case 16: bcomp = OpalPciBus4Bits; break; | |
808 | case 32: bcomp = OpalPciBus3Bits; break; | |
809 | default: | |
810 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", | |
811 | count); | |
812 | /* Do an exact match only */ | |
813 | bcomp = OpalPciBusAll; | |
814 | } | |
815 | rid_end = pe->rid + (count << 8); | |
816 | } else { | |
93e01a50 | 817 | #ifdef CONFIG_PCI_IOV |
781a868f WY |
818 | if (pe->flags & PNV_IODA_PE_VF) |
819 | parent = pe->parent_dev; | |
820 | else | |
93e01a50 | 821 | #endif |
781a868f WY |
822 | parent = pe->pdev->bus->self; |
823 | bcomp = OpalPciBusAll; | |
824 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
825 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
826 | rid_end = pe->rid + 1; | |
827 | } | |
828 | ||
829 | /* Clear the reverse map */ | |
830 | for (rid = pe->rid; rid < rid_end; rid++) | |
c127562a | 831 | phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; |
781a868f WY |
832 | |
833 | /* Release from all parents PELT-V */ | |
834 | while (parent) { | |
835 | struct pci_dn *pdn = pci_get_pdn(parent); | |
836 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
837 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
838 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
839 | /* XXX What to do in case of error ? */ | |
840 | } | |
841 | parent = parent->bus->self; | |
842 | } | |
843 | ||
f951e510 | 844 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
781a868f WY |
845 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
846 | ||
847 | /* Disassociate PE in PELT */ | |
848 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
849 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
850 | if (rc) | |
851 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); | |
852 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, | |
853 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); | |
854 | if (rc) | |
855 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
856 | ||
857 | pe->pbus = NULL; | |
858 | pe->pdev = NULL; | |
93e01a50 | 859 | #ifdef CONFIG_PCI_IOV |
781a868f | 860 | pe->parent_dev = NULL; |
93e01a50 | 861 | #endif |
781a868f WY |
862 | |
863 | return 0; | |
864 | } | |
781a868f | 865 | |
cad5cef6 | 866 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
867 | { |
868 | struct pci_dev *parent; | |
869 | uint8_t bcomp, dcomp, fcomp; | |
870 | long rc, rid_end, rid; | |
871 | ||
872 | /* Bus validation ? */ | |
873 | if (pe->pbus) { | |
874 | int count; | |
875 | ||
876 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
877 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
878 | parent = pe->pbus->self; | |
fb446ad0 GS |
879 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
880 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
881 | else | |
882 | count = 1; | |
883 | ||
184cd4a3 BH |
884 | switch(count) { |
885 | case 1: bcomp = OpalPciBusAll; break; | |
886 | case 2: bcomp = OpalPciBus7Bits; break; | |
887 | case 4: bcomp = OpalPciBus6Bits; break; | |
888 | case 8: bcomp = OpalPciBus5Bits; break; | |
889 | case 16: bcomp = OpalPciBus4Bits; break; | |
890 | case 32: bcomp = OpalPciBus3Bits; break; | |
891 | default: | |
781a868f WY |
892 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
893 | count); | |
184cd4a3 BH |
894 | /* Do an exact match only */ |
895 | bcomp = OpalPciBusAll; | |
896 | } | |
897 | rid_end = pe->rid + (count << 8); | |
898 | } else { | |
781a868f WY |
899 | #ifdef CONFIG_PCI_IOV |
900 | if (pe->flags & PNV_IODA_PE_VF) | |
901 | parent = pe->parent_dev; | |
902 | else | |
903 | #endif /* CONFIG_PCI_IOV */ | |
904 | parent = pe->pdev->bus->self; | |
184cd4a3 BH |
905 | bcomp = OpalPciBusAll; |
906 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
907 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
908 | rid_end = pe->rid + 1; | |
909 | } | |
910 | ||
631ad691 GS |
911 | /* |
912 | * Associate PE in PELT. We need add the PE into the | |
913 | * corresponding PELT-V as well. Otherwise, the error | |
914 | * originated from the PE might contribute to other | |
915 | * PEs. | |
916 | */ | |
184cd4a3 BH |
917 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
918 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
919 | if (rc) { | |
920 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
921 | return -ENXIO; | |
922 | } | |
631ad691 | 923 | |
5d2aa710 AP |
924 | /* |
925 | * Configure PELTV. NPUs don't have a PELTV table so skip | |
926 | * configuration on them. | |
927 | */ | |
928 | if (phb->type != PNV_PHB_NPU) | |
929 | pnv_ioda_set_peltv(phb, pe, true); | |
184cd4a3 | 930 | |
184cd4a3 BH |
931 | /* Setup reverse map */ |
932 | for (rid = pe->rid; rid < rid_end; rid++) | |
933 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
934 | ||
935 | /* Setup one MVTs on IODA1 */ | |
4773f76b GS |
936 | if (phb->type != PNV_PHB_IODA1) { |
937 | pe->mve_number = 0; | |
938 | goto out; | |
939 | } | |
940 | ||
941 | pe->mve_number = pe->pe_number; | |
942 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); | |
943 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 944 | pe_err(pe, "OPAL error %ld setting up MVE %x\n", |
4773f76b GS |
945 | rc, pe->mve_number); |
946 | pe->mve_number = -1; | |
947 | } else { | |
948 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
949 | pe->mve_number, OPAL_ENABLE_MVE); | |
184cd4a3 | 950 | if (rc) { |
1f52f176 | 951 | pe_err(pe, "OPAL error %ld enabling MVE %x\n", |
184cd4a3 BH |
952 | rc, pe->mve_number); |
953 | pe->mve_number = -1; | |
184cd4a3 | 954 | } |
4773f76b | 955 | } |
184cd4a3 | 956 | |
4773f76b | 957 | out: |
184cd4a3 BH |
958 | return 0; |
959 | } | |
960 | ||
781a868f WY |
961 | #ifdef CONFIG_PCI_IOV |
962 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) | |
963 | { | |
964 | struct pci_dn *pdn = pci_get_pdn(dev); | |
965 | int i; | |
966 | struct resource *res, res2; | |
967 | resource_size_t size; | |
968 | u16 num_vfs; | |
969 | ||
970 | if (!dev->is_physfn) | |
971 | return -EINVAL; | |
972 | ||
973 | /* | |
974 | * "offset" is in VFs. The M64 windows are sized so that when they | |
975 | * are segmented, each segment is the same size as the IOV BAR. | |
976 | * Each segment is in a separate PE, and the high order bits of the | |
977 | * address are the PE number. Therefore, each VF's BAR is in a | |
978 | * separate PE, and changing the IOV BAR start address changes the | |
979 | * range of PEs the VFs are in. | |
980 | */ | |
981 | num_vfs = pdn->num_vfs; | |
982 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
983 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
984 | if (!res->flags || !res->parent) | |
985 | continue; | |
986 | ||
781a868f WY |
987 | /* |
988 | * The actual IOV BAR range is determined by the start address | |
989 | * and the actual size for num_vfs VFs BAR. This check is to | |
990 | * make sure that after shifting, the range will not overlap | |
991 | * with another device. | |
992 | */ | |
993 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | |
994 | res2.flags = res->flags; | |
995 | res2.start = res->start + (size * offset); | |
996 | res2.end = res2.start + (size * num_vfs) - 1; | |
997 | ||
998 | if (res2.end > res->end) { | |
999 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", | |
1000 | i, &res2, res, num_vfs, offset); | |
1001 | return -EBUSY; | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | /* | |
1006 | * After doing so, there would be a "hole" in the /proc/iomem when | |
1007 | * offset is a positive value. It looks like the device return some | |
1008 | * mmio back to the system, which actually no one could use it. | |
1009 | */ | |
1010 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1011 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
1012 | if (!res->flags || !res->parent) | |
1013 | continue; | |
1014 | ||
781a868f WY |
1015 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
1016 | res2 = *res; | |
1017 | res->start += size * offset; | |
1018 | ||
74703cc4 WY |
1019 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", |
1020 | i, &res2, res, (offset > 0) ? "En" : "Dis", | |
1021 | num_vfs, offset); | |
781a868f WY |
1022 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); |
1023 | } | |
1024 | return 0; | |
1025 | } | |
1026 | #endif /* CONFIG_PCI_IOV */ | |
1027 | ||
cad5cef6 | 1028 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
1029 | { |
1030 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1031 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 1032 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 | 1033 | struct pnv_ioda_pe *pe; |
184cd4a3 BH |
1034 | |
1035 | if (!pdn) { | |
1036 | pr_err("%s: Device tree node not associated properly\n", | |
1037 | pci_name(dev)); | |
1038 | return NULL; | |
1039 | } | |
1040 | if (pdn->pe_number != IODA_INVALID_PE) | |
1041 | return NULL; | |
1042 | ||
1e916772 GS |
1043 | pe = pnv_ioda_alloc_pe(phb); |
1044 | if (!pe) { | |
184cd4a3 BH |
1045 | pr_warning("%s: Not enough PE# available, disabling device\n", |
1046 | pci_name(dev)); | |
1047 | return NULL; | |
1048 | } | |
1049 | ||
1050 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
1051 | * pointer in the PE data structure, both should be destroyed at the | |
1052 | * same time. However, this needs to be looked at more closely again | |
1053 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
1054 | * | |
1055 | * At some point we want to remove the PDN completely anyways | |
1056 | */ | |
184cd4a3 BH |
1057 | pci_dev_get(dev); |
1058 | pdn->pcidev = dev; | |
1e916772 | 1059 | pdn->pe_number = pe->pe_number; |
5d2aa710 | 1060 | pe->flags = PNV_IODA_PE_DEV; |
184cd4a3 BH |
1061 | pe->pdev = dev; |
1062 | pe->pbus = NULL; | |
184cd4a3 BH |
1063 | pe->mve_number = -1; |
1064 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
1065 | ||
1066 | pe_info(pe, "Associated device to PE\n"); | |
1067 | ||
1068 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1069 | /* XXX What do we do here ? */ | |
1e916772 | 1070 | pnv_ioda_free_pe(pe); |
184cd4a3 BH |
1071 | pdn->pe_number = IODA_INVALID_PE; |
1072 | pe->pdev = NULL; | |
1073 | pci_dev_put(dev); | |
1074 | return NULL; | |
1075 | } | |
1076 | ||
1d4e89cf AK |
1077 | /* Put PE to the list */ |
1078 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1079 | ||
184cd4a3 BH |
1080 | return pe; |
1081 | } | |
1082 | ||
1083 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
1084 | { | |
1085 | struct pci_dev *dev; | |
1086 | ||
1087 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 1088 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1089 | |
1090 | if (pdn == NULL) { | |
1091 | pr_warn("%s: No device node associated with device !\n", | |
1092 | pci_name(dev)); | |
1093 | continue; | |
1094 | } | |
ccd1c191 GS |
1095 | |
1096 | /* | |
1097 | * In partial hotplug case, the PCI device might be still | |
1098 | * associated with the PE and needn't attach it to the PE | |
1099 | * again. | |
1100 | */ | |
1101 | if (pdn->pe_number != IODA_INVALID_PE) | |
1102 | continue; | |
1103 | ||
c5f7700b | 1104 | pe->device_count++; |
94973b24 | 1105 | pdn->pcidev = dev; |
184cd4a3 | 1106 | pdn->pe_number = pe->pe_number; |
fb446ad0 | 1107 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
1108 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
1109 | } | |
1110 | } | |
1111 | ||
fb446ad0 GS |
1112 | /* |
1113 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
1114 | * single PCI bus. Another one that contains the primary PCI bus and its | |
1115 | * subordinate PCI devices and buses. The second type of PE is normally | |
1116 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
1117 | */ | |
1e916772 | 1118 | static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) |
184cd4a3 | 1119 | { |
fb446ad0 | 1120 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 1121 | struct pnv_phb *phb = hose->private_data; |
1e916772 | 1122 | struct pnv_ioda_pe *pe = NULL; |
ccd1c191 GS |
1123 | unsigned int pe_num; |
1124 | ||
1125 | /* | |
1126 | * In partial hotplug case, the PE instance might be still alive. | |
1127 | * We should reuse it instead of allocating a new one. | |
1128 | */ | |
1129 | pe_num = phb->ioda.pe_rmap[bus->number << 8]; | |
1130 | if (pe_num != IODA_INVALID_PE) { | |
1131 | pe = &phb->ioda.pe_array[pe_num]; | |
1132 | pnv_ioda_setup_same_PE(bus, pe); | |
1133 | return NULL; | |
1134 | } | |
262af557 | 1135 | |
63803c39 GS |
1136 | /* PE number for root bus should have been reserved */ |
1137 | if (pci_is_root_bus(bus) && | |
1138 | phb->ioda.root_pe_idx != IODA_INVALID_PE) | |
1139 | pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; | |
1140 | ||
262af557 | 1141 | /* Check if PE is determined by M64 */ |
63803c39 | 1142 | if (!pe && phb->pick_m64_pe) |
1e916772 | 1143 | pe = phb->pick_m64_pe(bus, all); |
262af557 GC |
1144 | |
1145 | /* The PE number isn't pinned by M64 */ | |
1e916772 GS |
1146 | if (!pe) |
1147 | pe = pnv_ioda_alloc_pe(phb); | |
184cd4a3 | 1148 | |
1e916772 | 1149 | if (!pe) { |
fb446ad0 GS |
1150 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
1151 | __func__, pci_domain_nr(bus), bus->number); | |
1e916772 | 1152 | return NULL; |
184cd4a3 BH |
1153 | } |
1154 | ||
262af557 | 1155 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
1156 | pe->pbus = bus; |
1157 | pe->pdev = NULL; | |
184cd4a3 | 1158 | pe->mve_number = -1; |
b918c62e | 1159 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 | 1160 | |
fb446ad0 | 1161 | if (all) |
1f52f176 | 1162 | pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", |
1e916772 | 1163 | bus->busn_res.start, bus->busn_res.end, pe->pe_number); |
fb446ad0 | 1164 | else |
1f52f176 | 1165 | pe_info(pe, "Secondary bus %d associated with PE#%x\n", |
1e916772 | 1166 | bus->busn_res.start, pe->pe_number); |
184cd4a3 BH |
1167 | |
1168 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1169 | /* XXX What do we do here ? */ | |
1e916772 | 1170 | pnv_ioda_free_pe(pe); |
184cd4a3 | 1171 | pe->pbus = NULL; |
1e916772 | 1172 | return NULL; |
184cd4a3 BH |
1173 | } |
1174 | ||
1175 | /* Associate it with all child devices */ | |
1176 | pnv_ioda_setup_same_PE(bus, pe); | |
1177 | ||
7ebdf956 GS |
1178 | /* Put PE to the list */ |
1179 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1e916772 GS |
1180 | |
1181 | return pe; | |
184cd4a3 BH |
1182 | } |
1183 | ||
b521549a AP |
1184 | static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) |
1185 | { | |
1186 | int pe_num, found_pe = false, rc; | |
1187 | long rid; | |
1188 | struct pnv_ioda_pe *pe; | |
1189 | struct pci_dev *gpu_pdev; | |
1190 | struct pci_dn *npu_pdn; | |
1191 | struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); | |
1192 | struct pnv_phb *phb = hose->private_data; | |
1193 | ||
1194 | /* | |
1195 | * Due to a hardware errata PE#0 on the NPU is reserved for | |
1196 | * error handling. This means we only have three PEs remaining | |
1197 | * which need to be assigned to four links, implying some | |
1198 | * links must share PEs. | |
1199 | * | |
1200 | * To achieve this we assign PEs such that NPUs linking the | |
1201 | * same GPU get assigned the same PE. | |
1202 | */ | |
1203 | gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); | |
92b8f137 | 1204 | for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { |
b521549a AP |
1205 | pe = &phb->ioda.pe_array[pe_num]; |
1206 | if (!pe->pdev) | |
1207 | continue; | |
1208 | ||
1209 | if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { | |
1210 | /* | |
1211 | * This device has the same peer GPU so should | |
1212 | * be assigned the same PE as the existing | |
1213 | * peer NPU. | |
1214 | */ | |
1215 | dev_info(&npu_pdev->dev, | |
1f52f176 | 1216 | "Associating to existing PE %x\n", pe_num); |
b521549a AP |
1217 | pci_dev_get(npu_pdev); |
1218 | npu_pdn = pci_get_pdn(npu_pdev); | |
1219 | rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; | |
1220 | npu_pdn->pcidev = npu_pdev; | |
1221 | npu_pdn->pe_number = pe_num; | |
b521549a AP |
1222 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
1223 | ||
1224 | /* Map the PE to this link */ | |
1225 | rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, | |
1226 | OpalPciBusAll, | |
1227 | OPAL_COMPARE_RID_DEVICE_NUMBER, | |
1228 | OPAL_COMPARE_RID_FUNCTION_NUMBER, | |
1229 | OPAL_MAP_PE); | |
1230 | WARN_ON(rc != OPAL_SUCCESS); | |
1231 | found_pe = true; | |
1232 | break; | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | if (!found_pe) | |
1237 | /* | |
1238 | * Could not find an existing PE so allocate a new | |
1239 | * one. | |
1240 | */ | |
1241 | return pnv_ioda_setup_dev_PE(npu_pdev); | |
1242 | else | |
1243 | return pe; | |
1244 | } | |
1245 | ||
1246 | static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) | |
5d2aa710 | 1247 | { |
5d2aa710 AP |
1248 | struct pci_dev *pdev; |
1249 | ||
1250 | list_for_each_entry(pdev, &bus->devices, bus_list) | |
b521549a | 1251 | pnv_ioda_setup_npu_PE(pdev); |
5d2aa710 AP |
1252 | } |
1253 | ||
cad5cef6 | 1254 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
1255 | { |
1256 | struct pci_controller *hose, *tmp; | |
262af557 | 1257 | struct pnv_phb *phb; |
fb446ad0 GS |
1258 | |
1259 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
262af557 | 1260 | phb = hose->private_data; |
08f48f32 AP |
1261 | if (phb->type == PNV_PHB_NPU) { |
1262 | /* PE#0 is needed for error reporting */ | |
1263 | pnv_ioda_reserve_pe(phb, 0); | |
b521549a | 1264 | pnv_ioda_setup_npu_PEs(hose->bus); |
ccd1c191 | 1265 | } |
184cd4a3 BH |
1266 | } |
1267 | } | |
1268 | ||
a8b2f828 | 1269 | #ifdef CONFIG_PCI_IOV |
ee8222fe | 1270 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1271 | { |
1272 | struct pci_bus *bus; | |
1273 | struct pci_controller *hose; | |
1274 | struct pnv_phb *phb; | |
1275 | struct pci_dn *pdn; | |
02639b0e | 1276 | int i, j; |
ee8222fe | 1277 | int m64_bars; |
781a868f WY |
1278 | |
1279 | bus = pdev->bus; | |
1280 | hose = pci_bus_to_host(bus); | |
1281 | phb = hose->private_data; | |
1282 | pdn = pci_get_pdn(pdev); | |
1283 | ||
ee8222fe WY |
1284 | if (pdn->m64_single_mode) |
1285 | m64_bars = num_vfs; | |
1286 | else | |
1287 | m64_bars = 1; | |
1288 | ||
02639b0e | 1289 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
ee8222fe WY |
1290 | for (j = 0; j < m64_bars; j++) { |
1291 | if (pdn->m64_map[j][i] == IODA_INVALID_M64) | |
02639b0e WY |
1292 | continue; |
1293 | opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe WY |
1294 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); |
1295 | clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); | |
1296 | pdn->m64_map[j][i] = IODA_INVALID_M64; | |
02639b0e | 1297 | } |
781a868f | 1298 | |
ee8222fe | 1299 | kfree(pdn->m64_map); |
781a868f WY |
1300 | return 0; |
1301 | } | |
1302 | ||
02639b0e | 1303 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1304 | { |
1305 | struct pci_bus *bus; | |
1306 | struct pci_controller *hose; | |
1307 | struct pnv_phb *phb; | |
1308 | struct pci_dn *pdn; | |
1309 | unsigned int win; | |
1310 | struct resource *res; | |
02639b0e | 1311 | int i, j; |
781a868f | 1312 | int64_t rc; |
02639b0e WY |
1313 | int total_vfs; |
1314 | resource_size_t size, start; | |
1315 | int pe_num; | |
ee8222fe | 1316 | int m64_bars; |
781a868f WY |
1317 | |
1318 | bus = pdev->bus; | |
1319 | hose = pci_bus_to_host(bus); | |
1320 | phb = hose->private_data; | |
1321 | pdn = pci_get_pdn(pdev); | |
02639b0e | 1322 | total_vfs = pci_sriov_get_totalvfs(pdev); |
781a868f | 1323 | |
ee8222fe WY |
1324 | if (pdn->m64_single_mode) |
1325 | m64_bars = num_vfs; | |
1326 | else | |
1327 | m64_bars = 1; | |
1328 | ||
fb37e128 ME |
1329 | pdn->m64_map = kmalloc_array(m64_bars, |
1330 | sizeof(*pdn->m64_map), | |
1331 | GFP_KERNEL); | |
ee8222fe WY |
1332 | if (!pdn->m64_map) |
1333 | return -ENOMEM; | |
1334 | /* Initialize the m64_map to IODA_INVALID_M64 */ | |
1335 | for (i = 0; i < m64_bars ; i++) | |
1336 | for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) | |
1337 | pdn->m64_map[i][j] = IODA_INVALID_M64; | |
02639b0e | 1338 | |
781a868f WY |
1339 | |
1340 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1341 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
1342 | if (!res->flags || !res->parent) | |
1343 | continue; | |
1344 | ||
ee8222fe | 1345 | for (j = 0; j < m64_bars; j++) { |
02639b0e WY |
1346 | do { |
1347 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, | |
1348 | phb->ioda.m64_bar_idx + 1, 0); | |
1349 | ||
1350 | if (win >= phb->ioda.m64_bar_idx + 1) | |
1351 | goto m64_failed; | |
1352 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); | |
1353 | ||
ee8222fe | 1354 | pdn->m64_map[j][i] = win; |
02639b0e | 1355 | |
ee8222fe | 1356 | if (pdn->m64_single_mode) { |
02639b0e WY |
1357 | size = pci_iov_resource_size(pdev, |
1358 | PCI_IOV_RESOURCES + i); | |
02639b0e WY |
1359 | start = res->start + size * j; |
1360 | } else { | |
1361 | size = resource_size(res); | |
1362 | start = res->start; | |
1363 | } | |
1364 | ||
1365 | /* Map the M64 here */ | |
ee8222fe | 1366 | if (pdn->m64_single_mode) { |
be283eeb | 1367 | pe_num = pdn->pe_num_map[j]; |
02639b0e WY |
1368 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
1369 | pe_num, OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1370 | pdn->m64_map[j][i], 0); |
02639b0e WY |
1371 | } |
1372 | ||
1373 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
1374 | OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1375 | pdn->m64_map[j][i], |
02639b0e WY |
1376 | start, |
1377 | 0, /* unused */ | |
1378 | size); | |
781a868f | 1379 | |
781a868f | 1380 | |
02639b0e WY |
1381 | if (rc != OPAL_SUCCESS) { |
1382 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", | |
1383 | win, rc); | |
1384 | goto m64_failed; | |
1385 | } | |
781a868f | 1386 | |
ee8222fe | 1387 | if (pdn->m64_single_mode) |
02639b0e | 1388 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
ee8222fe | 1389 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); |
02639b0e WY |
1390 | else |
1391 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe | 1392 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); |
781a868f | 1393 | |
02639b0e WY |
1394 | if (rc != OPAL_SUCCESS) { |
1395 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", | |
1396 | win, rc); | |
1397 | goto m64_failed; | |
1398 | } | |
781a868f WY |
1399 | } |
1400 | } | |
1401 | return 0; | |
1402 | ||
1403 | m64_failed: | |
ee8222fe | 1404 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1405 | return -EBUSY; |
1406 | } | |
1407 | ||
c035e37b AK |
1408 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
1409 | int num); | |
1410 | static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); | |
1411 | ||
781a868f WY |
1412 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) |
1413 | { | |
781a868f | 1414 | struct iommu_table *tbl; |
781a868f WY |
1415 | int64_t rc; |
1416 | ||
b348aa65 | 1417 | tbl = pe->table_group.tables[0]; |
c035e37b | 1418 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
781a868f WY |
1419 | if (rc) |
1420 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
1421 | ||
c035e37b | 1422 | pnv_pci_ioda2_set_bypass(pe, false); |
0eaf4def AK |
1423 | if (pe->table_group.group) { |
1424 | iommu_group_put(pe->table_group.group); | |
1425 | BUG_ON(pe->table_group.group); | |
ac9a5889 | 1426 | } |
aca6913f | 1427 | pnv_pci_ioda2_table_free_pages(tbl); |
781a868f | 1428 | iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); |
781a868f WY |
1429 | } |
1430 | ||
ee8222fe | 1431 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) |
781a868f WY |
1432 | { |
1433 | struct pci_bus *bus; | |
1434 | struct pci_controller *hose; | |
1435 | struct pnv_phb *phb; | |
1436 | struct pnv_ioda_pe *pe, *pe_n; | |
1437 | struct pci_dn *pdn; | |
1438 | ||
1439 | bus = pdev->bus; | |
1440 | hose = pci_bus_to_host(bus); | |
1441 | phb = hose->private_data; | |
02639b0e | 1442 | pdn = pci_get_pdn(pdev); |
781a868f WY |
1443 | |
1444 | if (!pdev->is_physfn) | |
1445 | return; | |
1446 | ||
781a868f WY |
1447 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
1448 | if (pe->parent_dev != pdev) | |
1449 | continue; | |
1450 | ||
1451 | pnv_pci_ioda2_release_dma_pe(pdev, pe); | |
1452 | ||
1453 | /* Remove from list */ | |
1454 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1455 | list_del(&pe->list); | |
1456 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1457 | ||
1458 | pnv_ioda_deconfigure_pe(phb, pe); | |
1459 | ||
1e916772 | 1460 | pnv_ioda_free_pe(pe); |
781a868f WY |
1461 | } |
1462 | } | |
1463 | ||
1464 | void pnv_pci_sriov_disable(struct pci_dev *pdev) | |
1465 | { | |
1466 | struct pci_bus *bus; | |
1467 | struct pci_controller *hose; | |
1468 | struct pnv_phb *phb; | |
1e916772 | 1469 | struct pnv_ioda_pe *pe; |
781a868f | 1470 | struct pci_dn *pdn; |
be283eeb | 1471 | u16 num_vfs, i; |
781a868f WY |
1472 | |
1473 | bus = pdev->bus; | |
1474 | hose = pci_bus_to_host(bus); | |
1475 | phb = hose->private_data; | |
1476 | pdn = pci_get_pdn(pdev); | |
781a868f WY |
1477 | num_vfs = pdn->num_vfs; |
1478 | ||
1479 | /* Release VF PEs */ | |
ee8222fe | 1480 | pnv_ioda_release_vf_PE(pdev); |
781a868f WY |
1481 | |
1482 | if (phb->type == PNV_PHB_IODA2) { | |
ee8222fe | 1483 | if (!pdn->m64_single_mode) |
be283eeb | 1484 | pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); |
781a868f WY |
1485 | |
1486 | /* Release M64 windows */ | |
ee8222fe | 1487 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1488 | |
1489 | /* Release PE numbers */ | |
be283eeb WY |
1490 | if (pdn->m64_single_mode) { |
1491 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1492 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
1493 | continue; | |
1494 | ||
1495 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; | |
1496 | pnv_ioda_free_pe(pe); | |
be283eeb WY |
1497 | } |
1498 | } else | |
1499 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1500 | /* Releasing pe_num_map */ | |
1501 | kfree(pdn->pe_num_map); | |
781a868f WY |
1502 | } |
1503 | } | |
1504 | ||
1505 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
1506 | struct pnv_ioda_pe *pe); | |
1507 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) | |
1508 | { | |
1509 | struct pci_bus *bus; | |
1510 | struct pci_controller *hose; | |
1511 | struct pnv_phb *phb; | |
1512 | struct pnv_ioda_pe *pe; | |
1513 | int pe_num; | |
1514 | u16 vf_index; | |
1515 | struct pci_dn *pdn; | |
1516 | ||
1517 | bus = pdev->bus; | |
1518 | hose = pci_bus_to_host(bus); | |
1519 | phb = hose->private_data; | |
1520 | pdn = pci_get_pdn(pdev); | |
1521 | ||
1522 | if (!pdev->is_physfn) | |
1523 | return; | |
1524 | ||
1525 | /* Reserve PE for each VF */ | |
1526 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { | |
be283eeb WY |
1527 | if (pdn->m64_single_mode) |
1528 | pe_num = pdn->pe_num_map[vf_index]; | |
1529 | else | |
1530 | pe_num = *pdn->pe_num_map + vf_index; | |
781a868f WY |
1531 | |
1532 | pe = &phb->ioda.pe_array[pe_num]; | |
1533 | pe->pe_number = pe_num; | |
1534 | pe->phb = phb; | |
1535 | pe->flags = PNV_IODA_PE_VF; | |
1536 | pe->pbus = NULL; | |
1537 | pe->parent_dev = pdev; | |
781a868f WY |
1538 | pe->mve_number = -1; |
1539 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | | |
1540 | pci_iov_virtfn_devfn(pdev, vf_index); | |
1541 | ||
1f52f176 | 1542 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", |
781a868f WY |
1543 | hose->global_number, pdev->bus->number, |
1544 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), | |
1545 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); | |
1546 | ||
1547 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1548 | /* XXX What do we do here ? */ | |
1e916772 | 1549 | pnv_ioda_free_pe(pe); |
781a868f WY |
1550 | pe->pdev = NULL; |
1551 | continue; | |
1552 | } | |
1553 | ||
781a868f WY |
1554 | /* Put PE to the list */ |
1555 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1556 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1557 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1558 | ||
1559 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
1560 | } | |
1561 | } | |
1562 | ||
1563 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1564 | { | |
1565 | struct pci_bus *bus; | |
1566 | struct pci_controller *hose; | |
1567 | struct pnv_phb *phb; | |
1e916772 | 1568 | struct pnv_ioda_pe *pe; |
781a868f WY |
1569 | struct pci_dn *pdn; |
1570 | int ret; | |
be283eeb | 1571 | u16 i; |
781a868f WY |
1572 | |
1573 | bus = pdev->bus; | |
1574 | hose = pci_bus_to_host(bus); | |
1575 | phb = hose->private_data; | |
1576 | pdn = pci_get_pdn(pdev); | |
1577 | ||
1578 | if (phb->type == PNV_PHB_IODA2) { | |
b0331854 WY |
1579 | if (!pdn->vfs_expanded) { |
1580 | dev_info(&pdev->dev, "don't support this SRIOV device" | |
1581 | " with non 64bit-prefetchable IOV BAR\n"); | |
1582 | return -ENOSPC; | |
1583 | } | |
1584 | ||
ee8222fe WY |
1585 | /* |
1586 | * When M64 BARs functions in Single PE mode, the number of VFs | |
1587 | * could be enabled must be less than the number of M64 BARs. | |
1588 | */ | |
1589 | if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { | |
1590 | dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); | |
1591 | return -EBUSY; | |
1592 | } | |
1593 | ||
be283eeb WY |
1594 | /* Allocating pe_num_map */ |
1595 | if (pdn->m64_single_mode) | |
fb37e128 ME |
1596 | pdn->pe_num_map = kmalloc_array(num_vfs, |
1597 | sizeof(*pdn->pe_num_map), | |
1598 | GFP_KERNEL); | |
be283eeb WY |
1599 | else |
1600 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); | |
1601 | ||
1602 | if (!pdn->pe_num_map) | |
1603 | return -ENOMEM; | |
1604 | ||
1605 | if (pdn->m64_single_mode) | |
1606 | for (i = 0; i < num_vfs; i++) | |
1607 | pdn->pe_num_map[i] = IODA_INVALID_PE; | |
1608 | ||
781a868f | 1609 | /* Calculate available PE for required VFs */ |
be283eeb WY |
1610 | if (pdn->m64_single_mode) { |
1611 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1612 | pe = pnv_ioda_alloc_pe(phb); |
1613 | if (!pe) { | |
be283eeb WY |
1614 | ret = -EBUSY; |
1615 | goto m64_failed; | |
1616 | } | |
1e916772 GS |
1617 | |
1618 | pdn->pe_num_map[i] = pe->pe_number; | |
be283eeb WY |
1619 | } |
1620 | } else { | |
1621 | mutex_lock(&phb->ioda.pe_alloc_mutex); | |
1622 | *pdn->pe_num_map = bitmap_find_next_zero_area( | |
92b8f137 | 1623 | phb->ioda.pe_alloc, phb->ioda.total_pe_num, |
be283eeb | 1624 | 0, num_vfs, 0); |
92b8f137 | 1625 | if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { |
be283eeb WY |
1626 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
1627 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); | |
1628 | kfree(pdn->pe_num_map); | |
1629 | return -EBUSY; | |
1630 | } | |
1631 | bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
781a868f | 1632 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
781a868f | 1633 | } |
781a868f | 1634 | pdn->num_vfs = num_vfs; |
781a868f WY |
1635 | |
1636 | /* Assign M64 window accordingly */ | |
02639b0e | 1637 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
781a868f WY |
1638 | if (ret) { |
1639 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); | |
1640 | goto m64_failed; | |
1641 | } | |
1642 | ||
1643 | /* | |
1644 | * When using one M64 BAR to map one IOV BAR, we need to shift | |
1645 | * the IOV BAR according to the PE# allocated to the VFs. | |
1646 | * Otherwise, the PE# for the VF will conflict with others. | |
1647 | */ | |
ee8222fe | 1648 | if (!pdn->m64_single_mode) { |
be283eeb | 1649 | ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); |
02639b0e WY |
1650 | if (ret) |
1651 | goto m64_failed; | |
1652 | } | |
781a868f WY |
1653 | } |
1654 | ||
1655 | /* Setup VF PEs */ | |
1656 | pnv_ioda_setup_vf_PE(pdev, num_vfs); | |
1657 | ||
1658 | return 0; | |
1659 | ||
1660 | m64_failed: | |
be283eeb WY |
1661 | if (pdn->m64_single_mode) { |
1662 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1663 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
1664 | continue; | |
1665 | ||
1666 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; | |
1667 | pnv_ioda_free_pe(pe); | |
be283eeb WY |
1668 | } |
1669 | } else | |
1670 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1671 | ||
1672 | /* Releasing pe_num_map */ | |
1673 | kfree(pdn->pe_num_map); | |
781a868f WY |
1674 | |
1675 | return ret; | |
1676 | } | |
1677 | ||
a8b2f828 GS |
1678 | int pcibios_sriov_disable(struct pci_dev *pdev) |
1679 | { | |
781a868f WY |
1680 | pnv_pci_sriov_disable(pdev); |
1681 | ||
a8b2f828 GS |
1682 | /* Release PCI data */ |
1683 | remove_dev_pci_data(pdev); | |
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1688 | { | |
1689 | /* Allocate PCI data */ | |
1690 | add_dev_pci_data(pdev); | |
781a868f | 1691 | |
ee8222fe | 1692 | return pnv_pci_sriov_enable(pdev, num_vfs); |
a8b2f828 GS |
1693 | } |
1694 | #endif /* CONFIG_PCI_IOV */ | |
1695 | ||
959c9bdd | 1696 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 1697 | { |
b72c1f65 | 1698 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 1699 | struct pnv_ioda_pe *pe; |
184cd4a3 | 1700 | |
959c9bdd GS |
1701 | /* |
1702 | * The function can be called while the PE# | |
1703 | * hasn't been assigned. Do nothing for the | |
1704 | * case. | |
1705 | */ | |
1706 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
1707 | return; | |
184cd4a3 | 1708 | |
959c9bdd | 1709 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
cd15b048 | 1710 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
0e1ffef0 | 1711 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); |
b348aa65 | 1712 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
4617082e AK |
1713 | /* |
1714 | * Note: iommu_add_device() will fail here as | |
1715 | * for physical PE: the device is already added by now; | |
1716 | * for virtual PE: sysfs entries are not ready yet and | |
1717 | * tce_iommu_bus_notifier will add the device to a group later. | |
1718 | */ | |
184cd4a3 BH |
1719 | } |
1720 | ||
763d2d8d | 1721 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
cd15b048 | 1722 | { |
763d2d8d DA |
1723 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1724 | struct pnv_phb *phb = hose->private_data; | |
cd15b048 BH |
1725 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1726 | struct pnv_ioda_pe *pe; | |
1727 | uint64_t top; | |
1728 | bool bypass = false; | |
1729 | ||
1730 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1731 | return -ENODEV;; | |
1732 | ||
1733 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1734 | if (pe->tce_bypass_enabled) { | |
1735 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; | |
1736 | bypass = (dma_mask >= top); | |
1737 | } | |
1738 | ||
1739 | if (bypass) { | |
1740 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); | |
1741 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
cd15b048 BH |
1742 | } else { |
1743 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | |
1744 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | |
cd15b048 | 1745 | } |
a32305bf | 1746 | *pdev->dev.dma_mask = dma_mask; |
5d2aa710 AP |
1747 | |
1748 | /* Update peer npu devices */ | |
f9f83456 | 1749 | pnv_npu_try_dma_set_bypass(pdev, bypass); |
5d2aa710 | 1750 | |
cd15b048 BH |
1751 | return 0; |
1752 | } | |
1753 | ||
53522982 | 1754 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) |
fe7e85c6 | 1755 | { |
53522982 AD |
1756 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1757 | struct pnv_phb *phb = hose->private_data; | |
fe7e85c6 GS |
1758 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1759 | struct pnv_ioda_pe *pe; | |
1760 | u64 end, mask; | |
1761 | ||
1762 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1763 | return 0; | |
1764 | ||
1765 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1766 | if (!pe->tce_bypass_enabled) | |
1767 | return __dma_get_required_mask(&pdev->dev); | |
1768 | ||
1769 | ||
1770 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); | |
1771 | mask = 1ULL << (fls64(end) - 1); | |
1772 | mask += mask - 1; | |
1773 | ||
1774 | return mask; | |
1775 | } | |
1776 | ||
dff4a39e | 1777 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
ea30e99e | 1778 | struct pci_bus *bus) |
74251fe2 BH |
1779 | { |
1780 | struct pci_dev *dev; | |
1781 | ||
1782 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b348aa65 | 1783 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
e91c2511 | 1784 | set_dma_offset(&dev->dev, pe->tce_bypass_base); |
4617082e | 1785 | iommu_add_device(&dev->dev); |
dff4a39e | 1786 | |
5c89a87d | 1787 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
ea30e99e | 1788 | pnv_ioda_setup_bus_dma(pe, dev->subordinate); |
74251fe2 BH |
1789 | } |
1790 | } | |
1791 | ||
fd141d1a BH |
1792 | static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, |
1793 | bool real_mode) | |
1794 | { | |
1795 | return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : | |
1796 | (phb->regs + 0x210); | |
1797 | } | |
1798 | ||
a34ab7c3 | 1799 | static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, |
decbda25 | 1800 | unsigned long index, unsigned long npages, bool rm) |
4cce9550 | 1801 | { |
0eaf4def AK |
1802 | struct iommu_table_group_link *tgl = list_first_entry_or_null( |
1803 | &tbl->it_group_list, struct iommu_table_group_link, | |
1804 | next); | |
1805 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, | |
b348aa65 | 1806 | struct pnv_ioda_pe, table_group); |
fd141d1a | 1807 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
4cce9550 GS |
1808 | unsigned long start, end, inc; |
1809 | ||
decbda25 AK |
1810 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
1811 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + | |
1812 | npages - 1); | |
4cce9550 | 1813 | |
08acce1c BH |
1814 | /* p7ioc-style invalidation, 2 TCEs per write */ |
1815 | start |= (1ull << 63); | |
1816 | end |= (1ull << 63); | |
1817 | inc = 16; | |
4cce9550 GS |
1818 | end |= inc - 1; /* round up end to be different than start */ |
1819 | ||
1820 | mb(); /* Ensure above stores are visible */ | |
1821 | while (start <= end) { | |
8e0a1611 | 1822 | if (rm) |
3ad26e5c | 1823 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1824 | else |
3ad26e5c | 1825 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1826 | start += inc; |
1827 | } | |
1828 | ||
1829 | /* | |
1830 | * The iommu layer will do another mb() for us on build() | |
1831 | * and we don't care on free() | |
1832 | */ | |
1833 | } | |
1834 | ||
decbda25 AK |
1835 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
1836 | long npages, unsigned long uaddr, | |
1837 | enum dma_data_direction direction, | |
00085f1e | 1838 | unsigned long attrs) |
decbda25 AK |
1839 | { |
1840 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, | |
1841 | attrs); | |
1842 | ||
08acce1c | 1843 | if (!ret) |
a34ab7c3 | 1844 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
decbda25 AK |
1845 | |
1846 | return ret; | |
1847 | } | |
1848 | ||
05c6cfb9 AK |
1849 | #ifdef CONFIG_IOMMU_API |
1850 | static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, | |
1851 | unsigned long *hpa, enum dma_data_direction *direction) | |
1852 | { | |
1853 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1854 | ||
08acce1c | 1855 | if (!ret) |
a34ab7c3 | 1856 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); |
05c6cfb9 AK |
1857 | |
1858 | return ret; | |
1859 | } | |
1860 | #endif | |
1861 | ||
decbda25 AK |
1862 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, |
1863 | long npages) | |
1864 | { | |
1865 | pnv_tce_free(tbl, index, npages); | |
1866 | ||
08acce1c | 1867 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
decbda25 AK |
1868 | } |
1869 | ||
da004c36 | 1870 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
decbda25 | 1871 | .set = pnv_ioda1_tce_build, |
05c6cfb9 AK |
1872 | #ifdef CONFIG_IOMMU_API |
1873 | .exchange = pnv_ioda1_tce_xchg, | |
1874 | #endif | |
decbda25 | 1875 | .clear = pnv_ioda1_tce_free, |
da004c36 AK |
1876 | .get = pnv_tce_get, |
1877 | }; | |
1878 | ||
a34ab7c3 BH |
1879 | #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) |
1880 | #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) | |
1881 | #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) | |
bef9253f | 1882 | |
a34ab7c3 | 1883 | void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
0bbcdb43 | 1884 | { |
fd141d1a | 1885 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); |
a34ab7c3 | 1886 | const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; |
0bbcdb43 AK |
1887 | |
1888 | mb(); /* Ensure previous TCE table stores are visible */ | |
1889 | if (rm) | |
fd141d1a | 1890 | __raw_rm_writeq(cpu_to_be64(val), invalidate); |
0bbcdb43 | 1891 | else |
fd141d1a | 1892 | __raw_writeq(cpu_to_be64(val), invalidate); |
0bbcdb43 AK |
1893 | } |
1894 | ||
a34ab7c3 | 1895 | static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
5780fb04 AK |
1896 | { |
1897 | /* 01xb - invalidate TCEs that match the specified PE# */ | |
fd141d1a | 1898 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); |
a34ab7c3 | 1899 | unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); |
5780fb04 AK |
1900 | |
1901 | mb(); /* Ensure above stores are visible */ | |
fd141d1a | 1902 | __raw_writeq(cpu_to_be64(val), invalidate); |
5780fb04 AK |
1903 | } |
1904 | ||
fd141d1a BH |
1905 | static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, |
1906 | unsigned shift, unsigned long index, | |
1907 | unsigned long npages) | |
4cce9550 | 1908 | { |
4d902195 | 1909 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
4cce9550 | 1910 | unsigned long start, end, inc; |
4cce9550 GS |
1911 | |
1912 | /* We'll invalidate DMA address in PE scope */ | |
a34ab7c3 | 1913 | start = PHB3_TCE_KILL_INVAL_ONE; |
fd141d1a | 1914 | start |= (pe->pe_number & 0xFF); |
4cce9550 GS |
1915 | end = start; |
1916 | ||
1917 | /* Figure out the start, end and step */ | |
decbda25 AK |
1918 | start |= (index << shift); |
1919 | end |= ((index + npages - 1) << shift); | |
b0376c9b | 1920 | inc = (0x1ull << shift); |
4cce9550 GS |
1921 | mb(); |
1922 | ||
1923 | while (start <= end) { | |
8e0a1611 | 1924 | if (rm) |
3ad26e5c | 1925 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1926 | else |
3ad26e5c | 1927 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1928 | start += inc; |
1929 | } | |
1930 | } | |
1931 | ||
f0228c41 BH |
1932 | static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
1933 | { | |
1934 | struct pnv_phb *phb = pe->phb; | |
1935 | ||
1936 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) | |
1937 | pnv_pci_phb3_tce_invalidate_pe(pe); | |
1938 | else | |
1939 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, | |
1940 | pe->pe_number, 0, 0, 0); | |
1941 | } | |
1942 | ||
e57080f1 AK |
1943 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
1944 | unsigned long index, unsigned long npages, bool rm) | |
1945 | { | |
1946 | struct iommu_table_group_link *tgl; | |
1947 | ||
1948 | list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { | |
1949 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, | |
1950 | struct pnv_ioda_pe, table_group); | |
f0228c41 BH |
1951 | struct pnv_phb *phb = pe->phb; |
1952 | unsigned int shift = tbl->it_page_shift; | |
1953 | ||
616badd2 AP |
1954 | /* |
1955 | * NVLink1 can use the TCE kill register directly as | |
1956 | * it's the same as PHB3. NVLink2 is different and | |
1957 | * should go via the OPAL call. | |
1958 | */ | |
1959 | if (phb->model == PNV_PHB_MODEL_NPU) { | |
0bbcdb43 AK |
1960 | /* |
1961 | * The NVLink hardware does not support TCE kill | |
1962 | * per TCE entry so we have to invalidate | |
1963 | * the entire cache for it. | |
1964 | */ | |
f0228c41 | 1965 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); |
85674868 AK |
1966 | continue; |
1967 | } | |
f0228c41 BH |
1968 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) |
1969 | pnv_pci_phb3_tce_invalidate(pe, rm, shift, | |
1970 | index, npages); | |
f0228c41 BH |
1971 | else |
1972 | opal_pci_tce_kill(phb->opal_id, | |
1973 | OPAL_PCI_TCE_KILL_PAGES, | |
1974 | pe->pe_number, 1u << shift, | |
1975 | index << shift, npages); | |
e57080f1 AK |
1976 | } |
1977 | } | |
1978 | ||
decbda25 AK |
1979 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
1980 | long npages, unsigned long uaddr, | |
1981 | enum dma_data_direction direction, | |
00085f1e | 1982 | unsigned long attrs) |
4cce9550 | 1983 | { |
decbda25 AK |
1984 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
1985 | attrs); | |
4cce9550 | 1986 | |
08acce1c | 1987 | if (!ret) |
decbda25 AK |
1988 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
1989 | ||
1990 | return ret; | |
1991 | } | |
1992 | ||
05c6cfb9 AK |
1993 | #ifdef CONFIG_IOMMU_API |
1994 | static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, | |
1995 | unsigned long *hpa, enum dma_data_direction *direction) | |
1996 | { | |
1997 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1998 | ||
08acce1c | 1999 | if (!ret) |
05c6cfb9 AK |
2000 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); |
2001 | ||
2002 | return ret; | |
2003 | } | |
2004 | #endif | |
2005 | ||
decbda25 AK |
2006 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, |
2007 | long npages) | |
2008 | { | |
2009 | pnv_tce_free(tbl, index, npages); | |
2010 | ||
08acce1c | 2011 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
4cce9550 GS |
2012 | } |
2013 | ||
4793d65d AK |
2014 | static void pnv_ioda2_table_free(struct iommu_table *tbl) |
2015 | { | |
2016 | pnv_pci_ioda2_table_free_pages(tbl); | |
2017 | iommu_free_table(tbl, "pnv"); | |
2018 | } | |
2019 | ||
da004c36 | 2020 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
decbda25 | 2021 | .set = pnv_ioda2_tce_build, |
05c6cfb9 AK |
2022 | #ifdef CONFIG_IOMMU_API |
2023 | .exchange = pnv_ioda2_tce_xchg, | |
2024 | #endif | |
decbda25 | 2025 | .clear = pnv_ioda2_tce_free, |
da004c36 | 2026 | .get = pnv_tce_get, |
4793d65d | 2027 | .free = pnv_ioda2_table_free, |
da004c36 AK |
2028 | }; |
2029 | ||
801846d1 GS |
2030 | static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) |
2031 | { | |
2032 | unsigned int *weight = (unsigned int *)data; | |
2033 | ||
2034 | /* This is quite simplistic. The "base" weight of a device | |
2035 | * is 10. 0 means no DMA is to be accounted for it. | |
2036 | */ | |
2037 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
2038 | return 0; | |
2039 | ||
2040 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
2041 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
2042 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
2043 | *weight += 3; | |
2044 | else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
2045 | *weight += 15; | |
2046 | else | |
2047 | *weight += 10; | |
2048 | ||
2049 | return 0; | |
2050 | } | |
2051 | ||
2052 | static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) | |
2053 | { | |
2054 | unsigned int weight = 0; | |
2055 | ||
2056 | /* SRIOV VF has same DMA32 weight as its PF */ | |
2057 | #ifdef CONFIG_PCI_IOV | |
2058 | if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { | |
2059 | pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); | |
2060 | return weight; | |
2061 | } | |
2062 | #endif | |
2063 | ||
2064 | if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { | |
2065 | pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); | |
2066 | } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { | |
2067 | struct pci_dev *pdev; | |
2068 | ||
2069 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) | |
2070 | pnv_pci_ioda_dev_dma_weight(pdev, &weight); | |
2071 | } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { | |
2072 | pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); | |
2073 | } | |
2074 | ||
2075 | return weight; | |
2076 | } | |
2077 | ||
b30d936f | 2078 | static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, |
2b923ed1 | 2079 | struct pnv_ioda_pe *pe) |
184cd4a3 BH |
2080 | { |
2081 | ||
2082 | struct page *tce_mem = NULL; | |
184cd4a3 | 2083 | struct iommu_table *tbl; |
2b923ed1 GS |
2084 | unsigned int weight, total_weight = 0; |
2085 | unsigned int tce32_segsz, base, segs, avail, i; | |
184cd4a3 BH |
2086 | int64_t rc; |
2087 | void *addr; | |
2088 | ||
184cd4a3 BH |
2089 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
2090 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
2091 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
2b923ed1 GS |
2092 | weight = pnv_pci_ioda_pe_dma_weight(pe); |
2093 | if (!weight) | |
2094 | return; | |
2095 | ||
2096 | pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, | |
2097 | &total_weight); | |
2098 | segs = (weight * phb->ioda.dma32_count) / total_weight; | |
2099 | if (!segs) | |
2100 | segs = 1; | |
184cd4a3 | 2101 | |
2b923ed1 GS |
2102 | /* |
2103 | * Allocate contiguous DMA32 segments. We begin with the expected | |
2104 | * number of segments. With one more attempt, the number of DMA32 | |
2105 | * segments to be allocated is decreased by one until one segment | |
2106 | * is allocated successfully. | |
2107 | */ | |
2108 | do { | |
2109 | for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { | |
2110 | for (avail = 0, i = base; i < base + segs; i++) { | |
2111 | if (phb->ioda.dma32_segmap[i] == | |
2112 | IODA_INVALID_PE) | |
2113 | avail++; | |
2114 | } | |
2115 | ||
2116 | if (avail == segs) | |
2117 | goto found; | |
2118 | } | |
2119 | } while (--segs); | |
2120 | ||
2121 | if (!segs) { | |
2122 | pe_warn(pe, "No available DMA32 segments\n"); | |
2123 | return; | |
2124 | } | |
2125 | ||
2126 | found: | |
0eaf4def | 2127 | tbl = pnv_pci_table_alloc(phb->hose->node); |
b348aa65 AK |
2128 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2129 | pe->pe_number); | |
0eaf4def | 2130 | pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); |
c5773822 | 2131 | |
184cd4a3 | 2132 | /* Grab a 32-bit TCE table */ |
2b923ed1 GS |
2133 | pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", |
2134 | weight, total_weight, base, segs); | |
184cd4a3 | 2135 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", |
acce971c GS |
2136 | base * PNV_IODA1_DMA32_SEGSIZE, |
2137 | (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); | |
184cd4a3 BH |
2138 | |
2139 | /* XXX Currently, we allocate one big contiguous table for the | |
2140 | * TCEs. We only really need one chunk per 256M of TCE space | |
2141 | * (ie per segment) but that's an optimization for later, it | |
2142 | * requires some added smarts with our get/put_tce implementation | |
acce971c GS |
2143 | * |
2144 | * Each TCE page is 4KB in size and each TCE entry occupies 8 | |
2145 | * bytes | |
184cd4a3 | 2146 | */ |
acce971c | 2147 | tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); |
184cd4a3 | 2148 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, |
acce971c | 2149 | get_order(tce32_segsz * segs)); |
184cd4a3 BH |
2150 | if (!tce_mem) { |
2151 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
2152 | goto fail; | |
2153 | } | |
2154 | addr = page_address(tce_mem); | |
acce971c | 2155 | memset(addr, 0, tce32_segsz * segs); |
184cd4a3 BH |
2156 | |
2157 | /* Configure HW */ | |
2158 | for (i = 0; i < segs; i++) { | |
2159 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2160 | pe->pe_number, | |
2161 | base + i, 1, | |
acce971c GS |
2162 | __pa(addr) + tce32_segsz * i, |
2163 | tce32_segsz, IOMMU_PAGE_SIZE_4K); | |
184cd4a3 BH |
2164 | if (rc) { |
2165 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
2166 | " err %ld\n", rc); | |
2167 | goto fail; | |
2168 | } | |
2169 | } | |
2170 | ||
2b923ed1 GS |
2171 | /* Setup DMA32 segment mapping */ |
2172 | for (i = base; i < base + segs; i++) | |
2173 | phb->ioda.dma32_segmap[i] = pe->pe_number; | |
2174 | ||
184cd4a3 | 2175 | /* Setup linux iommu table */ |
acce971c GS |
2176 | pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, |
2177 | base * PNV_IODA1_DMA32_SEGSIZE, | |
2178 | IOMMU_PAGE_SHIFT_4K); | |
184cd4a3 | 2179 | |
da004c36 | 2180 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
4793d65d AK |
2181 | pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; |
2182 | pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; | |
184cd4a3 BH |
2183 | iommu_init_table(tbl, phb->hose->node); |
2184 | ||
781a868f | 2185 | if (pe->flags & PNV_IODA_PE_DEV) { |
4617082e AK |
2186 | /* |
2187 | * Setting table base here only for carrying iommu_group | |
2188 | * further down to let iommu_add_device() do the job. | |
2189 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2190 | */ | |
2191 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2192 | iommu_add_device(&pe->pdev->dev); | |
c5773822 | 2193 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2194 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
74251fe2 | 2195 | |
184cd4a3 BH |
2196 | return; |
2197 | fail: | |
2198 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
184cd4a3 | 2199 | if (tce_mem) |
acce971c | 2200 | __free_pages(tce_mem, get_order(tce32_segsz * segs)); |
0eaf4def AK |
2201 | if (tbl) { |
2202 | pnv_pci_unlink_table_and_group(tbl, &pe->table_group); | |
2203 | iommu_free_table(tbl, "pnv"); | |
2204 | } | |
184cd4a3 BH |
2205 | } |
2206 | ||
43cb60ab AK |
2207 | static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, |
2208 | int num, struct iommu_table *tbl) | |
2209 | { | |
2210 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2211 | table_group); | |
2212 | struct pnv_phb *phb = pe->phb; | |
2213 | int64_t rc; | |
bbb845c4 AK |
2214 | const unsigned long size = tbl->it_indirect_levels ? |
2215 | tbl->it_level_size : tbl->it_size; | |
43cb60ab AK |
2216 | const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
2217 | const __u64 win_size = tbl->it_size << tbl->it_page_shift; | |
2218 | ||
4793d65d | 2219 | pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, |
43cb60ab AK |
2220 | start_addr, start_addr + win_size - 1, |
2221 | IOMMU_PAGE_SIZE(tbl)); | |
2222 | ||
2223 | /* | |
2224 | * Map TCE table through TVT. The TVE index is the PE number | |
2225 | * shifted by 1 bit for 32-bits DMA space. | |
2226 | */ | |
2227 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2228 | pe->pe_number, | |
4793d65d | 2229 | (pe->pe_number << 1) + num, |
bbb845c4 | 2230 | tbl->it_indirect_levels + 1, |
43cb60ab | 2231 | __pa(tbl->it_base), |
bbb845c4 | 2232 | size << 3, |
43cb60ab AK |
2233 | IOMMU_PAGE_SIZE(tbl)); |
2234 | if (rc) { | |
2235 | pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); | |
2236 | return rc; | |
2237 | } | |
2238 | ||
2239 | pnv_pci_link_table_and_group(phb->hose->node, num, | |
2240 | tbl, &pe->table_group); | |
ed7d9a1d | 2241 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
43cb60ab AK |
2242 | |
2243 | return 0; | |
2244 | } | |
2245 | ||
f87a8864 | 2246 | static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) |
cd15b048 | 2247 | { |
cd15b048 BH |
2248 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
2249 | int64_t rc; | |
2250 | ||
2251 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); | |
2252 | if (enable) { | |
2253 | phys_addr_t top = memblock_end_of_DRAM(); | |
2254 | ||
2255 | top = roundup_pow_of_two(top); | |
2256 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2257 | pe->pe_number, | |
2258 | window_id, | |
2259 | pe->tce_bypass_base, | |
2260 | top); | |
2261 | } else { | |
2262 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2263 | pe->pe_number, | |
2264 | window_id, | |
2265 | pe->tce_bypass_base, | |
2266 | 0); | |
cd15b048 BH |
2267 | } |
2268 | if (rc) | |
2269 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); | |
2270 | else | |
2271 | pe->tce_bypass_enabled = enable; | |
2272 | } | |
2273 | ||
4793d65d AK |
2274 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
2275 | __u32 page_shift, __u64 window_size, __u32 levels, | |
2276 | struct iommu_table *tbl); | |
2277 | ||
2278 | static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, | |
2279 | int num, __u32 page_shift, __u64 window_size, __u32 levels, | |
2280 | struct iommu_table **ptbl) | |
2281 | { | |
2282 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2283 | table_group); | |
2284 | int nid = pe->phb->hose->node; | |
2285 | __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; | |
2286 | long ret; | |
2287 | struct iommu_table *tbl; | |
2288 | ||
2289 | tbl = pnv_pci_table_alloc(nid); | |
2290 | if (!tbl) | |
2291 | return -ENOMEM; | |
2292 | ||
2293 | ret = pnv_pci_ioda2_table_alloc_pages(nid, | |
2294 | bus_offset, page_shift, window_size, | |
2295 | levels, tbl); | |
2296 | if (ret) { | |
2297 | iommu_free_table(tbl, "pnv"); | |
2298 | return ret; | |
2299 | } | |
2300 | ||
2301 | tbl->it_ops = &pnv_ioda2_iommu_ops; | |
4793d65d AK |
2302 | |
2303 | *ptbl = tbl; | |
2304 | ||
2305 | return 0; | |
2306 | } | |
2307 | ||
46d3e1e1 AK |
2308 | static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) |
2309 | { | |
2310 | struct iommu_table *tbl = NULL; | |
2311 | long rc; | |
2312 | ||
fa144869 NA |
2313 | /* |
2314 | * crashkernel= specifies the kdump kernel's maximum memory at | |
2315 | * some offset and there is no guaranteed the result is a power | |
2316 | * of 2, which will cause errors later. | |
2317 | */ | |
2318 | const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); | |
2319 | ||
bb005455 NA |
2320 | /* |
2321 | * In memory constrained environments, e.g. kdump kernel, the | |
2322 | * DMA window can be larger than available memory, which will | |
2323 | * cause errors later. | |
2324 | */ | |
fa144869 | 2325 | const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); |
bb005455 | 2326 | |
46d3e1e1 AK |
2327 | rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, |
2328 | IOMMU_PAGE_SHIFT_4K, | |
bb005455 | 2329 | window_size, |
46d3e1e1 AK |
2330 | POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); |
2331 | if (rc) { | |
2332 | pe_err(pe, "Failed to create 32-bit TCE table, err %ld", | |
2333 | rc); | |
2334 | return rc; | |
2335 | } | |
2336 | ||
2337 | iommu_init_table(tbl, pe->phb->hose->node); | |
2338 | ||
2339 | rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); | |
2340 | if (rc) { | |
2341 | pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", | |
2342 | rc); | |
2343 | pnv_ioda2_table_free(tbl); | |
2344 | return rc; | |
2345 | } | |
2346 | ||
2347 | if (!pnv_iommu_bypass_disabled) | |
2348 | pnv_pci_ioda2_set_bypass(pe, true); | |
2349 | ||
46d3e1e1 AK |
2350 | /* |
2351 | * Setting table base here only for carrying iommu_group | |
2352 | * further down to let iommu_add_device() do the job. | |
2353 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2354 | */ | |
2355 | if (pe->flags & PNV_IODA_PE_DEV) | |
2356 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2357 | ||
2358 | return 0; | |
2359 | } | |
2360 | ||
b5926430 AK |
2361 | #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) |
2362 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, | |
2363 | int num) | |
2364 | { | |
2365 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2366 | table_group); | |
2367 | struct pnv_phb *phb = pe->phb; | |
2368 | long ret; | |
2369 | ||
2370 | pe_info(pe, "Removing DMA window #%d\n", num); | |
2371 | ||
2372 | ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
2373 | (pe->pe_number << 1) + num, | |
2374 | 0/* levels */, 0/* table address */, | |
2375 | 0/* table size */, 0/* page size */); | |
2376 | if (ret) | |
2377 | pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); | |
2378 | else | |
ed7d9a1d | 2379 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
b5926430 AK |
2380 | |
2381 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); | |
2382 | ||
2383 | return ret; | |
2384 | } | |
2385 | #endif | |
2386 | ||
f87a8864 | 2387 | #ifdef CONFIG_IOMMU_API |
00547193 AK |
2388 | static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, |
2389 | __u64 window_size, __u32 levels) | |
2390 | { | |
2391 | unsigned long bytes = 0; | |
2392 | const unsigned window_shift = ilog2(window_size); | |
2393 | unsigned entries_shift = window_shift - page_shift; | |
2394 | unsigned table_shift = entries_shift + 3; | |
2395 | unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); | |
2396 | unsigned long direct_table_size; | |
2397 | ||
2398 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || | |
2399 | (window_size > memory_hotplug_max()) || | |
2400 | !is_power_of_2(window_size)) | |
2401 | return 0; | |
2402 | ||
2403 | /* Calculate a direct table size from window_size and levels */ | |
2404 | entries_shift = (entries_shift + levels - 1) / levels; | |
2405 | table_shift = entries_shift + 3; | |
2406 | table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); | |
2407 | direct_table_size = 1UL << table_shift; | |
2408 | ||
2409 | for ( ; levels; --levels) { | |
2410 | bytes += _ALIGN_UP(tce_table_size, direct_table_size); | |
2411 | ||
2412 | tce_table_size /= direct_table_size; | |
2413 | tce_table_size <<= 3; | |
2414 | tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); | |
2415 | } | |
2416 | ||
2417 | return bytes; | |
2418 | } | |
2419 | ||
f87a8864 | 2420 | static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) |
cd15b048 | 2421 | { |
f87a8864 AK |
2422 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
2423 | table_group); | |
46d3e1e1 AK |
2424 | /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ |
2425 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
cd15b048 | 2426 | |
f87a8864 | 2427 | pnv_pci_ioda2_set_bypass(pe, false); |
46d3e1e1 AK |
2428 | pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
2429 | pnv_ioda2_table_free(tbl); | |
f87a8864 | 2430 | } |
cd15b048 | 2431 | |
f87a8864 AK |
2432 | static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) |
2433 | { | |
2434 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2435 | table_group); | |
2436 | ||
46d3e1e1 | 2437 | pnv_pci_ioda2_setup_default_config(pe); |
cd15b048 BH |
2438 | } |
2439 | ||
f87a8864 | 2440 | static struct iommu_table_group_ops pnv_pci_ioda2_ops = { |
00547193 | 2441 | .get_table_size = pnv_pci_ioda2_get_table_size, |
4793d65d AK |
2442 | .create_table = pnv_pci_ioda2_create_table, |
2443 | .set_window = pnv_pci_ioda2_set_window, | |
2444 | .unset_window = pnv_pci_ioda2_unset_window, | |
f87a8864 AK |
2445 | .take_ownership = pnv_ioda2_take_ownership, |
2446 | .release_ownership = pnv_ioda2_release_ownership, | |
2447 | }; | |
b5cb9ab1 AK |
2448 | |
2449 | static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) | |
2450 | { | |
2451 | struct pci_controller *hose; | |
2452 | struct pnv_phb *phb; | |
2453 | struct pnv_ioda_pe **ptmppe = opaque; | |
2454 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
2455 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
2456 | ||
2457 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
2458 | return 0; | |
2459 | ||
2460 | hose = pci_bus_to_host(pdev->bus); | |
2461 | phb = hose->private_data; | |
2462 | if (phb->type != PNV_PHB_NPU) | |
2463 | return 0; | |
2464 | ||
2465 | *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; | |
2466 | ||
2467 | return 1; | |
2468 | } | |
2469 | ||
2470 | /* | |
2471 | * This returns PE of associated NPU. | |
2472 | * This assumes that NPU is in the same IOMMU group with GPU and there is | |
2473 | * no other PEs. | |
2474 | */ | |
2475 | static struct pnv_ioda_pe *gpe_table_group_to_npe( | |
2476 | struct iommu_table_group *table_group) | |
2477 | { | |
2478 | struct pnv_ioda_pe *npe = NULL; | |
2479 | int ret = iommu_group_for_each_dev(table_group->group, &npe, | |
2480 | gpe_table_group_to_npe_cb); | |
2481 | ||
2482 | BUG_ON(!ret || !npe); | |
2483 | ||
2484 | return npe; | |
2485 | } | |
2486 | ||
2487 | static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, | |
2488 | int num, struct iommu_table *tbl) | |
2489 | { | |
2490 | long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); | |
2491 | ||
2492 | if (ret) | |
2493 | return ret; | |
2494 | ||
2495 | ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); | |
2496 | if (ret) | |
2497 | pnv_pci_ioda2_unset_window(table_group, num); | |
2498 | ||
2499 | return ret; | |
2500 | } | |
2501 | ||
2502 | static long pnv_pci_ioda2_npu_unset_window( | |
2503 | struct iommu_table_group *table_group, | |
2504 | int num) | |
2505 | { | |
2506 | long ret = pnv_pci_ioda2_unset_window(table_group, num); | |
2507 | ||
2508 | if (ret) | |
2509 | return ret; | |
2510 | ||
2511 | return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); | |
2512 | } | |
2513 | ||
2514 | static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) | |
2515 | { | |
2516 | /* | |
2517 | * Detach NPU first as pnv_ioda2_take_ownership() will destroy | |
2518 | * the iommu_table if 32bit DMA is enabled. | |
2519 | */ | |
2520 | pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); | |
2521 | pnv_ioda2_take_ownership(table_group); | |
2522 | } | |
2523 | ||
2524 | static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { | |
2525 | .get_table_size = pnv_pci_ioda2_get_table_size, | |
2526 | .create_table = pnv_pci_ioda2_create_table, | |
2527 | .set_window = pnv_pci_ioda2_npu_set_window, | |
2528 | .unset_window = pnv_pci_ioda2_npu_unset_window, | |
2529 | .take_ownership = pnv_ioda2_npu_take_ownership, | |
2530 | .release_ownership = pnv_ioda2_release_ownership, | |
2531 | }; | |
2532 | ||
2533 | static void pnv_pci_ioda_setup_iommu_api(void) | |
2534 | { | |
2535 | struct pci_controller *hose, *tmp; | |
2536 | struct pnv_phb *phb; | |
2537 | struct pnv_ioda_pe *pe, *gpe; | |
2538 | ||
2539 | /* | |
2540 | * Now we have all PHBs discovered, time to add NPU devices to | |
2541 | * the corresponding IOMMU groups. | |
2542 | */ | |
2543 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
2544 | phb = hose->private_data; | |
2545 | ||
2546 | if (phb->type != PNV_PHB_NPU) | |
2547 | continue; | |
2548 | ||
2549 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
2550 | gpe = pnv_pci_npu_setup_iommu(pe); | |
2551 | if (gpe) | |
2552 | gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; | |
2553 | } | |
2554 | } | |
2555 | } | |
2556 | #else /* !CONFIG_IOMMU_API */ | |
2557 | static void pnv_pci_ioda_setup_iommu_api(void) { }; | |
f87a8864 AK |
2558 | #endif |
2559 | ||
bbb845c4 AK |
2560 | static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, |
2561 | unsigned levels, unsigned long limit, | |
3ba3a73e | 2562 | unsigned long *current_offset, unsigned long *total_allocated) |
373f5657 GS |
2563 | { |
2564 | struct page *tce_mem = NULL; | |
bbb845c4 | 2565 | __be64 *addr, *tmp; |
aca6913f | 2566 | unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; |
bbb845c4 AK |
2567 | unsigned long allocated = 1UL << (order + PAGE_SHIFT); |
2568 | unsigned entries = 1UL << (shift - 3); | |
2569 | long i; | |
aca6913f AK |
2570 | |
2571 | tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); | |
2572 | if (!tce_mem) { | |
2573 | pr_err("Failed to allocate a TCE memory, order=%d\n", order); | |
2574 | return NULL; | |
2575 | } | |
2576 | addr = page_address(tce_mem); | |
bbb845c4 | 2577 | memset(addr, 0, allocated); |
3ba3a73e | 2578 | *total_allocated += allocated; |
bbb845c4 AK |
2579 | |
2580 | --levels; | |
2581 | if (!levels) { | |
2582 | *current_offset += allocated; | |
2583 | return addr; | |
2584 | } | |
2585 | ||
2586 | for (i = 0; i < entries; ++i) { | |
2587 | tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, | |
3ba3a73e | 2588 | levels, limit, current_offset, total_allocated); |
bbb845c4 AK |
2589 | if (!tmp) |
2590 | break; | |
2591 | ||
2592 | addr[i] = cpu_to_be64(__pa(tmp) | | |
2593 | TCE_PCI_READ | TCE_PCI_WRITE); | |
2594 | ||
2595 | if (*current_offset >= limit) | |
2596 | break; | |
2597 | } | |
aca6913f AK |
2598 | |
2599 | return addr; | |
2600 | } | |
2601 | ||
bbb845c4 AK |
2602 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2603 | unsigned long size, unsigned level); | |
2604 | ||
aca6913f | 2605 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
bbb845c4 AK |
2606 | __u32 page_shift, __u64 window_size, __u32 levels, |
2607 | struct iommu_table *tbl) | |
aca6913f | 2608 | { |
373f5657 | 2609 | void *addr; |
3ba3a73e | 2610 | unsigned long offset = 0, level_shift, total_allocated = 0; |
aca6913f AK |
2611 | const unsigned window_shift = ilog2(window_size); |
2612 | unsigned entries_shift = window_shift - page_shift; | |
2613 | unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); | |
2614 | const unsigned long tce_table_size = 1UL << table_shift; | |
2615 | ||
bbb845c4 AK |
2616 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) |
2617 | return -EINVAL; | |
2618 | ||
aca6913f AK |
2619 | if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) |
2620 | return -EINVAL; | |
2621 | ||
bbb845c4 AK |
2622 | /* Adjust direct table size from window_size and levels */ |
2623 | entries_shift = (entries_shift + levels - 1) / levels; | |
2624 | level_shift = entries_shift + 3; | |
2625 | level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); | |
2626 | ||
aca6913f | 2627 | /* Allocate TCE table */ |
bbb845c4 | 2628 | addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, |
3ba3a73e | 2629 | levels, tce_table_size, &offset, &total_allocated); |
bbb845c4 AK |
2630 | |
2631 | /* addr==NULL means that the first level allocation failed */ | |
aca6913f AK |
2632 | if (!addr) |
2633 | return -ENOMEM; | |
2634 | ||
bbb845c4 AK |
2635 | /* |
2636 | * First level was allocated but some lower level failed as | |
2637 | * we did not allocate as much as we wanted, | |
2638 | * release partially allocated table. | |
2639 | */ | |
2640 | if (offset < tce_table_size) { | |
2641 | pnv_pci_ioda2_table_do_free_pages(addr, | |
2642 | 1ULL << (level_shift - 3), levels - 1); | |
2643 | return -ENOMEM; | |
2644 | } | |
2645 | ||
aca6913f AK |
2646 | /* Setup linux iommu table */ |
2647 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, | |
2648 | page_shift); | |
bbb845c4 AK |
2649 | tbl->it_level_size = 1ULL << (level_shift - 3); |
2650 | tbl->it_indirect_levels = levels - 1; | |
3ba3a73e | 2651 | tbl->it_allocated_size = total_allocated; |
aca6913f AK |
2652 | |
2653 | pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", | |
2654 | window_size, tce_table_size, bus_offset); | |
2655 | ||
2656 | return 0; | |
2657 | } | |
2658 | ||
bbb845c4 AK |
2659 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2660 | unsigned long size, unsigned level) | |
2661 | { | |
2662 | const unsigned long addr_ul = (unsigned long) addr & | |
2663 | ~(TCE_PCI_READ | TCE_PCI_WRITE); | |
2664 | ||
2665 | if (level) { | |
2666 | long i; | |
2667 | u64 *tmp = (u64 *) addr_ul; | |
2668 | ||
2669 | for (i = 0; i < size; ++i) { | |
2670 | unsigned long hpa = be64_to_cpu(tmp[i]); | |
2671 | ||
2672 | if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) | |
2673 | continue; | |
2674 | ||
2675 | pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, | |
2676 | level - 1); | |
2677 | } | |
2678 | } | |
2679 | ||
2680 | free_pages(addr_ul, get_order(size << 3)); | |
2681 | } | |
2682 | ||
aca6913f AK |
2683 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) |
2684 | { | |
bbb845c4 AK |
2685 | const unsigned long size = tbl->it_indirect_levels ? |
2686 | tbl->it_level_size : tbl->it_size; | |
2687 | ||
aca6913f AK |
2688 | if (!tbl->it_size) |
2689 | return; | |
2690 | ||
bbb845c4 AK |
2691 | pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, |
2692 | tbl->it_indirect_levels); | |
aca6913f AK |
2693 | } |
2694 | ||
2695 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
2696 | struct pnv_ioda_pe *pe) | |
2697 | { | |
373f5657 GS |
2698 | int64_t rc; |
2699 | ||
ccd1c191 GS |
2700 | if (!pnv_pci_ioda_pe_dma_weight(pe)) |
2701 | return; | |
2702 | ||
f87a8864 AK |
2703 | /* TVE #1 is selected by PCI address bit 59 */ |
2704 | pe->tce_bypass_base = 1ull << 59; | |
2705 | ||
b348aa65 AK |
2706 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2707 | pe->pe_number); | |
c5773822 | 2708 | |
373f5657 | 2709 | /* The PE will reserve all possible 32-bits space */ |
373f5657 | 2710 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", |
aca6913f | 2711 | phb->ioda.m32_pci_base); |
373f5657 | 2712 | |
aca6913f | 2713 | /* Setup linux iommu table */ |
4793d65d AK |
2714 | pe->table_group.tce32_start = 0; |
2715 | pe->table_group.tce32_size = phb->ioda.m32_pci_base; | |
2716 | pe->table_group.max_dynamic_windows_supported = | |
2717 | IOMMU_TABLE_GROUP_MAX_TABLES; | |
2718 | pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; | |
2719 | pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; | |
e5aad1e6 AK |
2720 | #ifdef CONFIG_IOMMU_API |
2721 | pe->table_group.ops = &pnv_pci_ioda2_ops; | |
2722 | #endif | |
2723 | ||
46d3e1e1 | 2724 | rc = pnv_pci_ioda2_setup_default_config(pe); |
801846d1 | 2725 | if (rc) |
46d3e1e1 | 2726 | return; |
373f5657 | 2727 | |
46d3e1e1 | 2728 | if (pe->flags & PNV_IODA_PE_DEV) |
4617082e | 2729 | iommu_add_device(&pe->pdev->dev); |
46d3e1e1 | 2730 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2731 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
373f5657 GS |
2732 | } |
2733 | ||
184cd4a3 | 2734 | #ifdef CONFIG_PCI_MSI |
4ee11c1a | 2735 | int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) |
137436c9 | 2736 | { |
137436c9 GS |
2737 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, |
2738 | ioda.irq_chip); | |
4ee11c1a SW |
2739 | |
2740 | return opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
2741 | } | |
2742 | ||
2743 | static void pnv_ioda2_msi_eoi(struct irq_data *d) | |
2744 | { | |
137436c9 | 2745 | int64_t rc; |
4ee11c1a SW |
2746 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); |
2747 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
137436c9 | 2748 | |
4ee11c1a | 2749 | rc = pnv_opal_pci_msi_eoi(chip, hw_irq); |
137436c9 GS |
2750 | WARN_ON_ONCE(rc); |
2751 | ||
2752 | icp_native_eoi(d); | |
2753 | } | |
2754 | ||
fd9a1c26 | 2755 | |
f456834a | 2756 | void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) |
fd9a1c26 IM |
2757 | { |
2758 | struct irq_data *idata; | |
2759 | struct irq_chip *ichip; | |
2760 | ||
fb111334 BH |
2761 | /* The MSI EOI OPAL call is only needed on PHB3 */ |
2762 | if (phb->model != PNV_PHB_MODEL_PHB3) | |
fd9a1c26 IM |
2763 | return; |
2764 | ||
2765 | if (!phb->ioda.irq_chip_init) { | |
2766 | /* | |
2767 | * First time we setup an MSI IRQ, we need to setup the | |
2768 | * corresponding IRQ chip to route correctly. | |
2769 | */ | |
2770 | idata = irq_get_irq_data(virq); | |
2771 | ichip = irq_data_get_irq_chip(idata); | |
2772 | phb->ioda.irq_chip_init = 1; | |
2773 | phb->ioda.irq_chip = *ichip; | |
2774 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
2775 | } | |
2776 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
2777 | } | |
2778 | ||
4ee11c1a SW |
2779 | /* |
2780 | * Returns true iff chip is something that we could call | |
2781 | * pnv_opal_pci_msi_eoi for. | |
2782 | */ | |
2783 | bool is_pnv_opal_msi(struct irq_chip *chip) | |
2784 | { | |
2785 | return chip->irq_eoi == pnv_ioda2_msi_eoi; | |
2786 | } | |
2787 | EXPORT_SYMBOL_GPL(is_pnv_opal_msi); | |
2788 | ||
184cd4a3 | 2789 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
2790 | unsigned int hwirq, unsigned int virq, |
2791 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
2792 | { |
2793 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
2794 | unsigned int xive_num = hwirq - phb->msi_base; | |
3a1a4661 | 2795 | __be32 data; |
184cd4a3 BH |
2796 | int rc; |
2797 | ||
2798 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
2799 | if (pe == NULL) | |
2800 | return -ENXIO; | |
2801 | ||
2802 | /* Check if we have an MVE */ | |
2803 | if (pe->mve_number < 0) | |
2804 | return -ENXIO; | |
2805 | ||
b72c1f65 | 2806 | /* Force 32-bit MSI on some broken devices */ |
36074381 | 2807 | if (dev->no_64bit_msi) |
b72c1f65 BH |
2808 | is_64 = 0; |
2809 | ||
184cd4a3 BH |
2810 | /* Assign XIVE to PE */ |
2811 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2812 | if (rc) { | |
2813 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
2814 | pci_name(dev), rc, xive_num); | |
2815 | return -EIO; | |
2816 | } | |
2817 | ||
2818 | if (is_64) { | |
3a1a4661 BH |
2819 | __be64 addr64; |
2820 | ||
184cd4a3 BH |
2821 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
2822 | &addr64, &data); | |
2823 | if (rc) { | |
2824 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
2825 | pci_name(dev), rc); | |
2826 | return -EIO; | |
2827 | } | |
3a1a4661 BH |
2828 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
2829 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 2830 | } else { |
3a1a4661 BH |
2831 | __be32 addr32; |
2832 | ||
184cd4a3 BH |
2833 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
2834 | &addr32, &data); | |
2835 | if (rc) { | |
2836 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
2837 | pci_name(dev), rc); | |
2838 | return -EIO; | |
2839 | } | |
2840 | msg->address_hi = 0; | |
3a1a4661 | 2841 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 2842 | } |
3a1a4661 | 2843 | msg->data = be32_to_cpu(data); |
184cd4a3 | 2844 | |
f456834a | 2845 | pnv_set_msi_irq_chip(phb, virq); |
137436c9 | 2846 | |
184cd4a3 | 2847 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
1f52f176 | 2848 | " address=%x_%08x data=%x PE# %x\n", |
184cd4a3 BH |
2849 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, |
2850 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
2851 | ||
2852 | return 0; | |
2853 | } | |
2854 | ||
2855 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
2856 | { | |
fb1b55d6 | 2857 | unsigned int count; |
184cd4a3 BH |
2858 | const __be32 *prop = of_get_property(phb->hose->dn, |
2859 | "ibm,opal-msi-ranges", NULL); | |
2860 | if (!prop) { | |
2861 | /* BML Fallback */ | |
2862 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
2863 | } | |
2864 | if (!prop) | |
2865 | return; | |
2866 | ||
2867 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
2868 | count = be32_to_cpup(prop + 1); |
2869 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
2870 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
2871 | phb->hose->global_number); | |
2872 | return; | |
2873 | } | |
fb1b55d6 | 2874 | |
184cd4a3 BH |
2875 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
2876 | phb->msi32_support = 1; | |
2877 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 2878 | count, phb->msi_base); |
184cd4a3 BH |
2879 | } |
2880 | #else | |
2881 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
2882 | #endif /* CONFIG_PCI_MSI */ | |
2883 | ||
6e628c7d WY |
2884 | #ifdef CONFIG_PCI_IOV |
2885 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) | |
2886 | { | |
f2dd0afe WY |
2887 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
2888 | struct pnv_phb *phb = hose->private_data; | |
2889 | const resource_size_t gate = phb->ioda.m64_segsize >> 2; | |
6e628c7d WY |
2890 | struct resource *res; |
2891 | int i; | |
dfcc8d45 | 2892 | resource_size_t size, total_vf_bar_sz; |
6e628c7d | 2893 | struct pci_dn *pdn; |
5b88ec22 | 2894 | int mul, total_vfs; |
6e628c7d WY |
2895 | |
2896 | if (!pdev->is_physfn || pdev->is_added) | |
2897 | return; | |
2898 | ||
6e628c7d WY |
2899 | pdn = pci_get_pdn(pdev); |
2900 | pdn->vfs_expanded = 0; | |
ee8222fe | 2901 | pdn->m64_single_mode = false; |
6e628c7d | 2902 | |
5b88ec22 | 2903 | total_vfs = pci_sriov_get_totalvfs(pdev); |
92b8f137 | 2904 | mul = phb->ioda.total_pe_num; |
dfcc8d45 | 2905 | total_vf_bar_sz = 0; |
5b88ec22 WY |
2906 | |
2907 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
2908 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2909 | if (!res->flags || res->parent) | |
2910 | continue; | |
b79331a5 | 2911 | if (!pnv_pci_is_m64_flags(res->flags)) { |
b0331854 WY |
2912 | dev_warn(&pdev->dev, "Don't support SR-IOV with" |
2913 | " non M64 VF BAR%d: %pR. \n", | |
5b88ec22 | 2914 | i, res); |
b0331854 | 2915 | goto truncate_iov; |
5b88ec22 WY |
2916 | } |
2917 | ||
dfcc8d45 WY |
2918 | total_vf_bar_sz += pci_iov_resource_size(pdev, |
2919 | i + PCI_IOV_RESOURCES); | |
5b88ec22 | 2920 | |
f2dd0afe WY |
2921 | /* |
2922 | * If bigger than quarter of M64 segment size, just round up | |
2923 | * power of two. | |
2924 | * | |
2925 | * Generally, one M64 BAR maps one IOV BAR. To avoid conflict | |
2926 | * with other devices, IOV BAR size is expanded to be | |
2927 | * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 | |
2928 | * segment size , the expanded size would equal to half of the | |
2929 | * whole M64 space size, which will exhaust the M64 Space and | |
2930 | * limit the system flexibility. This is a design decision to | |
2931 | * set the boundary to quarter of the M64 segment size. | |
2932 | */ | |
dfcc8d45 | 2933 | if (total_vf_bar_sz > gate) { |
5b88ec22 | 2934 | mul = roundup_pow_of_two(total_vfs); |
dfcc8d45 WY |
2935 | dev_info(&pdev->dev, |
2936 | "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", | |
2937 | total_vf_bar_sz, gate, mul); | |
ee8222fe | 2938 | pdn->m64_single_mode = true; |
5b88ec22 WY |
2939 | break; |
2940 | } | |
2941 | } | |
2942 | ||
6e628c7d WY |
2943 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
2944 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2945 | if (!res->flags || res->parent) | |
2946 | continue; | |
6e628c7d | 2947 | |
6e628c7d | 2948 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); |
ee8222fe WY |
2949 | /* |
2950 | * On PHB3, the minimum size alignment of M64 BAR in single | |
2951 | * mode is 32MB. | |
2952 | */ | |
2953 | if (pdn->m64_single_mode && (size < SZ_32M)) | |
2954 | goto truncate_iov; | |
2955 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); | |
5b88ec22 | 2956 | res->end = res->start + size * mul - 1; |
6e628c7d WY |
2957 | dev_dbg(&pdev->dev, " %pR\n", res); |
2958 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", | |
5b88ec22 | 2959 | i, res, mul); |
6e628c7d | 2960 | } |
5b88ec22 | 2961 | pdn->vfs_expanded = mul; |
b0331854 WY |
2962 | |
2963 | return; | |
2964 | ||
2965 | truncate_iov: | |
2966 | /* To save MMIO space, IOV BAR is truncated. */ | |
2967 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
2968 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2969 | res->flags = 0; | |
2970 | res->end = res->start - 1; | |
2971 | } | |
6e628c7d WY |
2972 | } |
2973 | #endif /* CONFIG_PCI_IOV */ | |
2974 | ||
23e79425 GS |
2975 | static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, |
2976 | struct resource *res) | |
2977 | { | |
2978 | struct pnv_phb *phb = pe->phb; | |
2979 | struct pci_bus_region region; | |
2980 | int index; | |
2981 | int64_t rc; | |
2982 | ||
2983 | if (!res || !res->flags || res->start > res->end) | |
2984 | return; | |
2985 | ||
2986 | if (res->flags & IORESOURCE_IO) { | |
2987 | region.start = res->start - phb->ioda.io_pci_base; | |
2988 | region.end = res->end - phb->ioda.io_pci_base; | |
2989 | index = region.start / phb->ioda.io_segsize; | |
2990 | ||
2991 | while (index < phb->ioda.total_pe_num && | |
2992 | region.start <= region.end) { | |
2993 | phb->ioda.io_segmap[index] = pe->pe_number; | |
2994 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
2995 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
2996 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 2997 | pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", |
23e79425 GS |
2998 | __func__, rc, index, pe->pe_number); |
2999 | break; | |
3000 | } | |
3001 | ||
3002 | region.start += phb->ioda.io_segsize; | |
3003 | index++; | |
3004 | } | |
3005 | } else if ((res->flags & IORESOURCE_MEM) && | |
5958d19a | 3006 | !pnv_pci_is_m64(phb, res)) { |
23e79425 GS |
3007 | region.start = res->start - |
3008 | phb->hose->mem_offset[0] - | |
3009 | phb->ioda.m32_pci_base; | |
3010 | region.end = res->end - | |
3011 | phb->hose->mem_offset[0] - | |
3012 | phb->ioda.m32_pci_base; | |
3013 | index = region.start / phb->ioda.m32_segsize; | |
3014 | ||
3015 | while (index < phb->ioda.total_pe_num && | |
3016 | region.start <= region.end) { | |
3017 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
3018 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3019 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
3020 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 3021 | pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", |
23e79425 GS |
3022 | __func__, rc, index, pe->pe_number); |
3023 | break; | |
3024 | } | |
3025 | ||
3026 | region.start += phb->ioda.m32_segsize; | |
3027 | index++; | |
3028 | } | |
3029 | } | |
3030 | } | |
3031 | ||
11685bec GS |
3032 | /* |
3033 | * This function is supposed to be called on basis of PE from top | |
3034 | * to bottom style. So the the I/O or MMIO segment assigned to | |
03671057 | 3035 | * parent PE could be overridden by its child PEs if necessary. |
11685bec | 3036 | */ |
23e79425 | 3037 | static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) |
11685bec | 3038 | { |
69d733e7 | 3039 | struct pci_dev *pdev; |
23e79425 | 3040 | int i; |
11685bec GS |
3041 | |
3042 | /* | |
3043 | * NOTE: We only care PCI bus based PE for now. For PCI | |
3044 | * device based PE, for example SRIOV sensitive VF should | |
3045 | * be figured out later. | |
3046 | */ | |
3047 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
3048 | ||
69d733e7 GS |
3049 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
3050 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
3051 | pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); | |
3052 | ||
3053 | /* | |
3054 | * If the PE contains all subordinate PCI buses, the | |
3055 | * windows of the child bridges should be mapped to | |
3056 | * the PE as well. | |
3057 | */ | |
3058 | if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) | |
3059 | continue; | |
3060 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
3061 | pnv_ioda_setup_pe_res(pe, | |
3062 | &pdev->resource[PCI_BRIDGE_RESOURCES + i]); | |
3063 | } | |
11685bec GS |
3064 | } |
3065 | ||
98b665da RC |
3066 | #ifdef CONFIG_DEBUG_FS |
3067 | static int pnv_pci_diag_data_set(void *data, u64 val) | |
3068 | { | |
3069 | struct pci_controller *hose; | |
3070 | struct pnv_phb *phb; | |
3071 | s64 ret; | |
3072 | ||
3073 | if (val != 1ULL) | |
3074 | return -EINVAL; | |
3075 | ||
3076 | hose = (struct pci_controller *)data; | |
3077 | if (!hose || !hose->private_data) | |
3078 | return -ENODEV; | |
3079 | ||
3080 | phb = hose->private_data; | |
3081 | ||
3082 | /* Retrieve the diag data from firmware */ | |
3083 | ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, | |
3084 | PNV_PCI_DIAG_BUF_SIZE); | |
3085 | if (ret != OPAL_SUCCESS) | |
3086 | return -EIO; | |
3087 | ||
3088 | /* Print the diag data to the kernel log */ | |
3089 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); | |
3090 | return 0; | |
3091 | } | |
3092 | ||
3093 | DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, | |
3094 | pnv_pci_diag_data_set, "%llu\n"); | |
3095 | ||
3096 | #endif /* CONFIG_DEBUG_FS */ | |
3097 | ||
37c367f2 GS |
3098 | static void pnv_pci_ioda_create_dbgfs(void) |
3099 | { | |
3100 | #ifdef CONFIG_DEBUG_FS | |
3101 | struct pci_controller *hose, *tmp; | |
3102 | struct pnv_phb *phb; | |
3103 | char name[16]; | |
3104 | ||
3105 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3106 | phb = hose->private_data; | |
3107 | ||
ccd1c191 GS |
3108 | /* Notify initialization of PHB done */ |
3109 | phb->initialized = 1; | |
3110 | ||
37c367f2 GS |
3111 | sprintf(name, "PCI%04x", hose->global_number); |
3112 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
98b665da | 3113 | if (!phb->dbgfs) { |
37c367f2 GS |
3114 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", |
3115 | __func__, hose->global_number); | |
98b665da RC |
3116 | continue; |
3117 | } | |
3118 | ||
3119 | debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, | |
3120 | &pnv_pci_diag_data_fops); | |
37c367f2 GS |
3121 | } |
3122 | #endif /* CONFIG_DEBUG_FS */ | |
3123 | } | |
3124 | ||
cad5cef6 | 3125 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
3126 | { |
3127 | pnv_pci_ioda_setup_PEs(); | |
ccd1c191 | 3128 | pnv_pci_ioda_setup_iommu_api(); |
37c367f2 GS |
3129 | pnv_pci_ioda_create_dbgfs(); |
3130 | ||
e9cc17d4 | 3131 | #ifdef CONFIG_EEH |
e9cc17d4 | 3132 | eeh_init(); |
dadcd6d6 | 3133 | eeh_addr_cache_build(); |
e9cc17d4 | 3134 | #endif |
fb446ad0 GS |
3135 | } |
3136 | ||
271fd03a GS |
3137 | /* |
3138 | * Returns the alignment for I/O or memory windows for P2P | |
3139 | * bridges. That actually depends on how PEs are segmented. | |
3140 | * For now, we return I/O or M32 segment size for PE sensitive | |
3141 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
3142 | * 1MiB for memory) will be returned. | |
3143 | * | |
3144 | * The current PCI bus might be put into one PE, which was | |
3145 | * create against the parent PCI bridge. For that case, we | |
3146 | * needn't enlarge the alignment so that we can save some | |
3147 | * resources. | |
3148 | */ | |
3149 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
3150 | unsigned long type) | |
3151 | { | |
3152 | struct pci_dev *bridge; | |
3153 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3154 | struct pnv_phb *phb = hose->private_data; | |
3155 | int num_pci_bridges = 0; | |
3156 | ||
3157 | bridge = bus->self; | |
3158 | while (bridge) { | |
3159 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
3160 | num_pci_bridges++; | |
3161 | if (num_pci_bridges >= 2) | |
3162 | return 1; | |
3163 | } | |
3164 | ||
3165 | bridge = bridge->bus->self; | |
3166 | } | |
3167 | ||
5958d19a BH |
3168 | /* |
3169 | * We fall back to M32 if M64 isn't supported. We enforce the M64 | |
3170 | * alignment for any 64-bit resource, PCIe doesn't care and | |
3171 | * bridges only do 64-bit prefetchable anyway. | |
3172 | */ | |
b79331a5 | 3173 | if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) |
262af557 | 3174 | return phb->ioda.m64_segsize; |
271fd03a GS |
3175 | if (type & IORESOURCE_MEM) |
3176 | return phb->ioda.m32_segsize; | |
3177 | ||
3178 | return phb->ioda.io_segsize; | |
3179 | } | |
3180 | ||
40e2a47e GS |
3181 | /* |
3182 | * We are updating root port or the upstream port of the | |
3183 | * bridge behind the root port with PHB's windows in order | |
3184 | * to accommodate the changes on required resources during | |
3185 | * PCI (slot) hotplug, which is connected to either root | |
3186 | * port or the downstream ports of PCIe switch behind the | |
3187 | * root port. | |
3188 | */ | |
3189 | static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, | |
3190 | unsigned long type) | |
3191 | { | |
3192 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3193 | struct pnv_phb *phb = hose->private_data; | |
3194 | struct pci_dev *bridge = bus->self; | |
3195 | struct resource *r, *w; | |
3196 | bool msi_region = false; | |
3197 | int i; | |
3198 | ||
3199 | /* Check if we need apply fixup to the bridge's windows */ | |
3200 | if (!pci_is_root_bus(bridge->bus) && | |
3201 | !pci_is_root_bus(bridge->bus->self->bus)) | |
3202 | return; | |
3203 | ||
3204 | /* Fixup the resources */ | |
3205 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { | |
3206 | r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; | |
3207 | if (!r->flags || !r->parent) | |
3208 | continue; | |
3209 | ||
3210 | w = NULL; | |
3211 | if (r->flags & type & IORESOURCE_IO) | |
3212 | w = &hose->io_resource; | |
5958d19a | 3213 | else if (pnv_pci_is_m64(phb, r) && |
40e2a47e GS |
3214 | (type & IORESOURCE_PREFETCH) && |
3215 | phb->ioda.m64_segsize) | |
3216 | w = &hose->mem_resources[1]; | |
3217 | else if (r->flags & type & IORESOURCE_MEM) { | |
3218 | w = &hose->mem_resources[0]; | |
3219 | msi_region = true; | |
3220 | } | |
3221 | ||
3222 | r->start = w->start; | |
3223 | r->end = w->end; | |
3224 | ||
3225 | /* The 64KB 32-bits MSI region shouldn't be included in | |
3226 | * the 32-bits bridge window. Otherwise, we can see strange | |
3227 | * issues. One of them is EEH error observed on Garrison. | |
3228 | * | |
3229 | * Exclude top 1MB region which is the minimal alignment of | |
3230 | * 32-bits bridge window. | |
3231 | */ | |
3232 | if (msi_region) { | |
3233 | r->end += 0x10000; | |
3234 | r->end -= 0x100000; | |
3235 | } | |
3236 | } | |
3237 | } | |
3238 | ||
ccd1c191 GS |
3239 | static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) |
3240 | { | |
3241 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3242 | struct pnv_phb *phb = hose->private_data; | |
3243 | struct pci_dev *bridge = bus->self; | |
3244 | struct pnv_ioda_pe *pe; | |
3245 | bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); | |
3246 | ||
40e2a47e GS |
3247 | /* Extend bridge's windows if necessary */ |
3248 | pnv_pci_fixup_bridge_resources(bus, type); | |
3249 | ||
63803c39 GS |
3250 | /* The PE for root bus should be realized before any one else */ |
3251 | if (!phb->ioda.root_pe_populated) { | |
3252 | pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); | |
3253 | if (pe) { | |
3254 | phb->ioda.root_pe_idx = pe->pe_number; | |
3255 | phb->ioda.root_pe_populated = true; | |
3256 | } | |
3257 | } | |
3258 | ||
ccd1c191 GS |
3259 | /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ |
3260 | if (list_empty(&bus->devices)) | |
3261 | return; | |
3262 | ||
3263 | /* Reserve PEs according to used M64 resources */ | |
3264 | if (phb->reserve_m64_pe) | |
3265 | phb->reserve_m64_pe(bus, NULL, all); | |
3266 | ||
3267 | /* | |
3268 | * Assign PE. We might run here because of partial hotplug. | |
3269 | * For the case, we just pick up the existing PE and should | |
3270 | * not allocate resources again. | |
3271 | */ | |
3272 | pe = pnv_ioda_setup_bus_PE(bus, all); | |
3273 | if (!pe) | |
3274 | return; | |
3275 | ||
3276 | pnv_ioda_setup_pe_seg(pe); | |
3277 | switch (phb->type) { | |
3278 | case PNV_PHB_IODA1: | |
3279 | pnv_pci_ioda1_setup_dma_pe(phb, pe); | |
3280 | break; | |
3281 | case PNV_PHB_IODA2: | |
3282 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
3283 | break; | |
3284 | default: | |
1f52f176 | 3285 | pr_warn("%s: No DMA for PHB#%x (type %d)\n", |
ccd1c191 GS |
3286 | __func__, phb->hose->global_number, phb->type); |
3287 | } | |
3288 | } | |
3289 | ||
5350ab3f WY |
3290 | #ifdef CONFIG_PCI_IOV |
3291 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, | |
3292 | int resno) | |
3293 | { | |
ee8222fe WY |
3294 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
3295 | struct pnv_phb *phb = hose->private_data; | |
5350ab3f | 3296 | struct pci_dn *pdn = pci_get_pdn(pdev); |
7fbe7a93 | 3297 | resource_size_t align; |
5350ab3f | 3298 | |
7fbe7a93 WY |
3299 | /* |
3300 | * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the | |
3301 | * SR-IOV. While from hardware perspective, the range mapped by M64 | |
3302 | * BAR should be size aligned. | |
3303 | * | |
ee8222fe WY |
3304 | * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra |
3305 | * powernv-specific hardware restriction is gone. But if just use the | |
3306 | * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with | |
3307 | * in one segment of M64 #15, which introduces the PE conflict between | |
3308 | * PF and VF. Based on this, the minimum alignment of an IOV BAR is | |
3309 | * m64_segsize. | |
3310 | * | |
7fbe7a93 WY |
3311 | * This function returns the total IOV BAR size if M64 BAR is in |
3312 | * Shared PE mode or just VF BAR size if not. | |
ee8222fe WY |
3313 | * If the M64 BAR is in Single PE mode, return the VF BAR size or |
3314 | * M64 segment size if IOV BAR size is less. | |
7fbe7a93 | 3315 | */ |
5350ab3f | 3316 | align = pci_iov_resource_size(pdev, resno); |
7fbe7a93 WY |
3317 | if (!pdn->vfs_expanded) |
3318 | return align; | |
ee8222fe WY |
3319 | if (pdn->m64_single_mode) |
3320 | return max(align, (resource_size_t)phb->ioda.m64_segsize); | |
5350ab3f | 3321 | |
7fbe7a93 | 3322 | return pdn->vfs_expanded * align; |
5350ab3f WY |
3323 | } |
3324 | #endif /* CONFIG_PCI_IOV */ | |
3325 | ||
184cd4a3 BH |
3326 | /* Prevent enabling devices for which we couldn't properly |
3327 | * assign a PE | |
3328 | */ | |
4361b034 | 3329 | bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 3330 | { |
db1266c8 GS |
3331 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
3332 | struct pnv_phb *phb = hose->private_data; | |
3333 | struct pci_dn *pdn; | |
184cd4a3 | 3334 | |
db1266c8 GS |
3335 | /* The function is probably called while the PEs have |
3336 | * not be created yet. For example, resource reassignment | |
3337 | * during PCI probe period. We just skip the check if | |
3338 | * PEs isn't ready. | |
3339 | */ | |
3340 | if (!phb->initialized) | |
c88c2a18 | 3341 | return true; |
db1266c8 | 3342 | |
b72c1f65 | 3343 | pdn = pci_get_pdn(dev); |
184cd4a3 | 3344 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
c88c2a18 | 3345 | return false; |
db1266c8 | 3346 | |
c88c2a18 | 3347 | return true; |
184cd4a3 BH |
3348 | } |
3349 | ||
c5f7700b GS |
3350 | static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, |
3351 | int num) | |
3352 | { | |
3353 | struct pnv_ioda_pe *pe = container_of(table_group, | |
3354 | struct pnv_ioda_pe, table_group); | |
3355 | struct pnv_phb *phb = pe->phb; | |
3356 | unsigned int idx; | |
3357 | long rc; | |
3358 | ||
3359 | pe_info(pe, "Removing DMA window #%d\n", num); | |
3360 | for (idx = 0; idx < phb->ioda.dma32_count; idx++) { | |
3361 | if (phb->ioda.dma32_segmap[idx] != pe->pe_number) | |
3362 | continue; | |
3363 | ||
3364 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
3365 | idx, 0, 0ul, 0ul, 0ul); | |
3366 | if (rc != OPAL_SUCCESS) { | |
3367 | pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", | |
3368 | rc, idx); | |
3369 | return rc; | |
3370 | } | |
3371 | ||
3372 | phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; | |
3373 | } | |
3374 | ||
3375 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); | |
3376 | return OPAL_SUCCESS; | |
3377 | } | |
3378 | ||
3379 | static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) | |
3380 | { | |
3381 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); | |
3382 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
3383 | int64_t rc; | |
3384 | ||
3385 | if (!weight) | |
3386 | return; | |
3387 | ||
3388 | rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); | |
3389 | if (rc != OPAL_SUCCESS) | |
3390 | return; | |
3391 | ||
a34ab7c3 | 3392 | pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); |
c5f7700b GS |
3393 | if (pe->table_group.group) { |
3394 | iommu_group_put(pe->table_group.group); | |
3395 | WARN_ON(pe->table_group.group); | |
3396 | } | |
3397 | ||
3398 | free_pages(tbl->it_base, get_order(tbl->it_size << 3)); | |
3399 | iommu_free_table(tbl, "pnv"); | |
3400 | } | |
3401 | ||
3402 | static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) | |
3403 | { | |
3404 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
3405 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); | |
3406 | #ifdef CONFIG_IOMMU_API | |
3407 | int64_t rc; | |
3408 | #endif | |
3409 | ||
3410 | if (!weight) | |
3411 | return; | |
3412 | ||
3413 | #ifdef CONFIG_IOMMU_API | |
3414 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); | |
3415 | if (rc) | |
3416 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
3417 | #endif | |
3418 | ||
3419 | pnv_pci_ioda2_set_bypass(pe, false); | |
3420 | if (pe->table_group.group) { | |
3421 | iommu_group_put(pe->table_group.group); | |
3422 | WARN_ON(pe->table_group.group); | |
3423 | } | |
3424 | ||
3425 | pnv_pci_ioda2_table_free_pages(tbl); | |
3426 | iommu_free_table(tbl, "pnv"); | |
3427 | } | |
3428 | ||
3429 | static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, | |
3430 | unsigned short win, | |
3431 | unsigned int *map) | |
3432 | { | |
3433 | struct pnv_phb *phb = pe->phb; | |
3434 | int idx; | |
3435 | int64_t rc; | |
3436 | ||
3437 | for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { | |
3438 | if (map[idx] != pe->pe_number) | |
3439 | continue; | |
3440 | ||
3441 | if (win == OPAL_M64_WINDOW_TYPE) | |
3442 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3443 | phb->ioda.reserved_pe_idx, win, | |
3444 | idx / PNV_IODA1_M64_SEGS, | |
3445 | idx % PNV_IODA1_M64_SEGS); | |
3446 | else | |
3447 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3448 | phb->ioda.reserved_pe_idx, win, 0, idx); | |
3449 | ||
3450 | if (rc != OPAL_SUCCESS) | |
3451 | pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", | |
3452 | rc, win, idx); | |
3453 | ||
3454 | map[idx] = IODA_INVALID_PE; | |
3455 | } | |
3456 | } | |
3457 | ||
3458 | static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) | |
3459 | { | |
3460 | struct pnv_phb *phb = pe->phb; | |
3461 | ||
3462 | if (phb->type == PNV_PHB_IODA1) { | |
3463 | pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, | |
3464 | phb->ioda.io_segmap); | |
3465 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, | |
3466 | phb->ioda.m32_segmap); | |
3467 | pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, | |
3468 | phb->ioda.m64_segmap); | |
3469 | } else if (phb->type == PNV_PHB_IODA2) { | |
3470 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, | |
3471 | phb->ioda.m32_segmap); | |
3472 | } | |
3473 | } | |
3474 | ||
3475 | static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) | |
3476 | { | |
3477 | struct pnv_phb *phb = pe->phb; | |
3478 | struct pnv_ioda_pe *slave, *tmp; | |
3479 | ||
c5f7700b GS |
3480 | list_del(&pe->list); |
3481 | switch (phb->type) { | |
3482 | case PNV_PHB_IODA1: | |
3483 | pnv_pci_ioda1_release_pe_dma(pe); | |
3484 | break; | |
3485 | case PNV_PHB_IODA2: | |
3486 | pnv_pci_ioda2_release_pe_dma(pe); | |
3487 | break; | |
3488 | default: | |
3489 | WARN_ON(1); | |
3490 | } | |
3491 | ||
3492 | pnv_ioda_release_pe_seg(pe); | |
3493 | pnv_ioda_deconfigure_pe(pe->phb, pe); | |
b314427a GS |
3494 | |
3495 | /* Release slave PEs in the compound PE */ | |
3496 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
3497 | list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { | |
3498 | list_del(&slave->list); | |
3499 | pnv_ioda_free_pe(slave); | |
3500 | } | |
3501 | } | |
3502 | ||
6eaed166 GS |
3503 | /* |
3504 | * The PE for root bus can be removed because of hotplug in EEH | |
3505 | * recovery for fenced PHB error. We need to mark the PE dead so | |
3506 | * that it can be populated again in PCI hot add path. The PE | |
3507 | * shouldn't be destroyed as it's the global reserved resource. | |
3508 | */ | |
3509 | if (phb->ioda.root_pe_populated && | |
3510 | phb->ioda.root_pe_idx == pe->pe_number) | |
3511 | phb->ioda.root_pe_populated = false; | |
3512 | else | |
3513 | pnv_ioda_free_pe(pe); | |
c5f7700b GS |
3514 | } |
3515 | ||
3516 | static void pnv_pci_release_device(struct pci_dev *pdev) | |
3517 | { | |
3518 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
3519 | struct pnv_phb *phb = hose->private_data; | |
3520 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
3521 | struct pnv_ioda_pe *pe; | |
3522 | ||
3523 | if (pdev->is_virtfn) | |
3524 | return; | |
3525 | ||
3526 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
3527 | return; | |
3528 | ||
29bf282d GS |
3529 | /* |
3530 | * PCI hotplug can happen as part of EEH error recovery. The @pdn | |
3531 | * isn't removed and added afterwards in this scenario. We should | |
3532 | * set the PE number in @pdn to an invalid one. Otherwise, the PE's | |
3533 | * device count is decreased on removing devices while failing to | |
3534 | * be increased on adding devices. It leads to unbalanced PE's device | |
3535 | * count and eventually make normal PCI hotplug path broken. | |
3536 | */ | |
c5f7700b | 3537 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
29bf282d GS |
3538 | pdn->pe_number = IODA_INVALID_PE; |
3539 | ||
c5f7700b GS |
3540 | WARN_ON(--pe->device_count < 0); |
3541 | if (pe->device_count == 0) | |
3542 | pnv_ioda_release_pe(pe); | |
3543 | } | |
3544 | ||
7a8e6bbf | 3545 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
73ed148a | 3546 | { |
7a8e6bbf MN |
3547 | struct pnv_phb *phb = hose->private_data; |
3548 | ||
d1a85eee | 3549 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
73ed148a BH |
3550 | OPAL_ASSERT_RESET); |
3551 | } | |
3552 | ||
92ae0353 | 3553 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
cb4224c5 GS |
3554 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
3555 | .dma_bus_setup = pnv_pci_dma_bus_setup, | |
92ae0353 | 3556 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3557 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3558 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
92ae0353 | 3559 | #endif |
cb4224c5 | 3560 | .enable_device_hook = pnv_pci_enable_device_hook, |
c5f7700b | 3561 | .release_device = pnv_pci_release_device, |
cb4224c5 | 3562 | .window_alignment = pnv_pci_window_alignment, |
ccd1c191 | 3563 | .setup_bridge = pnv_pci_setup_bridge, |
cb4224c5 GS |
3564 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
3565 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, | |
3566 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, | |
3567 | .shutdown = pnv_pci_ioda_shutdown, | |
92ae0353 DA |
3568 | }; |
3569 | ||
f9f83456 AK |
3570 | static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) |
3571 | { | |
3572 | dev_err_once(&npdev->dev, | |
3573 | "%s operation unsupported for NVLink devices\n", | |
3574 | __func__); | |
3575 | return -EPERM; | |
3576 | } | |
3577 | ||
5d2aa710 | 3578 | static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { |
cb4224c5 | 3579 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
5d2aa710 | 3580 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3581 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3582 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
5d2aa710 | 3583 | #endif |
cb4224c5 GS |
3584 | .enable_device_hook = pnv_pci_enable_device_hook, |
3585 | .window_alignment = pnv_pci_window_alignment, | |
3586 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3587 | .dma_set_mask = pnv_npu_dma_set_mask, | |
3588 | .shutdown = pnv_pci_ioda_shutdown, | |
5d2aa710 AP |
3589 | }; |
3590 | ||
4361b034 IM |
3591 | #ifdef CONFIG_CXL_BASE |
3592 | const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { | |
3593 | .dma_dev_setup = pnv_pci_dma_dev_setup, | |
3594 | .dma_bus_setup = pnv_pci_dma_bus_setup, | |
a2f67d5e IM |
3595 | #ifdef CONFIG_PCI_MSI |
3596 | .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, | |
3597 | .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, | |
3598 | #endif | |
4361b034 IM |
3599 | .enable_device_hook = pnv_cxl_enable_device_hook, |
3600 | .disable_device = pnv_cxl_disable_device, | |
3601 | .release_device = pnv_pci_release_device, | |
3602 | .window_alignment = pnv_pci_window_alignment, | |
3603 | .setup_bridge = pnv_pci_setup_bridge, | |
3604 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3605 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, | |
3606 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, | |
3607 | .shutdown = pnv_pci_ioda_shutdown, | |
3608 | }; | |
3609 | #endif | |
3610 | ||
e51df2c1 AB |
3611 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
3612 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
3613 | { |
3614 | struct pci_controller *hose; | |
184cd4a3 | 3615 | struct pnv_phb *phb; |
2b923ed1 GS |
3616 | unsigned long size, m64map_off, m32map_off, pemap_off; |
3617 | unsigned long iomap_off = 0, dma32map_off = 0; | |
fd141d1a | 3618 | struct resource r; |
c681b93c | 3619 | const __be64 *prop64; |
3a1a4661 | 3620 | const __be32 *prop32; |
f1b7cc3e | 3621 | int len; |
3fa23ff8 | 3622 | unsigned int segno; |
184cd4a3 BH |
3623 | u64 phb_id; |
3624 | void *aux; | |
3625 | long rc; | |
3626 | ||
08a45b32 BH |
3627 | if (!of_device_is_available(np)) |
3628 | return; | |
3629 | ||
9497a1c1 GS |
3630 | pr_info("Initializing %s PHB (%s)\n", |
3631 | pnv_phb_names[ioda_type], of_node_full_name(np)); | |
184cd4a3 BH |
3632 | |
3633 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
3634 | if (!prop64) { | |
3635 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
3636 | return; | |
3637 | } | |
3638 | phb_id = be64_to_cpup(prop64); | |
3639 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
3640 | ||
e39f223f | 3641 | phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); |
58d714ec GS |
3642 | |
3643 | /* Allocate PCI controller */ | |
58d714ec GS |
3644 | phb->hose = hose = pcibios_alloc_controller(np); |
3645 | if (!phb->hose) { | |
3646 | pr_err(" Can't allocate PCI controller for %s\n", | |
184cd4a3 | 3647 | np->full_name); |
e39f223f | 3648 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
184cd4a3 BH |
3649 | return; |
3650 | } | |
3651 | ||
3652 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
3653 | prop32 = of_get_property(np, "bus-range", &len); |
3654 | if (prop32 && len == 8) { | |
3a1a4661 BH |
3655 | hose->first_busno = be32_to_cpu(prop32[0]); |
3656 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e GS |
3657 | } else { |
3658 | pr_warn(" Broken <bus-range> on %s\n", np->full_name); | |
3659 | hose->first_busno = 0; | |
3660 | hose->last_busno = 0xff; | |
3661 | } | |
184cd4a3 | 3662 | hose->private_data = phb; |
e9cc17d4 | 3663 | phb->hub_id = hub_id; |
184cd4a3 | 3664 | phb->opal_id = phb_id; |
aa0c033f | 3665 | phb->type = ioda_type; |
781a868f | 3666 | mutex_init(&phb->ioda.pe_alloc_mutex); |
184cd4a3 | 3667 | |
cee72d5b BH |
3668 | /* Detect specific models for error handling */ |
3669 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
3670 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 3671 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 3672 | phb->model = PNV_PHB_MODEL_PHB3; |
5d2aa710 AP |
3673 | else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) |
3674 | phb->model = PNV_PHB_MODEL_NPU; | |
616badd2 AP |
3675 | else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) |
3676 | phb->model = PNV_PHB_MODEL_NPU2; | |
cee72d5b BH |
3677 | else |
3678 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
3679 | ||
aa0c033f | 3680 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 3681 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 3682 | |
aa0c033f | 3683 | /* Get registers */ |
fd141d1a BH |
3684 | if (!of_address_to_resource(np, 0, &r)) { |
3685 | phb->regs_phys = r.start; | |
3686 | phb->regs = ioremap(r.start, resource_size(&r)); | |
3687 | if (phb->regs == NULL) | |
3688 | pr_err(" Failed to map registers !\n"); | |
3689 | } | |
577c8c88 | 3690 | |
184cd4a3 | 3691 | /* Initialize more IODA stuff */ |
92b8f137 | 3692 | phb->ioda.total_pe_num = 1; |
aa0c033f | 3693 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 3694 | if (prop32) |
92b8f137 | 3695 | phb->ioda.total_pe_num = be32_to_cpup(prop32); |
36954dc7 GS |
3696 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
3697 | if (prop32) | |
92b8f137 | 3698 | phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); |
262af557 | 3699 | |
c127562a GS |
3700 | /* Invalidate RID to PE# mapping */ |
3701 | for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) | |
3702 | phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; | |
3703 | ||
262af557 GC |
3704 | /* Parse 64-bit MMIO range */ |
3705 | pnv_ioda_parse_m64_window(phb); | |
3706 | ||
184cd4a3 | 3707 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 3708 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
3709 | phb->ioda.m32_size += 0x10000; |
3710 | ||
92b8f137 | 3711 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; |
3fd47f06 | 3712 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 | 3713 | phb->ioda.io_size = hose->pci_io_size; |
92b8f137 | 3714 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; |
184cd4a3 BH |
3715 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ |
3716 | ||
2b923ed1 GS |
3717 | /* Calculate how many 32-bit TCE segments we have */ |
3718 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / | |
3719 | PNV_IODA1_DMA32_SEGSIZE; | |
3720 | ||
c35d2a8c | 3721 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
92a86756 AK |
3722 | size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, |
3723 | sizeof(unsigned long)); | |
93289d8c GS |
3724 | m64map_off = size; |
3725 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); | |
184cd4a3 | 3726 | m32map_off = size; |
92b8f137 | 3727 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
3728 | if (phb->type == PNV_PHB_IODA1) { |
3729 | iomap_off = size; | |
92b8f137 | 3730 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); |
2b923ed1 GS |
3731 | dma32map_off = size; |
3732 | size += phb->ioda.dma32_count * | |
3733 | sizeof(phb->ioda.dma32_segmap[0]); | |
c35d2a8c | 3734 | } |
184cd4a3 | 3735 | pemap_off = size; |
92b8f137 | 3736 | size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); |
e39f223f | 3737 | aux = memblock_virt_alloc(size, 0); |
184cd4a3 | 3738 | phb->ioda.pe_alloc = aux; |
93289d8c | 3739 | phb->ioda.m64_segmap = aux + m64map_off; |
184cd4a3 | 3740 | phb->ioda.m32_segmap = aux + m32map_off; |
93289d8c GS |
3741 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { |
3742 | phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3743 | phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; |
93289d8c | 3744 | } |
3fa23ff8 | 3745 | if (phb->type == PNV_PHB_IODA1) { |
c35d2a8c | 3746 | phb->ioda.io_segmap = aux + iomap_off; |
3fa23ff8 GS |
3747 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) |
3748 | phb->ioda.io_segmap[segno] = IODA_INVALID_PE; | |
2b923ed1 GS |
3749 | |
3750 | phb->ioda.dma32_segmap = aux + dma32map_off; | |
3751 | for (segno = 0; segno < phb->ioda.dma32_count; segno++) | |
3752 | phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3753 | } |
184cd4a3 | 3754 | phb->ioda.pe_array = aux + pemap_off; |
63803c39 GS |
3755 | |
3756 | /* | |
3757 | * Choose PE number for root bus, which shouldn't have | |
3758 | * M64 resources consumed by its child devices. To pick | |
3759 | * the PE number adjacent to the reserved one if possible. | |
3760 | */ | |
3761 | pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); | |
3762 | if (phb->ioda.reserved_pe_idx == 0) { | |
3763 | phb->ioda.root_pe_idx = 1; | |
3764 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); | |
3765 | } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { | |
3766 | phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; | |
3767 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); | |
3768 | } else { | |
3769 | phb->ioda.root_pe_idx = IODA_INVALID_PE; | |
3770 | } | |
184cd4a3 BH |
3771 | |
3772 | INIT_LIST_HEAD(&phb->ioda.pe_list); | |
781a868f | 3773 | mutex_init(&phb->ioda.pe_list_mutex); |
184cd4a3 BH |
3774 | |
3775 | /* Calculate how many 32-bit TCE segments we have */ | |
2b923ed1 | 3776 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
acce971c | 3777 | PNV_IODA1_DMA32_SEGSIZE; |
184cd4a3 | 3778 | |
aa0c033f | 3779 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
3780 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
3781 | window_type, | |
3782 | window_num, | |
3783 | starting_real_address, | |
3784 | starting_pci_address, | |
3785 | segment_size); | |
3786 | #endif | |
3787 | ||
262af557 | 3788 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
92b8f137 | 3789 | phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, |
262af557 GC |
3790 | phb->ioda.m32_size, phb->ioda.m32_segsize); |
3791 | if (phb->ioda.m64_size) | |
3792 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", | |
3793 | phb->ioda.m64_size, phb->ioda.m64_segsize); | |
3794 | if (phb->ioda.io_size) | |
3795 | pr_info(" IO: 0x%x [segment=0x%x]\n", | |
3796 | phb->ioda.io_size, phb->ioda.io_segsize); | |
3797 | ||
184cd4a3 | 3798 | |
184cd4a3 | 3799 | phb->hose->ops = &pnv_pci_ops; |
49dec922 GS |
3800 | phb->get_pe_state = pnv_ioda_get_pe_state; |
3801 | phb->freeze_pe = pnv_ioda_freeze_pe; | |
3802 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | |
184cd4a3 | 3803 | |
184cd4a3 BH |
3804 | /* Setup MSI support */ |
3805 | pnv_pci_init_ioda_msis(phb); | |
3806 | ||
c40a4210 GS |
3807 | /* |
3808 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
3809 | * to let the PCI core do resource assignment. It's supposed | |
3810 | * that the PCI core will do correct I/O and MMIO alignment | |
3811 | * for the P2P bridge bars so that each PCI bus (excluding | |
3812 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 3813 | */ |
fb446ad0 | 3814 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
5d2aa710 | 3815 | |
f9f83456 | 3816 | if (phb->type == PNV_PHB_NPU) { |
5d2aa710 | 3817 | hose->controller_ops = pnv_npu_ioda_controller_ops; |
f9f83456 AK |
3818 | } else { |
3819 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
5d2aa710 | 3820 | hose->controller_ops = pnv_pci_ioda_controller_ops; |
f9f83456 | 3821 | } |
ad30cb99 | 3822 | |
6e628c7d WY |
3823 | #ifdef CONFIG_PCI_IOV |
3824 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; | |
5350ab3f | 3825 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
ad30cb99 ME |
3826 | #endif |
3827 | ||
c40a4210 | 3828 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
3829 | |
3830 | /* Reset IODA tables to a clean state */ | |
d1a85eee | 3831 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
184cd4a3 | 3832 | if (rc) |
f11fe552 | 3833 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
361f2a2a | 3834 | |
6060e9ea AD |
3835 | /* |
3836 | * If we're running in kdump kernel, the previous kernel never | |
361f2a2a GS |
3837 | * shutdown PCI devices correctly. We already got IODA table |
3838 | * cleaned out. So we have to issue PHB reset to stop all PCI | |
6060e9ea | 3839 | * transactions from previous kernel. |
361f2a2a GS |
3840 | */ |
3841 | if (is_kdump_kernel()) { | |
3842 | pr_info(" Issue PHB reset ...\n"); | |
cadf364d GS |
3843 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
3844 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); | |
361f2a2a | 3845 | } |
262af557 | 3846 | |
9e9e8935 GS |
3847 | /* Remove M64 resource if we can't configure it successfully */ |
3848 | if (!phb->init_m64 || phb->init_m64(phb)) | |
262af557 | 3849 | hose->mem_resources[1].flags = 0; |
aa0c033f GS |
3850 | } |
3851 | ||
67975005 | 3852 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 3853 | { |
e9cc17d4 | 3854 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
3855 | } |
3856 | ||
5d2aa710 AP |
3857 | void __init pnv_pci_init_npu_phb(struct device_node *np) |
3858 | { | |
3859 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); | |
3860 | } | |
3861 | ||
184cd4a3 BH |
3862 | void __init pnv_pci_init_ioda_hub(struct device_node *np) |
3863 | { | |
3864 | struct device_node *phbn; | |
c681b93c | 3865 | const __be64 *prop64; |
184cd4a3 BH |
3866 | u64 hub_id; |
3867 | ||
3868 | pr_info("Probing IODA IO-Hub %s\n", np->full_name); | |
3869 | ||
3870 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
3871 | if (!prop64) { | |
3872 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
3873 | return; | |
3874 | } | |
3875 | hub_id = be64_to_cpup(prop64); | |
3876 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
3877 | ||
3878 | /* Count child PHBs */ | |
3879 | for_each_child_of_node(np, phbn) { | |
3880 | /* Look for IODA1 PHBs */ | |
3881 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 3882 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
3883 | } |
3884 | } |