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184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
361f2a2a | 16 | #include <linux/crash_dump.h> |
37c367f2 | 17 | #include <linux/debugfs.h> |
184cd4a3 BH |
18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/msi.h> | |
cd15b048 | 25 | #include <linux/memblock.h> |
184cd4a3 BH |
26 | |
27 | #include <asm/sections.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/prom.h> | |
30 | #include <asm/pci-bridge.h> | |
31 | #include <asm/machdep.h> | |
fb1b55d6 | 32 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
33 | #include <asm/ppc-pci.h> |
34 | #include <asm/opal.h> | |
35 | #include <asm/iommu.h> | |
36 | #include <asm/tce.h> | |
137436c9 | 37 | #include <asm/xics.h> |
37c367f2 | 38 | #include <asm/debug.h> |
262af557 | 39 | #include <asm/firmware.h> |
80c49c7e IM |
40 | #include <asm/pnv-pci.h> |
41 | ||
42 | #include <misc/cxl.h> | |
184cd4a3 BH |
43 | |
44 | #include "powernv.h" | |
45 | #include "pci.h" | |
46 | ||
6d31c2fa JP |
47 | static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
48 | const char *fmt, ...) | |
49 | { | |
50 | struct va_format vaf; | |
51 | va_list args; | |
52 | char pfix[32]; | |
53 | ||
54 | va_start(args, fmt); | |
55 | ||
56 | vaf.fmt = fmt; | |
57 | vaf.va = &args; | |
58 | ||
59 | if (pe->pdev) | |
60 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); | |
61 | else | |
62 | sprintf(pfix, "%04x:%02x ", | |
63 | pci_domain_nr(pe->pbus), pe->pbus->number); | |
64 | ||
65 | printk("%spci %s: [PE# %.3d] %pV", | |
66 | level, pfix, pe->pe_number, &vaf); | |
67 | ||
68 | va_end(args); | |
69 | } | |
184cd4a3 | 70 | |
6d31c2fa JP |
71 | #define pe_err(pe, fmt, ...) \ |
72 | pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) | |
73 | #define pe_warn(pe, fmt, ...) \ | |
74 | pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) | |
75 | #define pe_info(pe, fmt, ...) \ | |
76 | pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) | |
184cd4a3 | 77 | |
8e0a1611 AK |
78 | /* |
79 | * stdcix is only supposed to be used in hypervisor real mode as per | |
80 | * the architecture spec | |
81 | */ | |
82 | static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) | |
83 | { | |
84 | __asm__ __volatile__("stdcix %0,0,%1" | |
85 | : : "r" (val), "r" (paddr) : "memory"); | |
86 | } | |
87 | ||
262af557 GC |
88 | static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) |
89 | { | |
90 | return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == | |
91 | (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); | |
92 | } | |
93 | ||
4b82ab18 GS |
94 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
95 | { | |
96 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) { | |
97 | pr_warn("%s: Invalid PE %d on PHB#%x\n", | |
98 | __func__, pe_no, phb->hose->global_number); | |
99 | return; | |
100 | } | |
101 | ||
102 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) { | |
103 | pr_warn("%s: PE %d was assigned on PHB#%x\n", | |
104 | __func__, pe_no, phb->hose->global_number); | |
105 | return; | |
106 | } | |
107 | ||
108 | phb->ioda.pe_array[pe_no].phb = phb; | |
109 | phb->ioda.pe_array[pe_no].pe_number = pe_no; | |
110 | } | |
111 | ||
cad5cef6 | 112 | static int pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 BH |
113 | { |
114 | unsigned long pe; | |
115 | ||
116 | do { | |
117 | pe = find_next_zero_bit(phb->ioda.pe_alloc, | |
118 | phb->ioda.total_pe, 0); | |
119 | if (pe >= phb->ioda.total_pe) | |
120 | return IODA_INVALID_PE; | |
121 | } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); | |
122 | ||
4cce9550 | 123 | phb->ioda.pe_array[pe].phb = phb; |
184cd4a3 BH |
124 | phb->ioda.pe_array[pe].pe_number = pe; |
125 | return pe; | |
126 | } | |
127 | ||
cad5cef6 | 128 | static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) |
184cd4a3 BH |
129 | { |
130 | WARN_ON(phb->ioda.pe_array[pe].pdev); | |
131 | ||
132 | memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); | |
133 | clear_bit(pe, phb->ioda.pe_alloc); | |
134 | } | |
135 | ||
262af557 GC |
136 | /* The default M64 BAR is shared by all PEs */ |
137 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) | |
138 | { | |
139 | const char *desc; | |
140 | struct resource *r; | |
141 | s64 rc; | |
142 | ||
143 | /* Configure the default M64 BAR */ | |
144 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
145 | OPAL_M64_WINDOW_TYPE, | |
146 | phb->ioda.m64_bar_idx, | |
147 | phb->ioda.m64_base, | |
148 | 0, /* unused */ | |
149 | phb->ioda.m64_size); | |
150 | if (rc != OPAL_SUCCESS) { | |
151 | desc = "configuring"; | |
152 | goto fail; | |
153 | } | |
154 | ||
155 | /* Enable the default M64 BAR */ | |
156 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
157 | OPAL_M64_WINDOW_TYPE, | |
158 | phb->ioda.m64_bar_idx, | |
159 | OPAL_ENABLE_M64_SPLIT); | |
160 | if (rc != OPAL_SUCCESS) { | |
161 | desc = "enabling"; | |
162 | goto fail; | |
163 | } | |
164 | ||
165 | /* Mark the M64 BAR assigned */ | |
166 | set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); | |
167 | ||
168 | /* | |
169 | * Strip off the segment used by the reserved PE, which is | |
170 | * expected to be 0 or last one of PE capabicity. | |
171 | */ | |
172 | r = &phb->hose->mem_resources[1]; | |
173 | if (phb->ioda.reserved_pe == 0) | |
174 | r->start += phb->ioda.m64_segsize; | |
175 | else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) | |
176 | r->end -= phb->ioda.m64_segsize; | |
177 | else | |
178 | pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", | |
179 | phb->ioda.reserved_pe); | |
180 | ||
181 | return 0; | |
182 | ||
183 | fail: | |
184 | pr_warn(" Failure %lld %s M64 BAR#%d\n", | |
185 | rc, desc, phb->ioda.m64_bar_idx); | |
186 | opal_pci_phb_mmio_enable(phb->opal_id, | |
187 | OPAL_M64_WINDOW_TYPE, | |
188 | phb->ioda.m64_bar_idx, | |
189 | OPAL_DISABLE_M64); | |
190 | return -EIO; | |
191 | } | |
192 | ||
5ef73567 | 193 | static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) |
262af557 GC |
194 | { |
195 | resource_size_t sgsz = phb->ioda.m64_segsize; | |
196 | struct pci_dev *pdev; | |
197 | struct resource *r; | |
198 | int base, step, i; | |
199 | ||
200 | /* | |
201 | * Root bus always has full M64 range and root port has | |
202 | * M64 range used in reality. So we're checking root port | |
203 | * instead of root bus. | |
204 | */ | |
205 | list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) { | |
4b82ab18 GS |
206 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
207 | r = &pdev->resource[PCI_BRIDGE_RESOURCES + i]; | |
262af557 GC |
208 | if (!r->parent || |
209 | !pnv_pci_is_mem_pref_64(r->flags)) | |
210 | continue; | |
211 | ||
212 | base = (r->start - phb->ioda.m64_base) / sgsz; | |
213 | for (step = 0; step < resource_size(r) / sgsz; step++) | |
4b82ab18 | 214 | pnv_ioda_reserve_pe(phb, base + step); |
262af557 GC |
215 | } |
216 | } | |
217 | } | |
218 | ||
219 | static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, | |
220 | struct pci_bus *bus, int all) | |
221 | { | |
222 | resource_size_t segsz = phb->ioda.m64_segsize; | |
223 | struct pci_dev *pdev; | |
224 | struct resource *r; | |
225 | struct pnv_ioda_pe *master_pe, *pe; | |
226 | unsigned long size, *pe_alloc; | |
227 | bool found; | |
228 | int start, i, j; | |
229 | ||
230 | /* Root bus shouldn't use M64 */ | |
231 | if (pci_is_root_bus(bus)) | |
232 | return IODA_INVALID_PE; | |
233 | ||
234 | /* We support only one M64 window on each bus */ | |
235 | found = false; | |
236 | pci_bus_for_each_resource(bus, r, i) { | |
237 | if (r && r->parent && | |
238 | pnv_pci_is_mem_pref_64(r->flags)) { | |
239 | found = true; | |
240 | break; | |
241 | } | |
242 | } | |
243 | ||
244 | /* No M64 window found ? */ | |
245 | if (!found) | |
246 | return IODA_INVALID_PE; | |
247 | ||
248 | /* Allocate bitmap */ | |
249 | size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); | |
250 | pe_alloc = kzalloc(size, GFP_KERNEL); | |
251 | if (!pe_alloc) { | |
252 | pr_warn("%s: Out of memory !\n", | |
253 | __func__); | |
254 | return IODA_INVALID_PE; | |
255 | } | |
256 | ||
257 | /* | |
258 | * Figure out reserved PE numbers by the PE | |
259 | * the its child PEs. | |
260 | */ | |
261 | start = (r->start - phb->ioda.m64_base) / segsz; | |
262 | for (i = 0; i < resource_size(r) / segsz; i++) | |
263 | set_bit(start + i, pe_alloc); | |
264 | ||
265 | if (all) | |
266 | goto done; | |
267 | ||
268 | /* | |
269 | * If the PE doesn't cover all subordinate buses, | |
270 | * we need subtract from reserved PEs for children. | |
271 | */ | |
272 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
273 | if (!pdev->subordinate) | |
274 | continue; | |
275 | ||
276 | pci_bus_for_each_resource(pdev->subordinate, r, i) { | |
277 | if (!r || !r->parent || | |
278 | !pnv_pci_is_mem_pref_64(r->flags)) | |
279 | continue; | |
280 | ||
281 | start = (r->start - phb->ioda.m64_base) / segsz; | |
282 | for (j = 0; j < resource_size(r) / segsz ; j++) | |
283 | clear_bit(start + j, pe_alloc); | |
284 | } | |
285 | } | |
286 | ||
287 | /* | |
288 | * the current bus might not own M64 window and that's all | |
289 | * contributed by its child buses. For the case, we needn't | |
290 | * pick M64 dependent PE#. | |
291 | */ | |
292 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) { | |
293 | kfree(pe_alloc); | |
294 | return IODA_INVALID_PE; | |
295 | } | |
296 | ||
297 | /* | |
298 | * Figure out the master PE and put all slave PEs to master | |
299 | * PE's list to form compound PE. | |
300 | */ | |
301 | done: | |
302 | master_pe = NULL; | |
303 | i = -1; | |
304 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) < | |
305 | phb->ioda.total_pe) { | |
306 | pe = &phb->ioda.pe_array[i]; | |
262af557 GC |
307 | |
308 | if (!master_pe) { | |
309 | pe->flags |= PNV_IODA_PE_MASTER; | |
310 | INIT_LIST_HEAD(&pe->slaves); | |
311 | master_pe = pe; | |
312 | } else { | |
313 | pe->flags |= PNV_IODA_PE_SLAVE; | |
314 | pe->master = master_pe; | |
315 | list_add_tail(&pe->list, &master_pe->slaves); | |
316 | } | |
317 | } | |
318 | ||
319 | kfree(pe_alloc); | |
320 | return master_pe->pe_number; | |
321 | } | |
322 | ||
323 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) | |
324 | { | |
325 | struct pci_controller *hose = phb->hose; | |
326 | struct device_node *dn = hose->dn; | |
327 | struct resource *res; | |
328 | const u32 *r; | |
329 | u64 pci_addr; | |
330 | ||
1665c4a8 GS |
331 | /* FIXME: Support M64 for P7IOC */ |
332 | if (phb->type != PNV_PHB_IODA2) { | |
333 | pr_info(" Not support M64 window\n"); | |
334 | return; | |
335 | } | |
336 | ||
262af557 GC |
337 | if (!firmware_has_feature(FW_FEATURE_OPALv3)) { |
338 | pr_info(" Firmware too old to support M64 window\n"); | |
339 | return; | |
340 | } | |
341 | ||
342 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); | |
343 | if (!r) { | |
344 | pr_info(" No <ibm,opal-m64-window> on %s\n", | |
345 | dn->full_name); | |
346 | return; | |
347 | } | |
348 | ||
262af557 GC |
349 | res = &hose->mem_resources[1]; |
350 | res->start = of_translate_address(dn, r + 2); | |
351 | res->end = res->start + of_read_number(r + 4, 2) - 1; | |
352 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
353 | pci_addr = of_read_number(r, 2); | |
354 | hose->mem_offset[1] = res->start - pci_addr; | |
355 | ||
356 | phb->ioda.m64_size = resource_size(res); | |
357 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe; | |
358 | phb->ioda.m64_base = pci_addr; | |
359 | ||
360 | /* Use last M64 BAR to cover M64 window */ | |
361 | phb->ioda.m64_bar_idx = 15; | |
362 | phb->init_m64 = pnv_ioda2_init_m64; | |
5ef73567 | 363 | phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; |
262af557 GC |
364 | phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; |
365 | } | |
366 | ||
49dec922 GS |
367 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
368 | { | |
369 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; | |
370 | struct pnv_ioda_pe *slave; | |
371 | s64 rc; | |
372 | ||
373 | /* Fetch master PE */ | |
374 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
375 | pe = pe->master; | |
376 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
377 | pe_no = pe->pe_number; | |
378 | } | |
379 | ||
380 | /* Freeze master PE */ | |
381 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
382 | pe_no, | |
383 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
384 | if (rc != OPAL_SUCCESS) { | |
385 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
386 | __func__, rc, phb->hose->global_number, pe_no); | |
387 | return; | |
388 | } | |
389 | ||
390 | /* Freeze slave PEs */ | |
391 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
392 | return; | |
393 | ||
394 | list_for_each_entry(slave, &pe->slaves, list) { | |
395 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
396 | slave->pe_number, | |
397 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
398 | if (rc != OPAL_SUCCESS) | |
399 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
400 | __func__, rc, phb->hose->global_number, | |
401 | slave->pe_number); | |
402 | } | |
403 | } | |
404 | ||
e51df2c1 | 405 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
49dec922 GS |
406 | { |
407 | struct pnv_ioda_pe *pe, *slave; | |
408 | s64 rc; | |
409 | ||
410 | /* Find master PE */ | |
411 | pe = &phb->ioda.pe_array[pe_no]; | |
412 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
413 | pe = pe->master; | |
414 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
415 | pe_no = pe->pe_number; | |
416 | } | |
417 | ||
418 | /* Clear frozen state for master PE */ | |
419 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); | |
420 | if (rc != OPAL_SUCCESS) { | |
421 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
422 | __func__, rc, opt, phb->hose->global_number, pe_no); | |
423 | return -EIO; | |
424 | } | |
425 | ||
426 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
427 | return 0; | |
428 | ||
429 | /* Clear frozen state for slave PEs */ | |
430 | list_for_each_entry(slave, &pe->slaves, list) { | |
431 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
432 | slave->pe_number, | |
433 | opt); | |
434 | if (rc != OPAL_SUCCESS) { | |
435 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
436 | __func__, rc, opt, phb->hose->global_number, | |
437 | slave->pe_number); | |
438 | return -EIO; | |
439 | } | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) | |
446 | { | |
447 | struct pnv_ioda_pe *slave, *pe; | |
448 | u8 fstate, state; | |
449 | __be16 pcierr; | |
450 | s64 rc; | |
451 | ||
452 | /* Sanity check on PE number */ | |
453 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe) | |
454 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; | |
455 | ||
456 | /* | |
457 | * Fetch the master PE and the PE instance might be | |
458 | * not initialized yet. | |
459 | */ | |
460 | pe = &phb->ioda.pe_array[pe_no]; | |
461 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
462 | pe = pe->master; | |
463 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
464 | pe_no = pe->pe_number; | |
465 | } | |
466 | ||
467 | /* Check the master PE */ | |
468 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, | |
469 | &state, &pcierr, NULL); | |
470 | if (rc != OPAL_SUCCESS) { | |
471 | pr_warn("%s: Failure %lld getting " | |
472 | "PHB#%x-PE#%x state\n", | |
473 | __func__, rc, | |
474 | phb->hose->global_number, pe_no); | |
475 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
476 | } | |
477 | ||
478 | /* Check the slave PE */ | |
479 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
480 | return state; | |
481 | ||
482 | list_for_each_entry(slave, &pe->slaves, list) { | |
483 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
484 | slave->pe_number, | |
485 | &fstate, | |
486 | &pcierr, | |
487 | NULL); | |
488 | if (rc != OPAL_SUCCESS) { | |
489 | pr_warn("%s: Failure %lld getting " | |
490 | "PHB#%x-PE#%x state\n", | |
491 | __func__, rc, | |
492 | phb->hose->global_number, slave->pe_number); | |
493 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
494 | } | |
495 | ||
496 | /* | |
497 | * Override the result based on the ascending | |
498 | * priority. | |
499 | */ | |
500 | if (fstate > state) | |
501 | state = fstate; | |
502 | } | |
503 | ||
504 | return state; | |
505 | } | |
506 | ||
184cd4a3 BH |
507 | /* Currently those 2 are only used when MSIs are enabled, this will change |
508 | * but in the meantime, we need to protect them to avoid warnings | |
509 | */ | |
510 | #ifdef CONFIG_PCI_MSI | |
cad5cef6 | 511 | static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
512 | { |
513 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
514 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 515 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
516 | |
517 | if (!pdn) | |
518 | return NULL; | |
519 | if (pdn->pe_number == IODA_INVALID_PE) | |
520 | return NULL; | |
521 | return &phb->ioda.pe_array[pdn->pe_number]; | |
522 | } | |
184cd4a3 BH |
523 | #endif /* CONFIG_PCI_MSI */ |
524 | ||
cad5cef6 | 525 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
526 | { |
527 | struct pci_dev *parent; | |
528 | uint8_t bcomp, dcomp, fcomp; | |
529 | long rc, rid_end, rid; | |
530 | ||
531 | /* Bus validation ? */ | |
532 | if (pe->pbus) { | |
533 | int count; | |
534 | ||
535 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
536 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
537 | parent = pe->pbus->self; | |
fb446ad0 GS |
538 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
539 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
540 | else | |
541 | count = 1; | |
542 | ||
184cd4a3 BH |
543 | switch(count) { |
544 | case 1: bcomp = OpalPciBusAll; break; | |
545 | case 2: bcomp = OpalPciBus7Bits; break; | |
546 | case 4: bcomp = OpalPciBus6Bits; break; | |
547 | case 8: bcomp = OpalPciBus5Bits; break; | |
548 | case 16: bcomp = OpalPciBus4Bits; break; | |
549 | case 32: bcomp = OpalPciBus3Bits; break; | |
550 | default: | |
551 | pr_err("%s: Number of subordinate busses %d" | |
552 | " unsupported\n", | |
553 | pci_name(pe->pbus->self), count); | |
554 | /* Do an exact match only */ | |
555 | bcomp = OpalPciBusAll; | |
556 | } | |
557 | rid_end = pe->rid + (count << 8); | |
558 | } else { | |
559 | parent = pe->pdev->bus->self; | |
560 | bcomp = OpalPciBusAll; | |
561 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
562 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
563 | rid_end = pe->rid + 1; | |
564 | } | |
565 | ||
631ad691 GS |
566 | /* |
567 | * Associate PE in PELT. We need add the PE into the | |
568 | * corresponding PELT-V as well. Otherwise, the error | |
569 | * originated from the PE might contribute to other | |
570 | * PEs. | |
571 | */ | |
184cd4a3 BH |
572 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
573 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
574 | if (rc) { | |
575 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
576 | return -ENXIO; | |
577 | } | |
631ad691 GS |
578 | |
579 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
580 | pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); | |
581 | if (rc) | |
582 | pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); | |
184cd4a3 BH |
583 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
584 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
585 | ||
586 | /* Add to all parents PELT-V */ | |
587 | while (parent) { | |
b72c1f65 | 588 | struct pci_dn *pdn = pci_get_pdn(parent); |
184cd4a3 BH |
589 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { |
590 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
cee72d5b | 591 | pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); |
184cd4a3 BH |
592 | /* XXX What to do in case of error ? */ |
593 | } | |
594 | parent = parent->bus->self; | |
595 | } | |
596 | /* Setup reverse map */ | |
597 | for (rid = pe->rid; rid < rid_end; rid++) | |
598 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
599 | ||
600 | /* Setup one MVTs on IODA1 */ | |
601 | if (phb->type == PNV_PHB_IODA1) { | |
602 | pe->mve_number = pe->pe_number; | |
603 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, | |
604 | pe->pe_number); | |
605 | if (rc) { | |
606 | pe_err(pe, "OPAL error %ld setting up MVE %d\n", | |
607 | rc, pe->mve_number); | |
608 | pe->mve_number = -1; | |
609 | } else { | |
610 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
cee72d5b | 611 | pe->mve_number, OPAL_ENABLE_MVE); |
184cd4a3 BH |
612 | if (rc) { |
613 | pe_err(pe, "OPAL error %ld enabling MVE %d\n", | |
614 | rc, pe->mve_number); | |
615 | pe->mve_number = -1; | |
616 | } | |
617 | } | |
618 | } else if (phb->type == PNV_PHB_IODA2) | |
619 | pe->mve_number = 0; | |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
cad5cef6 GKH |
624 | static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, |
625 | struct pnv_ioda_pe *pe) | |
184cd4a3 BH |
626 | { |
627 | struct pnv_ioda_pe *lpe; | |
628 | ||
7ebdf956 | 629 | list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 | 630 | if (lpe->dma_weight < pe->dma_weight) { |
7ebdf956 | 631 | list_add_tail(&pe->dma_link, &lpe->dma_link); |
184cd4a3 BH |
632 | return; |
633 | } | |
634 | } | |
7ebdf956 | 635 | list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); |
184cd4a3 BH |
636 | } |
637 | ||
638 | static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) | |
639 | { | |
640 | /* This is quite simplistic. The "base" weight of a device | |
641 | * is 10. 0 means no DMA is to be accounted for it. | |
642 | */ | |
643 | ||
644 | /* If it's a bridge, no DMA */ | |
645 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
646 | return 0; | |
647 | ||
648 | /* Reduce the weight of slow USB controllers */ | |
649 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
650 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
651 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
652 | return 3; | |
653 | ||
654 | /* Increase the weight of RAID (includes Obsidian) */ | |
655 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
656 | return 15; | |
657 | ||
658 | /* Default */ | |
659 | return 10; | |
660 | } | |
661 | ||
fb446ad0 | 662 | #if 0 |
cad5cef6 | 663 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
664 | { |
665 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
666 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 667 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
668 | struct pnv_ioda_pe *pe; |
669 | int pe_num; | |
670 | ||
671 | if (!pdn) { | |
672 | pr_err("%s: Device tree node not associated properly\n", | |
673 | pci_name(dev)); | |
674 | return NULL; | |
675 | } | |
676 | if (pdn->pe_number != IODA_INVALID_PE) | |
677 | return NULL; | |
678 | ||
679 | /* PE#0 has been pre-set */ | |
680 | if (dev->bus->number == 0) | |
681 | pe_num = 0; | |
682 | else | |
683 | pe_num = pnv_ioda_alloc_pe(phb); | |
684 | if (pe_num == IODA_INVALID_PE) { | |
685 | pr_warning("%s: Not enough PE# available, disabling device\n", | |
686 | pci_name(dev)); | |
687 | return NULL; | |
688 | } | |
689 | ||
690 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
691 | * pointer in the PE data structure, both should be destroyed at the | |
692 | * same time. However, this needs to be looked at more closely again | |
693 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
694 | * | |
695 | * At some point we want to remove the PDN completely anyways | |
696 | */ | |
697 | pe = &phb->ioda.pe_array[pe_num]; | |
698 | pci_dev_get(dev); | |
699 | pdn->pcidev = dev; | |
700 | pdn->pe_number = pe_num; | |
701 | pe->pdev = dev; | |
702 | pe->pbus = NULL; | |
703 | pe->tce32_seg = -1; | |
704 | pe->mve_number = -1; | |
705 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
706 | ||
707 | pe_info(pe, "Associated device to PE\n"); | |
708 | ||
709 | if (pnv_ioda_configure_pe(phb, pe)) { | |
710 | /* XXX What do we do here ? */ | |
711 | if (pe_num) | |
712 | pnv_ioda_free_pe(phb, pe_num); | |
713 | pdn->pe_number = IODA_INVALID_PE; | |
714 | pe->pdev = NULL; | |
715 | pci_dev_put(dev); | |
716 | return NULL; | |
717 | } | |
718 | ||
719 | /* Assign a DMA weight to the device */ | |
720 | pe->dma_weight = pnv_ioda_dma_weight(dev); | |
721 | if (pe->dma_weight != 0) { | |
722 | phb->ioda.dma_weight += pe->dma_weight; | |
723 | phb->ioda.dma_pe_count++; | |
724 | } | |
725 | ||
726 | /* Link the PE */ | |
727 | pnv_ioda_link_pe_by_weight(phb, pe); | |
728 | ||
729 | return pe; | |
730 | } | |
fb446ad0 | 731 | #endif /* Useful for SRIOV case */ |
184cd4a3 BH |
732 | |
733 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
734 | { | |
735 | struct pci_dev *dev; | |
736 | ||
737 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 738 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
739 | |
740 | if (pdn == NULL) { | |
741 | pr_warn("%s: No device node associated with device !\n", | |
742 | pci_name(dev)); | |
743 | continue; | |
744 | } | |
184cd4a3 BH |
745 | pdn->pcidev = dev; |
746 | pdn->pe_number = pe->pe_number; | |
747 | pe->dma_weight += pnv_ioda_dma_weight(dev); | |
fb446ad0 | 748 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
749 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
750 | } | |
751 | } | |
752 | ||
fb446ad0 GS |
753 | /* |
754 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
755 | * single PCI bus. Another one that contains the primary PCI bus and its | |
756 | * subordinate PCI devices and buses. The second type of PE is normally | |
757 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
758 | */ | |
cad5cef6 | 759 | static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) |
184cd4a3 | 760 | { |
fb446ad0 | 761 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 762 | struct pnv_phb *phb = hose->private_data; |
184cd4a3 | 763 | struct pnv_ioda_pe *pe; |
262af557 GC |
764 | int pe_num = IODA_INVALID_PE; |
765 | ||
766 | /* Check if PE is determined by M64 */ | |
767 | if (phb->pick_m64_pe) | |
768 | pe_num = phb->pick_m64_pe(phb, bus, all); | |
769 | ||
770 | /* The PE number isn't pinned by M64 */ | |
771 | if (pe_num == IODA_INVALID_PE) | |
772 | pe_num = pnv_ioda_alloc_pe(phb); | |
184cd4a3 | 773 | |
184cd4a3 | 774 | if (pe_num == IODA_INVALID_PE) { |
fb446ad0 GS |
775 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
776 | __func__, pci_domain_nr(bus), bus->number); | |
184cd4a3 BH |
777 | return; |
778 | } | |
779 | ||
780 | pe = &phb->ioda.pe_array[pe_num]; | |
262af557 | 781 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
782 | pe->pbus = bus; |
783 | pe->pdev = NULL; | |
784 | pe->tce32_seg = -1; | |
785 | pe->mve_number = -1; | |
b918c62e | 786 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 BH |
787 | pe->dma_weight = 0; |
788 | ||
fb446ad0 GS |
789 | if (all) |
790 | pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", | |
791 | bus->busn_res.start, bus->busn_res.end, pe_num); | |
792 | else | |
793 | pe_info(pe, "Secondary bus %d associated with PE#%d\n", | |
794 | bus->busn_res.start, pe_num); | |
184cd4a3 BH |
795 | |
796 | if (pnv_ioda_configure_pe(phb, pe)) { | |
797 | /* XXX What do we do here ? */ | |
798 | if (pe_num) | |
799 | pnv_ioda_free_pe(phb, pe_num); | |
800 | pe->pbus = NULL; | |
801 | return; | |
802 | } | |
803 | ||
804 | /* Associate it with all child devices */ | |
805 | pnv_ioda_setup_same_PE(bus, pe); | |
806 | ||
7ebdf956 GS |
807 | /* Put PE to the list */ |
808 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
809 | ||
184cd4a3 BH |
810 | /* Account for one DMA PE if at least one DMA capable device exist |
811 | * below the bridge | |
812 | */ | |
813 | if (pe->dma_weight != 0) { | |
814 | phb->ioda.dma_weight += pe->dma_weight; | |
815 | phb->ioda.dma_pe_count++; | |
816 | } | |
817 | ||
818 | /* Link the PE */ | |
819 | pnv_ioda_link_pe_by_weight(phb, pe); | |
820 | } | |
821 | ||
cad5cef6 | 822 | static void pnv_ioda_setup_PEs(struct pci_bus *bus) |
184cd4a3 BH |
823 | { |
824 | struct pci_dev *dev; | |
fb446ad0 GS |
825 | |
826 | pnv_ioda_setup_bus_PE(bus, 0); | |
184cd4a3 BH |
827 | |
828 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
fb446ad0 GS |
829 | if (dev->subordinate) { |
830 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
831 | pnv_ioda_setup_bus_PE(dev->subordinate, 1); | |
832 | else | |
833 | pnv_ioda_setup_PEs(dev->subordinate); | |
834 | } | |
835 | } | |
836 | } | |
837 | ||
838 | /* | |
839 | * Configure PEs so that the downstream PCI buses and devices | |
840 | * could have their associated PE#. Unfortunately, we didn't | |
841 | * figure out the way to identify the PLX bridge yet. So we | |
842 | * simply put the PCI bus and the subordinate behind the root | |
843 | * port to PE# here. The game rule here is expected to be changed | |
844 | * as soon as we can detected PLX bridge correctly. | |
845 | */ | |
cad5cef6 | 846 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
847 | { |
848 | struct pci_controller *hose, *tmp; | |
262af557 | 849 | struct pnv_phb *phb; |
fb446ad0 GS |
850 | |
851 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
262af557 GC |
852 | phb = hose->private_data; |
853 | ||
854 | /* M64 layout might affect PE allocation */ | |
5ef73567 GS |
855 | if (phb->reserve_m64_pe) |
856 | phb->reserve_m64_pe(phb); | |
262af557 | 857 | |
fb446ad0 | 858 | pnv_ioda_setup_PEs(hose->bus); |
184cd4a3 BH |
859 | } |
860 | } | |
861 | ||
959c9bdd | 862 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 863 | { |
b72c1f65 | 864 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 865 | struct pnv_ioda_pe *pe; |
184cd4a3 | 866 | |
959c9bdd GS |
867 | /* |
868 | * The function can be called while the PE# | |
869 | * hasn't been assigned. Do nothing for the | |
870 | * case. | |
871 | */ | |
872 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
873 | return; | |
184cd4a3 | 874 | |
959c9bdd | 875 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
cd15b048 | 876 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
763fe0ad | 877 | set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); |
184cd4a3 BH |
878 | } |
879 | ||
cd15b048 BH |
880 | static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, |
881 | struct pci_dev *pdev, u64 dma_mask) | |
882 | { | |
883 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
884 | struct pnv_ioda_pe *pe; | |
885 | uint64_t top; | |
886 | bool bypass = false; | |
887 | ||
888 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
889 | return -ENODEV;; | |
890 | ||
891 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
892 | if (pe->tce_bypass_enabled) { | |
893 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; | |
894 | bypass = (dma_mask >= top); | |
895 | } | |
896 | ||
897 | if (bypass) { | |
898 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); | |
899 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
900 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); | |
901 | } else { | |
902 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | |
903 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | |
904 | set_iommu_table_base(&pdev->dev, &pe->tce32_table); | |
905 | } | |
a32305bf | 906 | *pdev->dev.dma_mask = dma_mask; |
cd15b048 BH |
907 | return 0; |
908 | } | |
909 | ||
fe7e85c6 GS |
910 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb, |
911 | struct pci_dev *pdev) | |
912 | { | |
913 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
914 | struct pnv_ioda_pe *pe; | |
915 | u64 end, mask; | |
916 | ||
917 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
918 | return 0; | |
919 | ||
920 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
921 | if (!pe->tce_bypass_enabled) | |
922 | return __dma_get_required_mask(&pdev->dev); | |
923 | ||
924 | ||
925 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); | |
926 | mask = 1ULL << (fls64(end) - 1); | |
927 | mask += mask - 1; | |
928 | ||
929 | return mask; | |
930 | } | |
931 | ||
dff4a39e GS |
932 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
933 | struct pci_bus *bus, | |
934 | bool add_to_iommu_group) | |
74251fe2 BH |
935 | { |
936 | struct pci_dev *dev; | |
937 | ||
938 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
dff4a39e GS |
939 | if (add_to_iommu_group) |
940 | set_iommu_table_base_and_group(&dev->dev, | |
941 | &pe->tce32_table); | |
942 | else | |
943 | set_iommu_table_base(&dev->dev, &pe->tce32_table); | |
944 | ||
74251fe2 | 945 | if (dev->subordinate) |
dff4a39e GS |
946 | pnv_ioda_setup_bus_dma(pe, dev->subordinate, |
947 | add_to_iommu_group); | |
74251fe2 BH |
948 | } |
949 | } | |
950 | ||
8e0a1611 AK |
951 | static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, |
952 | struct iommu_table *tbl, | |
3ad26e5c | 953 | __be64 *startp, __be64 *endp, bool rm) |
4cce9550 | 954 | { |
3ad26e5c BH |
955 | __be64 __iomem *invalidate = rm ? |
956 | (__be64 __iomem *)pe->tce_inval_reg_phys : | |
957 | (__be64 __iomem *)tbl->it_index; | |
4cce9550 | 958 | unsigned long start, end, inc; |
b0376c9b | 959 | const unsigned shift = tbl->it_page_shift; |
4cce9550 GS |
960 | |
961 | start = __pa(startp); | |
962 | end = __pa(endp); | |
963 | ||
964 | /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ | |
965 | if (tbl->it_busno) { | |
b0376c9b AK |
966 | start <<= shift; |
967 | end <<= shift; | |
968 | inc = 128ull << shift; | |
4cce9550 GS |
969 | start |= tbl->it_busno; |
970 | end |= tbl->it_busno; | |
971 | } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { | |
972 | /* p7ioc-style invalidation, 2 TCEs per write */ | |
973 | start |= (1ull << 63); | |
974 | end |= (1ull << 63); | |
975 | inc = 16; | |
976 | } else { | |
977 | /* Default (older HW) */ | |
978 | inc = 128; | |
979 | } | |
980 | ||
981 | end |= inc - 1; /* round up end to be different than start */ | |
982 | ||
983 | mb(); /* Ensure above stores are visible */ | |
984 | while (start <= end) { | |
8e0a1611 | 985 | if (rm) |
3ad26e5c | 986 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 987 | else |
3ad26e5c | 988 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
989 | start += inc; |
990 | } | |
991 | ||
992 | /* | |
993 | * The iommu layer will do another mb() for us on build() | |
994 | * and we don't care on free() | |
995 | */ | |
996 | } | |
997 | ||
998 | static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, | |
999 | struct iommu_table *tbl, | |
3ad26e5c | 1000 | __be64 *startp, __be64 *endp, bool rm) |
4cce9550 GS |
1001 | { |
1002 | unsigned long start, end, inc; | |
3ad26e5c BH |
1003 | __be64 __iomem *invalidate = rm ? |
1004 | (__be64 __iomem *)pe->tce_inval_reg_phys : | |
1005 | (__be64 __iomem *)tbl->it_index; | |
b0376c9b | 1006 | const unsigned shift = tbl->it_page_shift; |
4cce9550 GS |
1007 | |
1008 | /* We'll invalidate DMA address in PE scope */ | |
b0376c9b | 1009 | start = 0x2ull << 60; |
4cce9550 GS |
1010 | start |= (pe->pe_number & 0xFF); |
1011 | end = start; | |
1012 | ||
1013 | /* Figure out the start, end and step */ | |
1014 | inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); | |
b0376c9b | 1015 | start |= (inc << shift); |
4cce9550 | 1016 | inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); |
b0376c9b AK |
1017 | end |= (inc << shift); |
1018 | inc = (0x1ull << shift); | |
4cce9550 GS |
1019 | mb(); |
1020 | ||
1021 | while (start <= end) { | |
8e0a1611 | 1022 | if (rm) |
3ad26e5c | 1023 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1024 | else |
3ad26e5c | 1025 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1026 | start += inc; |
1027 | } | |
1028 | } | |
1029 | ||
1030 | void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, | |
3ad26e5c | 1031 | __be64 *startp, __be64 *endp, bool rm) |
4cce9550 GS |
1032 | { |
1033 | struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, | |
1034 | tce32_table); | |
1035 | struct pnv_phb *phb = pe->phb; | |
1036 | ||
1037 | if (phb->type == PNV_PHB_IODA1) | |
8e0a1611 | 1038 | pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); |
4cce9550 | 1039 | else |
8e0a1611 | 1040 | pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); |
4cce9550 GS |
1041 | } |
1042 | ||
cad5cef6 GKH |
1043 | static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, |
1044 | struct pnv_ioda_pe *pe, unsigned int base, | |
1045 | unsigned int segs) | |
184cd4a3 BH |
1046 | { |
1047 | ||
1048 | struct page *tce_mem = NULL; | |
1049 | const __be64 *swinvp; | |
1050 | struct iommu_table *tbl; | |
1051 | unsigned int i; | |
1052 | int64_t rc; | |
1053 | void *addr; | |
1054 | ||
1055 | /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ | |
1056 | #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) | |
1057 | ||
1058 | /* XXX FIXME: Handle 64-bit only DMA devices */ | |
1059 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
1060 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
1061 | ||
1062 | /* We shouldn't already have a 32-bit DMA associated */ | |
1063 | if (WARN_ON(pe->tce32_seg >= 0)) | |
1064 | return; | |
1065 | ||
1066 | /* Grab a 32-bit TCE table */ | |
1067 | pe->tce32_seg = base; | |
1068 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", | |
1069 | (base << 28), ((base + segs) << 28) - 1); | |
1070 | ||
1071 | /* XXX Currently, we allocate one big contiguous table for the | |
1072 | * TCEs. We only really need one chunk per 256M of TCE space | |
1073 | * (ie per segment) but that's an optimization for later, it | |
1074 | * requires some added smarts with our get/put_tce implementation | |
1075 | */ | |
1076 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
1077 | get_order(TCE32_TABLE_SIZE * segs)); | |
1078 | if (!tce_mem) { | |
1079 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
1080 | goto fail; | |
1081 | } | |
1082 | addr = page_address(tce_mem); | |
1083 | memset(addr, 0, TCE32_TABLE_SIZE * segs); | |
1084 | ||
1085 | /* Configure HW */ | |
1086 | for (i = 0; i < segs; i++) { | |
1087 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
1088 | pe->pe_number, | |
1089 | base + i, 1, | |
1090 | __pa(addr) + TCE32_TABLE_SIZE * i, | |
1091 | TCE32_TABLE_SIZE, 0x1000); | |
1092 | if (rc) { | |
1093 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
1094 | " err %ld\n", rc); | |
1095 | goto fail; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | /* Setup linux iommu table */ | |
1100 | tbl = &pe->tce32_table; | |
1101 | pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, | |
8fa5d454 | 1102 | base << 28, IOMMU_PAGE_SHIFT_4K); |
184cd4a3 BH |
1103 | |
1104 | /* OPAL variant of P7IOC SW invalidated TCEs */ | |
1105 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
1106 | if (swinvp) { | |
1107 | /* We need a couple more fields -- an address and a data | |
1108 | * to or. Since the bus is only printed out on table free | |
1109 | * errors, and on the first pass the data will be a relative | |
1110 | * bus number, print that out instead. | |
1111 | */ | |
8e0a1611 AK |
1112 | pe->tce_inval_reg_phys = be64_to_cpup(swinvp); |
1113 | tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, | |
1114 | 8); | |
65fd766b GS |
1115 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | |
1116 | TCE_PCI_SWINV_FREE | | |
1117 | TCE_PCI_SWINV_PAIR); | |
184cd4a3 BH |
1118 | } |
1119 | iommu_init_table(tbl, phb->hose->node); | |
e9bc03fe | 1120 | iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); |
184cd4a3 | 1121 | |
74251fe2 | 1122 | if (pe->pdev) |
d905c5df | 1123 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); |
74251fe2 | 1124 | else |
dff4a39e | 1125 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
74251fe2 | 1126 | |
184cd4a3 BH |
1127 | return; |
1128 | fail: | |
1129 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
1130 | if (pe->tce32_seg >= 0) | |
1131 | pe->tce32_seg = -1; | |
1132 | if (tce_mem) | |
1133 | __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); | |
1134 | } | |
1135 | ||
cd15b048 BH |
1136 | static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) |
1137 | { | |
1138 | struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, | |
1139 | tce32_table); | |
1140 | uint16_t window_id = (pe->pe_number << 1 ) + 1; | |
1141 | int64_t rc; | |
1142 | ||
1143 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); | |
1144 | if (enable) { | |
1145 | phys_addr_t top = memblock_end_of_DRAM(); | |
1146 | ||
1147 | top = roundup_pow_of_two(top); | |
1148 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
1149 | pe->pe_number, | |
1150 | window_id, | |
1151 | pe->tce_bypass_base, | |
1152 | top); | |
1153 | } else { | |
1154 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
1155 | pe->pe_number, | |
1156 | window_id, | |
1157 | pe->tce_bypass_base, | |
1158 | 0); | |
1159 | ||
1160 | /* | |
dff4a39e GS |
1161 | * EEH needs the mapping between IOMMU table and group |
1162 | * of those VFIO/KVM pass-through devices. We can postpone | |
1163 | * resetting DMA ops until the DMA mask is configured in | |
1164 | * host side. | |
cd15b048 | 1165 | */ |
dff4a39e GS |
1166 | if (pe->pdev) |
1167 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
1168 | else | |
1169 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); | |
cd15b048 BH |
1170 | } |
1171 | if (rc) | |
1172 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); | |
1173 | else | |
1174 | pe->tce_bypass_enabled = enable; | |
1175 | } | |
1176 | ||
1177 | static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb, | |
1178 | struct pnv_ioda_pe *pe) | |
1179 | { | |
1180 | /* TVE #1 is selected by PCI address bit 59 */ | |
1181 | pe->tce_bypass_base = 1ull << 59; | |
1182 | ||
1183 | /* Install set_bypass callback for VFIO */ | |
1184 | pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; | |
1185 | ||
1186 | /* Enable bypass by default */ | |
1187 | pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); | |
1188 | } | |
1189 | ||
373f5657 GS |
1190 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
1191 | struct pnv_ioda_pe *pe) | |
1192 | { | |
1193 | struct page *tce_mem = NULL; | |
1194 | void *addr; | |
1195 | const __be64 *swinvp; | |
1196 | struct iommu_table *tbl; | |
1197 | unsigned int tce_table_size, end; | |
1198 | int64_t rc; | |
1199 | ||
1200 | /* We shouldn't already have a 32-bit DMA associated */ | |
1201 | if (WARN_ON(pe->tce32_seg >= 0)) | |
1202 | return; | |
1203 | ||
1204 | /* The PE will reserve all possible 32-bits space */ | |
1205 | pe->tce32_seg = 0; | |
1206 | end = (1 << ilog2(phb->ioda.m32_pci_base)); | |
1207 | tce_table_size = (end / 0x1000) * 8; | |
1208 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", | |
1209 | end); | |
1210 | ||
1211 | /* Allocate TCE table */ | |
1212 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
1213 | get_order(tce_table_size)); | |
1214 | if (!tce_mem) { | |
1215 | pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); | |
1216 | goto fail; | |
1217 | } | |
1218 | addr = page_address(tce_mem); | |
1219 | memset(addr, 0, tce_table_size); | |
1220 | ||
1221 | /* | |
1222 | * Map TCE table through TVT. The TVE index is the PE number | |
1223 | * shifted by 1 bit for 32-bits DMA space. | |
1224 | */ | |
1225 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
1226 | pe->pe_number << 1, 1, __pa(addr), | |
1227 | tce_table_size, 0x1000); | |
1228 | if (rc) { | |
1229 | pe_err(pe, "Failed to configure 32-bit TCE table," | |
1230 | " err %ld\n", rc); | |
1231 | goto fail; | |
1232 | } | |
1233 | ||
1234 | /* Setup linux iommu table */ | |
1235 | tbl = &pe->tce32_table; | |
8fa5d454 AK |
1236 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, |
1237 | IOMMU_PAGE_SHIFT_4K); | |
373f5657 GS |
1238 | |
1239 | /* OPAL variant of PHB3 invalidated TCEs */ | |
1240 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
1241 | if (swinvp) { | |
1242 | /* We need a couple more fields -- an address and a data | |
1243 | * to or. Since the bus is only printed out on table free | |
1244 | * errors, and on the first pass the data will be a relative | |
1245 | * bus number, print that out instead. | |
1246 | */ | |
8e0a1611 AK |
1247 | pe->tce_inval_reg_phys = be64_to_cpup(swinvp); |
1248 | tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, | |
1249 | 8); | |
65fd766b | 1250 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); |
373f5657 GS |
1251 | } |
1252 | iommu_init_table(tbl, phb->hose->node); | |
e9bc03fe | 1253 | iommu_register_group(tbl, phb->hose->global_number, pe->pe_number); |
373f5657 | 1254 | |
74251fe2 | 1255 | if (pe->pdev) |
d905c5df | 1256 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); |
74251fe2 | 1257 | else |
dff4a39e | 1258 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
74251fe2 | 1259 | |
cd15b048 BH |
1260 | /* Also create a bypass window */ |
1261 | pnv_pci_ioda2_setup_bypass_pe(phb, pe); | |
373f5657 GS |
1262 | return; |
1263 | fail: | |
1264 | if (pe->tce32_seg >= 0) | |
1265 | pe->tce32_seg = -1; | |
1266 | if (tce_mem) | |
1267 | __free_pages(tce_mem, get_order(tce_table_size)); | |
1268 | } | |
1269 | ||
cad5cef6 | 1270 | static void pnv_ioda_setup_dma(struct pnv_phb *phb) |
184cd4a3 BH |
1271 | { |
1272 | struct pci_controller *hose = phb->hose; | |
1273 | unsigned int residual, remaining, segs, tw, base; | |
1274 | struct pnv_ioda_pe *pe; | |
1275 | ||
1276 | /* If we have more PE# than segments available, hand out one | |
1277 | * per PE until we run out and let the rest fail. If not, | |
1278 | * then we assign at least one segment per PE, plus more based | |
1279 | * on the amount of devices under that PE | |
1280 | */ | |
1281 | if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) | |
1282 | residual = 0; | |
1283 | else | |
1284 | residual = phb->ioda.tce32_count - | |
1285 | phb->ioda.dma_pe_count; | |
1286 | ||
1287 | pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", | |
1288 | hose->global_number, phb->ioda.tce32_count); | |
1289 | pr_info("PCI: %d PE# for a total weight of %d\n", | |
1290 | phb->ioda.dma_pe_count, phb->ioda.dma_weight); | |
1291 | ||
1292 | /* Walk our PE list and configure their DMA segments, hand them | |
1293 | * out one base segment plus any residual segments based on | |
1294 | * weight | |
1295 | */ | |
1296 | remaining = phb->ioda.tce32_count; | |
1297 | tw = phb->ioda.dma_weight; | |
1298 | base = 0; | |
7ebdf956 | 1299 | list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 BH |
1300 | if (!pe->dma_weight) |
1301 | continue; | |
1302 | if (!remaining) { | |
1303 | pe_warn(pe, "No DMA32 resources available\n"); | |
1304 | continue; | |
1305 | } | |
1306 | segs = 1; | |
1307 | if (residual) { | |
1308 | segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; | |
1309 | if (segs > remaining) | |
1310 | segs = remaining; | |
1311 | } | |
373f5657 GS |
1312 | |
1313 | /* | |
1314 | * For IODA2 compliant PHB3, we needn't care about the weight. | |
1315 | * The all available 32-bits DMA space will be assigned to | |
1316 | * the specific PE. | |
1317 | */ | |
1318 | if (phb->type == PNV_PHB_IODA1) { | |
1319 | pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", | |
1320 | pe->dma_weight, segs); | |
1321 | pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); | |
1322 | } else { | |
1323 | pe_info(pe, "Assign DMA32 space\n"); | |
1324 | segs = 0; | |
1325 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
1326 | } | |
1327 | ||
184cd4a3 BH |
1328 | remaining -= segs; |
1329 | base += segs; | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | #ifdef CONFIG_PCI_MSI | |
137436c9 GS |
1334 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
1335 | { | |
1336 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); | |
1337 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
1338 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, | |
1339 | ioda.irq_chip); | |
1340 | int64_t rc; | |
1341 | ||
1342 | rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
1343 | WARN_ON_ONCE(rc); | |
1344 | ||
1345 | icp_native_eoi(d); | |
1346 | } | |
1347 | ||
fd9a1c26 IM |
1348 | |
1349 | static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) | |
1350 | { | |
1351 | struct irq_data *idata; | |
1352 | struct irq_chip *ichip; | |
1353 | ||
1354 | if (phb->type != PNV_PHB_IODA2) | |
1355 | return; | |
1356 | ||
1357 | if (!phb->ioda.irq_chip_init) { | |
1358 | /* | |
1359 | * First time we setup an MSI IRQ, we need to setup the | |
1360 | * corresponding IRQ chip to route correctly. | |
1361 | */ | |
1362 | idata = irq_get_irq_data(virq); | |
1363 | ichip = irq_data_get_irq_chip(idata); | |
1364 | phb->ioda.irq_chip_init = 1; | |
1365 | phb->ioda.irq_chip = *ichip; | |
1366 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
1367 | } | |
1368 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
1369 | } | |
1370 | ||
80c49c7e IM |
1371 | #ifdef CONFIG_CXL_BASE |
1372 | ||
1373 | struct device_node *pnv_pci_to_phb_node(struct pci_dev *dev) | |
1374 | { | |
1375 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1376 | ||
1377 | return hose->dn; | |
1378 | } | |
1379 | EXPORT_SYMBOL(pnv_pci_to_phb_node); | |
1380 | ||
1381 | int pnv_phb_to_cxl(struct pci_dev *dev) | |
1382 | { | |
1383 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1384 | struct pnv_phb *phb = hose->private_data; | |
1385 | struct pnv_ioda_pe *pe; | |
1386 | int rc; | |
1387 | ||
1388 | pe = pnv_ioda_get_pe(dev); | |
1389 | if (!pe) | |
1390 | return -ENODEV; | |
1391 | ||
1392 | pe_info(pe, "Switching PHB to CXL\n"); | |
1393 | ||
1394 | rc = opal_pci_set_phb_cxl_mode(phb->opal_id, 1, pe->pe_number); | |
1395 | if (rc) | |
1396 | dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); | |
1397 | ||
1398 | return rc; | |
1399 | } | |
1400 | EXPORT_SYMBOL(pnv_phb_to_cxl); | |
1401 | ||
1402 | /* Find PHB for cxl dev and allocate MSI hwirqs? | |
1403 | * Returns the absolute hardware IRQ number | |
1404 | */ | |
1405 | int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) | |
1406 | { | |
1407 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1408 | struct pnv_phb *phb = hose->private_data; | |
1409 | int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); | |
1410 | ||
1411 | if (hwirq < 0) { | |
1412 | dev_warn(&dev->dev, "Failed to find a free MSI\n"); | |
1413 | return -ENOSPC; | |
1414 | } | |
1415 | ||
1416 | return phb->msi_base + hwirq; | |
1417 | } | |
1418 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); | |
1419 | ||
1420 | void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) | |
1421 | { | |
1422 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1423 | struct pnv_phb *phb = hose->private_data; | |
1424 | ||
1425 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); | |
1426 | } | |
1427 | EXPORT_SYMBOL(pnv_cxl_release_hwirqs); | |
1428 | ||
1429 | void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
1430 | struct pci_dev *dev) | |
1431 | { | |
1432 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1433 | struct pnv_phb *phb = hose->private_data; | |
1434 | int i, hwirq; | |
1435 | ||
1436 | for (i = 1; i < CXL_IRQ_RANGES; i++) { | |
1437 | if (!irqs->range[i]) | |
1438 | continue; | |
1439 | pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", | |
1440 | i, irqs->offset[i], | |
1441 | irqs->range[i]); | |
1442 | hwirq = irqs->offset[i] - phb->msi_base; | |
1443 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, | |
1444 | irqs->range[i]); | |
1445 | } | |
1446 | } | |
1447 | EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); | |
1448 | ||
1449 | int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
1450 | struct pci_dev *dev, int num) | |
1451 | { | |
1452 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1453 | struct pnv_phb *phb = hose->private_data; | |
1454 | int i, hwirq, try; | |
1455 | ||
1456 | memset(irqs, 0, sizeof(struct cxl_irq_ranges)); | |
1457 | ||
1458 | /* 0 is reserved for the multiplexed PSL DSI interrupt */ | |
1459 | for (i = 1; i < CXL_IRQ_RANGES && num; i++) { | |
1460 | try = num; | |
1461 | while (try) { | |
1462 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); | |
1463 | if (hwirq >= 0) | |
1464 | break; | |
1465 | try /= 2; | |
1466 | } | |
1467 | if (!try) | |
1468 | goto fail; | |
1469 | ||
1470 | irqs->offset[i] = phb->msi_base + hwirq; | |
1471 | irqs->range[i] = try; | |
1472 | pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", | |
1473 | i, irqs->offset[i], irqs->range[i]); | |
1474 | num -= try; | |
1475 | } | |
1476 | if (num) | |
1477 | goto fail; | |
1478 | ||
1479 | return 0; | |
1480 | fail: | |
1481 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
1482 | return -ENOSPC; | |
1483 | } | |
1484 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); | |
1485 | ||
1486 | int pnv_cxl_get_irq_count(struct pci_dev *dev) | |
1487 | { | |
1488 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1489 | struct pnv_phb *phb = hose->private_data; | |
1490 | ||
1491 | return phb->msi_bmp.irq_count; | |
1492 | } | |
1493 | EXPORT_SYMBOL(pnv_cxl_get_irq_count); | |
1494 | ||
1495 | int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, | |
1496 | unsigned int virq) | |
1497 | { | |
1498 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1499 | struct pnv_phb *phb = hose->private_data; | |
1500 | unsigned int xive_num = hwirq - phb->msi_base; | |
1501 | struct pnv_ioda_pe *pe; | |
1502 | int rc; | |
1503 | ||
1504 | if (!(pe = pnv_ioda_get_pe(dev))) | |
1505 | return -ENODEV; | |
1506 | ||
1507 | /* Assign XIVE to PE */ | |
1508 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
1509 | if (rc) { | |
1510 | pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " | |
1511 | "hwirq 0x%x XIVE 0x%x PE\n", | |
1512 | pci_name(dev), rc, phb->msi_base, hwirq, xive_num); | |
1513 | return -EIO; | |
1514 | } | |
1515 | set_msi_irq_chip(phb, virq); | |
1516 | ||
1517 | return 0; | |
1518 | } | |
1519 | EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); | |
1520 | #endif | |
1521 | ||
184cd4a3 | 1522 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
1523 | unsigned int hwirq, unsigned int virq, |
1524 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
1525 | { |
1526 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
b72c1f65 | 1527 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 | 1528 | unsigned int xive_num = hwirq - phb->msi_base; |
3a1a4661 | 1529 | __be32 data; |
184cd4a3 BH |
1530 | int rc; |
1531 | ||
1532 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
1533 | if (pe == NULL) | |
1534 | return -ENXIO; | |
1535 | ||
1536 | /* Check if we have an MVE */ | |
1537 | if (pe->mve_number < 0) | |
1538 | return -ENXIO; | |
1539 | ||
b72c1f65 BH |
1540 | /* Force 32-bit MSI on some broken devices */ |
1541 | if (pdn && pdn->force_32bit_msi) | |
1542 | is_64 = 0; | |
1543 | ||
184cd4a3 BH |
1544 | /* Assign XIVE to PE */ |
1545 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
1546 | if (rc) { | |
1547 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
1548 | pci_name(dev), rc, xive_num); | |
1549 | return -EIO; | |
1550 | } | |
1551 | ||
1552 | if (is_64) { | |
3a1a4661 BH |
1553 | __be64 addr64; |
1554 | ||
184cd4a3 BH |
1555 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
1556 | &addr64, &data); | |
1557 | if (rc) { | |
1558 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
1559 | pci_name(dev), rc); | |
1560 | return -EIO; | |
1561 | } | |
3a1a4661 BH |
1562 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
1563 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 1564 | } else { |
3a1a4661 BH |
1565 | __be32 addr32; |
1566 | ||
184cd4a3 BH |
1567 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
1568 | &addr32, &data); | |
1569 | if (rc) { | |
1570 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
1571 | pci_name(dev), rc); | |
1572 | return -EIO; | |
1573 | } | |
1574 | msg->address_hi = 0; | |
3a1a4661 | 1575 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 1576 | } |
3a1a4661 | 1577 | msg->data = be32_to_cpu(data); |
184cd4a3 | 1578 | |
fd9a1c26 | 1579 | set_msi_irq_chip(phb, virq); |
137436c9 | 1580 | |
184cd4a3 BH |
1581 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
1582 | " address=%x_%08x data=%x PE# %d\n", | |
1583 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, | |
1584 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
1589 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
1590 | { | |
fb1b55d6 | 1591 | unsigned int count; |
184cd4a3 BH |
1592 | const __be32 *prop = of_get_property(phb->hose->dn, |
1593 | "ibm,opal-msi-ranges", NULL); | |
1594 | if (!prop) { | |
1595 | /* BML Fallback */ | |
1596 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
1597 | } | |
1598 | if (!prop) | |
1599 | return; | |
1600 | ||
1601 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
1602 | count = be32_to_cpup(prop + 1); |
1603 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
1604 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
1605 | phb->hose->global_number); | |
1606 | return; | |
1607 | } | |
fb1b55d6 | 1608 | |
184cd4a3 BH |
1609 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
1610 | phb->msi32_support = 1; | |
1611 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 1612 | count, phb->msi_base); |
184cd4a3 BH |
1613 | } |
1614 | #else | |
1615 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
1616 | #endif /* CONFIG_PCI_MSI */ | |
1617 | ||
11685bec GS |
1618 | /* |
1619 | * This function is supposed to be called on basis of PE from top | |
1620 | * to bottom style. So the the I/O or MMIO segment assigned to | |
1621 | * parent PE could be overrided by its child PEs if necessary. | |
1622 | */ | |
cad5cef6 GKH |
1623 | static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, |
1624 | struct pnv_ioda_pe *pe) | |
11685bec GS |
1625 | { |
1626 | struct pnv_phb *phb = hose->private_data; | |
1627 | struct pci_bus_region region; | |
1628 | struct resource *res; | |
1629 | int i, index; | |
1630 | int rc; | |
1631 | ||
1632 | /* | |
1633 | * NOTE: We only care PCI bus based PE for now. For PCI | |
1634 | * device based PE, for example SRIOV sensitive VF should | |
1635 | * be figured out later. | |
1636 | */ | |
1637 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
1638 | ||
1639 | pci_bus_for_each_resource(pe->pbus, res, i) { | |
1640 | if (!res || !res->flags || | |
1641 | res->start > res->end) | |
1642 | continue; | |
1643 | ||
1644 | if (res->flags & IORESOURCE_IO) { | |
1645 | region.start = res->start - phb->ioda.io_pci_base; | |
1646 | region.end = res->end - phb->ioda.io_pci_base; | |
1647 | index = region.start / phb->ioda.io_segsize; | |
1648 | ||
1649 | while (index < phb->ioda.total_pe && | |
1650 | region.start <= region.end) { | |
1651 | phb->ioda.io_segmap[index] = pe->pe_number; | |
1652 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
1653 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
1654 | if (rc != OPAL_SUCCESS) { | |
1655 | pr_err("%s: OPAL error %d when mapping IO " | |
1656 | "segment #%d to PE#%d\n", | |
1657 | __func__, rc, index, pe->pe_number); | |
1658 | break; | |
1659 | } | |
1660 | ||
1661 | region.start += phb->ioda.io_segsize; | |
1662 | index++; | |
1663 | } | |
1664 | } else if (res->flags & IORESOURCE_MEM) { | |
1665 | region.start = res->start - | |
3fd47f06 | 1666 | hose->mem_offset[0] - |
11685bec GS |
1667 | phb->ioda.m32_pci_base; |
1668 | region.end = res->end - | |
3fd47f06 | 1669 | hose->mem_offset[0] - |
11685bec GS |
1670 | phb->ioda.m32_pci_base; |
1671 | index = region.start / phb->ioda.m32_segsize; | |
1672 | ||
1673 | while (index < phb->ioda.total_pe && | |
1674 | region.start <= region.end) { | |
1675 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
1676 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
1677 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
1678 | if (rc != OPAL_SUCCESS) { | |
1679 | pr_err("%s: OPAL error %d when mapping M32 " | |
1680 | "segment#%d to PE#%d", | |
1681 | __func__, rc, index, pe->pe_number); | |
1682 | break; | |
1683 | } | |
1684 | ||
1685 | region.start += phb->ioda.m32_segsize; | |
1686 | index++; | |
1687 | } | |
1688 | } | |
1689 | } | |
1690 | } | |
1691 | ||
cad5cef6 | 1692 | static void pnv_pci_ioda_setup_seg(void) |
11685bec GS |
1693 | { |
1694 | struct pci_controller *tmp, *hose; | |
1695 | struct pnv_phb *phb; | |
1696 | struct pnv_ioda_pe *pe; | |
1697 | ||
1698 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1699 | phb = hose->private_data; | |
1700 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
1701 | pnv_ioda_setup_pe_seg(hose, pe); | |
1702 | } | |
1703 | } | |
1704 | } | |
1705 | ||
cad5cef6 | 1706 | static void pnv_pci_ioda_setup_DMA(void) |
13395c48 GS |
1707 | { |
1708 | struct pci_controller *hose, *tmp; | |
db1266c8 | 1709 | struct pnv_phb *phb; |
13395c48 GS |
1710 | |
1711 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1712 | pnv_ioda_setup_dma(hose->private_data); | |
db1266c8 GS |
1713 | |
1714 | /* Mark the PHB initialization done */ | |
1715 | phb = hose->private_data; | |
1716 | phb->initialized = 1; | |
13395c48 GS |
1717 | } |
1718 | } | |
1719 | ||
37c367f2 GS |
1720 | static void pnv_pci_ioda_create_dbgfs(void) |
1721 | { | |
1722 | #ifdef CONFIG_DEBUG_FS | |
1723 | struct pci_controller *hose, *tmp; | |
1724 | struct pnv_phb *phb; | |
1725 | char name[16]; | |
1726 | ||
1727 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1728 | phb = hose->private_data; | |
1729 | ||
1730 | sprintf(name, "PCI%04x", hose->global_number); | |
1731 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
1732 | if (!phb->dbgfs) | |
1733 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", | |
1734 | __func__, hose->global_number); | |
1735 | } | |
1736 | #endif /* CONFIG_DEBUG_FS */ | |
1737 | } | |
1738 | ||
cad5cef6 | 1739 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
1740 | { |
1741 | pnv_pci_ioda_setup_PEs(); | |
11685bec | 1742 | pnv_pci_ioda_setup_seg(); |
13395c48 | 1743 | pnv_pci_ioda_setup_DMA(); |
e9cc17d4 | 1744 | |
37c367f2 GS |
1745 | pnv_pci_ioda_create_dbgfs(); |
1746 | ||
e9cc17d4 | 1747 | #ifdef CONFIG_EEH |
e9cc17d4 | 1748 | eeh_init(); |
dadcd6d6 | 1749 | eeh_addr_cache_build(); |
e9cc17d4 | 1750 | #endif |
fb446ad0 GS |
1751 | } |
1752 | ||
271fd03a GS |
1753 | /* |
1754 | * Returns the alignment for I/O or memory windows for P2P | |
1755 | * bridges. That actually depends on how PEs are segmented. | |
1756 | * For now, we return I/O or M32 segment size for PE sensitive | |
1757 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
1758 | * 1MiB for memory) will be returned. | |
1759 | * | |
1760 | * The current PCI bus might be put into one PE, which was | |
1761 | * create against the parent PCI bridge. For that case, we | |
1762 | * needn't enlarge the alignment so that we can save some | |
1763 | * resources. | |
1764 | */ | |
1765 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
1766 | unsigned long type) | |
1767 | { | |
1768 | struct pci_dev *bridge; | |
1769 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1770 | struct pnv_phb *phb = hose->private_data; | |
1771 | int num_pci_bridges = 0; | |
1772 | ||
1773 | bridge = bus->self; | |
1774 | while (bridge) { | |
1775 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
1776 | num_pci_bridges++; | |
1777 | if (num_pci_bridges >= 2) | |
1778 | return 1; | |
1779 | } | |
1780 | ||
1781 | bridge = bridge->bus->self; | |
1782 | } | |
1783 | ||
262af557 GC |
1784 | /* We fail back to M32 if M64 isn't supported */ |
1785 | if (phb->ioda.m64_segsize && | |
1786 | pnv_pci_is_mem_pref_64(type)) | |
1787 | return phb->ioda.m64_segsize; | |
271fd03a GS |
1788 | if (type & IORESOURCE_MEM) |
1789 | return phb->ioda.m32_segsize; | |
1790 | ||
1791 | return phb->ioda.io_segsize; | |
1792 | } | |
1793 | ||
184cd4a3 BH |
1794 | /* Prevent enabling devices for which we couldn't properly |
1795 | * assign a PE | |
1796 | */ | |
cad5cef6 | 1797 | static int pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 1798 | { |
db1266c8 GS |
1799 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
1800 | struct pnv_phb *phb = hose->private_data; | |
1801 | struct pci_dn *pdn; | |
184cd4a3 | 1802 | |
db1266c8 GS |
1803 | /* The function is probably called while the PEs have |
1804 | * not be created yet. For example, resource reassignment | |
1805 | * during PCI probe period. We just skip the check if | |
1806 | * PEs isn't ready. | |
1807 | */ | |
1808 | if (!phb->initialized) | |
1809 | return 0; | |
1810 | ||
b72c1f65 | 1811 | pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1812 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
1813 | return -EINVAL; | |
db1266c8 | 1814 | |
184cd4a3 BH |
1815 | return 0; |
1816 | } | |
1817 | ||
1818 | static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, | |
1819 | u32 devfn) | |
1820 | { | |
1821 | return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; | |
1822 | } | |
1823 | ||
73ed148a BH |
1824 | static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) |
1825 | { | |
d1a85eee | 1826 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
73ed148a BH |
1827 | OPAL_ASSERT_RESET); |
1828 | } | |
1829 | ||
e51df2c1 AB |
1830 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
1831 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
1832 | { |
1833 | struct pci_controller *hose; | |
184cd4a3 | 1834 | struct pnv_phb *phb; |
8184616f | 1835 | unsigned long size, m32map_off, pemap_off, iomap_off = 0; |
c681b93c | 1836 | const __be64 *prop64; |
3a1a4661 | 1837 | const __be32 *prop32; |
f1b7cc3e | 1838 | int len; |
184cd4a3 BH |
1839 | u64 phb_id; |
1840 | void *aux; | |
1841 | long rc; | |
1842 | ||
58d714ec | 1843 | pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); |
184cd4a3 BH |
1844 | |
1845 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
1846 | if (!prop64) { | |
1847 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
1848 | return; | |
1849 | } | |
1850 | phb_id = be64_to_cpup(prop64); | |
1851 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
1852 | ||
1853 | phb = alloc_bootmem(sizeof(struct pnv_phb)); | |
58d714ec GS |
1854 | if (!phb) { |
1855 | pr_err(" Out of memory !\n"); | |
1856 | return; | |
184cd4a3 | 1857 | } |
58d714ec GS |
1858 | |
1859 | /* Allocate PCI controller */ | |
1860 | memset(phb, 0, sizeof(struct pnv_phb)); | |
1861 | phb->hose = hose = pcibios_alloc_controller(np); | |
1862 | if (!phb->hose) { | |
1863 | pr_err(" Can't allocate PCI controller for %s\n", | |
184cd4a3 | 1864 | np->full_name); |
58d714ec | 1865 | free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); |
184cd4a3 BH |
1866 | return; |
1867 | } | |
1868 | ||
1869 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
1870 | prop32 = of_get_property(np, "bus-range", &len); |
1871 | if (prop32 && len == 8) { | |
3a1a4661 BH |
1872 | hose->first_busno = be32_to_cpu(prop32[0]); |
1873 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e GS |
1874 | } else { |
1875 | pr_warn(" Broken <bus-range> on %s\n", np->full_name); | |
1876 | hose->first_busno = 0; | |
1877 | hose->last_busno = 0xff; | |
1878 | } | |
184cd4a3 | 1879 | hose->private_data = phb; |
e9cc17d4 | 1880 | phb->hub_id = hub_id; |
184cd4a3 | 1881 | phb->opal_id = phb_id; |
aa0c033f | 1882 | phb->type = ioda_type; |
184cd4a3 | 1883 | |
cee72d5b BH |
1884 | /* Detect specific models for error handling */ |
1885 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
1886 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 1887 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 1888 | phb->model = PNV_PHB_MODEL_PHB3; |
cee72d5b BH |
1889 | else |
1890 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
1891 | ||
aa0c033f | 1892 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 1893 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 1894 | |
aa0c033f | 1895 | /* Get registers */ |
184cd4a3 BH |
1896 | phb->regs = of_iomap(np, 0); |
1897 | if (phb->regs == NULL) | |
1898 | pr_err(" Failed to map registers !\n"); | |
1899 | ||
184cd4a3 | 1900 | /* Initialize more IODA stuff */ |
36954dc7 | 1901 | phb->ioda.total_pe = 1; |
aa0c033f | 1902 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 1903 | if (prop32) |
3a1a4661 | 1904 | phb->ioda.total_pe = be32_to_cpup(prop32); |
36954dc7 GS |
1905 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
1906 | if (prop32) | |
1907 | phb->ioda.reserved_pe = be32_to_cpup(prop32); | |
262af557 GC |
1908 | |
1909 | /* Parse 64-bit MMIO range */ | |
1910 | pnv_ioda_parse_m64_window(phb); | |
1911 | ||
184cd4a3 | 1912 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 1913 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
1914 | phb->ioda.m32_size += 0x10000; |
1915 | ||
1916 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; | |
3fd47f06 | 1917 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 BH |
1918 | phb->ioda.io_size = hose->pci_io_size; |
1919 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; | |
1920 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ | |
1921 | ||
c35d2a8c | 1922 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
184cd4a3 BH |
1923 | size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); |
1924 | m32map_off = size; | |
e47747f4 | 1925 | size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
1926 | if (phb->type == PNV_PHB_IODA1) { |
1927 | iomap_off = size; | |
1928 | size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); | |
1929 | } | |
184cd4a3 BH |
1930 | pemap_off = size; |
1931 | size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); | |
1932 | aux = alloc_bootmem(size); | |
1933 | memset(aux, 0, size); | |
1934 | phb->ioda.pe_alloc = aux; | |
1935 | phb->ioda.m32_segmap = aux + m32map_off; | |
c35d2a8c GS |
1936 | if (phb->type == PNV_PHB_IODA1) |
1937 | phb->ioda.io_segmap = aux + iomap_off; | |
184cd4a3 | 1938 | phb->ioda.pe_array = aux + pemap_off; |
36954dc7 | 1939 | set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); |
184cd4a3 | 1940 | |
7ebdf956 | 1941 | INIT_LIST_HEAD(&phb->ioda.pe_dma_list); |
184cd4a3 BH |
1942 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
1943 | ||
1944 | /* Calculate how many 32-bit TCE segments we have */ | |
1945 | phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; | |
1946 | ||
aa0c033f | 1947 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
1948 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
1949 | window_type, | |
1950 | window_num, | |
1951 | starting_real_address, | |
1952 | starting_pci_address, | |
1953 | segment_size); | |
1954 | #endif | |
1955 | ||
262af557 GC |
1956 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
1957 | phb->ioda.total_pe, phb->ioda.reserved_pe, | |
1958 | phb->ioda.m32_size, phb->ioda.m32_segsize); | |
1959 | if (phb->ioda.m64_size) | |
1960 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", | |
1961 | phb->ioda.m64_size, phb->ioda.m64_segsize); | |
1962 | if (phb->ioda.io_size) | |
1963 | pr_info(" IO: 0x%x [segment=0x%x]\n", | |
1964 | phb->ioda.io_size, phb->ioda.io_segsize); | |
1965 | ||
184cd4a3 | 1966 | |
184cd4a3 | 1967 | phb->hose->ops = &pnv_pci_ops; |
49dec922 GS |
1968 | phb->get_pe_state = pnv_ioda_get_pe_state; |
1969 | phb->freeze_pe = pnv_ioda_freeze_pe; | |
1970 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | |
e9cc17d4 GS |
1971 | #ifdef CONFIG_EEH |
1972 | phb->eeh_ops = &ioda_eeh_ops; | |
1973 | #endif | |
184cd4a3 BH |
1974 | |
1975 | /* Setup RID -> PE mapping function */ | |
1976 | phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; | |
1977 | ||
1978 | /* Setup TCEs */ | |
1979 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
cd15b048 | 1980 | phb->dma_set_mask = pnv_pci_ioda_dma_set_mask; |
fe7e85c6 | 1981 | phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask; |
184cd4a3 | 1982 | |
73ed148a BH |
1983 | /* Setup shutdown function for kexec */ |
1984 | phb->shutdown = pnv_pci_ioda_shutdown; | |
1985 | ||
184cd4a3 BH |
1986 | /* Setup MSI support */ |
1987 | pnv_pci_init_ioda_msis(phb); | |
1988 | ||
c40a4210 GS |
1989 | /* |
1990 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
1991 | * to let the PCI core do resource assignment. It's supposed | |
1992 | * that the PCI core will do correct I/O and MMIO alignment | |
1993 | * for the P2P bridge bars so that each PCI bus (excluding | |
1994 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 1995 | */ |
fb446ad0 | 1996 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
184cd4a3 | 1997 | ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; |
271fd03a | 1998 | ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; |
d92a208d | 1999 | ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; |
c40a4210 | 2000 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
2001 | |
2002 | /* Reset IODA tables to a clean state */ | |
d1a85eee | 2003 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
184cd4a3 | 2004 | if (rc) |
f11fe552 | 2005 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
361f2a2a GS |
2006 | |
2007 | /* If we're running in kdump kerenl, the previous kerenl never | |
2008 | * shutdown PCI devices correctly. We already got IODA table | |
2009 | * cleaned out. So we have to issue PHB reset to stop all PCI | |
2010 | * transactions from previous kerenl. | |
2011 | */ | |
2012 | if (is_kdump_kernel()) { | |
2013 | pr_info(" Issue PHB reset ...\n"); | |
2014 | ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); | |
2015 | ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET); | |
2016 | } | |
262af557 | 2017 | |
9e9e8935 GS |
2018 | /* Remove M64 resource if we can't configure it successfully */ |
2019 | if (!phb->init_m64 || phb->init_m64(phb)) | |
262af557 | 2020 | hose->mem_resources[1].flags = 0; |
aa0c033f GS |
2021 | } |
2022 | ||
67975005 | 2023 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 2024 | { |
e9cc17d4 | 2025 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
2026 | } |
2027 | ||
2028 | void __init pnv_pci_init_ioda_hub(struct device_node *np) | |
2029 | { | |
2030 | struct device_node *phbn; | |
c681b93c | 2031 | const __be64 *prop64; |
184cd4a3 BH |
2032 | u64 hub_id; |
2033 | ||
2034 | pr_info("Probing IODA IO-Hub %s\n", np->full_name); | |
2035 | ||
2036 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
2037 | if (!prop64) { | |
2038 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
2039 | return; | |
2040 | } | |
2041 | hub_id = be64_to_cpup(prop64); | |
2042 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
2043 | ||
2044 | /* Count child PHBs */ | |
2045 | for_each_child_of_node(np, phbn) { | |
2046 | /* Look for IODA1 PHBs */ | |
2047 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 2048 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
2049 | } |
2050 | } |