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[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / powernv / pci-ioda.c
CommitLineData
184cd4a3
BH		 1/*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
cee72d5b 12#undef DEBUG
184cd4a3
BH		 13
14#include <linux/kernel.h>
15#include <linux/pci.h>
361f2a2a 16#include <linux/crash_dump.h>
37c367f2 17#include <linux/debugfs.h>
184cd4a3
BH		 18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/msi.h>
cd15b048 25#include <linux/memblock.h>
ac9a5889 26#include <linux/iommu.h>
e57080f1 27#include <linux/rculist.h>
4793d65d 28#include <linux/sizes.h>
184cd4a3
BH		 29
30#include <asm/sections.h>
31#include <asm/io.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/machdep.h>
fb1b55d6 35#include <asm/msi_bitmap.h>
184cd4a3
BH		 36#include <asm/ppc-pci.h>
37#include <asm/opal.h>
38#include <asm/iommu.h>
39#include <asm/tce.h>
137436c9 40#include <asm/xics.h>
37c367f2 41#include <asm/debug.h>
262af557 42#include <asm/firmware.h>
80c49c7e 43#include <asm/pnv-pci.h>
aca6913f 44#include <asm/mmzone.h>
80c49c7e 45
ec249dd8 46#include <misc/cxl-base.h>
184cd4a3
BH		 47
48#include "powernv.h"
49#include "pci.h"
50
781a868f
WY		 51/* 256M DMA window, 4K TCE pages, 8 bytes TCE */
52#define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
53
bbb845c4
AK		 54#define POWERNV_IOMMU_DEFAULT_LEVELS 1
55#define POWERNV_IOMMU_MAX_LEVELS 5
56
aca6913f
AK		 57static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
58
6d31c2fa
JP		 59static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
60 const char *fmt, ...)
61{
62 struct va_format vaf;
63 va_list args;
64 char pfix[32];
65
66 va_start(args, fmt);
67
68 vaf.fmt = fmt;
69 vaf.va = &args;
70
781a868f 71 if (pe->flags & PNV_IODA_PE_DEV)
6d31c2fa 72 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
781a868f 73 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
6d31c2fa
JP		 74 sprintf(pfix, "%04x:%02x ",
75 pci_domain_nr(pe->pbus), pe->pbus->number);
781a868f
WY		 76#ifdef CONFIG_PCI_IOV
77 else if (pe->flags & PNV_IODA_PE_VF)
78 sprintf(pfix, "%04x:%02x:%2x.%d",
79 pci_domain_nr(pe->parent_dev->bus),
80 (pe->rid & 0xff00) >> 8,
81 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
82#endif /* CONFIG_PCI_IOV*/
6d31c2fa
JP		 83
84 printk("%spci %s: [PE# %.3d] %pV",
85 level, pfix, pe->pe_number, &vaf);
86
87 va_end(args);
88}
184cd4a3 89
6d31c2fa
JP		 90#define pe_err(pe, fmt, ...) \
91 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
92#define pe_warn(pe, fmt, ...) \
93 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
94#define pe_info(pe, fmt, ...) \
95 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
184cd4a3 96
4e287840
TLSC		 97static bool pnv_iommu_bypass_disabled __read_mostly;
98
99static int __init iommu_setup(char *str)
100{
101 if (!str)
102 return -EINVAL;
103
104 while (*str) {
105 if (!strncmp(str, "nobypass", 8)) {
106 pnv_iommu_bypass_disabled = true;
107 pr_info("PowerNV: IOMMU bypass window disabled.\n");
108 break;
109 }
110 str += strcspn(str, ",");
111 if (*str == ',')
112 str++;
113 }
114
115 return 0;
116}
117early_param("iommu", iommu_setup);
118
8e0a1611
AK		 119/*
120 * stdcix is only supposed to be used in hypervisor real mode as per
121 * the architecture spec
122 */
123static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
124{
125 __asm__ __volatile__("stdcix %0,0,%1"
126 : : "r" (val), "r" (paddr) : "memory");
127}
128
262af557
GC		 129static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
130{
131 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
132 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
133}
134
4b82ab18
GS		 135static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
136{
137 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
138 pr_warn("%s: Invalid PE %d on PHB#%x\n",
139 __func__, pe_no, phb->hose->global_number);
140 return;
141 }
142
e9dc4d7f
GS		 143 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
144 pr_debug("%s: PE %d was reserved on PHB#%x\n",
145 __func__, pe_no, phb->hose->global_number);
4b82ab18
GS		 146
147 phb->ioda.pe_array[pe_no].phb = phb;
148 phb->ioda.pe_array[pe_no].pe_number = pe_no;
149}
150
cad5cef6 151static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
184cd4a3
BH		 152{
153 unsigned long pe;
154
155 do {
156 pe = find_next_zero_bit(phb->ioda.pe_alloc,
157 phb->ioda.total_pe, 0);
158 if (pe >= phb->ioda.total_pe)
159 return IODA_INVALID_PE;
160 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
161
4cce9550 162 phb->ioda.pe_array[pe].phb = phb;
184cd4a3
BH		 163 phb->ioda.pe_array[pe].pe_number = pe;
164 return pe;
165}
166
cad5cef6 167static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
184cd4a3
BH		 168{
169 WARN_ON(phb->ioda.pe_array[pe].pdev);
170
171 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
172 clear_bit(pe, phb->ioda.pe_alloc);
173}
174
262af557
GC		 175/* The default M64 BAR is shared by all PEs */
176static int pnv_ioda2_init_m64(struct pnv_phb *phb)
177{
178 const char *desc;
179 struct resource *r;
180 s64 rc;
181
182 /* Configure the default M64 BAR */
183 rc = opal_pci_set_phb_mem_window(phb->opal_id,
184 OPAL_M64_WINDOW_TYPE,
185 phb->ioda.m64_bar_idx,
186 phb->ioda.m64_base,
187 0, /* unused */
188 phb->ioda.m64_size);
189 if (rc != OPAL_SUCCESS) {
190 desc = "configuring";
191 goto fail;
192 }
193
194 /* Enable the default M64 BAR */
195 rc = opal_pci_phb_mmio_enable(phb->opal_id,
196 OPAL_M64_WINDOW_TYPE,
197 phb->ioda.m64_bar_idx,
198 OPAL_ENABLE_M64_SPLIT);
199 if (rc != OPAL_SUCCESS) {
200 desc = "enabling";
201 goto fail;
202 }
203
204 /* Mark the M64 BAR assigned */
205 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
206
207 /*
208 * Strip off the segment used by the reserved PE, which is
209 * expected to be 0 or last one of PE capabicity.
210 */
211 r = &phb->hose->mem_resources[1];
212 if (phb->ioda.reserved_pe == 0)
213 r->start += phb->ioda.m64_segsize;
214 else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
215 r->end -= phb->ioda.m64_segsize;
216 else
217 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
218 phb->ioda.reserved_pe);
219
220 return 0;
221
222fail:
223 pr_warn(" Failure %lld %s M64 BAR#%d\n",
224 rc, desc, phb->ioda.m64_bar_idx);
225 opal_pci_phb_mmio_enable(phb->opal_id,
226 OPAL_M64_WINDOW_TYPE,
227 phb->ioda.m64_bar_idx,
228 OPAL_DISABLE_M64);
229 return -EIO;
230}
231
96a2f92b
GS		 232static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
233 unsigned long *pe_bitmap)
262af557 234{
96a2f92b
GS		 235 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
236 struct pnv_phb *phb = hose->private_data;
262af557 237 struct resource *r;
96a2f92b
GS		 238 resource_size_t base, sgsz, start, end;
239 int segno, i;
240
241 base = phb->ioda.m64_base;
242 sgsz = phb->ioda.m64_segsize;
243 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
244 r = &pdev->resource[i];
245 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
246 continue;
262af557 247
96a2f92b
GS		 248 start = _ALIGN_DOWN(r->start - base, sgsz);
249 end = _ALIGN_UP(r->end - base, sgsz);
250 for (segno = start / sgsz; segno < end / sgsz; segno++) {
251 if (pe_bitmap)
252 set_bit(segno, pe_bitmap);
253 else
254 pnv_ioda_reserve_pe(phb, segno);
262af557
GC		 255 }
256 }
257}
258
96a2f92b
GS		 259static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
260 unsigned long *pe_bitmap,
261 bool all)
262{
263 struct pci_dev *pdev;
264
265 list_for_each_entry(pdev, &bus->devices, bus_list) {
266 pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
267
268 if (all && pdev->subordinate)
269 pnv_ioda2_reserve_m64_pe(pdev->subordinate,
270 pe_bitmap, all);
271 }
272}
273
26ba248d 274static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
262af557 275{
26ba248d
GS		 276 struct pci_controller *hose = pci_bus_to_host(bus);
277 struct pnv_phb *phb = hose->private_data;
262af557
GC		 278 struct pnv_ioda_pe *master_pe, *pe;
279 unsigned long size, *pe_alloc;
26ba248d 280 int i;
262af557
GC		 281
282 /* Root bus shouldn't use M64 */
283 if (pci_is_root_bus(bus))
284 return IODA_INVALID_PE;
285
262af557
GC		 286 /* Allocate bitmap */
287 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
288 pe_alloc = kzalloc(size, GFP_KERNEL);
289 if (!pe_alloc) {
290 pr_warn("%s: Out of memory !\n",
291 __func__);
292 return IODA_INVALID_PE;
293 }
294
26ba248d
GS		 295 /* Figure out reserved PE numbers by the PE */
296 pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
262af557
GC		 297
298 /*
299 * the current bus might not own M64 window and that's all
300 * contributed by its child buses. For the case, we needn't
301 * pick M64 dependent PE#.
302 */
303 if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
304 kfree(pe_alloc);
305 return IODA_INVALID_PE;
306 }
307
308 /*
309 * Figure out the master PE and put all slave PEs to master
310 * PE's list to form compound PE.
311 */
262af557
GC		 312 master_pe = NULL;
313 i = -1;
314 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
315 phb->ioda.total_pe) {
316 pe = &phb->ioda.pe_array[i];
262af557
GC		 317
318 if (!master_pe) {
319 pe->flags |= PNV_IODA_PE_MASTER;
320 INIT_LIST_HEAD(&pe->slaves);
321 master_pe = pe;
322 } else {
323 pe->flags |= PNV_IODA_PE_SLAVE;
324 pe->master = master_pe;
325 list_add_tail(&pe->list, &master_pe->slaves);
326 }
327 }
328
329 kfree(pe_alloc);
330 return master_pe->pe_number;
331}
332
333static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
334{
335 struct pci_controller *hose = phb->hose;
336 struct device_node *dn = hose->dn;
337 struct resource *res;
338 const u32 *r;
339 u64 pci_addr;
340
1665c4a8
GS		 341 /* FIXME: Support M64 for P7IOC */
342 if (phb->type != PNV_PHB_IODA2) {
343 pr_info(" Not support M64 window\n");
344 return;
345 }
346
262af557
GC		 347 if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
348 pr_info(" Firmware too old to support M64 window\n");
349 return;
350 }
351
352 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
353 if (!r) {
354 pr_info(" No <ibm,opal-m64-window> on %s\n",
355 dn->full_name);
356 return;
357 }
358
262af557
GC		 359 res = &hose->mem_resources[1];
360 res->start = of_translate_address(dn, r + 2);
361 res->end = res->start + of_read_number(r + 4, 2) - 1;
362 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
363 pci_addr = of_read_number(r, 2);
364 hose->mem_offset[1] = res->start - pci_addr;
365
366 phb->ioda.m64_size = resource_size(res);
367 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
368 phb->ioda.m64_base = pci_addr;
369
e9863e68
WY		 370 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
371 res->start, res->end, pci_addr);
372
262af557
GC		 373 /* Use last M64 BAR to cover M64 window */
374 phb->ioda.m64_bar_idx = 15;
375 phb->init_m64 = pnv_ioda2_init_m64;
5ef73567 376 phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
262af557
GC		 377 phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
378}
379
49dec922
GS		 380static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
381{
382 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
383 struct pnv_ioda_pe *slave;
384 s64 rc;
385
386 /* Fetch master PE */
387 if (pe->flags & PNV_IODA_PE_SLAVE) {
388 pe = pe->master;
ec8e4e9d
GS		 389 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
390 return;
391
49dec922
GS		 392 pe_no = pe->pe_number;
393 }
394
395 /* Freeze master PE */
396 rc = opal_pci_eeh_freeze_set(phb->opal_id,
397 pe_no,
398 OPAL_EEH_ACTION_SET_FREEZE_ALL);
399 if (rc != OPAL_SUCCESS) {
400 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
401 __func__, rc, phb->hose->global_number, pe_no);
402 return;
403 }
404
405 /* Freeze slave PEs */
406 if (!(pe->flags & PNV_IODA_PE_MASTER))
407 return;
408
409 list_for_each_entry(slave, &pe->slaves, list) {
410 rc = opal_pci_eeh_freeze_set(phb->opal_id,
411 slave->pe_number,
412 OPAL_EEH_ACTION_SET_FREEZE_ALL);
413 if (rc != OPAL_SUCCESS)
414 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
415 __func__, rc, phb->hose->global_number,
416 slave->pe_number);
417 }
418}
419
e51df2c1 420static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
49dec922
GS		 421{
422 struct pnv_ioda_pe *pe, *slave;
423 s64 rc;
424
425 /* Find master PE */
426 pe = &phb->ioda.pe_array[pe_no];
427 if (pe->flags & PNV_IODA_PE_SLAVE) {
428 pe = pe->master;
429 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
430 pe_no = pe->pe_number;
431 }
432
433 /* Clear frozen state for master PE */
434 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
435 if (rc != OPAL_SUCCESS) {
436 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
437 __func__, rc, opt, phb->hose->global_number, pe_no);
438 return -EIO;
439 }
440
441 if (!(pe->flags & PNV_IODA_PE_MASTER))
442 return 0;
443
444 /* Clear frozen state for slave PEs */
445 list_for_each_entry(slave, &pe->slaves, list) {
446 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
447 slave->pe_number,
448 opt);
449 if (rc != OPAL_SUCCESS) {
450 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
451 __func__, rc, opt, phb->hose->global_number,
452 slave->pe_number);
453 return -EIO;
454 }
455 }
456
457 return 0;
458}
459
460static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
461{
462 struct pnv_ioda_pe *slave, *pe;
463 u8 fstate, state;
464 __be16 pcierr;
465 s64 rc;
466
467 /* Sanity check on PE number */
468 if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
469 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
470
471 /*
472 * Fetch the master PE and the PE instance might be
473 * not initialized yet.
474 */
475 pe = &phb->ioda.pe_array[pe_no];
476 if (pe->flags & PNV_IODA_PE_SLAVE) {
477 pe = pe->master;
478 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
479 pe_no = pe->pe_number;
480 }
481
482 /* Check the master PE */
483 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
484 &state, &pcierr, NULL);
485 if (rc != OPAL_SUCCESS) {
486 pr_warn("%s: Failure %lld getting "
487 "PHB#%x-PE#%x state\n",
488 __func__, rc,
489 phb->hose->global_number, pe_no);
490 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
491 }
492
493 /* Check the slave PE */
494 if (!(pe->flags & PNV_IODA_PE_MASTER))
495 return state;
496
497 list_for_each_entry(slave, &pe->slaves, list) {
498 rc = opal_pci_eeh_freeze_status(phb->opal_id,
499 slave->pe_number,
500 &fstate,
501 &pcierr,
502 NULL);
503 if (rc != OPAL_SUCCESS) {
504 pr_warn("%s: Failure %lld getting "
505 "PHB#%x-PE#%x state\n",
506 __func__, rc,
507 phb->hose->global_number, slave->pe_number);
508 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
509 }
510
511 /*
512 * Override the result based on the ascending
513 * priority.
514 */
515 if (fstate > state)
516 state = fstate;
517 }
518
519 return state;
520}
521
184cd4a3
BH		 522/* Currently those 2 are only used when MSIs are enabled, this will change
523 * but in the meantime, we need to protect them to avoid warnings
524 */
525#ifdef CONFIG_PCI_MSI
cad5cef6 526static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
184cd4a3
BH		 527{
528 struct pci_controller *hose = pci_bus_to_host(dev->bus);
529 struct pnv_phb *phb = hose->private_data;
b72c1f65 530 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 531
532 if (!pdn)
533 return NULL;
534 if (pdn->pe_number == IODA_INVALID_PE)
535 return NULL;
536 return &phb->ioda.pe_array[pdn->pe_number];
537}
184cd4a3
BH		 538#endif /* CONFIG_PCI_MSI */
539
b131a842
GS		 540static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
541 struct pnv_ioda_pe *parent,
542 struct pnv_ioda_pe *child,
543 bool is_add)
544{
545 const char *desc = is_add ? "adding" : "removing";
546 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
547 OPAL_REMOVE_PE_FROM_DOMAIN;
548 struct pnv_ioda_pe *slave;
549 long rc;
550
551 /* Parent PE affects child PE */
552 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
553 child->pe_number, op);
554 if (rc != OPAL_SUCCESS) {
555 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
556 rc, desc);
557 return -ENXIO;
558 }
559
560 if (!(child->flags & PNV_IODA_PE_MASTER))
561 return 0;
562
563 /* Compound case: parent PE affects slave PEs */
564 list_for_each_entry(slave, &child->slaves, list) {
565 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
566 slave->pe_number, op);
567 if (rc != OPAL_SUCCESS) {
568 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
569 rc, desc);
570 return -ENXIO;
571 }
572 }
573
574 return 0;
575}
576
577static int pnv_ioda_set_peltv(struct pnv_phb *phb,
578 struct pnv_ioda_pe *pe,
579 bool is_add)
580{
581 struct pnv_ioda_pe *slave;
781a868f 582 struct pci_dev *pdev = NULL;
b131a842
GS		 583 int ret;
584
585 /*
586 * Clear PE frozen state. If it's master PE, we need
587 * clear slave PE frozen state as well.
588 */
589 if (is_add) {
590 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
591 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
592 if (pe->flags & PNV_IODA_PE_MASTER) {
593 list_for_each_entry(slave, &pe->slaves, list)
594 opal_pci_eeh_freeze_clear(phb->opal_id,
595 slave->pe_number,
596 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
597 }
598 }
599
600 /*
601 * Associate PE in PELT. We need add the PE into the
602 * corresponding PELT-V as well. Otherwise, the error
603 * originated from the PE might contribute to other
604 * PEs.
605 */
606 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
607 if (ret)
608 return ret;
609
610 /* For compound PEs, any one affects all of them */
611 if (pe->flags & PNV_IODA_PE_MASTER) {
612 list_for_each_entry(slave, &pe->slaves, list) {
613 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
614 if (ret)
615 return ret;
616 }
617 }
618
619 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
620 pdev = pe->pbus->self;
781a868f 621 else if (pe->flags & PNV_IODA_PE_DEV)
b131a842 622 pdev = pe->pdev->bus->self;
781a868f
WY		 623#ifdef CONFIG_PCI_IOV
624 else if (pe->flags & PNV_IODA_PE_VF)
283e2d8a 625 pdev = pe->parent_dev;
781a868f 626#endif /* CONFIG_PCI_IOV */
b131a842
GS		 627 while (pdev) {
628 struct pci_dn *pdn = pci_get_pdn(pdev);
629 struct pnv_ioda_pe *parent;
630
631 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
632 parent = &phb->ioda.pe_array[pdn->pe_number];
633 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
634 if (ret)
635 return ret;
636 }
637
638 pdev = pdev->bus->self;
639 }
640
641 return 0;
642}
643
781a868f
WY		 644#ifdef CONFIG_PCI_IOV
645static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
646{
647 struct pci_dev *parent;
648 uint8_t bcomp, dcomp, fcomp;
649 int64_t rc;
650 long rid_end, rid;
651
652 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
653 if (pe->pbus) {
654 int count;
655
656 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
657 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
658 parent = pe->pbus->self;
659 if (pe->flags & PNV_IODA_PE_BUS_ALL)
660 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
661 else
662 count = 1;
663
664 switch(count) {
665 case 1: bcomp = OpalPciBusAll; break;
666 case 2: bcomp = OpalPciBus7Bits; break;
667 case 4: bcomp = OpalPciBus6Bits; break;
668 case 8: bcomp = OpalPciBus5Bits; break;
669 case 16: bcomp = OpalPciBus4Bits; break;
670 case 32: bcomp = OpalPciBus3Bits; break;
671 default:
672 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
673 count);
674 /* Do an exact match only */
675 bcomp = OpalPciBusAll;
676 }
677 rid_end = pe->rid + (count << 8);
678 } else {
679 if (pe->flags & PNV_IODA_PE_VF)
680 parent = pe->parent_dev;
681 else
682 parent = pe->pdev->bus->self;
683 bcomp = OpalPciBusAll;
684 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
685 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
686 rid_end = pe->rid + 1;
687 }
688
689 /* Clear the reverse map */
690 for (rid = pe->rid; rid < rid_end; rid++)
691 phb->ioda.pe_rmap[rid] = 0;
692
693 /* Release from all parents PELT-V */
694 while (parent) {
695 struct pci_dn *pdn = pci_get_pdn(parent);
696 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
697 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
698 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
699 /* XXX What to do in case of error ? */
700 }
701 parent = parent->bus->self;
702 }
703
f951e510 704 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
781a868f
WY		 705 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
706
707 /* Disassociate PE in PELT */
708 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
709 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
710 if (rc)
711 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
712 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
713 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
714 if (rc)
715 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
716
717 pe->pbus = NULL;
718 pe->pdev = NULL;
719 pe->parent_dev = NULL;
720
721 return 0;
722}
723#endif /* CONFIG_PCI_IOV */
724
cad5cef6 725static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
184cd4a3
BH		 726{
727 struct pci_dev *parent;
728 uint8_t bcomp, dcomp, fcomp;
729 long rc, rid_end, rid;
730
731 /* Bus validation ? */
732 if (pe->pbus) {
733 int count;
734
735 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
736 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
737 parent = pe->pbus->self;
fb446ad0
GS		 738 if (pe->flags & PNV_IODA_PE_BUS_ALL)
739 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
740 else
741 count = 1;
742
184cd4a3
BH		 743 switch(count) {
744 case 1: bcomp = OpalPciBusAll; break;
745 case 2: bcomp = OpalPciBus7Bits; break;
746 case 4: bcomp = OpalPciBus6Bits; break;
747 case 8: bcomp = OpalPciBus5Bits; break;
748 case 16: bcomp = OpalPciBus4Bits; break;
749 case 32: bcomp = OpalPciBus3Bits; break;
750 default:
781a868f
WY		 751 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
752 count);
184cd4a3
BH		 753 /* Do an exact match only */
754 bcomp = OpalPciBusAll;
755 }
756 rid_end = pe->rid + (count << 8);
757 } else {
781a868f
WY		 758#ifdef CONFIG_PCI_IOV
759 if (pe->flags & PNV_IODA_PE_VF)
760 parent = pe->parent_dev;
761 else
762#endif /* CONFIG_PCI_IOV */
763 parent = pe->pdev->bus->self;
184cd4a3
BH		 764 bcomp = OpalPciBusAll;
765 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
766 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
767 rid_end = pe->rid + 1;
768 }
769
631ad691
GS		 770 /*
771 * Associate PE in PELT. We need add the PE into the
772 * corresponding PELT-V as well. Otherwise, the error
773 * originated from the PE might contribute to other
774 * PEs.
775 */
184cd4a3
BH		 776 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
777 bcomp, dcomp, fcomp, OPAL_MAP_PE);
778 if (rc) {
779 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
780 return -ENXIO;
781 }
631ad691 782
b131a842
GS		 783 /* Configure PELTV */
784 pnv_ioda_set_peltv(phb, pe, true);
184cd4a3 785
184cd4a3
BH		 786 /* Setup reverse map */
787 for (rid = pe->rid; rid < rid_end; rid++)
788 phb->ioda.pe_rmap[rid] = pe->pe_number;
789
790 /* Setup one MVTs on IODA1 */
4773f76b
GS		 791 if (phb->type != PNV_PHB_IODA1) {
792 pe->mve_number = 0;
793 goto out;
794 }
795
796 pe->mve_number = pe->pe_number;
797 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
798 if (rc != OPAL_SUCCESS) {
799 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
800 rc, pe->mve_number);
801 pe->mve_number = -1;
802 } else {
803 rc = opal_pci_set_mve_enable(phb->opal_id,
804 pe->mve_number, OPAL_ENABLE_MVE);
184cd4a3 805 if (rc) {
4773f76b 806 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
184cd4a3
BH		 807 rc, pe->mve_number);
808 pe->mve_number = -1;
184cd4a3 809 }
4773f76b 810 }
184cd4a3 811
4773f76b 812out:
184cd4a3
BH		 813 return 0;
814}
815
cad5cef6
GKH		 816static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
817 struct pnv_ioda_pe *pe)
184cd4a3
BH		 818{
819 struct pnv_ioda_pe *lpe;
820
7ebdf956 821 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
184cd4a3 822 if (lpe->dma_weight < pe->dma_weight) {
7ebdf956 823 list_add_tail(&pe->dma_link, &lpe->dma_link);
184cd4a3
BH		 824 return;
825 }
826 }
7ebdf956 827 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
184cd4a3
BH		 828}
829
830static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
831{
832 /* This is quite simplistic. The "base" weight of a device
833 * is 10. 0 means no DMA is to be accounted for it.
834 */
835
836 /* If it's a bridge, no DMA */
837 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
838 return 0;
839
840 /* Reduce the weight of slow USB controllers */
841 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
842 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
843 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
844 return 3;
845
846 /* Increase the weight of RAID (includes Obsidian) */
847 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
848 return 15;
849
850 /* Default */
851 return 10;
852}
853
781a868f
WY		 854#ifdef CONFIG_PCI_IOV
855static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
856{
857 struct pci_dn *pdn = pci_get_pdn(dev);
858 int i;
859 struct resource *res, res2;
860 resource_size_t size;
861 u16 num_vfs;
862
863 if (!dev->is_physfn)
864 return -EINVAL;
865
866 /*
867 * "offset" is in VFs. The M64 windows are sized so that when they
868 * are segmented, each segment is the same size as the IOV BAR.
869 * Each segment is in a separate PE, and the high order bits of the
870 * address are the PE number. Therefore, each VF's BAR is in a
871 * separate PE, and changing the IOV BAR start address changes the
872 * range of PEs the VFs are in.
873 */
874 num_vfs = pdn->num_vfs;
875 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
876 res = &dev->resource[i + PCI_IOV_RESOURCES];
877 if (!res->flags || !res->parent)
878 continue;
879
880 if (!pnv_pci_is_mem_pref_64(res->flags))
881 continue;
882
883 /*
884 * The actual IOV BAR range is determined by the start address
885 * and the actual size for num_vfs VFs BAR. This check is to
886 * make sure that after shifting, the range will not overlap
887 * with another device.
888 */
889 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
890 res2.flags = res->flags;
891 res2.start = res->start + (size * offset);
892 res2.end = res2.start + (size * num_vfs) - 1;
893
894 if (res2.end > res->end) {
895 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
896 i, &res2, res, num_vfs, offset);
897 return -EBUSY;
898 }
899 }
900
901 /*
902 * After doing so, there would be a "hole" in the /proc/iomem when
903 * offset is a positive value. It looks like the device return some
904 * mmio back to the system, which actually no one could use it.
905 */
906 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
907 res = &dev->resource[i + PCI_IOV_RESOURCES];
908 if (!res->flags || !res->parent)
909 continue;
910
911 if (!pnv_pci_is_mem_pref_64(res->flags))
912 continue;
913
914 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
915 res2 = *res;
916 res->start += size * offset;
917
918 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
919 i, &res2, res, num_vfs, offset);
920 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
921 }
922 return 0;
923}
924#endif /* CONFIG_PCI_IOV */
925
fb446ad0 926#if 0
cad5cef6 927static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
184cd4a3
BH		 928{
929 struct pci_controller *hose = pci_bus_to_host(dev->bus);
930 struct pnv_phb *phb = hose->private_data;
b72c1f65 931 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 932 struct pnv_ioda_pe *pe;
933 int pe_num;
934
935 if (!pdn) {
936 pr_err("%s: Device tree node not associated properly\n",
937 pci_name(dev));
938 return NULL;
939 }
940 if (pdn->pe_number != IODA_INVALID_PE)
941 return NULL;
942
943 /* PE#0 has been pre-set */
944 if (dev->bus->number == 0)
945 pe_num = 0;
946 else
947 pe_num = pnv_ioda_alloc_pe(phb);
948 if (pe_num == IODA_INVALID_PE) {
949 pr_warning("%s: Not enough PE# available, disabling device\n",
950 pci_name(dev));
951 return NULL;
952 }
953
954 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
955 * pointer in the PE data structure, both should be destroyed at the
956 * same time. However, this needs to be looked at more closely again
957 * once we actually start removing things (Hotplug, SR-IOV, ...)
958 *
959 * At some point we want to remove the PDN completely anyways
960 */
961 pe = &phb->ioda.pe_array[pe_num];
962 pci_dev_get(dev);
963 pdn->pcidev = dev;
964 pdn->pe_number = pe_num;
965 pe->pdev = dev;
966 pe->pbus = NULL;
967 pe->tce32_seg = -1;
968 pe->mve_number = -1;
969 pe->rid = dev->bus->number << 8 | pdn->devfn;
970
971 pe_info(pe, "Associated device to PE\n");
972
973 if (pnv_ioda_configure_pe(phb, pe)) {
974 /* XXX What do we do here ? */
975 if (pe_num)
976 pnv_ioda_free_pe(phb, pe_num);
977 pdn->pe_number = IODA_INVALID_PE;
978 pe->pdev = NULL;
979 pci_dev_put(dev);
980 return NULL;
981 }
982
983 /* Assign a DMA weight to the device */
984 pe->dma_weight = pnv_ioda_dma_weight(dev);
985 if (pe->dma_weight != 0) {
986 phb->ioda.dma_weight += pe->dma_weight;
987 phb->ioda.dma_pe_count++;
988 }
989
990 /* Link the PE */
991 pnv_ioda_link_pe_by_weight(phb, pe);
992
993 return pe;
994}
fb446ad0 995#endif /* Useful for SRIOV case */
184cd4a3
BH		 996
997static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
998{
999 struct pci_dev *dev;
1000
1001 list_for_each_entry(dev, &bus->devices, bus_list) {
b72c1f65 1002 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 1003
1004 if (pdn == NULL) {
1005 pr_warn("%s: No device node associated with device !\n",
1006 pci_name(dev));
1007 continue;
1008 }
184cd4a3
BH		 1009 pdn->pe_number = pe->pe_number;
1010 pe->dma_weight += pnv_ioda_dma_weight(dev);
fb446ad0 1011 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
184cd4a3
BH		 1012 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1013 }
1014}
1015
fb446ad0
GS		 1016/*
1017 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1018 * single PCI bus. Another one that contains the primary PCI bus and its
1019 * subordinate PCI devices and buses. The second type of PE is normally
1020 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1021 */
d1203852 1022static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
184cd4a3 1023{
fb446ad0 1024 struct pci_controller *hose = pci_bus_to_host(bus);
184cd4a3 1025 struct pnv_phb *phb = hose->private_data;
184cd4a3 1026 struct pnv_ioda_pe *pe;
262af557
GC		 1027 int pe_num = IODA_INVALID_PE;
1028
1029 /* Check if PE is determined by M64 */
1030 if (phb->pick_m64_pe)
26ba248d 1031 pe_num = phb->pick_m64_pe(bus, all);
262af557
GC		 1032
1033 /* The PE number isn't pinned by M64 */
1034 if (pe_num == IODA_INVALID_PE)
1035 pe_num = pnv_ioda_alloc_pe(phb);
184cd4a3 1036
184cd4a3 1037 if (pe_num == IODA_INVALID_PE) {
fb446ad0
GS		 1038 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1039 __func__, pci_domain_nr(bus), bus->number);
184cd4a3
BH		 1040 return;
1041 }
1042
1043 pe = &phb->ioda.pe_array[pe_num];
262af557 1044 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
184cd4a3
BH		 1045 pe->pbus = bus;
1046 pe->pdev = NULL;
1047 pe->tce32_seg = -1;
1048 pe->mve_number = -1;
b918c62e 1049 pe->rid = bus->busn_res.start << 8;
184cd4a3
BH		 1050 pe->dma_weight = 0;
1051
fb446ad0
GS		 1052 if (all)
1053 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1054 bus->busn_res.start, bus->busn_res.end, pe_num);
1055 else
1056 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1057 bus->busn_res.start, pe_num);
184cd4a3
BH		 1058
1059 if (pnv_ioda_configure_pe(phb, pe)) {
1060 /* XXX What do we do here ? */
1061 if (pe_num)
1062 pnv_ioda_free_pe(phb, pe_num);
1063 pe->pbus = NULL;
1064 return;
1065 }
1066
1067 /* Associate it with all child devices */
1068 pnv_ioda_setup_same_PE(bus, pe);
1069
7ebdf956
GS		 1070 /* Put PE to the list */
1071 list_add_tail(&pe->list, &phb->ioda.pe_list);
1072
184cd4a3
BH		 1073 /* Account for one DMA PE if at least one DMA capable device exist
1074 * below the bridge
1075 */
1076 if (pe->dma_weight != 0) {
1077 phb->ioda.dma_weight += pe->dma_weight;
1078 phb->ioda.dma_pe_count++;
1079 }
1080
1081 /* Link the PE */
1082 pnv_ioda_link_pe_by_weight(phb, pe);
1083}
1084
cad5cef6 1085static void pnv_ioda_setup_PEs(struct pci_bus *bus)
184cd4a3
BH		 1086{
1087 struct pci_dev *dev;
fb446ad0 1088
d1203852 1089 pnv_ioda_setup_bus_PE(bus, false);
184cd4a3
BH		 1090
1091 list_for_each_entry(dev, &bus->devices, bus_list) {
fb446ad0
GS		 1092 if (dev->subordinate) {
1093 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
d1203852 1094 pnv_ioda_setup_bus_PE(dev->subordinate, true);
fb446ad0
GS		 1095 else
1096 pnv_ioda_setup_PEs(dev->subordinate);
1097 }
1098 }
1099}
1100
1101/*
1102 * Configure PEs so that the downstream PCI buses and devices
1103 * could have their associated PE#. Unfortunately, we didn't
1104 * figure out the way to identify the PLX bridge yet. So we
1105 * simply put the PCI bus and the subordinate behind the root
1106 * port to PE# here. The game rule here is expected to be changed
1107 * as soon as we can detected PLX bridge correctly.
1108 */
cad5cef6 1109static void pnv_pci_ioda_setup_PEs(void)
fb446ad0
GS		 1110{
1111 struct pci_controller *hose, *tmp;
262af557 1112 struct pnv_phb *phb;
fb446ad0
GS		 1113
1114 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
262af557
GC		 1115 phb = hose->private_data;
1116
1117 /* M64 layout might affect PE allocation */
5ef73567 1118 if (phb->reserve_m64_pe)
96a2f92b 1119 phb->reserve_m64_pe(hose->bus, NULL, true);
262af557 1120
fb446ad0 1121 pnv_ioda_setup_PEs(hose->bus);
184cd4a3
BH		 1122 }
1123}
1124
a8b2f828 1125#ifdef CONFIG_PCI_IOV
781a868f
WY		 1126static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1127{
1128 struct pci_bus *bus;
1129 struct pci_controller *hose;
1130 struct pnv_phb *phb;
1131 struct pci_dn *pdn;
02639b0e 1132 int i, j;
781a868f
WY		 1133
1134 bus = pdev->bus;
1135 hose = pci_bus_to_host(bus);
1136 phb = hose->private_data;
1137 pdn = pci_get_pdn(pdev);
1138
02639b0e
WY		 1139 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1140 for (j = 0; j < M64_PER_IOV; j++) {
1141 if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1142 continue;
1143 opal_pci_phb_mmio_enable(phb->opal_id,
1144 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1145 clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1146 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1147 }
781a868f
WY		 1148
1149 return 0;
1150}
1151
02639b0e 1152static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1153{
1154 struct pci_bus *bus;
1155 struct pci_controller *hose;
1156 struct pnv_phb *phb;
1157 struct pci_dn *pdn;
1158 unsigned int win;
1159 struct resource *res;
02639b0e 1160 int i, j;
781a868f 1161 int64_t rc;
02639b0e
WY		 1162 int total_vfs;
1163 resource_size_t size, start;
1164 int pe_num;
1165 int vf_groups;
1166 int vf_per_group;
781a868f
WY		 1167
1168 bus = pdev->bus;
1169 hose = pci_bus_to_host(bus);
1170 phb = hose->private_data;
1171 pdn = pci_get_pdn(pdev);
02639b0e 1172 total_vfs = pci_sriov_get_totalvfs(pdev);
781a868f
WY		 1173
1174 /* Initialize the m64_wins to IODA_INVALID_M64 */
1175 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
02639b0e
WY		 1176 for (j = 0; j < M64_PER_IOV; j++)
1177 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1178
1179 if (pdn->m64_per_iov == M64_PER_IOV) {
1180 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1181 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1182 roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1183 } else {
1184 vf_groups = 1;
1185 vf_per_group = 1;
1186 }
781a868f
WY		 1187
1188 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1189 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1190 if (!res->flags || !res->parent)
1191 continue;
1192
1193 if (!pnv_pci_is_mem_pref_64(res->flags))
1194 continue;
1195
02639b0e
WY		 1196 for (j = 0; j < vf_groups; j++) {
1197 do {
1198 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1199 phb->ioda.m64_bar_idx + 1, 0);
1200
1201 if (win >= phb->ioda.m64_bar_idx + 1)
1202 goto m64_failed;
1203 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1204
1205 pdn->m64_wins[i][j] = win;
1206
1207 if (pdn->m64_per_iov == M64_PER_IOV) {
1208 size = pci_iov_resource_size(pdev,
1209 PCI_IOV_RESOURCES + i);
1210 size = size * vf_per_group;
1211 start = res->start + size * j;
1212 } else {
1213 size = resource_size(res);
1214 start = res->start;
1215 }
1216
1217 /* Map the M64 here */
1218 if (pdn->m64_per_iov == M64_PER_IOV) {
1219 pe_num = pdn->offset + j;
1220 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1221 pe_num, OPAL_M64_WINDOW_TYPE,
1222 pdn->m64_wins[i][j], 0);
1223 }
1224
1225 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1226 OPAL_M64_WINDOW_TYPE,
1227 pdn->m64_wins[i][j],
1228 start,
1229 0, /* unused */
1230 size);
781a868f 1231
781a868f 1232
02639b0e
WY		 1233 if (rc != OPAL_SUCCESS) {
1234 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1235 win, rc);
1236 goto m64_failed;
1237 }
781a868f 1238
02639b0e
WY		 1239 if (pdn->m64_per_iov == M64_PER_IOV)
1240 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1241 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1242 else
1243 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1244 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
781a868f 1245
02639b0e
WY		 1246 if (rc != OPAL_SUCCESS) {
1247 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1248 win, rc);
1249 goto m64_failed;
1250 }
781a868f
WY		 1251 }
1252 }
1253 return 0;
1254
1255m64_failed:
1256 pnv_pci_vf_release_m64(pdev);
1257 return -EBUSY;
1258}
1259
c035e37b
AK		 1260static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1261 int num);
1262static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1263
781a868f
WY		 1264static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1265{
781a868f 1266 struct iommu_table *tbl;
781a868f
WY		 1267 int64_t rc;
1268
b348aa65 1269 tbl = pe->table_group.tables[0];
c035e37b 1270 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
781a868f
WY		 1271 if (rc)
1272 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1273
c035e37b 1274 pnv_pci_ioda2_set_bypass(pe, false);
0eaf4def
AK		 1275 if (pe->table_group.group) {
1276 iommu_group_put(pe->table_group.group);
1277 BUG_ON(pe->table_group.group);
ac9a5889 1278 }
aca6913f 1279 pnv_pci_ioda2_table_free_pages(tbl);
781a868f 1280 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
781a868f
WY		 1281}
1282
02639b0e 1283static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1284{
1285 struct pci_bus *bus;
1286 struct pci_controller *hose;
1287 struct pnv_phb *phb;
1288 struct pnv_ioda_pe *pe, *pe_n;
1289 struct pci_dn *pdn;
02639b0e
WY		 1290 u16 vf_index;
1291 int64_t rc;
781a868f
WY		 1292
1293 bus = pdev->bus;
1294 hose = pci_bus_to_host(bus);
1295 phb = hose->private_data;
02639b0e 1296 pdn = pci_get_pdn(pdev);
781a868f
WY		 1297
1298 if (!pdev->is_physfn)
1299 return;
1300
02639b0e
WY		 1301 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1302 int vf_group;
1303 int vf_per_group;
1304 int vf_index1;
1305
1306 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1307
1308 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1309 for (vf_index = vf_group * vf_per_group;
1310 vf_index < (vf_group + 1) * vf_per_group &&
1311 vf_index < num_vfs;
1312 vf_index++)
1313 for (vf_index1 = vf_group * vf_per_group;
1314 vf_index1 < (vf_group + 1) * vf_per_group &&
1315 vf_index1 < num_vfs;
1316 vf_index1++){
1317
1318 rc = opal_pci_set_peltv(phb->opal_id,
1319 pdn->offset + vf_index,
1320 pdn->offset + vf_index1,
1321 OPAL_REMOVE_PE_FROM_DOMAIN);
1322
1323 if (rc)
1324 dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1325 __func__,
1326 pdn->offset + vf_index1, rc);
1327 }
1328 }
1329
781a868f
WY		 1330 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1331 if (pe->parent_dev != pdev)
1332 continue;
1333
1334 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1335
1336 /* Remove from list */
1337 mutex_lock(&phb->ioda.pe_list_mutex);
1338 list_del(&pe->list);
1339 mutex_unlock(&phb->ioda.pe_list_mutex);
1340
1341 pnv_ioda_deconfigure_pe(phb, pe);
1342
1343 pnv_ioda_free_pe(phb, pe->pe_number);
1344 }
1345}
1346
1347void pnv_pci_sriov_disable(struct pci_dev *pdev)
1348{
1349 struct pci_bus *bus;
1350 struct pci_controller *hose;
1351 struct pnv_phb *phb;
1352 struct pci_dn *pdn;
1353 struct pci_sriov *iov;
1354 u16 num_vfs;
1355
1356 bus = pdev->bus;
1357 hose = pci_bus_to_host(bus);
1358 phb = hose->private_data;
1359 pdn = pci_get_pdn(pdev);
1360 iov = pdev->sriov;
1361 num_vfs = pdn->num_vfs;
1362
1363 /* Release VF PEs */
02639b0e 1364 pnv_ioda_release_vf_PE(pdev, num_vfs);
781a868f
WY		 1365
1366 if (phb->type == PNV_PHB_IODA2) {
02639b0e
WY		 1367 if (pdn->m64_per_iov == 1)
1368 pnv_pci_vf_resource_shift(pdev, -pdn->offset);
781a868f
WY		 1369
1370 /* Release M64 windows */
1371 pnv_pci_vf_release_m64(pdev);
1372
1373 /* Release PE numbers */
1374 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1375 pdn->offset = 0;
1376 }
1377}
1378
1379static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1380 struct pnv_ioda_pe *pe);
1381static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1382{
1383 struct pci_bus *bus;
1384 struct pci_controller *hose;
1385 struct pnv_phb *phb;
1386 struct pnv_ioda_pe *pe;
1387 int pe_num;
1388 u16 vf_index;
1389 struct pci_dn *pdn;
02639b0e 1390 int64_t rc;
781a868f
WY		 1391
1392 bus = pdev->bus;
1393 hose = pci_bus_to_host(bus);
1394 phb = hose->private_data;
1395 pdn = pci_get_pdn(pdev);
1396
1397 if (!pdev->is_physfn)
1398 return;
1399
1400 /* Reserve PE for each VF */
1401 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1402 pe_num = pdn->offset + vf_index;
1403
1404 pe = &phb->ioda.pe_array[pe_num];
1405 pe->pe_number = pe_num;
1406 pe->phb = phb;
1407 pe->flags = PNV_IODA_PE_VF;
1408 pe->pbus = NULL;
1409 pe->parent_dev = pdev;
1410 pe->tce32_seg = -1;
1411 pe->mve_number = -1;
1412 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1413 pci_iov_virtfn_devfn(pdev, vf_index);
1414
1415 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1416 hose->global_number, pdev->bus->number,
1417 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1418 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1419
1420 if (pnv_ioda_configure_pe(phb, pe)) {
1421 /* XXX What do we do here ? */
1422 if (pe_num)
1423 pnv_ioda_free_pe(phb, pe_num);
1424 pe->pdev = NULL;
1425 continue;
1426 }
1427
781a868f
WY		 1428 /* Put PE to the list */
1429 mutex_lock(&phb->ioda.pe_list_mutex);
1430 list_add_tail(&pe->list, &phb->ioda.pe_list);
1431 mutex_unlock(&phb->ioda.pe_list_mutex);
1432
1433 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1434 }
02639b0e
WY		 1435
1436 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1437 int vf_group;
1438 int vf_per_group;
1439 int vf_index1;
1440
1441 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1442
1443 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1444 for (vf_index = vf_group * vf_per_group;
1445 vf_index < (vf_group + 1) * vf_per_group &&
1446 vf_index < num_vfs;
1447 vf_index++) {
1448 for (vf_index1 = vf_group * vf_per_group;
1449 vf_index1 < (vf_group + 1) * vf_per_group &&
1450 vf_index1 < num_vfs;
1451 vf_index1++) {
1452
1453 rc = opal_pci_set_peltv(phb->opal_id,
1454 pdn->offset + vf_index,
1455 pdn->offset + vf_index1,
1456 OPAL_ADD_PE_TO_DOMAIN);
1457
1458 if (rc)
1459 dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1460 __func__,
1461 pdn->offset + vf_index1, rc);
1462 }
1463 }
1464 }
1465 }
781a868f
WY		 1466}
1467
1468int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1469{
1470 struct pci_bus *bus;
1471 struct pci_controller *hose;
1472 struct pnv_phb *phb;
1473 struct pci_dn *pdn;
1474 int ret;
1475
1476 bus = pdev->bus;
1477 hose = pci_bus_to_host(bus);
1478 phb = hose->private_data;
1479 pdn = pci_get_pdn(pdev);
1480
1481 if (phb->type == PNV_PHB_IODA2) {
1482 /* Calculate available PE for required VFs */
1483 mutex_lock(&phb->ioda.pe_alloc_mutex);
1484 pdn->offset = bitmap_find_next_zero_area(
1485 phb->ioda.pe_alloc, phb->ioda.total_pe,
1486 0, num_vfs, 0);
1487 if (pdn->offset >= phb->ioda.total_pe) {
1488 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1489 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1490 pdn->offset = 0;
1491 return -EBUSY;
1492 }
1493 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1494 pdn->num_vfs = num_vfs;
1495 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1496
1497 /* Assign M64 window accordingly */
02639b0e 1498 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
781a868f
WY		 1499 if (ret) {
1500 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1501 goto m64_failed;
1502 }
1503
1504 /*
1505 * When using one M64 BAR to map one IOV BAR, we need to shift
1506 * the IOV BAR according to the PE# allocated to the VFs.
1507 * Otherwise, the PE# for the VF will conflict with others.
1508 */
02639b0e
WY		 1509 if (pdn->m64_per_iov == 1) {
1510 ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1511 if (ret)
1512 goto m64_failed;
1513 }
781a868f
WY		 1514 }
1515
1516 /* Setup VF PEs */
1517 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1518
1519 return 0;
1520
1521m64_failed:
1522 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1523 pdn->offset = 0;
1524
1525 return ret;
1526}
1527
a8b2f828
GS		 1528int pcibios_sriov_disable(struct pci_dev *pdev)
1529{
781a868f
WY		 1530 pnv_pci_sriov_disable(pdev);
1531
a8b2f828
GS		 1532 /* Release PCI data */
1533 remove_dev_pci_data(pdev);
1534 return 0;
1535}
1536
1537int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1538{
1539 /* Allocate PCI data */
1540 add_dev_pci_data(pdev);
781a868f
WY		 1541
1542 pnv_pci_sriov_enable(pdev, num_vfs);
a8b2f828
GS		 1543 return 0;
1544}
1545#endif /* CONFIG_PCI_IOV */
1546
959c9bdd 1547static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
184cd4a3 1548{
b72c1f65 1549 struct pci_dn *pdn = pci_get_pdn(pdev);
959c9bdd 1550 struct pnv_ioda_pe *pe;
184cd4a3 1551
959c9bdd
GS		 1552 /*
1553 * The function can be called while the PE#
1554 * hasn't been assigned. Do nothing for the
1555 * case.
1556 */
1557 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1558 return;
184cd4a3 1559
959c9bdd 1560 pe = &phb->ioda.pe_array[pdn->pe_number];
cd15b048 1561 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
b348aa65 1562 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
4617082e
AK		 1563 /*
1564 * Note: iommu_add_device() will fail here as
1565 * for physical PE: the device is already added by now;
1566 * for virtual PE: sysfs entries are not ready yet and
1567 * tce_iommu_bus_notifier will add the device to a group later.
1568 */
184cd4a3
BH		 1569}
1570
763d2d8d 1571static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
cd15b048 1572{
763d2d8d
DA		 1573 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1574 struct pnv_phb *phb = hose->private_data;
cd15b048
BH		 1575 struct pci_dn *pdn = pci_get_pdn(pdev);
1576 struct pnv_ioda_pe *pe;
1577 uint64_t top;
1578 bool bypass = false;
1579
1580 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1581 return -ENODEV;;
1582
1583 pe = &phb->ioda.pe_array[pdn->pe_number];
1584 if (pe->tce_bypass_enabled) {
1585 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1586 bypass = (dma_mask >= top);
1587 }
1588
1589 if (bypass) {
1590 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1591 set_dma_ops(&pdev->dev, &dma_direct_ops);
cd15b048
BH		 1592 } else {
1593 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1594 set_dma_ops(&pdev->dev, &dma_iommu_ops);
cd15b048 1595 }
a32305bf 1596 *pdev->dev.dma_mask = dma_mask;
cd15b048
BH		 1597 return 0;
1598}
1599
fe7e85c6
GS		 1600static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb,
1601 struct pci_dev *pdev)
1602{
1603 struct pci_dn *pdn = pci_get_pdn(pdev);
1604 struct pnv_ioda_pe *pe;
1605 u64 end, mask;
1606
1607 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1608 return 0;
1609
1610 pe = &phb->ioda.pe_array[pdn->pe_number];
1611 if (!pe->tce_bypass_enabled)
1612 return __dma_get_required_mask(&pdev->dev);
1613
1614
1615 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1616 mask = 1ULL << (fls64(end) - 1);
1617 mask += mask - 1;
1618
1619 return mask;
1620}
1621
dff4a39e 1622static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
ea30e99e 1623 struct pci_bus *bus)
74251fe2
BH		 1624{
1625 struct pci_dev *dev;
1626
1627 list_for_each_entry(dev, &bus->devices, bus_list) {
b348aa65 1628 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
e91c2511 1629 set_dma_offset(&dev->dev, pe->tce_bypass_base);
4617082e 1630 iommu_add_device(&dev->dev);
dff4a39e 1631
5c89a87d 1632 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
ea30e99e 1633 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
74251fe2
BH		 1634 }
1635}
1636
decbda25
AK		 1637static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1638 unsigned long index, unsigned long npages, bool rm)
4cce9550 1639{
0eaf4def
AK		 1640 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1641 &tbl->it_group_list, struct iommu_table_group_link,
1642 next);
1643 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
b348aa65 1644 struct pnv_ioda_pe, table_group);
3ad26e5c 1645 __be64 __iomem *invalidate = rm ?
5780fb04
AK		 1646 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1647 pe->phb->ioda.tce_inval_reg;
4cce9550 1648 unsigned long start, end, inc;
b0376c9b 1649 const unsigned shift = tbl->it_page_shift;
4cce9550 1650
decbda25
AK		 1651 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1652 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1653 npages - 1);
4cce9550
GS		 1654
1655 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1656 if (tbl->it_busno) {
b0376c9b
AK		 1657 start <<= shift;
1658 end <<= shift;
1659 inc = 128ull << shift;
4cce9550
GS		 1660 start |= tbl->it_busno;
1661 end |= tbl->it_busno;
1662 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1663 /* p7ioc-style invalidation, 2 TCEs per write */
1664 start |= (1ull << 63);
1665 end |= (1ull << 63);
1666 inc = 16;
1667 } else {
1668 /* Default (older HW) */
1669 inc = 128;
1670 }
1671
1672 end |= inc - 1; /* round up end to be different than start */
1673
1674 mb(); /* Ensure above stores are visible */
1675 while (start <= end) {
8e0a1611 1676 if (rm)
3ad26e5c 1677 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1678 else
3ad26e5c 1679 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1680 start += inc;
1681 }
1682
1683 /*
1684 * The iommu layer will do another mb() for us on build()
1685 * and we don't care on free()
1686 */
1687}
1688
decbda25
AK		 1689static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1690 long npages, unsigned long uaddr,
1691 enum dma_data_direction direction,
1692 struct dma_attrs *attrs)
1693{
1694 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1695 attrs);
1696
1697 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1698 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1699
1700 return ret;
1701}
1702
05c6cfb9
AK		 1703#ifdef CONFIG_IOMMU_API
1704static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1705 unsigned long *hpa, enum dma_data_direction *direction)
1706{
1707 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1708
1709 if (!ret && (tbl->it_type &
1710 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1711 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1712
1713 return ret;
1714}
1715#endif
1716
decbda25
AK		 1717static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1718 long npages)
1719{
1720 pnv_tce_free(tbl, index, npages);
1721
1722 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1723 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1724}
1725
da004c36 1726static struct iommu_table_ops pnv_ioda1_iommu_ops = {
decbda25 1727 .set = pnv_ioda1_tce_build,
05c6cfb9
AK		 1728#ifdef CONFIG_IOMMU_API
1729 .exchange = pnv_ioda1_tce_xchg,
1730#endif
decbda25 1731 .clear = pnv_ioda1_tce_free,
da004c36
AK		 1732 .get = pnv_tce_get,
1733};
1734
5780fb04
AK		 1735static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1736{
1737 /* 01xb - invalidate TCEs that match the specified PE# */
1738 unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1739 struct pnv_phb *phb = pe->phb;
1740
1741 if (!phb->ioda.tce_inval_reg)
1742 return;
1743
1744 mb(); /* Ensure above stores are visible */
1745 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1746}
1747
e57080f1
AK		 1748static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1749 __be64 __iomem *invalidate, unsigned shift,
1750 unsigned long index, unsigned long npages)
4cce9550
GS		 1751{
1752 unsigned long start, end, inc;
4cce9550
GS		 1753
1754 /* We'll invalidate DMA address in PE scope */
b0376c9b 1755 start = 0x2ull << 60;
e57080f1 1756 start |= (pe_number & 0xFF);
4cce9550
GS		 1757 end = start;
1758
1759 /* Figure out the start, end and step */
decbda25
AK		 1760 start |= (index << shift);
1761 end |= ((index + npages - 1) << shift);
b0376c9b 1762 inc = (0x1ull << shift);
4cce9550
GS		 1763 mb();
1764
1765 while (start <= end) {
8e0a1611 1766 if (rm)
3ad26e5c 1767 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1768 else
3ad26e5c 1769 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1770 start += inc;
1771 }
1772}
1773
e57080f1
AK		 1774static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1775 unsigned long index, unsigned long npages, bool rm)
1776{
1777 struct iommu_table_group_link *tgl;
1778
1779 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1780 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1781 struct pnv_ioda_pe, table_group);
1782 __be64 __iomem *invalidate = rm ?
1783 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1784 pe->phb->ioda.tce_inval_reg;
1785
1786 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1787 invalidate, tbl->it_page_shift,
1788 index, npages);
1789 }
1790}
1791
decbda25
AK		 1792static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1793 long npages, unsigned long uaddr,
1794 enum dma_data_direction direction,
1795 struct dma_attrs *attrs)
4cce9550 1796{
decbda25
AK		 1797 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1798 attrs);
4cce9550 1799
decbda25
AK		 1800 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1801 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1802
1803 return ret;
1804}
1805
05c6cfb9
AK		 1806#ifdef CONFIG_IOMMU_API
1807static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1808 unsigned long *hpa, enum dma_data_direction *direction)
1809{
1810 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1811
1812 if (!ret && (tbl->it_type &
1813 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1814 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1815
1816 return ret;
1817}
1818#endif
1819
decbda25
AK		 1820static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1821 long npages)
1822{
1823 pnv_tce_free(tbl, index, npages);
1824
1825 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1826 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
4cce9550
GS		 1827}
1828
4793d65d
AK		 1829static void pnv_ioda2_table_free(struct iommu_table *tbl)
1830{
1831 pnv_pci_ioda2_table_free_pages(tbl);
1832 iommu_free_table(tbl, "pnv");
1833}
1834
da004c36 1835static struct iommu_table_ops pnv_ioda2_iommu_ops = {
decbda25 1836 .set = pnv_ioda2_tce_build,
05c6cfb9
AK		 1837#ifdef CONFIG_IOMMU_API
1838 .exchange = pnv_ioda2_tce_xchg,
1839#endif
decbda25 1840 .clear = pnv_ioda2_tce_free,
da004c36 1841 .get = pnv_tce_get,
4793d65d 1842 .free = pnv_ioda2_table_free,
da004c36
AK		 1843};
1844
cad5cef6
GKH		 1845static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1846 struct pnv_ioda_pe *pe, unsigned int base,
1847 unsigned int segs)
184cd4a3
BH		 1848{
1849
1850 struct page *tce_mem = NULL;
184cd4a3
BH		 1851 struct iommu_table *tbl;
1852 unsigned int i;
1853 int64_t rc;
1854 void *addr;
1855
184cd4a3
BH		 1856 /* XXX FIXME: Handle 64-bit only DMA devices */
1857 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1858 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1859
1860 /* We shouldn't already have a 32-bit DMA associated */
1861 if (WARN_ON(pe->tce32_seg >= 0))
1862 return;
1863
0eaf4def 1864 tbl = pnv_pci_table_alloc(phb->hose->node);
b348aa65
AK		 1865 iommu_register_group(&pe->table_group, phb->hose->global_number,
1866 pe->pe_number);
0eaf4def 1867 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
c5773822 1868
184cd4a3
BH		 1869 /* Grab a 32-bit TCE table */
1870 pe->tce32_seg = base;
1871 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1872 (base << 28), ((base + segs) << 28) - 1);
1873
1874 /* XXX Currently, we allocate one big contiguous table for the
1875 * TCEs. We only really need one chunk per 256M of TCE space
1876 * (ie per segment) but that's an optimization for later, it
1877 * requires some added smarts with our get/put_tce implementation
1878 */
1879 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1880 get_order(TCE32_TABLE_SIZE * segs));
1881 if (!tce_mem) {
1882 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1883 goto fail;
1884 }
1885 addr = page_address(tce_mem);
1886 memset(addr, 0, TCE32_TABLE_SIZE * segs);
1887
1888 /* Configure HW */
1889 for (i = 0; i < segs; i++) {
1890 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1891 pe->pe_number,
1892 base + i, 1,
1893 __pa(addr) + TCE32_TABLE_SIZE * i,
1894 TCE32_TABLE_SIZE, 0x1000);
1895 if (rc) {
1896 pe_err(pe, " Failed to configure 32-bit TCE table,"
1897 " err %ld\n", rc);
1898 goto fail;
1899 }
1900 }
1901
1902 /* Setup linux iommu table */
184cd4a3 1903 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
8fa5d454 1904 base << 28, IOMMU_PAGE_SHIFT_4K);
184cd4a3
BH		 1905
1906 /* OPAL variant of P7IOC SW invalidated TCEs */
5780fb04 1907 if (phb->ioda.tce_inval_reg)
65fd766b
GS		 1908 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
1909 TCE_PCI_SWINV_FREE |
1910 TCE_PCI_SWINV_PAIR);
5780fb04 1911
da004c36 1912 tbl->it_ops = &pnv_ioda1_iommu_ops;
4793d65d
AK		 1913 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
1914 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
184cd4a3
BH		 1915 iommu_init_table(tbl, phb->hose->node);
1916
781a868f 1917 if (pe->flags & PNV_IODA_PE_DEV) {
4617082e
AK		 1918 /*
1919 * Setting table base here only for carrying iommu_group
1920 * further down to let iommu_add_device() do the job.
1921 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
1922 */
1923 set_iommu_table_base(&pe->pdev->dev, tbl);
1924 iommu_add_device(&pe->pdev->dev);
c5773822 1925 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
ea30e99e 1926 pnv_ioda_setup_bus_dma(pe, pe->pbus);
74251fe2 1927
184cd4a3
BH		 1928 return;
1929 fail:
1930 /* XXX Failure: Try to fallback to 64-bit only ? */
1931 if (pe->tce32_seg >= 0)
1932 pe->tce32_seg = -1;
1933 if (tce_mem)
1934 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
0eaf4def
AK		 1935 if (tbl) {
1936 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1937 iommu_free_table(tbl, "pnv");
1938 }
184cd4a3
BH		 1939}
1940
43cb60ab
AK		 1941static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1942 int num, struct iommu_table *tbl)
1943{
1944 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1945 table_group);
1946 struct pnv_phb *phb = pe->phb;
1947 int64_t rc;
bbb845c4
AK		 1948 const unsigned long size = tbl->it_indirect_levels ?
1949 tbl->it_level_size : tbl->it_size;
43cb60ab
AK		 1950 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1951 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1952
4793d65d 1953 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
43cb60ab
AK		 1954 start_addr, start_addr + win_size - 1,
1955 IOMMU_PAGE_SIZE(tbl));
1956
1957 /*
1958 * Map TCE table through TVT. The TVE index is the PE number
1959 * shifted by 1 bit for 32-bits DMA space.
1960 */
1961 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1962 pe->pe_number,
4793d65d 1963 (pe->pe_number << 1) + num,
bbb845c4 1964 tbl->it_indirect_levels + 1,
43cb60ab 1965 __pa(tbl->it_base),
bbb845c4 1966 size << 3,
43cb60ab
AK		 1967 IOMMU_PAGE_SIZE(tbl));
1968 if (rc) {
1969 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
1970 return rc;
1971 }
1972
1973 pnv_pci_link_table_and_group(phb->hose->node, num,
1974 tbl, &pe->table_group);
1975 pnv_pci_ioda2_tce_invalidate_entire(pe);
1976
1977 return 0;
1978}
1979
f87a8864 1980static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
cd15b048 1981{
cd15b048
BH		 1982 uint16_t window_id = (pe->pe_number << 1 ) + 1;
1983 int64_t rc;
1984
1985 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1986 if (enable) {
1987 phys_addr_t top = memblock_end_of_DRAM();
1988
1989 top = roundup_pow_of_two(top);
1990 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1991 pe->pe_number,
1992 window_id,
1993 pe->tce_bypass_base,
1994 top);
1995 } else {
1996 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1997 pe->pe_number,
1998 window_id,
1999 pe->tce_bypass_base,
2000 0);
cd15b048
BH		 2001 }
2002 if (rc)
2003 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2004 else
2005 pe->tce_bypass_enabled = enable;
2006}
2007
4793d65d
AK		 2008static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2009 __u32 page_shift, __u64 window_size, __u32 levels,
2010 struct iommu_table *tbl);
2011
2012static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2013 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2014 struct iommu_table **ptbl)
2015{
2016 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2017 table_group);
2018 int nid = pe->phb->hose->node;
2019 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2020 long ret;
2021 struct iommu_table *tbl;
2022
2023 tbl = pnv_pci_table_alloc(nid);
2024 if (!tbl)
2025 return -ENOMEM;
2026
2027 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2028 bus_offset, page_shift, window_size,
2029 levels, tbl);
2030 if (ret) {
2031 iommu_free_table(tbl, "pnv");
2032 return ret;
2033 }
2034
2035 tbl->it_ops = &pnv_ioda2_iommu_ops;
2036 if (pe->phb->ioda.tce_inval_reg)
2037 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2038
2039 *ptbl = tbl;
2040
2041 return 0;
2042}
2043
46d3e1e1
AK		 2044static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2045{
2046 struct iommu_table *tbl = NULL;
2047 long rc;
2048
2049 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2050 IOMMU_PAGE_SHIFT_4K,
2051 pe->table_group.tce32_size,
2052 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2053 if (rc) {
2054 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2055 rc);
2056 return rc;
2057 }
2058
2059 iommu_init_table(tbl, pe->phb->hose->node);
2060
2061 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2062 if (rc) {
2063 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2064 rc);
2065 pnv_ioda2_table_free(tbl);
2066 return rc;
2067 }
2068
2069 if (!pnv_iommu_bypass_disabled)
2070 pnv_pci_ioda2_set_bypass(pe, true);
2071
2072 /* OPAL variant of PHB3 invalidated TCEs */
2073 if (pe->phb->ioda.tce_inval_reg)
2074 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2075
2076 /*
2077 * Setting table base here only for carrying iommu_group
2078 * further down to let iommu_add_device() do the job.
2079 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2080 */
2081 if (pe->flags & PNV_IODA_PE_DEV)
2082 set_iommu_table_base(&pe->pdev->dev, tbl);
2083
2084 return 0;
2085}
2086
b5926430
AK		 2087#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2088static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2089 int num)
2090{
2091 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2092 table_group);
2093 struct pnv_phb *phb = pe->phb;
2094 long ret;
2095
2096 pe_info(pe, "Removing DMA window #%d\n", num);
2097
2098 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2099 (pe->pe_number << 1) + num,
2100 0/* levels */, 0/* table address */,
2101 0/* table size */, 0/* page size */);
2102 if (ret)
2103 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2104 else
2105 pnv_pci_ioda2_tce_invalidate_entire(pe);
2106
2107 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2108
2109 return ret;
2110}
2111#endif
2112
f87a8864 2113#ifdef CONFIG_IOMMU_API
00547193
AK		 2114static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2115 __u64 window_size, __u32 levels)
2116{
2117 unsigned long bytes = 0;
2118 const unsigned window_shift = ilog2(window_size);
2119 unsigned entries_shift = window_shift - page_shift;
2120 unsigned table_shift = entries_shift + 3;
2121 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2122 unsigned long direct_table_size;
2123
2124 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2125 (window_size > memory_hotplug_max()) ||
2126 !is_power_of_2(window_size))
2127 return 0;
2128
2129 /* Calculate a direct table size from window_size and levels */
2130 entries_shift = (entries_shift + levels - 1) / levels;
2131 table_shift = entries_shift + 3;
2132 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2133 direct_table_size = 1UL << table_shift;
2134
2135 for ( ; levels; --levels) {
2136 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2137
2138 tce_table_size /= direct_table_size;
2139 tce_table_size <<= 3;
2140 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2141 }
2142
2143 return bytes;
2144}
2145
f87a8864 2146static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
cd15b048 2147{
f87a8864
AK		 2148 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2149 table_group);
46d3e1e1
AK		 2150 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2151 struct iommu_table *tbl = pe->table_group.tables[0];
cd15b048 2152
f87a8864 2153 pnv_pci_ioda2_set_bypass(pe, false);
46d3e1e1
AK		 2154 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2155 pnv_ioda2_table_free(tbl);
f87a8864 2156}
cd15b048 2157
f87a8864
AK		 2158static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2159{
2160 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2161 table_group);
2162
46d3e1e1 2163 pnv_pci_ioda2_setup_default_config(pe);
cd15b048
BH		 2164}
2165
f87a8864 2166static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
00547193 2167 .get_table_size = pnv_pci_ioda2_get_table_size,
4793d65d
AK		 2168 .create_table = pnv_pci_ioda2_create_table,
2169 .set_window = pnv_pci_ioda2_set_window,
2170 .unset_window = pnv_pci_ioda2_unset_window,
f87a8864
AK		 2171 .take_ownership = pnv_ioda2_take_ownership,
2172 .release_ownership = pnv_ioda2_release_ownership,
2173};
2174#endif
2175
5780fb04
AK		 2176static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2177{
2178 const __be64 *swinvp;
2179
2180 /* OPAL variant of PHB3 invalidated TCEs */
2181 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2182 if (!swinvp)
2183 return;
2184
2185 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2186 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2187}
2188
bbb845c4
AK		 2189static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2190 unsigned levels, unsigned long limit,
2191 unsigned long *current_offset)
373f5657
GS		 2192{
2193 struct page *tce_mem = NULL;
bbb845c4 2194 __be64 *addr, *tmp;
aca6913f 2195 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
bbb845c4
AK		 2196 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2197 unsigned entries = 1UL << (shift - 3);
2198 long i;
aca6913f
AK		 2199
2200 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2201 if (!tce_mem) {
2202 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2203 return NULL;
2204 }
2205 addr = page_address(tce_mem);
bbb845c4
AK		 2206 memset(addr, 0, allocated);
2207
2208 --levels;
2209 if (!levels) {
2210 *current_offset += allocated;
2211 return addr;
2212 }
2213
2214 for (i = 0; i < entries; ++i) {
2215 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2216 levels, limit, current_offset);
2217 if (!tmp)
2218 break;
2219
2220 addr[i] = cpu_to_be64(__pa(tmp) |
2221 TCE_PCI_READ | TCE_PCI_WRITE);
2222
2223 if (*current_offset >= limit)
2224 break;
2225 }
aca6913f
AK		 2226
2227 return addr;
2228}
2229
bbb845c4
AK		 2230static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2231 unsigned long size, unsigned level);
2232
aca6913f 2233static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
bbb845c4
AK		 2234 __u32 page_shift, __u64 window_size, __u32 levels,
2235 struct iommu_table *tbl)
aca6913f 2236{
373f5657 2237 void *addr;
bbb845c4 2238 unsigned long offset = 0, level_shift;
aca6913f
AK		 2239 const unsigned window_shift = ilog2(window_size);
2240 unsigned entries_shift = window_shift - page_shift;
2241 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2242 const unsigned long tce_table_size = 1UL << table_shift;
2243
bbb845c4
AK		 2244 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2245 return -EINVAL;
2246
aca6913f
AK		 2247 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2248 return -EINVAL;
2249
bbb845c4
AK		 2250 /* Adjust direct table size from window_size and levels */
2251 entries_shift = (entries_shift + levels - 1) / levels;
2252 level_shift = entries_shift + 3;
2253 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2254
aca6913f 2255 /* Allocate TCE table */
bbb845c4
AK		 2256 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2257 levels, tce_table_size, &offset);
2258
2259 /* addr==NULL means that the first level allocation failed */
aca6913f
AK		 2260 if (!addr)
2261 return -ENOMEM;
2262
bbb845c4
AK		 2263 /*
2264 * First level was allocated but some lower level failed as
2265 * we did not allocate as much as we wanted,
2266 * release partially allocated table.
2267 */
2268 if (offset < tce_table_size) {
2269 pnv_pci_ioda2_table_do_free_pages(addr,
2270 1ULL << (level_shift - 3), levels - 1);
2271 return -ENOMEM;
2272 }
2273
aca6913f
AK		 2274 /* Setup linux iommu table */
2275 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2276 page_shift);
bbb845c4
AK		 2277 tbl->it_level_size = 1ULL << (level_shift - 3);
2278 tbl->it_indirect_levels = levels - 1;
00547193 2279 tbl->it_allocated_size = offset;
aca6913f
AK		 2280
2281 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2282 window_size, tce_table_size, bus_offset);
2283
2284 return 0;
2285}
2286
bbb845c4
AK		 2287static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2288 unsigned long size, unsigned level)
2289{
2290 const unsigned long addr_ul = (unsigned long) addr &
2291 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2292
2293 if (level) {
2294 long i;
2295 u64 *tmp = (u64 *) addr_ul;
2296
2297 for (i = 0; i < size; ++i) {
2298 unsigned long hpa = be64_to_cpu(tmp[i]);
2299
2300 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2301 continue;
2302
2303 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2304 level - 1);
2305 }
2306 }
2307
2308 free_pages(addr_ul, get_order(size << 3));
2309}
2310
aca6913f
AK		 2311static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2312{
bbb845c4
AK		 2313 const unsigned long size = tbl->it_indirect_levels ?
2314 tbl->it_level_size : tbl->it_size;
2315
aca6913f
AK		 2316 if (!tbl->it_size)
2317 return;
2318
bbb845c4
AK		 2319 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2320 tbl->it_indirect_levels);
aca6913f
AK		 2321}
2322
2323static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2324 struct pnv_ioda_pe *pe)
2325{
373f5657
GS		 2326 int64_t rc;
2327
2328 /* We shouldn't already have a 32-bit DMA associated */
2329 if (WARN_ON(pe->tce32_seg >= 0))
2330 return;
2331
f87a8864
AK		 2332 /* TVE #1 is selected by PCI address bit 59 */
2333 pe->tce_bypass_base = 1ull << 59;
2334
b348aa65
AK		 2335 iommu_register_group(&pe->table_group, phb->hose->global_number,
2336 pe->pe_number);
c5773822 2337
373f5657
GS		 2338 /* The PE will reserve all possible 32-bits space */
2339 pe->tce32_seg = 0;
373f5657 2340 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
aca6913f 2341 phb->ioda.m32_pci_base);
373f5657 2342
aca6913f 2343 /* Setup linux iommu table */
4793d65d
AK		 2344 pe->table_group.tce32_start = 0;
2345 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2346 pe->table_group.max_dynamic_windows_supported =
2347 IOMMU_TABLE_GROUP_MAX_TABLES;
2348 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2349 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
e5aad1e6
AK		 2350#ifdef CONFIG_IOMMU_API
2351 pe->table_group.ops = &pnv_pci_ioda2_ops;
2352#endif
2353
46d3e1e1 2354 rc = pnv_pci_ioda2_setup_default_config(pe);
373f5657 2355 if (rc) {
46d3e1e1
AK		 2356 if (pe->tce32_seg >= 0)
2357 pe->tce32_seg = -1;
2358 return;
373f5657
GS		 2359 }
2360
46d3e1e1 2361 if (pe->flags & PNV_IODA_PE_DEV)
4617082e 2362 iommu_add_device(&pe->pdev->dev);
46d3e1e1 2363 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
ea30e99e 2364 pnv_ioda_setup_bus_dma(pe, pe->pbus);
373f5657
GS		 2365}
2366
cad5cef6 2367static void pnv_ioda_setup_dma(struct pnv_phb *phb)
184cd4a3
BH		 2368{
2369 struct pci_controller *hose = phb->hose;
2370 unsigned int residual, remaining, segs, tw, base;
2371 struct pnv_ioda_pe *pe;
2372
2373 /* If we have more PE# than segments available, hand out one
2374 * per PE until we run out and let the rest fail. If not,
2375 * then we assign at least one segment per PE, plus more based
2376 * on the amount of devices under that PE
2377 */
2378 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2379 residual = 0;
2380 else
2381 residual = phb->ioda.tce32_count -
2382 phb->ioda.dma_pe_count;
2383
2384 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2385 hose->global_number, phb->ioda.tce32_count);
2386 pr_info("PCI: %d PE# for a total weight of %d\n",
2387 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2388
5780fb04
AK		 2389 pnv_pci_ioda_setup_opal_tce_kill(phb);
2390
184cd4a3
BH		 2391 /* Walk our PE list and configure their DMA segments, hand them
2392 * out one base segment plus any residual segments based on
2393 * weight
2394 */
2395 remaining = phb->ioda.tce32_count;
2396 tw = phb->ioda.dma_weight;
2397 base = 0;
7ebdf956 2398 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
184cd4a3
BH		 2399 if (!pe->dma_weight)
2400 continue;
2401 if (!remaining) {
2402 pe_warn(pe, "No DMA32 resources available\n");
2403 continue;
2404 }
2405 segs = 1;
2406 if (residual) {
2407 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
2408 if (segs > remaining)
2409 segs = remaining;
2410 }
373f5657
GS		 2411
2412 /*
2413 * For IODA2 compliant PHB3, we needn't care about the weight.
2414 * The all available 32-bits DMA space will be assigned to
2415 * the specific PE.
2416 */
2417 if (phb->type == PNV_PHB_IODA1) {
2418 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2419 pe->dma_weight, segs);
2420 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
2421 } else {
2422 pe_info(pe, "Assign DMA32 space\n");
2423 segs = 0;
2424 pnv_pci_ioda2_setup_dma_pe(phb, pe);
2425 }
2426
184cd4a3
BH		 2427 remaining -= segs;
2428 base += segs;
2429 }
2430}
2431
2432#ifdef CONFIG_PCI_MSI
137436c9
GS		 2433static void pnv_ioda2_msi_eoi(struct irq_data *d)
2434{
2435 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2436 struct irq_chip *chip = irq_data_get_irq_chip(d);
2437 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2438 ioda.irq_chip);
2439 int64_t rc;
2440
2441 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2442 WARN_ON_ONCE(rc);
2443
2444 icp_native_eoi(d);
2445}
2446
fd9a1c26
IM		 2447
2448static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2449{
2450 struct irq_data *idata;
2451 struct irq_chip *ichip;
2452
2453 if (phb->type != PNV_PHB_IODA2)
2454 return;
2455
2456 if (!phb->ioda.irq_chip_init) {
2457 /*
2458 * First time we setup an MSI IRQ, we need to setup the
2459 * corresponding IRQ chip to route correctly.
2460 */
2461 idata = irq_get_irq_data(virq);
2462 ichip = irq_data_get_irq_chip(idata);
2463 phb->ioda.irq_chip_init = 1;
2464 phb->ioda.irq_chip = *ichip;
2465 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2466 }
2467 irq_set_chip(virq, &phb->ioda.irq_chip);
2468}
2469
80c49c7e
IM		 2470#ifdef CONFIG_CXL_BASE
2471
6f963ec2 2472struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
80c49c7e
IM		 2473{
2474 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2475
6f963ec2 2476 return of_node_get(hose->dn);
80c49c7e 2477}
6f963ec2 2478EXPORT_SYMBOL(pnv_pci_get_phb_node);
80c49c7e 2479
1212aa1c 2480int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
80c49c7e
IM		 2481{
2482 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2483 struct pnv_phb *phb = hose->private_data;
2484 struct pnv_ioda_pe *pe;
2485 int rc;
2486
2487 pe = pnv_ioda_get_pe(dev);
2488 if (!pe)
2489 return -ENODEV;
2490
2491 pe_info(pe, "Switching PHB to CXL\n");
2492
1212aa1c 2493 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
80c49c7e
IM		 2494 if (rc)
2495 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2496
2497 return rc;
2498}
1212aa1c 2499EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
80c49c7e
IM		 2500
2501/* Find PHB for cxl dev and allocate MSI hwirqs?
2502 * Returns the absolute hardware IRQ number
2503 */
2504int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2505{
2506 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2507 struct pnv_phb *phb = hose->private_data;
2508 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2509
2510 if (hwirq < 0) {
2511 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2512 return -ENOSPC;
2513 }
2514
2515 return phb->msi_base + hwirq;
2516}
2517EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2518
2519void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2520{
2521 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2522 struct pnv_phb *phb = hose->private_data;
2523
2524 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2525}
2526EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2527
2528void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2529 struct pci_dev *dev)
2530{
2531 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2532 struct pnv_phb *phb = hose->private_data;
2533 int i, hwirq;
2534
2535 for (i = 1; i < CXL_IRQ_RANGES; i++) {
2536 if (!irqs->range[i])
2537 continue;
2538 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2539 i, irqs->offset[i],
2540 irqs->range[i]);
2541 hwirq = irqs->offset[i] - phb->msi_base;
2542 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2543 irqs->range[i]);
2544 }
2545}
2546EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2547
2548int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2549 struct pci_dev *dev, int num)
2550{
2551 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2552 struct pnv_phb *phb = hose->private_data;
2553 int i, hwirq, try;
2554
2555 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2556
2557 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2558 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2559 try = num;
2560 while (try) {
2561 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2562 if (hwirq >= 0)
2563 break;
2564 try /= 2;
2565 }
2566 if (!try)
2567 goto fail;
2568
2569 irqs->offset[i] = phb->msi_base + hwirq;
2570 irqs->range[i] = try;
2571 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2572 i, irqs->offset[i], irqs->range[i]);
2573 num -= try;
2574 }
2575 if (num)
2576 goto fail;
2577
2578 return 0;
2579fail:
2580 pnv_cxl_release_hwirq_ranges(irqs, dev);
2581 return -ENOSPC;
2582}
2583EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2584
2585int pnv_cxl_get_irq_count(struct pci_dev *dev)
2586{
2587 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2588 struct pnv_phb *phb = hose->private_data;
2589
2590 return phb->msi_bmp.irq_count;
2591}
2592EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2593
2594int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2595 unsigned int virq)
2596{
2597 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2598 struct pnv_phb *phb = hose->private_data;
2599 unsigned int xive_num = hwirq - phb->msi_base;
2600 struct pnv_ioda_pe *pe;
2601 int rc;
2602
2603 if (!(pe = pnv_ioda_get_pe(dev)))
2604 return -ENODEV;
2605
2606 /* Assign XIVE to PE */
2607 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2608 if (rc) {
2609 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2610 "hwirq 0x%x XIVE 0x%x PE\n",
2611 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2612 return -EIO;
2613 }
2614 set_msi_irq_chip(phb, virq);
2615
2616 return 0;
2617}
2618EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2619#endif
2620
184cd4a3 2621static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
137436c9
GS		 2622 unsigned int hwirq, unsigned int virq,
2623 unsigned int is_64, struct msi_msg *msg)
184cd4a3
BH		 2624{
2625 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2626 unsigned int xive_num = hwirq - phb->msi_base;
3a1a4661 2627 __be32 data;
184cd4a3
BH		 2628 int rc;
2629
2630 /* No PE assigned ? bail out ... no MSI for you ! */
2631 if (pe == NULL)
2632 return -ENXIO;
2633
2634 /* Check if we have an MVE */
2635 if (pe->mve_number < 0)
2636 return -ENXIO;
2637
b72c1f65 2638 /* Force 32-bit MSI on some broken devices */
36074381 2639 if (dev->no_64bit_msi)
b72c1f65
BH		 2640 is_64 = 0;
2641
184cd4a3
BH		 2642 /* Assign XIVE to PE */
2643 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2644 if (rc) {
2645 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2646 pci_name(dev), rc, xive_num);
2647 return -EIO;
2648 }
2649
2650 if (is_64) {
3a1a4661
BH		 2651 __be64 addr64;
2652
184cd4a3
BH		 2653 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2654 &addr64, &data);
2655 if (rc) {
2656 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2657 pci_name(dev), rc);
2658 return -EIO;
2659 }
3a1a4661
BH		 2660 msg->address_hi = be64_to_cpu(addr64) >> 32;
2661 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
184cd4a3 2662 } else {
3a1a4661
BH		 2663 __be32 addr32;
2664
184cd4a3
BH		 2665 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2666 &addr32, &data);
2667 if (rc) {
2668 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2669 pci_name(dev), rc);
2670 return -EIO;
2671 }
2672 msg->address_hi = 0;
3a1a4661 2673 msg->address_lo = be32_to_cpu(addr32);
184cd4a3 2674 }
3a1a4661 2675 msg->data = be32_to_cpu(data);
184cd4a3 2676
fd9a1c26 2677 set_msi_irq_chip(phb, virq);
137436c9 2678
184cd4a3
BH		 2679 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2680 " address=%x_%08x data=%x PE# %d\n",
2681 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2682 msg->address_hi, msg->address_lo, data, pe->pe_number);
2683
2684 return 0;
2685}
2686
2687static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2688{
fb1b55d6 2689 unsigned int count;
184cd4a3
BH		 2690 const __be32 *prop = of_get_property(phb->hose->dn,
2691 "ibm,opal-msi-ranges", NULL);
2692 if (!prop) {
2693 /* BML Fallback */
2694 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2695 }
2696 if (!prop)
2697 return;
2698
2699 phb->msi_base = be32_to_cpup(prop);
fb1b55d6
GS		 2700 count = be32_to_cpup(prop + 1);
2701 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
184cd4a3
BH		 2702 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2703 phb->hose->global_number);
2704 return;
2705 }
fb1b55d6 2706
184cd4a3
BH		 2707 phb->msi_setup = pnv_pci_ioda_msi_setup;
2708 phb->msi32_support = 1;
2709 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
fb1b55d6 2710 count, phb->msi_base);
184cd4a3
BH		 2711}
2712#else
2713static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2714#endif /* CONFIG_PCI_MSI */
2715
6e628c7d
WY		 2716#ifdef CONFIG_PCI_IOV
2717static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2718{
2719 struct pci_controller *hose;
2720 struct pnv_phb *phb;
2721 struct resource *res;
2722 int i;
2723 resource_size_t size;
2724 struct pci_dn *pdn;
5b88ec22 2725 int mul, total_vfs;
6e628c7d
WY		 2726
2727 if (!pdev->is_physfn || pdev->is_added)
2728 return;
2729
2730 hose = pci_bus_to_host(pdev->bus);
2731 phb = hose->private_data;
2732
2733 pdn = pci_get_pdn(pdev);
2734 pdn->vfs_expanded = 0;
2735
5b88ec22
WY		 2736 total_vfs = pci_sriov_get_totalvfs(pdev);
2737 pdn->m64_per_iov = 1;
2738 mul = phb->ioda.total_pe;
2739
2740 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2741 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2742 if (!res->flags || res->parent)
2743 continue;
2744 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2745 dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2746 i, res);
2747 continue;
2748 }
2749
2750 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2751
2752 /* bigger than 64M */
2753 if (size > (1 << 26)) {
2754 dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2755 i, res);
2756 pdn->m64_per_iov = M64_PER_IOV;
2757 mul = roundup_pow_of_two(total_vfs);
2758 break;
2759 }
2760 }
2761
6e628c7d
WY		 2762 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2763 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2764 if (!res->flags || res->parent)
2765 continue;
2766 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2767 dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2768 i, res);
2769 continue;
2770 }
2771
2772 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2773 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
5b88ec22 2774 res->end = res->start + size * mul - 1;
6e628c7d
WY		 2775 dev_dbg(&pdev->dev, " %pR\n", res);
2776 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
5b88ec22 2777 i, res, mul);
6e628c7d 2778 }
5b88ec22 2779 pdn->vfs_expanded = mul;
6e628c7d
WY		 2780}
2781#endif /* CONFIG_PCI_IOV */
2782
11685bec
GS		 2783/*
2784 * This function is supposed to be called on basis of PE from top
2785 * to bottom style. So the the I/O or MMIO segment assigned to
2786 * parent PE could be overrided by its child PEs if necessary.
2787 */
cad5cef6
GKH		 2788static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2789 struct pnv_ioda_pe *pe)
11685bec
GS		 2790{
2791 struct pnv_phb *phb = hose->private_data;
2792 struct pci_bus_region region;
2793 struct resource *res;
2794 int i, index;
2795 int rc;
2796
2797 /*
2798 * NOTE: We only care PCI bus based PE for now. For PCI
2799 * device based PE, for example SRIOV sensitive VF should
2800 * be figured out later.
2801 */
2802 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2803
2804 pci_bus_for_each_resource(pe->pbus, res, i) {
2805 if (!res || !res->flags ||
2806 res->start > res->end)
2807 continue;
2808
2809 if (res->flags & IORESOURCE_IO) {
2810 region.start = res->start - phb->ioda.io_pci_base;
2811 region.end = res->end - phb->ioda.io_pci_base;
2812 index = region.start / phb->ioda.io_segsize;
2813
2814 while (index < phb->ioda.total_pe &&
2815 region.start <= region.end) {
2816 phb->ioda.io_segmap[index] = pe->pe_number;
2817 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2818 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2819 if (rc != OPAL_SUCCESS) {
2820 pr_err("%s: OPAL error %d when mapping IO "
2821 "segment #%d to PE#%d\n",
2822 __func__, rc, index, pe->pe_number);
2823 break;
2824 }
2825
2826 region.start += phb->ioda.io_segsize;
2827 index++;
2828 }
027fa02f
GS		 2829 } else if ((res->flags & IORESOURCE_MEM) &&
2830 !pnv_pci_is_mem_pref_64(res->flags)) {
11685bec 2831 region.start = res->start -
3fd47f06 2832 hose->mem_offset[0] -
11685bec
GS		 2833 phb->ioda.m32_pci_base;
2834 region.end = res->end -
3fd47f06 2835 hose->mem_offset[0] -
11685bec
GS		 2836 phb->ioda.m32_pci_base;
2837 index = region.start / phb->ioda.m32_segsize;
2838
2839 while (index < phb->ioda.total_pe &&
2840 region.start <= region.end) {
2841 phb->ioda.m32_segmap[index] = pe->pe_number;
2842 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2843 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2844 if (rc != OPAL_SUCCESS) {
2845 pr_err("%s: OPAL error %d when mapping M32 "
2846 "segment#%d to PE#%d",
2847 __func__, rc, index, pe->pe_number);
2848 break;
2849 }
2850
2851 region.start += phb->ioda.m32_segsize;
2852 index++;
2853 }
2854 }
2855 }
2856}
2857
cad5cef6 2858static void pnv_pci_ioda_setup_seg(void)
11685bec
GS		 2859{
2860 struct pci_controller *tmp, *hose;
2861 struct pnv_phb *phb;
2862 struct pnv_ioda_pe *pe;
2863
2864 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2865 phb = hose->private_data;
2866 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2867 pnv_ioda_setup_pe_seg(hose, pe);
2868 }
2869 }
2870}
2871
cad5cef6 2872static void pnv_pci_ioda_setup_DMA(void)
13395c48
GS		 2873{
2874 struct pci_controller *hose, *tmp;
db1266c8 2875 struct pnv_phb *phb;
13395c48
GS		 2876
2877 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2878 pnv_ioda_setup_dma(hose->private_data);
db1266c8
GS		 2879
2880 /* Mark the PHB initialization done */
2881 phb = hose->private_data;
2882 phb->initialized = 1;
13395c48
GS		 2883 }
2884}
2885
37c367f2
GS		 2886static void pnv_pci_ioda_create_dbgfs(void)
2887{
2888#ifdef CONFIG_DEBUG_FS
2889 struct pci_controller *hose, *tmp;
2890 struct pnv_phb *phb;
2891 char name[16];
2892
2893 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2894 phb = hose->private_data;
2895
2896 sprintf(name, "PCI%04x", hose->global_number);
2897 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2898 if (!phb->dbgfs)
2899 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2900 __func__, hose->global_number);
2901 }
2902#endif /* CONFIG_DEBUG_FS */
2903}
2904
cad5cef6 2905static void pnv_pci_ioda_fixup(void)
fb446ad0
GS		 2906{
2907 pnv_pci_ioda_setup_PEs();
11685bec 2908 pnv_pci_ioda_setup_seg();
13395c48 2909 pnv_pci_ioda_setup_DMA();
e9cc17d4 2910
37c367f2
GS		 2911 pnv_pci_ioda_create_dbgfs();
2912
e9cc17d4 2913#ifdef CONFIG_EEH
e9cc17d4 2914 eeh_init();
dadcd6d6 2915 eeh_addr_cache_build();
e9cc17d4 2916#endif
fb446ad0
GS		 2917}
2918
271fd03a
GS		 2919/*
2920 * Returns the alignment for I/O or memory windows for P2P
2921 * bridges. That actually depends on how PEs are segmented.
2922 * For now, we return I/O or M32 segment size for PE sensitive
2923 * P2P bridges. Otherwise, the default values (4KiB for I/O,
2924 * 1MiB for memory) will be returned.
2925 *
2926 * The current PCI bus might be put into one PE, which was
2927 * create against the parent PCI bridge. For that case, we
2928 * needn't enlarge the alignment so that we can save some
2929 * resources.
2930 */
2931static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2932 unsigned long type)
2933{
2934 struct pci_dev *bridge;
2935 struct pci_controller *hose = pci_bus_to_host(bus);
2936 struct pnv_phb *phb = hose->private_data;
2937 int num_pci_bridges = 0;
2938
2939 bridge = bus->self;
2940 while (bridge) {
2941 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2942 num_pci_bridges++;
2943 if (num_pci_bridges >= 2)
2944 return 1;
2945 }
2946
2947 bridge = bridge->bus->self;
2948 }
2949
262af557
GC		 2950 /* We fail back to M32 if M64 isn't supported */
2951 if (phb->ioda.m64_segsize &&
2952 pnv_pci_is_mem_pref_64(type))
2953 return phb->ioda.m64_segsize;
271fd03a
GS		 2954 if (type & IORESOURCE_MEM)
2955 return phb->ioda.m32_segsize;
2956
2957 return phb->ioda.io_segsize;
2958}
2959
5350ab3f
WY		 2960#ifdef CONFIG_PCI_IOV
2961static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
2962 int resno)
2963{
2964 struct pci_dn *pdn = pci_get_pdn(pdev);
2965 resource_size_t align, iov_align;
2966
2967 iov_align = resource_size(&pdev->resource[resno]);
2968 if (iov_align)
2969 return iov_align;
2970
2971 align = pci_iov_resource_size(pdev, resno);
2972 if (pdn->vfs_expanded)
2973 return pdn->vfs_expanded * align;
2974
2975 return align;
2976}
2977#endif /* CONFIG_PCI_IOV */
2978
184cd4a3
BH		 2979/* Prevent enabling devices for which we couldn't properly
2980 * assign a PE
2981 */
c88c2a18 2982static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
184cd4a3 2983{
db1266c8
GS		 2984 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2985 struct pnv_phb *phb = hose->private_data;
2986 struct pci_dn *pdn;
184cd4a3 2987
db1266c8
GS		 2988 /* The function is probably called while the PEs have
2989 * not be created yet. For example, resource reassignment
2990 * during PCI probe period. We just skip the check if
2991 * PEs isn't ready.
2992 */
2993 if (!phb->initialized)
c88c2a18 2994 return true;
db1266c8 2995
b72c1f65 2996 pdn = pci_get_pdn(dev);
184cd4a3 2997 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
c88c2a18 2998 return false;
db1266c8 2999
c88c2a18 3000 return true;
184cd4a3
BH		 3001}
3002
3003static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3004 u32 devfn)
3005{
3006 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3007}
3008
7a8e6bbf 3009static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
73ed148a 3010{
7a8e6bbf
MN		 3011 struct pnv_phb *phb = hose->private_data;
3012
d1a85eee 3013 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
73ed148a
BH		 3014 OPAL_ASSERT_RESET);
3015}
3016
92ae0353
DA		 3017static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3018 .dma_dev_setup = pnv_pci_dma_dev_setup,
3019#ifdef CONFIG_PCI_MSI
3020 .setup_msi_irqs = pnv_setup_msi_irqs,
3021 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3022#endif
3023 .enable_device_hook = pnv_pci_enable_device_hook,
3024 .window_alignment = pnv_pci_window_alignment,
3025 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
763d2d8d 3026 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
7a8e6bbf 3027 .shutdown = pnv_pci_ioda_shutdown,
92ae0353
DA		 3028};
3029
e51df2c1
AB		 3030static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3031 u64 hub_id, int ioda_type)
184cd4a3
BH		 3032{
3033 struct pci_controller *hose;
184cd4a3 3034 struct pnv_phb *phb;
8184616f 3035 unsigned long size, m32map_off, pemap_off, iomap_off = 0;
c681b93c 3036 const __be64 *prop64;
3a1a4661 3037 const __be32 *prop32;
f1b7cc3e 3038 int len;
184cd4a3
BH		 3039 u64 phb_id;
3040 void *aux;
3041 long rc;
3042
58d714ec 3043 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
184cd4a3
BH		 3044
3045 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3046 if (!prop64) {
3047 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3048 return;
3049 }
3050 phb_id = be64_to_cpup(prop64);
3051 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3052
e39f223f 3053 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
58d714ec
GS		 3054
3055 /* Allocate PCI controller */
58d714ec
GS		 3056 phb->hose = hose = pcibios_alloc_controller(np);
3057 if (!phb->hose) {
3058 pr_err(" Can't allocate PCI controller for %s\n",
184cd4a3 3059 np->full_name);
e39f223f 3060 memblock_free(__pa(phb), sizeof(struct pnv_phb));
184cd4a3
BH		 3061 return;
3062 }
3063
3064 spin_lock_init(&phb->lock);
f1b7cc3e
GS		 3065 prop32 = of_get_property(np, "bus-range", &len);
3066 if (prop32 && len == 8) {
3a1a4661
BH		 3067 hose->first_busno = be32_to_cpu(prop32[0]);
3068 hose->last_busno = be32_to_cpu(prop32[1]);
f1b7cc3e
GS		 3069 } else {
3070 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3071 hose->first_busno = 0;
3072 hose->last_busno = 0xff;
3073 }
184cd4a3 3074 hose->private_data = phb;
e9cc17d4 3075 phb->hub_id = hub_id;
184cd4a3 3076 phb->opal_id = phb_id;
aa0c033f 3077 phb->type = ioda_type;
781a868f 3078 mutex_init(&phb->ioda.pe_alloc_mutex);
184cd4a3 3079
cee72d5b
BH		 3080 /* Detect specific models for error handling */
3081 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3082 phb->model = PNV_PHB_MODEL_P7IOC;
f3d40c25 3083 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
aa0c033f 3084 phb->model = PNV_PHB_MODEL_PHB3;
cee72d5b
BH		 3085 else
3086 phb->model = PNV_PHB_MODEL_UNKNOWN;
3087
aa0c033f 3088 /* Parse 32-bit and IO ranges (if any) */
2f1ec02e 3089 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
184cd4a3 3090
aa0c033f 3091 /* Get registers */
184cd4a3
BH		 3092 phb->regs = of_iomap(np, 0);
3093 if (phb->regs == NULL)
3094 pr_err(" Failed to map registers !\n");
3095
184cd4a3 3096 /* Initialize more IODA stuff */
36954dc7 3097 phb->ioda.total_pe = 1;
aa0c033f 3098 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
36954dc7 3099 if (prop32)
3a1a4661 3100 phb->ioda.total_pe = be32_to_cpup(prop32);
36954dc7
GS		 3101 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3102 if (prop32)
3103 phb->ioda.reserved_pe = be32_to_cpup(prop32);
262af557
GC		 3104
3105 /* Parse 64-bit MMIO range */
3106 pnv_ioda_parse_m64_window(phb);
3107
184cd4a3 3108 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
aa0c033f 3109 /* FW Has already off top 64k of M32 space (MSI space) */
184cd4a3
BH		 3110 phb->ioda.m32_size += 0x10000;
3111
3112 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3fd47f06 3113 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
184cd4a3
BH		 3114 phb->ioda.io_size = hose->pci_io_size;
3115 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3116 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3117
c35d2a8c 3118 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
184cd4a3
BH		 3119 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3120 m32map_off = size;
e47747f4 3121 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
c35d2a8c
GS		 3122 if (phb->type == PNV_PHB_IODA1) {
3123 iomap_off = size;
3124 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3125 }
184cd4a3
BH		 3126 pemap_off = size;
3127 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
e39f223f 3128 aux = memblock_virt_alloc(size, 0);
184cd4a3
BH		 3129 phb->ioda.pe_alloc = aux;
3130 phb->ioda.m32_segmap = aux + m32map_off;
c35d2a8c
GS		 3131 if (phb->type == PNV_PHB_IODA1)
3132 phb->ioda.io_segmap = aux + iomap_off;
184cd4a3 3133 phb->ioda.pe_array = aux + pemap_off;
36954dc7 3134 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
184cd4a3 3135
7ebdf956 3136 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
184cd4a3 3137 INIT_LIST_HEAD(&phb->ioda.pe_list);
781a868f 3138 mutex_init(&phb->ioda.pe_list_mutex);
184cd4a3
BH		 3139
3140 /* Calculate how many 32-bit TCE segments we have */
3141 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3142
aa0c033f 3143#if 0 /* We should really do that ... */
184cd4a3
BH		 3144 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3145 window_type,
3146 window_num,
3147 starting_real_address,
3148 starting_pci_address,
3149 segment_size);
3150#endif
3151
262af557
GC		 3152 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3153 phb->ioda.total_pe, phb->ioda.reserved_pe,
3154 phb->ioda.m32_size, phb->ioda.m32_segsize);
3155 if (phb->ioda.m64_size)
3156 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3157 phb->ioda.m64_size, phb->ioda.m64_segsize);
3158 if (phb->ioda.io_size)
3159 pr_info(" IO: 0x%x [segment=0x%x]\n",
3160 phb->ioda.io_size, phb->ioda.io_segsize);
3161
184cd4a3 3162
184cd4a3 3163 phb->hose->ops = &pnv_pci_ops;
49dec922
GS		 3164 phb->get_pe_state = pnv_ioda_get_pe_state;
3165 phb->freeze_pe = pnv_ioda_freeze_pe;
3166 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
184cd4a3
BH		 3167
3168 /* Setup RID -> PE mapping function */
3169 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3170
3171 /* Setup TCEs */
3172 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
fe7e85c6 3173 phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask;
184cd4a3
BH		 3174
3175 /* Setup MSI support */
3176 pnv_pci_init_ioda_msis(phb);
3177
c40a4210
GS		 3178 /*
3179 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3180 * to let the PCI core do resource assignment. It's supposed
3181 * that the PCI core will do correct I/O and MMIO alignment
3182 * for the P2P bridge bars so that each PCI bus (excluding
3183 * the child P2P bridges) can form individual PE.
184cd4a3 3184 */
fb446ad0 3185 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
92ae0353 3186 hose->controller_ops = pnv_pci_ioda_controller_ops;
ad30cb99 3187
6e628c7d
WY		 3188#ifdef CONFIG_PCI_IOV
3189 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
5350ab3f 3190 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
ad30cb99
ME		 3191#endif
3192
c40a4210 3193 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
184cd4a3
BH		 3194
3195 /* Reset IODA tables to a clean state */
d1a85eee 3196 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
184cd4a3 3197 if (rc)
f11fe552 3198 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
361f2a2a
GS		 3199
3200 /* If we're running in kdump kerenl, the previous kerenl never
3201 * shutdown PCI devices correctly. We already got IODA table
3202 * cleaned out. So we have to issue PHB reset to stop all PCI
3203 * transactions from previous kerenl.
3204 */
3205 if (is_kdump_kernel()) {
3206 pr_info(" Issue PHB reset ...\n");
cadf364d
GS		 3207 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3208 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
361f2a2a 3209 }
262af557 3210
9e9e8935
GS		 3211 /* Remove M64 resource if we can't configure it successfully */
3212 if (!phb->init_m64 || phb->init_m64(phb))
262af557 3213 hose->mem_resources[1].flags = 0;
aa0c033f
GS		 3214}
3215
67975005 3216void __init pnv_pci_init_ioda2_phb(struct device_node *np)
aa0c033f 3217{
e9cc17d4 3218 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
184cd4a3
BH		 3219}
3220
3221void __init pnv_pci_init_ioda_hub(struct device_node *np)
3222{
3223 struct device_node *phbn;
c681b93c 3224 const __be64 *prop64;
184cd4a3
BH		 3225 u64 hub_id;
3226
3227 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3228
3229 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3230 if (!prop64) {
3231 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3232 return;
3233 }
3234 hub_id = be64_to_cpup(prop64);
3235 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3236
3237 /* Count child PHBs */
3238 for_each_child_of_node(np, phbn) {
3239 /* Look for IODA1 PHBs */
3240 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
e9cc17d4 3241 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
184cd4a3
BH		 3242 }
3243}
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