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184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
361f2a2a | 16 | #include <linux/crash_dump.h> |
37c367f2 | 17 | #include <linux/debugfs.h> |
184cd4a3 BH |
18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/msi.h> | |
cd15b048 | 25 | #include <linux/memblock.h> |
ac9a5889 | 26 | #include <linux/iommu.h> |
e57080f1 | 27 | #include <linux/rculist.h> |
4793d65d | 28 | #include <linux/sizes.h> |
184cd4a3 BH |
29 | |
30 | #include <asm/sections.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/pci-bridge.h> | |
34 | #include <asm/machdep.h> | |
fb1b55d6 | 35 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
36 | #include <asm/ppc-pci.h> |
37 | #include <asm/opal.h> | |
38 | #include <asm/iommu.h> | |
39 | #include <asm/tce.h> | |
137436c9 | 40 | #include <asm/xics.h> |
37c367f2 | 41 | #include <asm/debug.h> |
262af557 | 42 | #include <asm/firmware.h> |
80c49c7e | 43 | #include <asm/pnv-pci.h> |
aca6913f | 44 | #include <asm/mmzone.h> |
80c49c7e | 45 | |
ec249dd8 | 46 | #include <misc/cxl-base.h> |
184cd4a3 BH |
47 | |
48 | #include "powernv.h" | |
49 | #include "pci.h" | |
50 | ||
99451551 GS |
51 | #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ |
52 | #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ | |
53 | ||
781a868f WY |
54 | /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ |
55 | #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) | |
56 | ||
bbb845c4 AK |
57 | #define POWERNV_IOMMU_DEFAULT_LEVELS 1 |
58 | #define POWERNV_IOMMU_MAX_LEVELS 5 | |
59 | ||
aca6913f AK |
60 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); |
61 | ||
6d31c2fa JP |
62 | static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
63 | const char *fmt, ...) | |
64 | { | |
65 | struct va_format vaf; | |
66 | va_list args; | |
67 | char pfix[32]; | |
68 | ||
69 | va_start(args, fmt); | |
70 | ||
71 | vaf.fmt = fmt; | |
72 | vaf.va = &args; | |
73 | ||
781a868f | 74 | if (pe->flags & PNV_IODA_PE_DEV) |
6d31c2fa | 75 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
781a868f | 76 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
6d31c2fa JP |
77 | sprintf(pfix, "%04x:%02x ", |
78 | pci_domain_nr(pe->pbus), pe->pbus->number); | |
781a868f WY |
79 | #ifdef CONFIG_PCI_IOV |
80 | else if (pe->flags & PNV_IODA_PE_VF) | |
81 | sprintf(pfix, "%04x:%02x:%2x.%d", | |
82 | pci_domain_nr(pe->parent_dev->bus), | |
83 | (pe->rid & 0xff00) >> 8, | |
84 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); | |
85 | #endif /* CONFIG_PCI_IOV*/ | |
6d31c2fa JP |
86 | |
87 | printk("%spci %s: [PE# %.3d] %pV", | |
88 | level, pfix, pe->pe_number, &vaf); | |
89 | ||
90 | va_end(args); | |
91 | } | |
184cd4a3 | 92 | |
6d31c2fa JP |
93 | #define pe_err(pe, fmt, ...) \ |
94 | pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) | |
95 | #define pe_warn(pe, fmt, ...) \ | |
96 | pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) | |
97 | #define pe_info(pe, fmt, ...) \ | |
98 | pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) | |
184cd4a3 | 99 | |
4e287840 TLSC |
100 | static bool pnv_iommu_bypass_disabled __read_mostly; |
101 | ||
102 | static int __init iommu_setup(char *str) | |
103 | { | |
104 | if (!str) | |
105 | return -EINVAL; | |
106 | ||
107 | while (*str) { | |
108 | if (!strncmp(str, "nobypass", 8)) { | |
109 | pnv_iommu_bypass_disabled = true; | |
110 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); | |
111 | break; | |
112 | } | |
113 | str += strcspn(str, ","); | |
114 | if (*str == ',') | |
115 | str++; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | early_param("iommu", iommu_setup); | |
121 | ||
262af557 GC |
122 | static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) |
123 | { | |
124 | return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == | |
125 | (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); | |
126 | } | |
127 | ||
4b82ab18 GS |
128 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
129 | { | |
92b8f137 | 130 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { |
4b82ab18 GS |
131 | pr_warn("%s: Invalid PE %d on PHB#%x\n", |
132 | __func__, pe_no, phb->hose->global_number); | |
133 | return; | |
134 | } | |
135 | ||
e9dc4d7f GS |
136 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) |
137 | pr_debug("%s: PE %d was reserved on PHB#%x\n", | |
138 | __func__, pe_no, phb->hose->global_number); | |
4b82ab18 GS |
139 | |
140 | phb->ioda.pe_array[pe_no].phb = phb; | |
141 | phb->ioda.pe_array[pe_no].pe_number = pe_no; | |
142 | } | |
143 | ||
689ee8c9 | 144 | static unsigned int pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 BH |
145 | { |
146 | unsigned long pe; | |
147 | ||
148 | do { | |
149 | pe = find_next_zero_bit(phb->ioda.pe_alloc, | |
92b8f137 GS |
150 | phb->ioda.total_pe_num, 0); |
151 | if (pe >= phb->ioda.total_pe_num) | |
184cd4a3 BH |
152 | return IODA_INVALID_PE; |
153 | } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); | |
154 | ||
4cce9550 | 155 | phb->ioda.pe_array[pe].phb = phb; |
184cd4a3 BH |
156 | phb->ioda.pe_array[pe].pe_number = pe; |
157 | return pe; | |
158 | } | |
159 | ||
cad5cef6 | 160 | static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) |
184cd4a3 BH |
161 | { |
162 | WARN_ON(phb->ioda.pe_array[pe].pdev); | |
163 | ||
164 | memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); | |
165 | clear_bit(pe, phb->ioda.pe_alloc); | |
166 | } | |
167 | ||
262af557 GC |
168 | /* The default M64 BAR is shared by all PEs */ |
169 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) | |
170 | { | |
171 | const char *desc; | |
172 | struct resource *r; | |
173 | s64 rc; | |
174 | ||
175 | /* Configure the default M64 BAR */ | |
176 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
177 | OPAL_M64_WINDOW_TYPE, | |
178 | phb->ioda.m64_bar_idx, | |
179 | phb->ioda.m64_base, | |
180 | 0, /* unused */ | |
181 | phb->ioda.m64_size); | |
182 | if (rc != OPAL_SUCCESS) { | |
183 | desc = "configuring"; | |
184 | goto fail; | |
185 | } | |
186 | ||
187 | /* Enable the default M64 BAR */ | |
188 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
189 | OPAL_M64_WINDOW_TYPE, | |
190 | phb->ioda.m64_bar_idx, | |
191 | OPAL_ENABLE_M64_SPLIT); | |
192 | if (rc != OPAL_SUCCESS) { | |
193 | desc = "enabling"; | |
194 | goto fail; | |
195 | } | |
196 | ||
197 | /* Mark the M64 BAR assigned */ | |
198 | set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); | |
199 | ||
200 | /* | |
201 | * Strip off the segment used by the reserved PE, which is | |
202 | * expected to be 0 or last one of PE capabicity. | |
203 | */ | |
204 | r = &phb->hose->mem_resources[1]; | |
92b8f137 | 205 | if (phb->ioda.reserved_pe_idx == 0) |
262af557 | 206 | r->start += phb->ioda.m64_segsize; |
92b8f137 | 207 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
262af557 GC |
208 | r->end -= phb->ioda.m64_segsize; |
209 | else | |
210 | pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", | |
92b8f137 | 211 | phb->ioda.reserved_pe_idx); |
262af557 GC |
212 | |
213 | return 0; | |
214 | ||
215 | fail: | |
216 | pr_warn(" Failure %lld %s M64 BAR#%d\n", | |
217 | rc, desc, phb->ioda.m64_bar_idx); | |
218 | opal_pci_phb_mmio_enable(phb->opal_id, | |
219 | OPAL_M64_WINDOW_TYPE, | |
220 | phb->ioda.m64_bar_idx, | |
221 | OPAL_DISABLE_M64); | |
222 | return -EIO; | |
223 | } | |
224 | ||
c430670a | 225 | static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, |
96a2f92b | 226 | unsigned long *pe_bitmap) |
262af557 | 227 | { |
96a2f92b GS |
228 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
229 | struct pnv_phb *phb = hose->private_data; | |
262af557 | 230 | struct resource *r; |
96a2f92b GS |
231 | resource_size_t base, sgsz, start, end; |
232 | int segno, i; | |
233 | ||
234 | base = phb->ioda.m64_base; | |
235 | sgsz = phb->ioda.m64_segsize; | |
236 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
237 | r = &pdev->resource[i]; | |
238 | if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) | |
239 | continue; | |
262af557 | 240 | |
96a2f92b GS |
241 | start = _ALIGN_DOWN(r->start - base, sgsz); |
242 | end = _ALIGN_UP(r->end - base, sgsz); | |
243 | for (segno = start / sgsz; segno < end / sgsz; segno++) { | |
244 | if (pe_bitmap) | |
245 | set_bit(segno, pe_bitmap); | |
246 | else | |
247 | pnv_ioda_reserve_pe(phb, segno); | |
262af557 GC |
248 | } |
249 | } | |
250 | } | |
251 | ||
99451551 GS |
252 | static int pnv_ioda1_init_m64(struct pnv_phb *phb) |
253 | { | |
254 | struct resource *r; | |
255 | int index; | |
256 | ||
257 | /* | |
258 | * There are 16 M64 BARs, each of which has 8 segments. So | |
259 | * there are as many M64 segments as the maximum number of | |
260 | * PEs, which is 128. | |
261 | */ | |
262 | for (index = 0; index < PNV_IODA1_M64_NUM; index++) { | |
263 | unsigned long base, segsz = phb->ioda.m64_segsize; | |
264 | int64_t rc; | |
265 | ||
266 | base = phb->ioda.m64_base + | |
267 | index * PNV_IODA1_M64_SEGS * segsz; | |
268 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
269 | OPAL_M64_WINDOW_TYPE, index, base, 0, | |
270 | PNV_IODA1_M64_SEGS * segsz); | |
271 | if (rc != OPAL_SUCCESS) { | |
272 | pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", | |
273 | rc, phb->hose->global_number, index); | |
274 | goto fail; | |
275 | } | |
276 | ||
277 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
278 | OPAL_M64_WINDOW_TYPE, index, | |
279 | OPAL_ENABLE_M64_SPLIT); | |
280 | if (rc != OPAL_SUCCESS) { | |
281 | pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", | |
282 | rc, phb->hose->global_number, index); | |
283 | goto fail; | |
284 | } | |
285 | } | |
286 | ||
287 | /* | |
288 | * Exclude the segment used by the reserved PE, which | |
289 | * is expected to be 0 or last supported PE#. | |
290 | */ | |
291 | r = &phb->hose->mem_resources[1]; | |
292 | if (phb->ioda.reserved_pe_idx == 0) | |
293 | r->start += phb->ioda.m64_segsize; | |
294 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) | |
295 | r->end -= phb->ioda.m64_segsize; | |
296 | else | |
297 | WARN(1, "Wrong reserved PE#%d on PHB#%d\n", | |
298 | phb->ioda.reserved_pe_idx, phb->hose->global_number); | |
299 | ||
300 | return 0; | |
301 | ||
302 | fail: | |
303 | for ( ; index >= 0; index--) | |
304 | opal_pci_phb_mmio_enable(phb->opal_id, | |
305 | OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); | |
306 | ||
307 | return -EIO; | |
308 | } | |
309 | ||
c430670a GS |
310 | static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, |
311 | unsigned long *pe_bitmap, | |
312 | bool all) | |
262af557 | 313 | { |
262af557 | 314 | struct pci_dev *pdev; |
96a2f92b GS |
315 | |
316 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
c430670a | 317 | pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); |
96a2f92b GS |
318 | |
319 | if (all && pdev->subordinate) | |
c430670a GS |
320 | pnv_ioda_reserve_m64_pe(pdev->subordinate, |
321 | pe_bitmap, all); | |
96a2f92b GS |
322 | } |
323 | } | |
324 | ||
c430670a | 325 | static unsigned int pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) |
262af557 | 326 | { |
26ba248d GS |
327 | struct pci_controller *hose = pci_bus_to_host(bus); |
328 | struct pnv_phb *phb = hose->private_data; | |
262af557 GC |
329 | struct pnv_ioda_pe *master_pe, *pe; |
330 | unsigned long size, *pe_alloc; | |
26ba248d | 331 | int i; |
262af557 GC |
332 | |
333 | /* Root bus shouldn't use M64 */ | |
334 | if (pci_is_root_bus(bus)) | |
335 | return IODA_INVALID_PE; | |
336 | ||
262af557 | 337 | /* Allocate bitmap */ |
92b8f137 | 338 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
262af557 GC |
339 | pe_alloc = kzalloc(size, GFP_KERNEL); |
340 | if (!pe_alloc) { | |
341 | pr_warn("%s: Out of memory !\n", | |
342 | __func__); | |
343 | return IODA_INVALID_PE; | |
344 | } | |
345 | ||
26ba248d | 346 | /* Figure out reserved PE numbers by the PE */ |
c430670a | 347 | pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); |
262af557 GC |
348 | |
349 | /* | |
350 | * the current bus might not own M64 window and that's all | |
351 | * contributed by its child buses. For the case, we needn't | |
352 | * pick M64 dependent PE#. | |
353 | */ | |
92b8f137 | 354 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { |
262af557 GC |
355 | kfree(pe_alloc); |
356 | return IODA_INVALID_PE; | |
357 | } | |
358 | ||
359 | /* | |
360 | * Figure out the master PE and put all slave PEs to master | |
361 | * PE's list to form compound PE. | |
362 | */ | |
262af557 GC |
363 | master_pe = NULL; |
364 | i = -1; | |
92b8f137 GS |
365 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < |
366 | phb->ioda.total_pe_num) { | |
262af557 | 367 | pe = &phb->ioda.pe_array[i]; |
262af557 | 368 | |
93289d8c | 369 | phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; |
262af557 GC |
370 | if (!master_pe) { |
371 | pe->flags |= PNV_IODA_PE_MASTER; | |
372 | INIT_LIST_HEAD(&pe->slaves); | |
373 | master_pe = pe; | |
374 | } else { | |
375 | pe->flags |= PNV_IODA_PE_SLAVE; | |
376 | pe->master = master_pe; | |
377 | list_add_tail(&pe->list, &master_pe->slaves); | |
378 | } | |
99451551 GS |
379 | |
380 | /* | |
381 | * P7IOC supports M64DT, which helps mapping M64 segment | |
382 | * to one particular PE#. However, PHB3 has fixed mapping | |
383 | * between M64 segment and PE#. In order to have same logic | |
384 | * for P7IOC and PHB3, we enforce fixed mapping between M64 | |
385 | * segment and PE# on P7IOC. | |
386 | */ | |
387 | if (phb->type == PNV_PHB_IODA1) { | |
388 | int64_t rc; | |
389 | ||
390 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
391 | pe->pe_number, OPAL_M64_WINDOW_TYPE, | |
392 | pe->pe_number / PNV_IODA1_M64_SEGS, | |
393 | pe->pe_number % PNV_IODA1_M64_SEGS); | |
394 | if (rc != OPAL_SUCCESS) | |
395 | pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", | |
396 | __func__, rc, phb->hose->global_number, | |
397 | pe->pe_number); | |
398 | } | |
262af557 GC |
399 | } |
400 | ||
401 | kfree(pe_alloc); | |
402 | return master_pe->pe_number; | |
403 | } | |
404 | ||
405 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) | |
406 | { | |
407 | struct pci_controller *hose = phb->hose; | |
408 | struct device_node *dn = hose->dn; | |
409 | struct resource *res; | |
410 | const u32 *r; | |
411 | u64 pci_addr; | |
412 | ||
99451551 | 413 | if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { |
1665c4a8 GS |
414 | pr_info(" Not support M64 window\n"); |
415 | return; | |
416 | } | |
417 | ||
e4d54f71 | 418 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
262af557 GC |
419 | pr_info(" Firmware too old to support M64 window\n"); |
420 | return; | |
421 | } | |
422 | ||
423 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); | |
424 | if (!r) { | |
425 | pr_info(" No <ibm,opal-m64-window> on %s\n", | |
426 | dn->full_name); | |
427 | return; | |
428 | } | |
429 | ||
262af557 | 430 | res = &hose->mem_resources[1]; |
e80c4e7c | 431 | res->name = dn->full_name; |
262af557 GC |
432 | res->start = of_translate_address(dn, r + 2); |
433 | res->end = res->start + of_read_number(r + 4, 2) - 1; | |
434 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
435 | pci_addr = of_read_number(r, 2); | |
436 | hose->mem_offset[1] = res->start - pci_addr; | |
437 | ||
438 | phb->ioda.m64_size = resource_size(res); | |
92b8f137 | 439 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; |
262af557 GC |
440 | phb->ioda.m64_base = pci_addr; |
441 | ||
e9863e68 WY |
442 | pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", |
443 | res->start, res->end, pci_addr); | |
444 | ||
262af557 GC |
445 | /* Use last M64 BAR to cover M64 window */ |
446 | phb->ioda.m64_bar_idx = 15; | |
99451551 GS |
447 | if (phb->type == PNV_PHB_IODA1) |
448 | phb->init_m64 = pnv_ioda1_init_m64; | |
449 | else | |
450 | phb->init_m64 = pnv_ioda2_init_m64; | |
c430670a GS |
451 | phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; |
452 | phb->pick_m64_pe = pnv_ioda_pick_m64_pe; | |
262af557 GC |
453 | } |
454 | ||
49dec922 GS |
455 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
456 | { | |
457 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; | |
458 | struct pnv_ioda_pe *slave; | |
459 | s64 rc; | |
460 | ||
461 | /* Fetch master PE */ | |
462 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
463 | pe = pe->master; | |
ec8e4e9d GS |
464 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
465 | return; | |
466 | ||
49dec922 GS |
467 | pe_no = pe->pe_number; |
468 | } | |
469 | ||
470 | /* Freeze master PE */ | |
471 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
472 | pe_no, | |
473 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
474 | if (rc != OPAL_SUCCESS) { | |
475 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
476 | __func__, rc, phb->hose->global_number, pe_no); | |
477 | return; | |
478 | } | |
479 | ||
480 | /* Freeze slave PEs */ | |
481 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
482 | return; | |
483 | ||
484 | list_for_each_entry(slave, &pe->slaves, list) { | |
485 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
486 | slave->pe_number, | |
487 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
488 | if (rc != OPAL_SUCCESS) | |
489 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
490 | __func__, rc, phb->hose->global_number, | |
491 | slave->pe_number); | |
492 | } | |
493 | } | |
494 | ||
e51df2c1 | 495 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
49dec922 GS |
496 | { |
497 | struct pnv_ioda_pe *pe, *slave; | |
498 | s64 rc; | |
499 | ||
500 | /* Find master PE */ | |
501 | pe = &phb->ioda.pe_array[pe_no]; | |
502 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
503 | pe = pe->master; | |
504 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
505 | pe_no = pe->pe_number; | |
506 | } | |
507 | ||
508 | /* Clear frozen state for master PE */ | |
509 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); | |
510 | if (rc != OPAL_SUCCESS) { | |
511 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
512 | __func__, rc, opt, phb->hose->global_number, pe_no); | |
513 | return -EIO; | |
514 | } | |
515 | ||
516 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
517 | return 0; | |
518 | ||
519 | /* Clear frozen state for slave PEs */ | |
520 | list_for_each_entry(slave, &pe->slaves, list) { | |
521 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
522 | slave->pe_number, | |
523 | opt); | |
524 | if (rc != OPAL_SUCCESS) { | |
525 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
526 | __func__, rc, opt, phb->hose->global_number, | |
527 | slave->pe_number); | |
528 | return -EIO; | |
529 | } | |
530 | } | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) | |
536 | { | |
537 | struct pnv_ioda_pe *slave, *pe; | |
538 | u8 fstate, state; | |
539 | __be16 pcierr; | |
540 | s64 rc; | |
541 | ||
542 | /* Sanity check on PE number */ | |
92b8f137 | 543 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) |
49dec922 GS |
544 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; |
545 | ||
546 | /* | |
547 | * Fetch the master PE and the PE instance might be | |
548 | * not initialized yet. | |
549 | */ | |
550 | pe = &phb->ioda.pe_array[pe_no]; | |
551 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
552 | pe = pe->master; | |
553 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
554 | pe_no = pe->pe_number; | |
555 | } | |
556 | ||
557 | /* Check the master PE */ | |
558 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, | |
559 | &state, &pcierr, NULL); | |
560 | if (rc != OPAL_SUCCESS) { | |
561 | pr_warn("%s: Failure %lld getting " | |
562 | "PHB#%x-PE#%x state\n", | |
563 | __func__, rc, | |
564 | phb->hose->global_number, pe_no); | |
565 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
566 | } | |
567 | ||
568 | /* Check the slave PE */ | |
569 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
570 | return state; | |
571 | ||
572 | list_for_each_entry(slave, &pe->slaves, list) { | |
573 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
574 | slave->pe_number, | |
575 | &fstate, | |
576 | &pcierr, | |
577 | NULL); | |
578 | if (rc != OPAL_SUCCESS) { | |
579 | pr_warn("%s: Failure %lld getting " | |
580 | "PHB#%x-PE#%x state\n", | |
581 | __func__, rc, | |
582 | phb->hose->global_number, slave->pe_number); | |
583 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
584 | } | |
585 | ||
586 | /* | |
587 | * Override the result based on the ascending | |
588 | * priority. | |
589 | */ | |
590 | if (fstate > state) | |
591 | state = fstate; | |
592 | } | |
593 | ||
594 | return state; | |
595 | } | |
596 | ||
184cd4a3 BH |
597 | /* Currently those 2 are only used when MSIs are enabled, this will change |
598 | * but in the meantime, we need to protect them to avoid warnings | |
599 | */ | |
600 | #ifdef CONFIG_PCI_MSI | |
cad5cef6 | 601 | static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
602 | { |
603 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
604 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 605 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
606 | |
607 | if (!pdn) | |
608 | return NULL; | |
609 | if (pdn->pe_number == IODA_INVALID_PE) | |
610 | return NULL; | |
611 | return &phb->ioda.pe_array[pdn->pe_number]; | |
612 | } | |
184cd4a3 BH |
613 | #endif /* CONFIG_PCI_MSI */ |
614 | ||
b131a842 GS |
615 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
616 | struct pnv_ioda_pe *parent, | |
617 | struct pnv_ioda_pe *child, | |
618 | bool is_add) | |
619 | { | |
620 | const char *desc = is_add ? "adding" : "removing"; | |
621 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : | |
622 | OPAL_REMOVE_PE_FROM_DOMAIN; | |
623 | struct pnv_ioda_pe *slave; | |
624 | long rc; | |
625 | ||
626 | /* Parent PE affects child PE */ | |
627 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
628 | child->pe_number, op); | |
629 | if (rc != OPAL_SUCCESS) { | |
630 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", | |
631 | rc, desc); | |
632 | return -ENXIO; | |
633 | } | |
634 | ||
635 | if (!(child->flags & PNV_IODA_PE_MASTER)) | |
636 | return 0; | |
637 | ||
638 | /* Compound case: parent PE affects slave PEs */ | |
639 | list_for_each_entry(slave, &child->slaves, list) { | |
640 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
641 | slave->pe_number, op); | |
642 | if (rc != OPAL_SUCCESS) { | |
643 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", | |
644 | rc, desc); | |
645 | return -ENXIO; | |
646 | } | |
647 | } | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |
653 | struct pnv_ioda_pe *pe, | |
654 | bool is_add) | |
655 | { | |
656 | struct pnv_ioda_pe *slave; | |
781a868f | 657 | struct pci_dev *pdev = NULL; |
b131a842 GS |
658 | int ret; |
659 | ||
660 | /* | |
661 | * Clear PE frozen state. If it's master PE, we need | |
662 | * clear slave PE frozen state as well. | |
663 | */ | |
664 | if (is_add) { | |
665 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, | |
666 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
667 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
668 | list_for_each_entry(slave, &pe->slaves, list) | |
669 | opal_pci_eeh_freeze_clear(phb->opal_id, | |
670 | slave->pe_number, | |
671 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
672 | } | |
673 | } | |
674 | ||
675 | /* | |
676 | * Associate PE in PELT. We need add the PE into the | |
677 | * corresponding PELT-V as well. Otherwise, the error | |
678 | * originated from the PE might contribute to other | |
679 | * PEs. | |
680 | */ | |
681 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); | |
682 | if (ret) | |
683 | return ret; | |
684 | ||
685 | /* For compound PEs, any one affects all of them */ | |
686 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
687 | list_for_each_entry(slave, &pe->slaves, list) { | |
688 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); | |
689 | if (ret) | |
690 | return ret; | |
691 | } | |
692 | } | |
693 | ||
694 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) | |
695 | pdev = pe->pbus->self; | |
781a868f | 696 | else if (pe->flags & PNV_IODA_PE_DEV) |
b131a842 | 697 | pdev = pe->pdev->bus->self; |
781a868f WY |
698 | #ifdef CONFIG_PCI_IOV |
699 | else if (pe->flags & PNV_IODA_PE_VF) | |
283e2d8a | 700 | pdev = pe->parent_dev; |
781a868f | 701 | #endif /* CONFIG_PCI_IOV */ |
b131a842 GS |
702 | while (pdev) { |
703 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
704 | struct pnv_ioda_pe *parent; | |
705 | ||
706 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
707 | parent = &phb->ioda.pe_array[pdn->pe_number]; | |
708 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); | |
709 | if (ret) | |
710 | return ret; | |
711 | } | |
712 | ||
713 | pdev = pdev->bus->self; | |
714 | } | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
781a868f WY |
719 | #ifdef CONFIG_PCI_IOV |
720 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) | |
721 | { | |
722 | struct pci_dev *parent; | |
723 | uint8_t bcomp, dcomp, fcomp; | |
724 | int64_t rc; | |
725 | long rid_end, rid; | |
726 | ||
727 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ | |
728 | if (pe->pbus) { | |
729 | int count; | |
730 | ||
731 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
732 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
733 | parent = pe->pbus->self; | |
734 | if (pe->flags & PNV_IODA_PE_BUS_ALL) | |
735 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
736 | else | |
737 | count = 1; | |
738 | ||
739 | switch(count) { | |
740 | case 1: bcomp = OpalPciBusAll; break; | |
741 | case 2: bcomp = OpalPciBus7Bits; break; | |
742 | case 4: bcomp = OpalPciBus6Bits; break; | |
743 | case 8: bcomp = OpalPciBus5Bits; break; | |
744 | case 16: bcomp = OpalPciBus4Bits; break; | |
745 | case 32: bcomp = OpalPciBus3Bits; break; | |
746 | default: | |
747 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", | |
748 | count); | |
749 | /* Do an exact match only */ | |
750 | bcomp = OpalPciBusAll; | |
751 | } | |
752 | rid_end = pe->rid + (count << 8); | |
753 | } else { | |
754 | if (pe->flags & PNV_IODA_PE_VF) | |
755 | parent = pe->parent_dev; | |
756 | else | |
757 | parent = pe->pdev->bus->self; | |
758 | bcomp = OpalPciBusAll; | |
759 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
760 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
761 | rid_end = pe->rid + 1; | |
762 | } | |
763 | ||
764 | /* Clear the reverse map */ | |
765 | for (rid = pe->rid; rid < rid_end; rid++) | |
766 | phb->ioda.pe_rmap[rid] = 0; | |
767 | ||
768 | /* Release from all parents PELT-V */ | |
769 | while (parent) { | |
770 | struct pci_dn *pdn = pci_get_pdn(parent); | |
771 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
772 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
773 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
774 | /* XXX What to do in case of error ? */ | |
775 | } | |
776 | parent = parent->bus->self; | |
777 | } | |
778 | ||
f951e510 | 779 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
781a868f WY |
780 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
781 | ||
782 | /* Disassociate PE in PELT */ | |
783 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
784 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
785 | if (rc) | |
786 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); | |
787 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, | |
788 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); | |
789 | if (rc) | |
790 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
791 | ||
792 | pe->pbus = NULL; | |
793 | pe->pdev = NULL; | |
794 | pe->parent_dev = NULL; | |
795 | ||
796 | return 0; | |
797 | } | |
798 | #endif /* CONFIG_PCI_IOV */ | |
799 | ||
cad5cef6 | 800 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
801 | { |
802 | struct pci_dev *parent; | |
803 | uint8_t bcomp, dcomp, fcomp; | |
804 | long rc, rid_end, rid; | |
805 | ||
806 | /* Bus validation ? */ | |
807 | if (pe->pbus) { | |
808 | int count; | |
809 | ||
810 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
811 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
812 | parent = pe->pbus->self; | |
fb446ad0 GS |
813 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
814 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
815 | else | |
816 | count = 1; | |
817 | ||
184cd4a3 BH |
818 | switch(count) { |
819 | case 1: bcomp = OpalPciBusAll; break; | |
820 | case 2: bcomp = OpalPciBus7Bits; break; | |
821 | case 4: bcomp = OpalPciBus6Bits; break; | |
822 | case 8: bcomp = OpalPciBus5Bits; break; | |
823 | case 16: bcomp = OpalPciBus4Bits; break; | |
824 | case 32: bcomp = OpalPciBus3Bits; break; | |
825 | default: | |
781a868f WY |
826 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
827 | count); | |
184cd4a3 BH |
828 | /* Do an exact match only */ |
829 | bcomp = OpalPciBusAll; | |
830 | } | |
831 | rid_end = pe->rid + (count << 8); | |
832 | } else { | |
781a868f WY |
833 | #ifdef CONFIG_PCI_IOV |
834 | if (pe->flags & PNV_IODA_PE_VF) | |
835 | parent = pe->parent_dev; | |
836 | else | |
837 | #endif /* CONFIG_PCI_IOV */ | |
838 | parent = pe->pdev->bus->self; | |
184cd4a3 BH |
839 | bcomp = OpalPciBusAll; |
840 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
841 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
842 | rid_end = pe->rid + 1; | |
843 | } | |
844 | ||
631ad691 GS |
845 | /* |
846 | * Associate PE in PELT. We need add the PE into the | |
847 | * corresponding PELT-V as well. Otherwise, the error | |
848 | * originated from the PE might contribute to other | |
849 | * PEs. | |
850 | */ | |
184cd4a3 BH |
851 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
852 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
853 | if (rc) { | |
854 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
855 | return -ENXIO; | |
856 | } | |
631ad691 | 857 | |
5d2aa710 AP |
858 | /* |
859 | * Configure PELTV. NPUs don't have a PELTV table so skip | |
860 | * configuration on them. | |
861 | */ | |
862 | if (phb->type != PNV_PHB_NPU) | |
863 | pnv_ioda_set_peltv(phb, pe, true); | |
184cd4a3 | 864 | |
184cd4a3 BH |
865 | /* Setup reverse map */ |
866 | for (rid = pe->rid; rid < rid_end; rid++) | |
867 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
868 | ||
869 | /* Setup one MVTs on IODA1 */ | |
4773f76b GS |
870 | if (phb->type != PNV_PHB_IODA1) { |
871 | pe->mve_number = 0; | |
872 | goto out; | |
873 | } | |
874 | ||
875 | pe->mve_number = pe->pe_number; | |
876 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); | |
877 | if (rc != OPAL_SUCCESS) { | |
878 | pe_err(pe, "OPAL error %ld setting up MVE %d\n", | |
879 | rc, pe->mve_number); | |
880 | pe->mve_number = -1; | |
881 | } else { | |
882 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
883 | pe->mve_number, OPAL_ENABLE_MVE); | |
184cd4a3 | 884 | if (rc) { |
4773f76b | 885 | pe_err(pe, "OPAL error %ld enabling MVE %d\n", |
184cd4a3 BH |
886 | rc, pe->mve_number); |
887 | pe->mve_number = -1; | |
184cd4a3 | 888 | } |
4773f76b | 889 | } |
184cd4a3 | 890 | |
4773f76b | 891 | out: |
184cd4a3 BH |
892 | return 0; |
893 | } | |
894 | ||
cad5cef6 GKH |
895 | static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, |
896 | struct pnv_ioda_pe *pe) | |
184cd4a3 BH |
897 | { |
898 | struct pnv_ioda_pe *lpe; | |
899 | ||
7ebdf956 | 900 | list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 | 901 | if (lpe->dma_weight < pe->dma_weight) { |
7ebdf956 | 902 | list_add_tail(&pe->dma_link, &lpe->dma_link); |
184cd4a3 BH |
903 | return; |
904 | } | |
905 | } | |
7ebdf956 | 906 | list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); |
184cd4a3 BH |
907 | } |
908 | ||
909 | static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) | |
910 | { | |
911 | /* This is quite simplistic. The "base" weight of a device | |
912 | * is 10. 0 means no DMA is to be accounted for it. | |
913 | */ | |
914 | ||
915 | /* If it's a bridge, no DMA */ | |
916 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
917 | return 0; | |
918 | ||
919 | /* Reduce the weight of slow USB controllers */ | |
920 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
921 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
922 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
923 | return 3; | |
924 | ||
925 | /* Increase the weight of RAID (includes Obsidian) */ | |
926 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
927 | return 15; | |
928 | ||
929 | /* Default */ | |
930 | return 10; | |
931 | } | |
932 | ||
781a868f WY |
933 | #ifdef CONFIG_PCI_IOV |
934 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) | |
935 | { | |
936 | struct pci_dn *pdn = pci_get_pdn(dev); | |
937 | int i; | |
938 | struct resource *res, res2; | |
939 | resource_size_t size; | |
940 | u16 num_vfs; | |
941 | ||
942 | if (!dev->is_physfn) | |
943 | return -EINVAL; | |
944 | ||
945 | /* | |
946 | * "offset" is in VFs. The M64 windows are sized so that when they | |
947 | * are segmented, each segment is the same size as the IOV BAR. | |
948 | * Each segment is in a separate PE, and the high order bits of the | |
949 | * address are the PE number. Therefore, each VF's BAR is in a | |
950 | * separate PE, and changing the IOV BAR start address changes the | |
951 | * range of PEs the VFs are in. | |
952 | */ | |
953 | num_vfs = pdn->num_vfs; | |
954 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
955 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
956 | if (!res->flags || !res->parent) | |
957 | continue; | |
958 | ||
781a868f WY |
959 | /* |
960 | * The actual IOV BAR range is determined by the start address | |
961 | * and the actual size for num_vfs VFs BAR. This check is to | |
962 | * make sure that after shifting, the range will not overlap | |
963 | * with another device. | |
964 | */ | |
965 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | |
966 | res2.flags = res->flags; | |
967 | res2.start = res->start + (size * offset); | |
968 | res2.end = res2.start + (size * num_vfs) - 1; | |
969 | ||
970 | if (res2.end > res->end) { | |
971 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", | |
972 | i, &res2, res, num_vfs, offset); | |
973 | return -EBUSY; | |
974 | } | |
975 | } | |
976 | ||
977 | /* | |
978 | * After doing so, there would be a "hole" in the /proc/iomem when | |
979 | * offset is a positive value. It looks like the device return some | |
980 | * mmio back to the system, which actually no one could use it. | |
981 | */ | |
982 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
983 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
984 | if (!res->flags || !res->parent) | |
985 | continue; | |
986 | ||
781a868f WY |
987 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
988 | res2 = *res; | |
989 | res->start += size * offset; | |
990 | ||
74703cc4 WY |
991 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", |
992 | i, &res2, res, (offset > 0) ? "En" : "Dis", | |
993 | num_vfs, offset); | |
781a868f WY |
994 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); |
995 | } | |
996 | return 0; | |
997 | } | |
998 | #endif /* CONFIG_PCI_IOV */ | |
999 | ||
cad5cef6 | 1000 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
1001 | { |
1002 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1003 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 1004 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 | 1005 | struct pnv_ioda_pe *pe; |
689ee8c9 | 1006 | unsigned int pe_num; |
184cd4a3 BH |
1007 | |
1008 | if (!pdn) { | |
1009 | pr_err("%s: Device tree node not associated properly\n", | |
1010 | pci_name(dev)); | |
1011 | return NULL; | |
1012 | } | |
1013 | if (pdn->pe_number != IODA_INVALID_PE) | |
1014 | return NULL; | |
1015 | ||
5d2aa710 | 1016 | pe_num = pnv_ioda_alloc_pe(phb); |
184cd4a3 BH |
1017 | if (pe_num == IODA_INVALID_PE) { |
1018 | pr_warning("%s: Not enough PE# available, disabling device\n", | |
1019 | pci_name(dev)); | |
1020 | return NULL; | |
1021 | } | |
1022 | ||
1023 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
1024 | * pointer in the PE data structure, both should be destroyed at the | |
1025 | * same time. However, this needs to be looked at more closely again | |
1026 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
1027 | * | |
1028 | * At some point we want to remove the PDN completely anyways | |
1029 | */ | |
1030 | pe = &phb->ioda.pe_array[pe_num]; | |
1031 | pci_dev_get(dev); | |
1032 | pdn->pcidev = dev; | |
1033 | pdn->pe_number = pe_num; | |
5d2aa710 | 1034 | pe->flags = PNV_IODA_PE_DEV; |
184cd4a3 BH |
1035 | pe->pdev = dev; |
1036 | pe->pbus = NULL; | |
1037 | pe->tce32_seg = -1; | |
1038 | pe->mve_number = -1; | |
1039 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
1040 | ||
1041 | pe_info(pe, "Associated device to PE\n"); | |
1042 | ||
1043 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1044 | /* XXX What do we do here ? */ | |
1045 | if (pe_num) | |
1046 | pnv_ioda_free_pe(phb, pe_num); | |
1047 | pdn->pe_number = IODA_INVALID_PE; | |
1048 | pe->pdev = NULL; | |
1049 | pci_dev_put(dev); | |
1050 | return NULL; | |
1051 | } | |
1052 | ||
1053 | /* Assign a DMA weight to the device */ | |
1054 | pe->dma_weight = pnv_ioda_dma_weight(dev); | |
1055 | if (pe->dma_weight != 0) { | |
1056 | phb->ioda.dma_weight += pe->dma_weight; | |
1057 | phb->ioda.dma_pe_count++; | |
1058 | } | |
1059 | ||
1060 | /* Link the PE */ | |
1061 | pnv_ioda_link_pe_by_weight(phb, pe); | |
1062 | ||
1063 | return pe; | |
1064 | } | |
1065 | ||
1066 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
1067 | { | |
1068 | struct pci_dev *dev; | |
1069 | ||
1070 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 1071 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1072 | |
1073 | if (pdn == NULL) { | |
1074 | pr_warn("%s: No device node associated with device !\n", | |
1075 | pci_name(dev)); | |
1076 | continue; | |
1077 | } | |
94973b24 | 1078 | pdn->pcidev = dev; |
184cd4a3 BH |
1079 | pdn->pe_number = pe->pe_number; |
1080 | pe->dma_weight += pnv_ioda_dma_weight(dev); | |
fb446ad0 | 1081 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
1082 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
1083 | } | |
1084 | } | |
1085 | ||
fb446ad0 GS |
1086 | /* |
1087 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
1088 | * single PCI bus. Another one that contains the primary PCI bus and its | |
1089 | * subordinate PCI devices and buses. The second type of PE is normally | |
1090 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
1091 | */ | |
d1203852 | 1092 | static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) |
184cd4a3 | 1093 | { |
fb446ad0 | 1094 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 1095 | struct pnv_phb *phb = hose->private_data; |
184cd4a3 | 1096 | struct pnv_ioda_pe *pe; |
689ee8c9 | 1097 | unsigned int pe_num = IODA_INVALID_PE; |
262af557 GC |
1098 | |
1099 | /* Check if PE is determined by M64 */ | |
1100 | if (phb->pick_m64_pe) | |
26ba248d | 1101 | pe_num = phb->pick_m64_pe(bus, all); |
262af557 GC |
1102 | |
1103 | /* The PE number isn't pinned by M64 */ | |
1104 | if (pe_num == IODA_INVALID_PE) | |
1105 | pe_num = pnv_ioda_alloc_pe(phb); | |
184cd4a3 | 1106 | |
184cd4a3 | 1107 | if (pe_num == IODA_INVALID_PE) { |
fb446ad0 GS |
1108 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
1109 | __func__, pci_domain_nr(bus), bus->number); | |
184cd4a3 BH |
1110 | return; |
1111 | } | |
1112 | ||
1113 | pe = &phb->ioda.pe_array[pe_num]; | |
262af557 | 1114 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
1115 | pe->pbus = bus; |
1116 | pe->pdev = NULL; | |
1117 | pe->tce32_seg = -1; | |
1118 | pe->mve_number = -1; | |
b918c62e | 1119 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 BH |
1120 | pe->dma_weight = 0; |
1121 | ||
fb446ad0 GS |
1122 | if (all) |
1123 | pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", | |
1124 | bus->busn_res.start, bus->busn_res.end, pe_num); | |
1125 | else | |
1126 | pe_info(pe, "Secondary bus %d associated with PE#%d\n", | |
1127 | bus->busn_res.start, pe_num); | |
184cd4a3 BH |
1128 | |
1129 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1130 | /* XXX What do we do here ? */ | |
1131 | if (pe_num) | |
1132 | pnv_ioda_free_pe(phb, pe_num); | |
1133 | pe->pbus = NULL; | |
1134 | return; | |
1135 | } | |
1136 | ||
1137 | /* Associate it with all child devices */ | |
1138 | pnv_ioda_setup_same_PE(bus, pe); | |
1139 | ||
7ebdf956 GS |
1140 | /* Put PE to the list */ |
1141 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1142 | ||
184cd4a3 BH |
1143 | /* Account for one DMA PE if at least one DMA capable device exist |
1144 | * below the bridge | |
1145 | */ | |
1146 | if (pe->dma_weight != 0) { | |
1147 | phb->ioda.dma_weight += pe->dma_weight; | |
1148 | phb->ioda.dma_pe_count++; | |
1149 | } | |
1150 | ||
1151 | /* Link the PE */ | |
1152 | pnv_ioda_link_pe_by_weight(phb, pe); | |
1153 | } | |
1154 | ||
b521549a AP |
1155 | static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) |
1156 | { | |
1157 | int pe_num, found_pe = false, rc; | |
1158 | long rid; | |
1159 | struct pnv_ioda_pe *pe; | |
1160 | struct pci_dev *gpu_pdev; | |
1161 | struct pci_dn *npu_pdn; | |
1162 | struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); | |
1163 | struct pnv_phb *phb = hose->private_data; | |
1164 | ||
1165 | /* | |
1166 | * Due to a hardware errata PE#0 on the NPU is reserved for | |
1167 | * error handling. This means we only have three PEs remaining | |
1168 | * which need to be assigned to four links, implying some | |
1169 | * links must share PEs. | |
1170 | * | |
1171 | * To achieve this we assign PEs such that NPUs linking the | |
1172 | * same GPU get assigned the same PE. | |
1173 | */ | |
1174 | gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); | |
92b8f137 | 1175 | for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { |
b521549a AP |
1176 | pe = &phb->ioda.pe_array[pe_num]; |
1177 | if (!pe->pdev) | |
1178 | continue; | |
1179 | ||
1180 | if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { | |
1181 | /* | |
1182 | * This device has the same peer GPU so should | |
1183 | * be assigned the same PE as the existing | |
1184 | * peer NPU. | |
1185 | */ | |
1186 | dev_info(&npu_pdev->dev, | |
1187 | "Associating to existing PE %d\n", pe_num); | |
1188 | pci_dev_get(npu_pdev); | |
1189 | npu_pdn = pci_get_pdn(npu_pdev); | |
1190 | rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; | |
1191 | npu_pdn->pcidev = npu_pdev; | |
1192 | npu_pdn->pe_number = pe_num; | |
1193 | pe->dma_weight += pnv_ioda_dma_weight(npu_pdev); | |
1194 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
1195 | ||
1196 | /* Map the PE to this link */ | |
1197 | rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, | |
1198 | OpalPciBusAll, | |
1199 | OPAL_COMPARE_RID_DEVICE_NUMBER, | |
1200 | OPAL_COMPARE_RID_FUNCTION_NUMBER, | |
1201 | OPAL_MAP_PE); | |
1202 | WARN_ON(rc != OPAL_SUCCESS); | |
1203 | found_pe = true; | |
1204 | break; | |
1205 | } | |
1206 | } | |
1207 | ||
1208 | if (!found_pe) | |
1209 | /* | |
1210 | * Could not find an existing PE so allocate a new | |
1211 | * one. | |
1212 | */ | |
1213 | return pnv_ioda_setup_dev_PE(npu_pdev); | |
1214 | else | |
1215 | return pe; | |
1216 | } | |
1217 | ||
1218 | static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) | |
5d2aa710 | 1219 | { |
5d2aa710 AP |
1220 | struct pci_dev *pdev; |
1221 | ||
1222 | list_for_each_entry(pdev, &bus->devices, bus_list) | |
b521549a | 1223 | pnv_ioda_setup_npu_PE(pdev); |
5d2aa710 AP |
1224 | } |
1225 | ||
cad5cef6 | 1226 | static void pnv_ioda_setup_PEs(struct pci_bus *bus) |
184cd4a3 BH |
1227 | { |
1228 | struct pci_dev *dev; | |
fb446ad0 | 1229 | |
d1203852 | 1230 | pnv_ioda_setup_bus_PE(bus, false); |
184cd4a3 BH |
1231 | |
1232 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
fb446ad0 GS |
1233 | if (dev->subordinate) { |
1234 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
d1203852 | 1235 | pnv_ioda_setup_bus_PE(dev->subordinate, true); |
fb446ad0 GS |
1236 | else |
1237 | pnv_ioda_setup_PEs(dev->subordinate); | |
1238 | } | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | /* | |
1243 | * Configure PEs so that the downstream PCI buses and devices | |
1244 | * could have their associated PE#. Unfortunately, we didn't | |
1245 | * figure out the way to identify the PLX bridge yet. So we | |
1246 | * simply put the PCI bus and the subordinate behind the root | |
1247 | * port to PE# here. The game rule here is expected to be changed | |
1248 | * as soon as we can detected PLX bridge correctly. | |
1249 | */ | |
cad5cef6 | 1250 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
1251 | { |
1252 | struct pci_controller *hose, *tmp; | |
262af557 | 1253 | struct pnv_phb *phb; |
fb446ad0 GS |
1254 | |
1255 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
262af557 GC |
1256 | phb = hose->private_data; |
1257 | ||
1258 | /* M64 layout might affect PE allocation */ | |
5ef73567 | 1259 | if (phb->reserve_m64_pe) |
96a2f92b | 1260 | phb->reserve_m64_pe(hose->bus, NULL, true); |
262af557 | 1261 | |
5d2aa710 AP |
1262 | /* |
1263 | * On NPU PHB, we expect separate PEs for individual PCI | |
1264 | * functions. PCI bus dependent PEs are required for the | |
1265 | * remaining types of PHBs. | |
1266 | */ | |
08f48f32 AP |
1267 | if (phb->type == PNV_PHB_NPU) { |
1268 | /* PE#0 is needed for error reporting */ | |
1269 | pnv_ioda_reserve_pe(phb, 0); | |
b521549a | 1270 | pnv_ioda_setup_npu_PEs(hose->bus); |
08f48f32 | 1271 | } else |
5d2aa710 | 1272 | pnv_ioda_setup_PEs(hose->bus); |
184cd4a3 BH |
1273 | } |
1274 | } | |
1275 | ||
a8b2f828 | 1276 | #ifdef CONFIG_PCI_IOV |
ee8222fe | 1277 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1278 | { |
1279 | struct pci_bus *bus; | |
1280 | struct pci_controller *hose; | |
1281 | struct pnv_phb *phb; | |
1282 | struct pci_dn *pdn; | |
02639b0e | 1283 | int i, j; |
ee8222fe | 1284 | int m64_bars; |
781a868f WY |
1285 | |
1286 | bus = pdev->bus; | |
1287 | hose = pci_bus_to_host(bus); | |
1288 | phb = hose->private_data; | |
1289 | pdn = pci_get_pdn(pdev); | |
1290 | ||
ee8222fe WY |
1291 | if (pdn->m64_single_mode) |
1292 | m64_bars = num_vfs; | |
1293 | else | |
1294 | m64_bars = 1; | |
1295 | ||
02639b0e | 1296 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
ee8222fe WY |
1297 | for (j = 0; j < m64_bars; j++) { |
1298 | if (pdn->m64_map[j][i] == IODA_INVALID_M64) | |
02639b0e WY |
1299 | continue; |
1300 | opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe WY |
1301 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); |
1302 | clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); | |
1303 | pdn->m64_map[j][i] = IODA_INVALID_M64; | |
02639b0e | 1304 | } |
781a868f | 1305 | |
ee8222fe | 1306 | kfree(pdn->m64_map); |
781a868f WY |
1307 | return 0; |
1308 | } | |
1309 | ||
02639b0e | 1310 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1311 | { |
1312 | struct pci_bus *bus; | |
1313 | struct pci_controller *hose; | |
1314 | struct pnv_phb *phb; | |
1315 | struct pci_dn *pdn; | |
1316 | unsigned int win; | |
1317 | struct resource *res; | |
02639b0e | 1318 | int i, j; |
781a868f | 1319 | int64_t rc; |
02639b0e WY |
1320 | int total_vfs; |
1321 | resource_size_t size, start; | |
1322 | int pe_num; | |
ee8222fe | 1323 | int m64_bars; |
781a868f WY |
1324 | |
1325 | bus = pdev->bus; | |
1326 | hose = pci_bus_to_host(bus); | |
1327 | phb = hose->private_data; | |
1328 | pdn = pci_get_pdn(pdev); | |
02639b0e | 1329 | total_vfs = pci_sriov_get_totalvfs(pdev); |
781a868f | 1330 | |
ee8222fe WY |
1331 | if (pdn->m64_single_mode) |
1332 | m64_bars = num_vfs; | |
1333 | else | |
1334 | m64_bars = 1; | |
1335 | ||
1336 | pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); | |
1337 | if (!pdn->m64_map) | |
1338 | return -ENOMEM; | |
1339 | /* Initialize the m64_map to IODA_INVALID_M64 */ | |
1340 | for (i = 0; i < m64_bars ; i++) | |
1341 | for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) | |
1342 | pdn->m64_map[i][j] = IODA_INVALID_M64; | |
02639b0e | 1343 | |
781a868f WY |
1344 | |
1345 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1346 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
1347 | if (!res->flags || !res->parent) | |
1348 | continue; | |
1349 | ||
ee8222fe | 1350 | for (j = 0; j < m64_bars; j++) { |
02639b0e WY |
1351 | do { |
1352 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, | |
1353 | phb->ioda.m64_bar_idx + 1, 0); | |
1354 | ||
1355 | if (win >= phb->ioda.m64_bar_idx + 1) | |
1356 | goto m64_failed; | |
1357 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); | |
1358 | ||
ee8222fe | 1359 | pdn->m64_map[j][i] = win; |
02639b0e | 1360 | |
ee8222fe | 1361 | if (pdn->m64_single_mode) { |
02639b0e WY |
1362 | size = pci_iov_resource_size(pdev, |
1363 | PCI_IOV_RESOURCES + i); | |
02639b0e WY |
1364 | start = res->start + size * j; |
1365 | } else { | |
1366 | size = resource_size(res); | |
1367 | start = res->start; | |
1368 | } | |
1369 | ||
1370 | /* Map the M64 here */ | |
ee8222fe | 1371 | if (pdn->m64_single_mode) { |
be283eeb | 1372 | pe_num = pdn->pe_num_map[j]; |
02639b0e WY |
1373 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
1374 | pe_num, OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1375 | pdn->m64_map[j][i], 0); |
02639b0e WY |
1376 | } |
1377 | ||
1378 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
1379 | OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1380 | pdn->m64_map[j][i], |
02639b0e WY |
1381 | start, |
1382 | 0, /* unused */ | |
1383 | size); | |
781a868f | 1384 | |
781a868f | 1385 | |
02639b0e WY |
1386 | if (rc != OPAL_SUCCESS) { |
1387 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", | |
1388 | win, rc); | |
1389 | goto m64_failed; | |
1390 | } | |
781a868f | 1391 | |
ee8222fe | 1392 | if (pdn->m64_single_mode) |
02639b0e | 1393 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
ee8222fe | 1394 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); |
02639b0e WY |
1395 | else |
1396 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe | 1397 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); |
781a868f | 1398 | |
02639b0e WY |
1399 | if (rc != OPAL_SUCCESS) { |
1400 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", | |
1401 | win, rc); | |
1402 | goto m64_failed; | |
1403 | } | |
781a868f WY |
1404 | } |
1405 | } | |
1406 | return 0; | |
1407 | ||
1408 | m64_failed: | |
ee8222fe | 1409 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1410 | return -EBUSY; |
1411 | } | |
1412 | ||
c035e37b AK |
1413 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
1414 | int num); | |
1415 | static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); | |
1416 | ||
781a868f WY |
1417 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) |
1418 | { | |
781a868f | 1419 | struct iommu_table *tbl; |
781a868f WY |
1420 | int64_t rc; |
1421 | ||
b348aa65 | 1422 | tbl = pe->table_group.tables[0]; |
c035e37b | 1423 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
781a868f WY |
1424 | if (rc) |
1425 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
1426 | ||
c035e37b | 1427 | pnv_pci_ioda2_set_bypass(pe, false); |
0eaf4def AK |
1428 | if (pe->table_group.group) { |
1429 | iommu_group_put(pe->table_group.group); | |
1430 | BUG_ON(pe->table_group.group); | |
ac9a5889 | 1431 | } |
aca6913f | 1432 | pnv_pci_ioda2_table_free_pages(tbl); |
781a868f | 1433 | iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); |
781a868f WY |
1434 | } |
1435 | ||
ee8222fe | 1436 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) |
781a868f WY |
1437 | { |
1438 | struct pci_bus *bus; | |
1439 | struct pci_controller *hose; | |
1440 | struct pnv_phb *phb; | |
1441 | struct pnv_ioda_pe *pe, *pe_n; | |
1442 | struct pci_dn *pdn; | |
1443 | ||
1444 | bus = pdev->bus; | |
1445 | hose = pci_bus_to_host(bus); | |
1446 | phb = hose->private_data; | |
02639b0e | 1447 | pdn = pci_get_pdn(pdev); |
781a868f WY |
1448 | |
1449 | if (!pdev->is_physfn) | |
1450 | return; | |
1451 | ||
781a868f WY |
1452 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
1453 | if (pe->parent_dev != pdev) | |
1454 | continue; | |
1455 | ||
1456 | pnv_pci_ioda2_release_dma_pe(pdev, pe); | |
1457 | ||
1458 | /* Remove from list */ | |
1459 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1460 | list_del(&pe->list); | |
1461 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1462 | ||
1463 | pnv_ioda_deconfigure_pe(phb, pe); | |
1464 | ||
1465 | pnv_ioda_free_pe(phb, pe->pe_number); | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | void pnv_pci_sriov_disable(struct pci_dev *pdev) | |
1470 | { | |
1471 | struct pci_bus *bus; | |
1472 | struct pci_controller *hose; | |
1473 | struct pnv_phb *phb; | |
1474 | struct pci_dn *pdn; | |
1475 | struct pci_sriov *iov; | |
be283eeb | 1476 | u16 num_vfs, i; |
781a868f WY |
1477 | |
1478 | bus = pdev->bus; | |
1479 | hose = pci_bus_to_host(bus); | |
1480 | phb = hose->private_data; | |
1481 | pdn = pci_get_pdn(pdev); | |
1482 | iov = pdev->sriov; | |
1483 | num_vfs = pdn->num_vfs; | |
1484 | ||
1485 | /* Release VF PEs */ | |
ee8222fe | 1486 | pnv_ioda_release_vf_PE(pdev); |
781a868f WY |
1487 | |
1488 | if (phb->type == PNV_PHB_IODA2) { | |
ee8222fe | 1489 | if (!pdn->m64_single_mode) |
be283eeb | 1490 | pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); |
781a868f WY |
1491 | |
1492 | /* Release M64 windows */ | |
ee8222fe | 1493 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1494 | |
1495 | /* Release PE numbers */ | |
be283eeb WY |
1496 | if (pdn->m64_single_mode) { |
1497 | for (i = 0; i < num_vfs; i++) { | |
1498 | if (pdn->pe_num_map[i] != IODA_INVALID_PE) | |
1499 | pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); | |
1500 | } | |
1501 | } else | |
1502 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1503 | /* Releasing pe_num_map */ | |
1504 | kfree(pdn->pe_num_map); | |
781a868f WY |
1505 | } |
1506 | } | |
1507 | ||
1508 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
1509 | struct pnv_ioda_pe *pe); | |
1510 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) | |
1511 | { | |
1512 | struct pci_bus *bus; | |
1513 | struct pci_controller *hose; | |
1514 | struct pnv_phb *phb; | |
1515 | struct pnv_ioda_pe *pe; | |
1516 | int pe_num; | |
1517 | u16 vf_index; | |
1518 | struct pci_dn *pdn; | |
1519 | ||
1520 | bus = pdev->bus; | |
1521 | hose = pci_bus_to_host(bus); | |
1522 | phb = hose->private_data; | |
1523 | pdn = pci_get_pdn(pdev); | |
1524 | ||
1525 | if (!pdev->is_physfn) | |
1526 | return; | |
1527 | ||
1528 | /* Reserve PE for each VF */ | |
1529 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { | |
be283eeb WY |
1530 | if (pdn->m64_single_mode) |
1531 | pe_num = pdn->pe_num_map[vf_index]; | |
1532 | else | |
1533 | pe_num = *pdn->pe_num_map + vf_index; | |
781a868f WY |
1534 | |
1535 | pe = &phb->ioda.pe_array[pe_num]; | |
1536 | pe->pe_number = pe_num; | |
1537 | pe->phb = phb; | |
1538 | pe->flags = PNV_IODA_PE_VF; | |
1539 | pe->pbus = NULL; | |
1540 | pe->parent_dev = pdev; | |
1541 | pe->tce32_seg = -1; | |
1542 | pe->mve_number = -1; | |
1543 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | | |
1544 | pci_iov_virtfn_devfn(pdev, vf_index); | |
1545 | ||
1546 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", | |
1547 | hose->global_number, pdev->bus->number, | |
1548 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), | |
1549 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); | |
1550 | ||
1551 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1552 | /* XXX What do we do here ? */ | |
1553 | if (pe_num) | |
1554 | pnv_ioda_free_pe(phb, pe_num); | |
1555 | pe->pdev = NULL; | |
1556 | continue; | |
1557 | } | |
1558 | ||
781a868f WY |
1559 | /* Put PE to the list */ |
1560 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1561 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1562 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1563 | ||
1564 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
1565 | } | |
1566 | } | |
1567 | ||
1568 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1569 | { | |
1570 | struct pci_bus *bus; | |
1571 | struct pci_controller *hose; | |
1572 | struct pnv_phb *phb; | |
1573 | struct pci_dn *pdn; | |
1574 | int ret; | |
be283eeb | 1575 | u16 i; |
781a868f WY |
1576 | |
1577 | bus = pdev->bus; | |
1578 | hose = pci_bus_to_host(bus); | |
1579 | phb = hose->private_data; | |
1580 | pdn = pci_get_pdn(pdev); | |
1581 | ||
1582 | if (phb->type == PNV_PHB_IODA2) { | |
b0331854 WY |
1583 | if (!pdn->vfs_expanded) { |
1584 | dev_info(&pdev->dev, "don't support this SRIOV device" | |
1585 | " with non 64bit-prefetchable IOV BAR\n"); | |
1586 | return -ENOSPC; | |
1587 | } | |
1588 | ||
ee8222fe WY |
1589 | /* |
1590 | * When M64 BARs functions in Single PE mode, the number of VFs | |
1591 | * could be enabled must be less than the number of M64 BARs. | |
1592 | */ | |
1593 | if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { | |
1594 | dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); | |
1595 | return -EBUSY; | |
1596 | } | |
1597 | ||
be283eeb WY |
1598 | /* Allocating pe_num_map */ |
1599 | if (pdn->m64_single_mode) | |
1600 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, | |
1601 | GFP_KERNEL); | |
1602 | else | |
1603 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); | |
1604 | ||
1605 | if (!pdn->pe_num_map) | |
1606 | return -ENOMEM; | |
1607 | ||
1608 | if (pdn->m64_single_mode) | |
1609 | for (i = 0; i < num_vfs; i++) | |
1610 | pdn->pe_num_map[i] = IODA_INVALID_PE; | |
1611 | ||
781a868f | 1612 | /* Calculate available PE for required VFs */ |
be283eeb WY |
1613 | if (pdn->m64_single_mode) { |
1614 | for (i = 0; i < num_vfs; i++) { | |
1615 | pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb); | |
1616 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) { | |
1617 | ret = -EBUSY; | |
1618 | goto m64_failed; | |
1619 | } | |
1620 | } | |
1621 | } else { | |
1622 | mutex_lock(&phb->ioda.pe_alloc_mutex); | |
1623 | *pdn->pe_num_map = bitmap_find_next_zero_area( | |
92b8f137 | 1624 | phb->ioda.pe_alloc, phb->ioda.total_pe_num, |
be283eeb | 1625 | 0, num_vfs, 0); |
92b8f137 | 1626 | if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { |
be283eeb WY |
1627 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
1628 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); | |
1629 | kfree(pdn->pe_num_map); | |
1630 | return -EBUSY; | |
1631 | } | |
1632 | bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
781a868f | 1633 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
781a868f | 1634 | } |
781a868f | 1635 | pdn->num_vfs = num_vfs; |
781a868f WY |
1636 | |
1637 | /* Assign M64 window accordingly */ | |
02639b0e | 1638 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
781a868f WY |
1639 | if (ret) { |
1640 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); | |
1641 | goto m64_failed; | |
1642 | } | |
1643 | ||
1644 | /* | |
1645 | * When using one M64 BAR to map one IOV BAR, we need to shift | |
1646 | * the IOV BAR according to the PE# allocated to the VFs. | |
1647 | * Otherwise, the PE# for the VF will conflict with others. | |
1648 | */ | |
ee8222fe | 1649 | if (!pdn->m64_single_mode) { |
be283eeb | 1650 | ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); |
02639b0e WY |
1651 | if (ret) |
1652 | goto m64_failed; | |
1653 | } | |
781a868f WY |
1654 | } |
1655 | ||
1656 | /* Setup VF PEs */ | |
1657 | pnv_ioda_setup_vf_PE(pdev, num_vfs); | |
1658 | ||
1659 | return 0; | |
1660 | ||
1661 | m64_failed: | |
be283eeb WY |
1662 | if (pdn->m64_single_mode) { |
1663 | for (i = 0; i < num_vfs; i++) { | |
1664 | if (pdn->pe_num_map[i] != IODA_INVALID_PE) | |
1665 | pnv_ioda_free_pe(phb, pdn->pe_num_map[i]); | |
1666 | } | |
1667 | } else | |
1668 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1669 | ||
1670 | /* Releasing pe_num_map */ | |
1671 | kfree(pdn->pe_num_map); | |
781a868f WY |
1672 | |
1673 | return ret; | |
1674 | } | |
1675 | ||
a8b2f828 GS |
1676 | int pcibios_sriov_disable(struct pci_dev *pdev) |
1677 | { | |
781a868f WY |
1678 | pnv_pci_sriov_disable(pdev); |
1679 | ||
a8b2f828 GS |
1680 | /* Release PCI data */ |
1681 | remove_dev_pci_data(pdev); | |
1682 | return 0; | |
1683 | } | |
1684 | ||
1685 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1686 | { | |
1687 | /* Allocate PCI data */ | |
1688 | add_dev_pci_data(pdev); | |
781a868f | 1689 | |
ee8222fe | 1690 | return pnv_pci_sriov_enable(pdev, num_vfs); |
a8b2f828 GS |
1691 | } |
1692 | #endif /* CONFIG_PCI_IOV */ | |
1693 | ||
959c9bdd | 1694 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 1695 | { |
b72c1f65 | 1696 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 1697 | struct pnv_ioda_pe *pe; |
184cd4a3 | 1698 | |
959c9bdd GS |
1699 | /* |
1700 | * The function can be called while the PE# | |
1701 | * hasn't been assigned. Do nothing for the | |
1702 | * case. | |
1703 | */ | |
1704 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
1705 | return; | |
184cd4a3 | 1706 | |
959c9bdd | 1707 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
cd15b048 | 1708 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
0e1ffef0 | 1709 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); |
b348aa65 | 1710 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
4617082e AK |
1711 | /* |
1712 | * Note: iommu_add_device() will fail here as | |
1713 | * for physical PE: the device is already added by now; | |
1714 | * for virtual PE: sysfs entries are not ready yet and | |
1715 | * tce_iommu_bus_notifier will add the device to a group later. | |
1716 | */ | |
184cd4a3 BH |
1717 | } |
1718 | ||
763d2d8d | 1719 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
cd15b048 | 1720 | { |
763d2d8d DA |
1721 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1722 | struct pnv_phb *phb = hose->private_data; | |
cd15b048 BH |
1723 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1724 | struct pnv_ioda_pe *pe; | |
1725 | uint64_t top; | |
1726 | bool bypass = false; | |
5d2aa710 AP |
1727 | struct pci_dev *linked_npu_dev; |
1728 | int i; | |
cd15b048 BH |
1729 | |
1730 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1731 | return -ENODEV;; | |
1732 | ||
1733 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1734 | if (pe->tce_bypass_enabled) { | |
1735 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; | |
1736 | bypass = (dma_mask >= top); | |
1737 | } | |
1738 | ||
1739 | if (bypass) { | |
1740 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); | |
1741 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
cd15b048 BH |
1742 | } else { |
1743 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | |
1744 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | |
cd15b048 | 1745 | } |
a32305bf | 1746 | *pdev->dev.dma_mask = dma_mask; |
5d2aa710 AP |
1747 | |
1748 | /* Update peer npu devices */ | |
1749 | if (pe->flags & PNV_IODA_PE_PEER) | |
419dbd5e AP |
1750 | for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { |
1751 | if (!pe->peers[i]) | |
1752 | continue; | |
1753 | ||
5d2aa710 AP |
1754 | linked_npu_dev = pe->peers[i]->pdev; |
1755 | if (dma_get_mask(&linked_npu_dev->dev) != dma_mask) | |
1756 | dma_set_mask(&linked_npu_dev->dev, dma_mask); | |
1757 | } | |
1758 | ||
cd15b048 BH |
1759 | return 0; |
1760 | } | |
1761 | ||
53522982 | 1762 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) |
fe7e85c6 | 1763 | { |
53522982 AD |
1764 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1765 | struct pnv_phb *phb = hose->private_data; | |
fe7e85c6 GS |
1766 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1767 | struct pnv_ioda_pe *pe; | |
1768 | u64 end, mask; | |
1769 | ||
1770 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1771 | return 0; | |
1772 | ||
1773 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1774 | if (!pe->tce_bypass_enabled) | |
1775 | return __dma_get_required_mask(&pdev->dev); | |
1776 | ||
1777 | ||
1778 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); | |
1779 | mask = 1ULL << (fls64(end) - 1); | |
1780 | mask += mask - 1; | |
1781 | ||
1782 | return mask; | |
1783 | } | |
1784 | ||
dff4a39e | 1785 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
ea30e99e | 1786 | struct pci_bus *bus) |
74251fe2 BH |
1787 | { |
1788 | struct pci_dev *dev; | |
1789 | ||
1790 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b348aa65 | 1791 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
e91c2511 | 1792 | set_dma_offset(&dev->dev, pe->tce_bypass_base); |
4617082e | 1793 | iommu_add_device(&dev->dev); |
dff4a39e | 1794 | |
5c89a87d | 1795 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
ea30e99e | 1796 | pnv_ioda_setup_bus_dma(pe, dev->subordinate); |
74251fe2 BH |
1797 | } |
1798 | } | |
1799 | ||
decbda25 AK |
1800 | static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, |
1801 | unsigned long index, unsigned long npages, bool rm) | |
4cce9550 | 1802 | { |
0eaf4def AK |
1803 | struct iommu_table_group_link *tgl = list_first_entry_or_null( |
1804 | &tbl->it_group_list, struct iommu_table_group_link, | |
1805 | next); | |
1806 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, | |
b348aa65 | 1807 | struct pnv_ioda_pe, table_group); |
3ad26e5c | 1808 | __be64 __iomem *invalidate = rm ? |
5780fb04 AK |
1809 | (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : |
1810 | pe->phb->ioda.tce_inval_reg; | |
4cce9550 | 1811 | unsigned long start, end, inc; |
b0376c9b | 1812 | const unsigned shift = tbl->it_page_shift; |
4cce9550 | 1813 | |
decbda25 AK |
1814 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
1815 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + | |
1816 | npages - 1); | |
4cce9550 GS |
1817 | |
1818 | /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ | |
1819 | if (tbl->it_busno) { | |
b0376c9b AK |
1820 | start <<= shift; |
1821 | end <<= shift; | |
1822 | inc = 128ull << shift; | |
4cce9550 GS |
1823 | start |= tbl->it_busno; |
1824 | end |= tbl->it_busno; | |
1825 | } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { | |
1826 | /* p7ioc-style invalidation, 2 TCEs per write */ | |
1827 | start |= (1ull << 63); | |
1828 | end |= (1ull << 63); | |
1829 | inc = 16; | |
1830 | } else { | |
1831 | /* Default (older HW) */ | |
1832 | inc = 128; | |
1833 | } | |
1834 | ||
1835 | end |= inc - 1; /* round up end to be different than start */ | |
1836 | ||
1837 | mb(); /* Ensure above stores are visible */ | |
1838 | while (start <= end) { | |
8e0a1611 | 1839 | if (rm) |
3ad26e5c | 1840 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1841 | else |
3ad26e5c | 1842 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1843 | start += inc; |
1844 | } | |
1845 | ||
1846 | /* | |
1847 | * The iommu layer will do another mb() for us on build() | |
1848 | * and we don't care on free() | |
1849 | */ | |
1850 | } | |
1851 | ||
decbda25 AK |
1852 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
1853 | long npages, unsigned long uaddr, | |
1854 | enum dma_data_direction direction, | |
1855 | struct dma_attrs *attrs) | |
1856 | { | |
1857 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, | |
1858 | attrs); | |
1859 | ||
1860 | if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) | |
1861 | pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); | |
1862 | ||
1863 | return ret; | |
1864 | } | |
1865 | ||
05c6cfb9 AK |
1866 | #ifdef CONFIG_IOMMU_API |
1867 | static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, | |
1868 | unsigned long *hpa, enum dma_data_direction *direction) | |
1869 | { | |
1870 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1871 | ||
1872 | if (!ret && (tbl->it_type & | |
1873 | (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) | |
1874 | pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); | |
1875 | ||
1876 | return ret; | |
1877 | } | |
1878 | #endif | |
1879 | ||
decbda25 AK |
1880 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, |
1881 | long npages) | |
1882 | { | |
1883 | pnv_tce_free(tbl, index, npages); | |
1884 | ||
1885 | if (tbl->it_type & TCE_PCI_SWINV_FREE) | |
1886 | pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); | |
1887 | } | |
1888 | ||
da004c36 | 1889 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
decbda25 | 1890 | .set = pnv_ioda1_tce_build, |
05c6cfb9 AK |
1891 | #ifdef CONFIG_IOMMU_API |
1892 | .exchange = pnv_ioda1_tce_xchg, | |
1893 | #endif | |
decbda25 | 1894 | .clear = pnv_ioda1_tce_free, |
da004c36 AK |
1895 | .get = pnv_tce_get, |
1896 | }; | |
1897 | ||
5780fb04 AK |
1898 | static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) |
1899 | { | |
1900 | /* 01xb - invalidate TCEs that match the specified PE# */ | |
1901 | unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); | |
1902 | struct pnv_phb *phb = pe->phb; | |
5d2aa710 AP |
1903 | struct pnv_ioda_pe *npe; |
1904 | int i; | |
5780fb04 AK |
1905 | |
1906 | if (!phb->ioda.tce_inval_reg) | |
1907 | return; | |
1908 | ||
1909 | mb(); /* Ensure above stores are visible */ | |
1910 | __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); | |
5d2aa710 AP |
1911 | |
1912 | if (pe->flags & PNV_IODA_PE_PEER) | |
1913 | for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { | |
1914 | npe = pe->peers[i]; | |
1915 | if (!npe || npe->phb->type != PNV_PHB_NPU) | |
1916 | continue; | |
1917 | ||
1918 | pnv_npu_tce_invalidate_entire(npe); | |
1919 | } | |
5780fb04 AK |
1920 | } |
1921 | ||
e57080f1 AK |
1922 | static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, |
1923 | __be64 __iomem *invalidate, unsigned shift, | |
1924 | unsigned long index, unsigned long npages) | |
4cce9550 GS |
1925 | { |
1926 | unsigned long start, end, inc; | |
4cce9550 GS |
1927 | |
1928 | /* We'll invalidate DMA address in PE scope */ | |
b0376c9b | 1929 | start = 0x2ull << 60; |
e57080f1 | 1930 | start |= (pe_number & 0xFF); |
4cce9550 GS |
1931 | end = start; |
1932 | ||
1933 | /* Figure out the start, end and step */ | |
decbda25 AK |
1934 | start |= (index << shift); |
1935 | end |= ((index + npages - 1) << shift); | |
b0376c9b | 1936 | inc = (0x1ull << shift); |
4cce9550 GS |
1937 | mb(); |
1938 | ||
1939 | while (start <= end) { | |
8e0a1611 | 1940 | if (rm) |
3ad26e5c | 1941 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1942 | else |
3ad26e5c | 1943 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1944 | start += inc; |
1945 | } | |
1946 | } | |
1947 | ||
e57080f1 AK |
1948 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
1949 | unsigned long index, unsigned long npages, bool rm) | |
1950 | { | |
1951 | struct iommu_table_group_link *tgl; | |
1952 | ||
1953 | list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { | |
5d2aa710 | 1954 | struct pnv_ioda_pe *npe; |
e57080f1 AK |
1955 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
1956 | struct pnv_ioda_pe, table_group); | |
1957 | __be64 __iomem *invalidate = rm ? | |
1958 | (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : | |
1959 | pe->phb->ioda.tce_inval_reg; | |
5d2aa710 | 1960 | int i; |
e57080f1 AK |
1961 | |
1962 | pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, | |
1963 | invalidate, tbl->it_page_shift, | |
1964 | index, npages); | |
5d2aa710 AP |
1965 | |
1966 | if (pe->flags & PNV_IODA_PE_PEER) | |
1967 | /* Invalidate PEs using the same TCE table */ | |
1968 | for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { | |
1969 | npe = pe->peers[i]; | |
1970 | if (!npe || npe->phb->type != PNV_PHB_NPU) | |
1971 | continue; | |
1972 | ||
1973 | pnv_npu_tce_invalidate(npe, tbl, index, | |
1974 | npages, rm); | |
1975 | } | |
e57080f1 AK |
1976 | } |
1977 | } | |
1978 | ||
decbda25 AK |
1979 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
1980 | long npages, unsigned long uaddr, | |
1981 | enum dma_data_direction direction, | |
1982 | struct dma_attrs *attrs) | |
4cce9550 | 1983 | { |
decbda25 AK |
1984 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
1985 | attrs); | |
4cce9550 | 1986 | |
decbda25 AK |
1987 | if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) |
1988 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); | |
1989 | ||
1990 | return ret; | |
1991 | } | |
1992 | ||
05c6cfb9 AK |
1993 | #ifdef CONFIG_IOMMU_API |
1994 | static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, | |
1995 | unsigned long *hpa, enum dma_data_direction *direction) | |
1996 | { | |
1997 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1998 | ||
1999 | if (!ret && (tbl->it_type & | |
2000 | (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) | |
2001 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); | |
2002 | ||
2003 | return ret; | |
2004 | } | |
2005 | #endif | |
2006 | ||
decbda25 AK |
2007 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, |
2008 | long npages) | |
2009 | { | |
2010 | pnv_tce_free(tbl, index, npages); | |
2011 | ||
2012 | if (tbl->it_type & TCE_PCI_SWINV_FREE) | |
2013 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); | |
4cce9550 GS |
2014 | } |
2015 | ||
4793d65d AK |
2016 | static void pnv_ioda2_table_free(struct iommu_table *tbl) |
2017 | { | |
2018 | pnv_pci_ioda2_table_free_pages(tbl); | |
2019 | iommu_free_table(tbl, "pnv"); | |
2020 | } | |
2021 | ||
da004c36 | 2022 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
decbda25 | 2023 | .set = pnv_ioda2_tce_build, |
05c6cfb9 AK |
2024 | #ifdef CONFIG_IOMMU_API |
2025 | .exchange = pnv_ioda2_tce_xchg, | |
2026 | #endif | |
decbda25 | 2027 | .clear = pnv_ioda2_tce_free, |
da004c36 | 2028 | .get = pnv_tce_get, |
4793d65d | 2029 | .free = pnv_ioda2_table_free, |
da004c36 AK |
2030 | }; |
2031 | ||
b30d936f GS |
2032 | static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, |
2033 | struct pnv_ioda_pe *pe, | |
2034 | unsigned int base, | |
2035 | unsigned int segs) | |
184cd4a3 BH |
2036 | { |
2037 | ||
2038 | struct page *tce_mem = NULL; | |
184cd4a3 BH |
2039 | struct iommu_table *tbl; |
2040 | unsigned int i; | |
2041 | int64_t rc; | |
2042 | void *addr; | |
2043 | ||
184cd4a3 BH |
2044 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
2045 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
2046 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
2047 | ||
2048 | /* We shouldn't already have a 32-bit DMA associated */ | |
2049 | if (WARN_ON(pe->tce32_seg >= 0)) | |
2050 | return; | |
2051 | ||
0eaf4def | 2052 | tbl = pnv_pci_table_alloc(phb->hose->node); |
b348aa65 AK |
2053 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2054 | pe->pe_number); | |
0eaf4def | 2055 | pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); |
c5773822 | 2056 | |
184cd4a3 BH |
2057 | /* Grab a 32-bit TCE table */ |
2058 | pe->tce32_seg = base; | |
2059 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", | |
2060 | (base << 28), ((base + segs) << 28) - 1); | |
2061 | ||
2062 | /* XXX Currently, we allocate one big contiguous table for the | |
2063 | * TCEs. We only really need one chunk per 256M of TCE space | |
2064 | * (ie per segment) but that's an optimization for later, it | |
2065 | * requires some added smarts with our get/put_tce implementation | |
2066 | */ | |
2067 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
2068 | get_order(TCE32_TABLE_SIZE * segs)); | |
2069 | if (!tce_mem) { | |
2070 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
2071 | goto fail; | |
2072 | } | |
2073 | addr = page_address(tce_mem); | |
2074 | memset(addr, 0, TCE32_TABLE_SIZE * segs); | |
2075 | ||
2076 | /* Configure HW */ | |
2077 | for (i = 0; i < segs; i++) { | |
2078 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2079 | pe->pe_number, | |
2080 | base + i, 1, | |
2081 | __pa(addr) + TCE32_TABLE_SIZE * i, | |
2082 | TCE32_TABLE_SIZE, 0x1000); | |
2083 | if (rc) { | |
2084 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
2085 | " err %ld\n", rc); | |
2086 | goto fail; | |
2087 | } | |
2088 | } | |
2089 | ||
2090 | /* Setup linux iommu table */ | |
184cd4a3 | 2091 | pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, |
8fa5d454 | 2092 | base << 28, IOMMU_PAGE_SHIFT_4K); |
184cd4a3 BH |
2093 | |
2094 | /* OPAL variant of P7IOC SW invalidated TCEs */ | |
5780fb04 | 2095 | if (phb->ioda.tce_inval_reg) |
65fd766b GS |
2096 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | |
2097 | TCE_PCI_SWINV_FREE | | |
2098 | TCE_PCI_SWINV_PAIR); | |
5780fb04 | 2099 | |
da004c36 | 2100 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
4793d65d AK |
2101 | pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; |
2102 | pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; | |
184cd4a3 BH |
2103 | iommu_init_table(tbl, phb->hose->node); |
2104 | ||
781a868f | 2105 | if (pe->flags & PNV_IODA_PE_DEV) { |
4617082e AK |
2106 | /* |
2107 | * Setting table base here only for carrying iommu_group | |
2108 | * further down to let iommu_add_device() do the job. | |
2109 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2110 | */ | |
2111 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2112 | iommu_add_device(&pe->pdev->dev); | |
c5773822 | 2113 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2114 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
74251fe2 | 2115 | |
184cd4a3 BH |
2116 | return; |
2117 | fail: | |
2118 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
2119 | if (pe->tce32_seg >= 0) | |
2120 | pe->tce32_seg = -1; | |
2121 | if (tce_mem) | |
2122 | __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); | |
0eaf4def AK |
2123 | if (tbl) { |
2124 | pnv_pci_unlink_table_and_group(tbl, &pe->table_group); | |
2125 | iommu_free_table(tbl, "pnv"); | |
2126 | } | |
184cd4a3 BH |
2127 | } |
2128 | ||
43cb60ab AK |
2129 | static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, |
2130 | int num, struct iommu_table *tbl) | |
2131 | { | |
2132 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2133 | table_group); | |
2134 | struct pnv_phb *phb = pe->phb; | |
2135 | int64_t rc; | |
bbb845c4 AK |
2136 | const unsigned long size = tbl->it_indirect_levels ? |
2137 | tbl->it_level_size : tbl->it_size; | |
43cb60ab AK |
2138 | const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
2139 | const __u64 win_size = tbl->it_size << tbl->it_page_shift; | |
2140 | ||
4793d65d | 2141 | pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, |
43cb60ab AK |
2142 | start_addr, start_addr + win_size - 1, |
2143 | IOMMU_PAGE_SIZE(tbl)); | |
2144 | ||
2145 | /* | |
2146 | * Map TCE table through TVT. The TVE index is the PE number | |
2147 | * shifted by 1 bit for 32-bits DMA space. | |
2148 | */ | |
2149 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2150 | pe->pe_number, | |
4793d65d | 2151 | (pe->pe_number << 1) + num, |
bbb845c4 | 2152 | tbl->it_indirect_levels + 1, |
43cb60ab | 2153 | __pa(tbl->it_base), |
bbb845c4 | 2154 | size << 3, |
43cb60ab AK |
2155 | IOMMU_PAGE_SIZE(tbl)); |
2156 | if (rc) { | |
2157 | pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); | |
2158 | return rc; | |
2159 | } | |
2160 | ||
2161 | pnv_pci_link_table_and_group(phb->hose->node, num, | |
2162 | tbl, &pe->table_group); | |
2163 | pnv_pci_ioda2_tce_invalidate_entire(pe); | |
2164 | ||
2165 | return 0; | |
2166 | } | |
2167 | ||
f87a8864 | 2168 | static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) |
cd15b048 | 2169 | { |
cd15b048 BH |
2170 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
2171 | int64_t rc; | |
2172 | ||
2173 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); | |
2174 | if (enable) { | |
2175 | phys_addr_t top = memblock_end_of_DRAM(); | |
2176 | ||
2177 | top = roundup_pow_of_two(top); | |
2178 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2179 | pe->pe_number, | |
2180 | window_id, | |
2181 | pe->tce_bypass_base, | |
2182 | top); | |
2183 | } else { | |
2184 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2185 | pe->pe_number, | |
2186 | window_id, | |
2187 | pe->tce_bypass_base, | |
2188 | 0); | |
cd15b048 BH |
2189 | } |
2190 | if (rc) | |
2191 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); | |
2192 | else | |
2193 | pe->tce_bypass_enabled = enable; | |
2194 | } | |
2195 | ||
4793d65d AK |
2196 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
2197 | __u32 page_shift, __u64 window_size, __u32 levels, | |
2198 | struct iommu_table *tbl); | |
2199 | ||
2200 | static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, | |
2201 | int num, __u32 page_shift, __u64 window_size, __u32 levels, | |
2202 | struct iommu_table **ptbl) | |
2203 | { | |
2204 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2205 | table_group); | |
2206 | int nid = pe->phb->hose->node; | |
2207 | __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; | |
2208 | long ret; | |
2209 | struct iommu_table *tbl; | |
2210 | ||
2211 | tbl = pnv_pci_table_alloc(nid); | |
2212 | if (!tbl) | |
2213 | return -ENOMEM; | |
2214 | ||
2215 | ret = pnv_pci_ioda2_table_alloc_pages(nid, | |
2216 | bus_offset, page_shift, window_size, | |
2217 | levels, tbl); | |
2218 | if (ret) { | |
2219 | iommu_free_table(tbl, "pnv"); | |
2220 | return ret; | |
2221 | } | |
2222 | ||
2223 | tbl->it_ops = &pnv_ioda2_iommu_ops; | |
2224 | if (pe->phb->ioda.tce_inval_reg) | |
2225 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); | |
2226 | ||
2227 | *ptbl = tbl; | |
2228 | ||
2229 | return 0; | |
2230 | } | |
2231 | ||
46d3e1e1 AK |
2232 | static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) |
2233 | { | |
2234 | struct iommu_table *tbl = NULL; | |
2235 | long rc; | |
2236 | ||
fa144869 NA |
2237 | /* |
2238 | * crashkernel= specifies the kdump kernel's maximum memory at | |
2239 | * some offset and there is no guaranteed the result is a power | |
2240 | * of 2, which will cause errors later. | |
2241 | */ | |
2242 | const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); | |
2243 | ||
bb005455 NA |
2244 | /* |
2245 | * In memory constrained environments, e.g. kdump kernel, the | |
2246 | * DMA window can be larger than available memory, which will | |
2247 | * cause errors later. | |
2248 | */ | |
fa144869 | 2249 | const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); |
bb005455 | 2250 | |
46d3e1e1 AK |
2251 | rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, |
2252 | IOMMU_PAGE_SHIFT_4K, | |
bb005455 | 2253 | window_size, |
46d3e1e1 AK |
2254 | POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); |
2255 | if (rc) { | |
2256 | pe_err(pe, "Failed to create 32-bit TCE table, err %ld", | |
2257 | rc); | |
2258 | return rc; | |
2259 | } | |
2260 | ||
2261 | iommu_init_table(tbl, pe->phb->hose->node); | |
2262 | ||
2263 | rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); | |
2264 | if (rc) { | |
2265 | pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", | |
2266 | rc); | |
2267 | pnv_ioda2_table_free(tbl); | |
2268 | return rc; | |
2269 | } | |
2270 | ||
2271 | if (!pnv_iommu_bypass_disabled) | |
2272 | pnv_pci_ioda2_set_bypass(pe, true); | |
2273 | ||
2274 | /* OPAL variant of PHB3 invalidated TCEs */ | |
2275 | if (pe->phb->ioda.tce_inval_reg) | |
2276 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); | |
2277 | ||
2278 | /* | |
2279 | * Setting table base here only for carrying iommu_group | |
2280 | * further down to let iommu_add_device() do the job. | |
2281 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2282 | */ | |
2283 | if (pe->flags & PNV_IODA_PE_DEV) | |
2284 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2285 | ||
2286 | return 0; | |
2287 | } | |
2288 | ||
b5926430 AK |
2289 | #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) |
2290 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, | |
2291 | int num) | |
2292 | { | |
2293 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2294 | table_group); | |
2295 | struct pnv_phb *phb = pe->phb; | |
2296 | long ret; | |
2297 | ||
2298 | pe_info(pe, "Removing DMA window #%d\n", num); | |
2299 | ||
2300 | ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
2301 | (pe->pe_number << 1) + num, | |
2302 | 0/* levels */, 0/* table address */, | |
2303 | 0/* table size */, 0/* page size */); | |
2304 | if (ret) | |
2305 | pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); | |
2306 | else | |
2307 | pnv_pci_ioda2_tce_invalidate_entire(pe); | |
2308 | ||
2309 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); | |
2310 | ||
2311 | return ret; | |
2312 | } | |
2313 | #endif | |
2314 | ||
f87a8864 | 2315 | #ifdef CONFIG_IOMMU_API |
00547193 AK |
2316 | static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, |
2317 | __u64 window_size, __u32 levels) | |
2318 | { | |
2319 | unsigned long bytes = 0; | |
2320 | const unsigned window_shift = ilog2(window_size); | |
2321 | unsigned entries_shift = window_shift - page_shift; | |
2322 | unsigned table_shift = entries_shift + 3; | |
2323 | unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); | |
2324 | unsigned long direct_table_size; | |
2325 | ||
2326 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || | |
2327 | (window_size > memory_hotplug_max()) || | |
2328 | !is_power_of_2(window_size)) | |
2329 | return 0; | |
2330 | ||
2331 | /* Calculate a direct table size from window_size and levels */ | |
2332 | entries_shift = (entries_shift + levels - 1) / levels; | |
2333 | table_shift = entries_shift + 3; | |
2334 | table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); | |
2335 | direct_table_size = 1UL << table_shift; | |
2336 | ||
2337 | for ( ; levels; --levels) { | |
2338 | bytes += _ALIGN_UP(tce_table_size, direct_table_size); | |
2339 | ||
2340 | tce_table_size /= direct_table_size; | |
2341 | tce_table_size <<= 3; | |
2342 | tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); | |
2343 | } | |
2344 | ||
2345 | return bytes; | |
2346 | } | |
2347 | ||
f87a8864 | 2348 | static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) |
cd15b048 | 2349 | { |
f87a8864 AK |
2350 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
2351 | table_group); | |
46d3e1e1 AK |
2352 | /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ |
2353 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
cd15b048 | 2354 | |
f87a8864 | 2355 | pnv_pci_ioda2_set_bypass(pe, false); |
46d3e1e1 AK |
2356 | pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
2357 | pnv_ioda2_table_free(tbl); | |
f87a8864 | 2358 | } |
cd15b048 | 2359 | |
f87a8864 AK |
2360 | static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) |
2361 | { | |
2362 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2363 | table_group); | |
2364 | ||
46d3e1e1 | 2365 | pnv_pci_ioda2_setup_default_config(pe); |
cd15b048 BH |
2366 | } |
2367 | ||
f87a8864 | 2368 | static struct iommu_table_group_ops pnv_pci_ioda2_ops = { |
00547193 | 2369 | .get_table_size = pnv_pci_ioda2_get_table_size, |
4793d65d AK |
2370 | .create_table = pnv_pci_ioda2_create_table, |
2371 | .set_window = pnv_pci_ioda2_set_window, | |
2372 | .unset_window = pnv_pci_ioda2_unset_window, | |
f87a8864 AK |
2373 | .take_ownership = pnv_ioda2_take_ownership, |
2374 | .release_ownership = pnv_ioda2_release_ownership, | |
2375 | }; | |
2376 | #endif | |
2377 | ||
5780fb04 AK |
2378 | static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) |
2379 | { | |
2380 | const __be64 *swinvp; | |
2381 | ||
2382 | /* OPAL variant of PHB3 invalidated TCEs */ | |
2383 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
2384 | if (!swinvp) | |
2385 | return; | |
2386 | ||
2387 | phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); | |
2388 | phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); | |
2389 | } | |
2390 | ||
bbb845c4 AK |
2391 | static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, |
2392 | unsigned levels, unsigned long limit, | |
3ba3a73e | 2393 | unsigned long *current_offset, unsigned long *total_allocated) |
373f5657 GS |
2394 | { |
2395 | struct page *tce_mem = NULL; | |
bbb845c4 | 2396 | __be64 *addr, *tmp; |
aca6913f | 2397 | unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; |
bbb845c4 AK |
2398 | unsigned long allocated = 1UL << (order + PAGE_SHIFT); |
2399 | unsigned entries = 1UL << (shift - 3); | |
2400 | long i; | |
aca6913f AK |
2401 | |
2402 | tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); | |
2403 | if (!tce_mem) { | |
2404 | pr_err("Failed to allocate a TCE memory, order=%d\n", order); | |
2405 | return NULL; | |
2406 | } | |
2407 | addr = page_address(tce_mem); | |
bbb845c4 | 2408 | memset(addr, 0, allocated); |
3ba3a73e | 2409 | *total_allocated += allocated; |
bbb845c4 AK |
2410 | |
2411 | --levels; | |
2412 | if (!levels) { | |
2413 | *current_offset += allocated; | |
2414 | return addr; | |
2415 | } | |
2416 | ||
2417 | for (i = 0; i < entries; ++i) { | |
2418 | tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, | |
3ba3a73e | 2419 | levels, limit, current_offset, total_allocated); |
bbb845c4 AK |
2420 | if (!tmp) |
2421 | break; | |
2422 | ||
2423 | addr[i] = cpu_to_be64(__pa(tmp) | | |
2424 | TCE_PCI_READ | TCE_PCI_WRITE); | |
2425 | ||
2426 | if (*current_offset >= limit) | |
2427 | break; | |
2428 | } | |
aca6913f AK |
2429 | |
2430 | return addr; | |
2431 | } | |
2432 | ||
bbb845c4 AK |
2433 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2434 | unsigned long size, unsigned level); | |
2435 | ||
aca6913f | 2436 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
bbb845c4 AK |
2437 | __u32 page_shift, __u64 window_size, __u32 levels, |
2438 | struct iommu_table *tbl) | |
aca6913f | 2439 | { |
373f5657 | 2440 | void *addr; |
3ba3a73e | 2441 | unsigned long offset = 0, level_shift, total_allocated = 0; |
aca6913f AK |
2442 | const unsigned window_shift = ilog2(window_size); |
2443 | unsigned entries_shift = window_shift - page_shift; | |
2444 | unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); | |
2445 | const unsigned long tce_table_size = 1UL << table_shift; | |
2446 | ||
bbb845c4 AK |
2447 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) |
2448 | return -EINVAL; | |
2449 | ||
aca6913f AK |
2450 | if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) |
2451 | return -EINVAL; | |
2452 | ||
bbb845c4 AK |
2453 | /* Adjust direct table size from window_size and levels */ |
2454 | entries_shift = (entries_shift + levels - 1) / levels; | |
2455 | level_shift = entries_shift + 3; | |
2456 | level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); | |
2457 | ||
aca6913f | 2458 | /* Allocate TCE table */ |
bbb845c4 | 2459 | addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, |
3ba3a73e | 2460 | levels, tce_table_size, &offset, &total_allocated); |
bbb845c4 AK |
2461 | |
2462 | /* addr==NULL means that the first level allocation failed */ | |
aca6913f AK |
2463 | if (!addr) |
2464 | return -ENOMEM; | |
2465 | ||
bbb845c4 AK |
2466 | /* |
2467 | * First level was allocated but some lower level failed as | |
2468 | * we did not allocate as much as we wanted, | |
2469 | * release partially allocated table. | |
2470 | */ | |
2471 | if (offset < tce_table_size) { | |
2472 | pnv_pci_ioda2_table_do_free_pages(addr, | |
2473 | 1ULL << (level_shift - 3), levels - 1); | |
2474 | return -ENOMEM; | |
2475 | } | |
2476 | ||
aca6913f AK |
2477 | /* Setup linux iommu table */ |
2478 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, | |
2479 | page_shift); | |
bbb845c4 AK |
2480 | tbl->it_level_size = 1ULL << (level_shift - 3); |
2481 | tbl->it_indirect_levels = levels - 1; | |
3ba3a73e | 2482 | tbl->it_allocated_size = total_allocated; |
aca6913f AK |
2483 | |
2484 | pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", | |
2485 | window_size, tce_table_size, bus_offset); | |
2486 | ||
2487 | return 0; | |
2488 | } | |
2489 | ||
bbb845c4 AK |
2490 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2491 | unsigned long size, unsigned level) | |
2492 | { | |
2493 | const unsigned long addr_ul = (unsigned long) addr & | |
2494 | ~(TCE_PCI_READ | TCE_PCI_WRITE); | |
2495 | ||
2496 | if (level) { | |
2497 | long i; | |
2498 | u64 *tmp = (u64 *) addr_ul; | |
2499 | ||
2500 | for (i = 0; i < size; ++i) { | |
2501 | unsigned long hpa = be64_to_cpu(tmp[i]); | |
2502 | ||
2503 | if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) | |
2504 | continue; | |
2505 | ||
2506 | pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, | |
2507 | level - 1); | |
2508 | } | |
2509 | } | |
2510 | ||
2511 | free_pages(addr_ul, get_order(size << 3)); | |
2512 | } | |
2513 | ||
aca6913f AK |
2514 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) |
2515 | { | |
bbb845c4 AK |
2516 | const unsigned long size = tbl->it_indirect_levels ? |
2517 | tbl->it_level_size : tbl->it_size; | |
2518 | ||
aca6913f AK |
2519 | if (!tbl->it_size) |
2520 | return; | |
2521 | ||
bbb845c4 AK |
2522 | pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, |
2523 | tbl->it_indirect_levels); | |
aca6913f AK |
2524 | } |
2525 | ||
2526 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
2527 | struct pnv_ioda_pe *pe) | |
2528 | { | |
373f5657 GS |
2529 | int64_t rc; |
2530 | ||
2531 | /* We shouldn't already have a 32-bit DMA associated */ | |
2532 | if (WARN_ON(pe->tce32_seg >= 0)) | |
2533 | return; | |
2534 | ||
f87a8864 AK |
2535 | /* TVE #1 is selected by PCI address bit 59 */ |
2536 | pe->tce_bypass_base = 1ull << 59; | |
2537 | ||
b348aa65 AK |
2538 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2539 | pe->pe_number); | |
c5773822 | 2540 | |
373f5657 GS |
2541 | /* The PE will reserve all possible 32-bits space */ |
2542 | pe->tce32_seg = 0; | |
373f5657 | 2543 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", |
aca6913f | 2544 | phb->ioda.m32_pci_base); |
373f5657 | 2545 | |
aca6913f | 2546 | /* Setup linux iommu table */ |
4793d65d AK |
2547 | pe->table_group.tce32_start = 0; |
2548 | pe->table_group.tce32_size = phb->ioda.m32_pci_base; | |
2549 | pe->table_group.max_dynamic_windows_supported = | |
2550 | IOMMU_TABLE_GROUP_MAX_TABLES; | |
2551 | pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; | |
2552 | pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; | |
e5aad1e6 AK |
2553 | #ifdef CONFIG_IOMMU_API |
2554 | pe->table_group.ops = &pnv_pci_ioda2_ops; | |
2555 | #endif | |
2556 | ||
46d3e1e1 | 2557 | rc = pnv_pci_ioda2_setup_default_config(pe); |
373f5657 | 2558 | if (rc) { |
46d3e1e1 AK |
2559 | if (pe->tce32_seg >= 0) |
2560 | pe->tce32_seg = -1; | |
2561 | return; | |
373f5657 GS |
2562 | } |
2563 | ||
46d3e1e1 | 2564 | if (pe->flags & PNV_IODA_PE_DEV) |
4617082e | 2565 | iommu_add_device(&pe->pdev->dev); |
46d3e1e1 | 2566 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2567 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
373f5657 GS |
2568 | } |
2569 | ||
cad5cef6 | 2570 | static void pnv_ioda_setup_dma(struct pnv_phb *phb) |
184cd4a3 BH |
2571 | { |
2572 | struct pci_controller *hose = phb->hose; | |
2573 | unsigned int residual, remaining, segs, tw, base; | |
2574 | struct pnv_ioda_pe *pe; | |
2575 | ||
2576 | /* If we have more PE# than segments available, hand out one | |
2577 | * per PE until we run out and let the rest fail. If not, | |
2578 | * then we assign at least one segment per PE, plus more based | |
2579 | * on the amount of devices under that PE | |
2580 | */ | |
2581 | if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) | |
2582 | residual = 0; | |
2583 | else | |
2584 | residual = phb->ioda.tce32_count - | |
2585 | phb->ioda.dma_pe_count; | |
2586 | ||
2587 | pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", | |
2588 | hose->global_number, phb->ioda.tce32_count); | |
2589 | pr_info("PCI: %d PE# for a total weight of %d\n", | |
2590 | phb->ioda.dma_pe_count, phb->ioda.dma_weight); | |
2591 | ||
5780fb04 AK |
2592 | pnv_pci_ioda_setup_opal_tce_kill(phb); |
2593 | ||
184cd4a3 BH |
2594 | /* Walk our PE list and configure their DMA segments, hand them |
2595 | * out one base segment plus any residual segments based on | |
2596 | * weight | |
2597 | */ | |
2598 | remaining = phb->ioda.tce32_count; | |
2599 | tw = phb->ioda.dma_weight; | |
2600 | base = 0; | |
7ebdf956 | 2601 | list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 BH |
2602 | if (!pe->dma_weight) |
2603 | continue; | |
2604 | if (!remaining) { | |
2605 | pe_warn(pe, "No DMA32 resources available\n"); | |
2606 | continue; | |
2607 | } | |
2608 | segs = 1; | |
2609 | if (residual) { | |
2610 | segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; | |
2611 | if (segs > remaining) | |
2612 | segs = remaining; | |
2613 | } | |
373f5657 GS |
2614 | |
2615 | /* | |
2616 | * For IODA2 compliant PHB3, we needn't care about the weight. | |
2617 | * The all available 32-bits DMA space will be assigned to | |
2618 | * the specific PE. | |
2619 | */ | |
2620 | if (phb->type == PNV_PHB_IODA1) { | |
2621 | pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", | |
2622 | pe->dma_weight, segs); | |
b30d936f | 2623 | pnv_pci_ioda1_setup_dma_pe(phb, pe, base, segs); |
5d2aa710 | 2624 | } else if (phb->type == PNV_PHB_IODA2) { |
373f5657 GS |
2625 | pe_info(pe, "Assign DMA32 space\n"); |
2626 | segs = 0; | |
2627 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
5d2aa710 AP |
2628 | } else if (phb->type == PNV_PHB_NPU) { |
2629 | /* | |
2630 | * We initialise the DMA space for an NPU PHB | |
2631 | * after setup of the PHB is complete as we | |
2632 | * point the NPU TVT to the the same location | |
2633 | * as the PHB3 TVT. | |
2634 | */ | |
373f5657 GS |
2635 | } |
2636 | ||
184cd4a3 BH |
2637 | remaining -= segs; |
2638 | base += segs; | |
2639 | } | |
2640 | } | |
2641 | ||
2642 | #ifdef CONFIG_PCI_MSI | |
137436c9 GS |
2643 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
2644 | { | |
2645 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); | |
2646 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
2647 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, | |
2648 | ioda.irq_chip); | |
2649 | int64_t rc; | |
2650 | ||
2651 | rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
2652 | WARN_ON_ONCE(rc); | |
2653 | ||
2654 | icp_native_eoi(d); | |
2655 | } | |
2656 | ||
fd9a1c26 IM |
2657 | |
2658 | static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) | |
2659 | { | |
2660 | struct irq_data *idata; | |
2661 | struct irq_chip *ichip; | |
2662 | ||
2663 | if (phb->type != PNV_PHB_IODA2) | |
2664 | return; | |
2665 | ||
2666 | if (!phb->ioda.irq_chip_init) { | |
2667 | /* | |
2668 | * First time we setup an MSI IRQ, we need to setup the | |
2669 | * corresponding IRQ chip to route correctly. | |
2670 | */ | |
2671 | idata = irq_get_irq_data(virq); | |
2672 | ichip = irq_data_get_irq_chip(idata); | |
2673 | phb->ioda.irq_chip_init = 1; | |
2674 | phb->ioda.irq_chip = *ichip; | |
2675 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
2676 | } | |
2677 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
2678 | } | |
2679 | ||
80c49c7e IM |
2680 | #ifdef CONFIG_CXL_BASE |
2681 | ||
6f963ec2 | 2682 | struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) |
80c49c7e IM |
2683 | { |
2684 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2685 | ||
6f963ec2 | 2686 | return of_node_get(hose->dn); |
80c49c7e | 2687 | } |
6f963ec2 | 2688 | EXPORT_SYMBOL(pnv_pci_get_phb_node); |
80c49c7e | 2689 | |
1212aa1c | 2690 | int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) |
80c49c7e IM |
2691 | { |
2692 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2693 | struct pnv_phb *phb = hose->private_data; | |
2694 | struct pnv_ioda_pe *pe; | |
2695 | int rc; | |
2696 | ||
2697 | pe = pnv_ioda_get_pe(dev); | |
2698 | if (!pe) | |
2699 | return -ENODEV; | |
2700 | ||
2701 | pe_info(pe, "Switching PHB to CXL\n"); | |
2702 | ||
1212aa1c | 2703 | rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); |
80c49c7e IM |
2704 | if (rc) |
2705 | dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); | |
2706 | ||
2707 | return rc; | |
2708 | } | |
1212aa1c | 2709 | EXPORT_SYMBOL(pnv_phb_to_cxl_mode); |
80c49c7e IM |
2710 | |
2711 | /* Find PHB for cxl dev and allocate MSI hwirqs? | |
2712 | * Returns the absolute hardware IRQ number | |
2713 | */ | |
2714 | int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) | |
2715 | { | |
2716 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2717 | struct pnv_phb *phb = hose->private_data; | |
2718 | int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); | |
2719 | ||
2720 | if (hwirq < 0) { | |
2721 | dev_warn(&dev->dev, "Failed to find a free MSI\n"); | |
2722 | return -ENOSPC; | |
2723 | } | |
2724 | ||
2725 | return phb->msi_base + hwirq; | |
2726 | } | |
2727 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); | |
2728 | ||
2729 | void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) | |
2730 | { | |
2731 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2732 | struct pnv_phb *phb = hose->private_data; | |
2733 | ||
2734 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); | |
2735 | } | |
2736 | EXPORT_SYMBOL(pnv_cxl_release_hwirqs); | |
2737 | ||
2738 | void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
2739 | struct pci_dev *dev) | |
2740 | { | |
2741 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2742 | struct pnv_phb *phb = hose->private_data; | |
2743 | int i, hwirq; | |
2744 | ||
2745 | for (i = 1; i < CXL_IRQ_RANGES; i++) { | |
2746 | if (!irqs->range[i]) | |
2747 | continue; | |
2748 | pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", | |
2749 | i, irqs->offset[i], | |
2750 | irqs->range[i]); | |
2751 | hwirq = irqs->offset[i] - phb->msi_base; | |
2752 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, | |
2753 | irqs->range[i]); | |
2754 | } | |
2755 | } | |
2756 | EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); | |
2757 | ||
2758 | int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
2759 | struct pci_dev *dev, int num) | |
2760 | { | |
2761 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2762 | struct pnv_phb *phb = hose->private_data; | |
2763 | int i, hwirq, try; | |
2764 | ||
2765 | memset(irqs, 0, sizeof(struct cxl_irq_ranges)); | |
2766 | ||
2767 | /* 0 is reserved for the multiplexed PSL DSI interrupt */ | |
2768 | for (i = 1; i < CXL_IRQ_RANGES && num; i++) { | |
2769 | try = num; | |
2770 | while (try) { | |
2771 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); | |
2772 | if (hwirq >= 0) | |
2773 | break; | |
2774 | try /= 2; | |
2775 | } | |
2776 | if (!try) | |
2777 | goto fail; | |
2778 | ||
2779 | irqs->offset[i] = phb->msi_base + hwirq; | |
2780 | irqs->range[i] = try; | |
2781 | pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", | |
2782 | i, irqs->offset[i], irqs->range[i]); | |
2783 | num -= try; | |
2784 | } | |
2785 | if (num) | |
2786 | goto fail; | |
2787 | ||
2788 | return 0; | |
2789 | fail: | |
2790 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
2791 | return -ENOSPC; | |
2792 | } | |
2793 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); | |
2794 | ||
2795 | int pnv_cxl_get_irq_count(struct pci_dev *dev) | |
2796 | { | |
2797 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2798 | struct pnv_phb *phb = hose->private_data; | |
2799 | ||
2800 | return phb->msi_bmp.irq_count; | |
2801 | } | |
2802 | EXPORT_SYMBOL(pnv_cxl_get_irq_count); | |
2803 | ||
2804 | int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, | |
2805 | unsigned int virq) | |
2806 | { | |
2807 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2808 | struct pnv_phb *phb = hose->private_data; | |
2809 | unsigned int xive_num = hwirq - phb->msi_base; | |
2810 | struct pnv_ioda_pe *pe; | |
2811 | int rc; | |
2812 | ||
2813 | if (!(pe = pnv_ioda_get_pe(dev))) | |
2814 | return -ENODEV; | |
2815 | ||
2816 | /* Assign XIVE to PE */ | |
2817 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2818 | if (rc) { | |
2819 | pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " | |
2820 | "hwirq 0x%x XIVE 0x%x PE\n", | |
2821 | pci_name(dev), rc, phb->msi_base, hwirq, xive_num); | |
2822 | return -EIO; | |
2823 | } | |
2824 | set_msi_irq_chip(phb, virq); | |
2825 | ||
2826 | return 0; | |
2827 | } | |
2828 | EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); | |
2829 | #endif | |
2830 | ||
184cd4a3 | 2831 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
2832 | unsigned int hwirq, unsigned int virq, |
2833 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
2834 | { |
2835 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
2836 | unsigned int xive_num = hwirq - phb->msi_base; | |
3a1a4661 | 2837 | __be32 data; |
184cd4a3 BH |
2838 | int rc; |
2839 | ||
2840 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
2841 | if (pe == NULL) | |
2842 | return -ENXIO; | |
2843 | ||
2844 | /* Check if we have an MVE */ | |
2845 | if (pe->mve_number < 0) | |
2846 | return -ENXIO; | |
2847 | ||
b72c1f65 | 2848 | /* Force 32-bit MSI on some broken devices */ |
36074381 | 2849 | if (dev->no_64bit_msi) |
b72c1f65 BH |
2850 | is_64 = 0; |
2851 | ||
184cd4a3 BH |
2852 | /* Assign XIVE to PE */ |
2853 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2854 | if (rc) { | |
2855 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
2856 | pci_name(dev), rc, xive_num); | |
2857 | return -EIO; | |
2858 | } | |
2859 | ||
2860 | if (is_64) { | |
3a1a4661 BH |
2861 | __be64 addr64; |
2862 | ||
184cd4a3 BH |
2863 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
2864 | &addr64, &data); | |
2865 | if (rc) { | |
2866 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
2867 | pci_name(dev), rc); | |
2868 | return -EIO; | |
2869 | } | |
3a1a4661 BH |
2870 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
2871 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 2872 | } else { |
3a1a4661 BH |
2873 | __be32 addr32; |
2874 | ||
184cd4a3 BH |
2875 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
2876 | &addr32, &data); | |
2877 | if (rc) { | |
2878 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
2879 | pci_name(dev), rc); | |
2880 | return -EIO; | |
2881 | } | |
2882 | msg->address_hi = 0; | |
3a1a4661 | 2883 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 2884 | } |
3a1a4661 | 2885 | msg->data = be32_to_cpu(data); |
184cd4a3 | 2886 | |
fd9a1c26 | 2887 | set_msi_irq_chip(phb, virq); |
137436c9 | 2888 | |
184cd4a3 BH |
2889 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
2890 | " address=%x_%08x data=%x PE# %d\n", | |
2891 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, | |
2892 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
2893 | ||
2894 | return 0; | |
2895 | } | |
2896 | ||
2897 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
2898 | { | |
fb1b55d6 | 2899 | unsigned int count; |
184cd4a3 BH |
2900 | const __be32 *prop = of_get_property(phb->hose->dn, |
2901 | "ibm,opal-msi-ranges", NULL); | |
2902 | if (!prop) { | |
2903 | /* BML Fallback */ | |
2904 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
2905 | } | |
2906 | if (!prop) | |
2907 | return; | |
2908 | ||
2909 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
2910 | count = be32_to_cpup(prop + 1); |
2911 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
2912 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
2913 | phb->hose->global_number); | |
2914 | return; | |
2915 | } | |
fb1b55d6 | 2916 | |
184cd4a3 BH |
2917 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
2918 | phb->msi32_support = 1; | |
2919 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 2920 | count, phb->msi_base); |
184cd4a3 BH |
2921 | } |
2922 | #else | |
2923 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
2924 | #endif /* CONFIG_PCI_MSI */ | |
2925 | ||
6e628c7d WY |
2926 | #ifdef CONFIG_PCI_IOV |
2927 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) | |
2928 | { | |
f2dd0afe WY |
2929 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
2930 | struct pnv_phb *phb = hose->private_data; | |
2931 | const resource_size_t gate = phb->ioda.m64_segsize >> 2; | |
6e628c7d WY |
2932 | struct resource *res; |
2933 | int i; | |
dfcc8d45 | 2934 | resource_size_t size, total_vf_bar_sz; |
6e628c7d | 2935 | struct pci_dn *pdn; |
5b88ec22 | 2936 | int mul, total_vfs; |
6e628c7d WY |
2937 | |
2938 | if (!pdev->is_physfn || pdev->is_added) | |
2939 | return; | |
2940 | ||
6e628c7d WY |
2941 | pdn = pci_get_pdn(pdev); |
2942 | pdn->vfs_expanded = 0; | |
ee8222fe | 2943 | pdn->m64_single_mode = false; |
6e628c7d | 2944 | |
5b88ec22 | 2945 | total_vfs = pci_sriov_get_totalvfs(pdev); |
92b8f137 | 2946 | mul = phb->ioda.total_pe_num; |
dfcc8d45 | 2947 | total_vf_bar_sz = 0; |
5b88ec22 WY |
2948 | |
2949 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
2950 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2951 | if (!res->flags || res->parent) | |
2952 | continue; | |
2953 | if (!pnv_pci_is_mem_pref_64(res->flags)) { | |
b0331854 WY |
2954 | dev_warn(&pdev->dev, "Don't support SR-IOV with" |
2955 | " non M64 VF BAR%d: %pR. \n", | |
5b88ec22 | 2956 | i, res); |
b0331854 | 2957 | goto truncate_iov; |
5b88ec22 WY |
2958 | } |
2959 | ||
dfcc8d45 WY |
2960 | total_vf_bar_sz += pci_iov_resource_size(pdev, |
2961 | i + PCI_IOV_RESOURCES); | |
5b88ec22 | 2962 | |
f2dd0afe WY |
2963 | /* |
2964 | * If bigger than quarter of M64 segment size, just round up | |
2965 | * power of two. | |
2966 | * | |
2967 | * Generally, one M64 BAR maps one IOV BAR. To avoid conflict | |
2968 | * with other devices, IOV BAR size is expanded to be | |
2969 | * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 | |
2970 | * segment size , the expanded size would equal to half of the | |
2971 | * whole M64 space size, which will exhaust the M64 Space and | |
2972 | * limit the system flexibility. This is a design decision to | |
2973 | * set the boundary to quarter of the M64 segment size. | |
2974 | */ | |
dfcc8d45 | 2975 | if (total_vf_bar_sz > gate) { |
5b88ec22 | 2976 | mul = roundup_pow_of_two(total_vfs); |
dfcc8d45 WY |
2977 | dev_info(&pdev->dev, |
2978 | "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", | |
2979 | total_vf_bar_sz, gate, mul); | |
ee8222fe | 2980 | pdn->m64_single_mode = true; |
5b88ec22 WY |
2981 | break; |
2982 | } | |
2983 | } | |
2984 | ||
6e628c7d WY |
2985 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
2986 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2987 | if (!res->flags || res->parent) | |
2988 | continue; | |
6e628c7d | 2989 | |
6e628c7d | 2990 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); |
ee8222fe WY |
2991 | /* |
2992 | * On PHB3, the minimum size alignment of M64 BAR in single | |
2993 | * mode is 32MB. | |
2994 | */ | |
2995 | if (pdn->m64_single_mode && (size < SZ_32M)) | |
2996 | goto truncate_iov; | |
2997 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); | |
5b88ec22 | 2998 | res->end = res->start + size * mul - 1; |
6e628c7d WY |
2999 | dev_dbg(&pdev->dev, " %pR\n", res); |
3000 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", | |
5b88ec22 | 3001 | i, res, mul); |
6e628c7d | 3002 | } |
5b88ec22 | 3003 | pdn->vfs_expanded = mul; |
b0331854 WY |
3004 | |
3005 | return; | |
3006 | ||
3007 | truncate_iov: | |
3008 | /* To save MMIO space, IOV BAR is truncated. */ | |
3009 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
3010 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
3011 | res->flags = 0; | |
3012 | res->end = res->start - 1; | |
3013 | } | |
6e628c7d WY |
3014 | } |
3015 | #endif /* CONFIG_PCI_IOV */ | |
3016 | ||
23e79425 GS |
3017 | static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, |
3018 | struct resource *res) | |
3019 | { | |
3020 | struct pnv_phb *phb = pe->phb; | |
3021 | struct pci_bus_region region; | |
3022 | int index; | |
3023 | int64_t rc; | |
3024 | ||
3025 | if (!res || !res->flags || res->start > res->end) | |
3026 | return; | |
3027 | ||
3028 | if (res->flags & IORESOURCE_IO) { | |
3029 | region.start = res->start - phb->ioda.io_pci_base; | |
3030 | region.end = res->end - phb->ioda.io_pci_base; | |
3031 | index = region.start / phb->ioda.io_segsize; | |
3032 | ||
3033 | while (index < phb->ioda.total_pe_num && | |
3034 | region.start <= region.end) { | |
3035 | phb->ioda.io_segmap[index] = pe->pe_number; | |
3036 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3037 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
3038 | if (rc != OPAL_SUCCESS) { | |
3039 | pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", | |
3040 | __func__, rc, index, pe->pe_number); | |
3041 | break; | |
3042 | } | |
3043 | ||
3044 | region.start += phb->ioda.io_segsize; | |
3045 | index++; | |
3046 | } | |
3047 | } else if ((res->flags & IORESOURCE_MEM) && | |
3048 | !pnv_pci_is_mem_pref_64(res->flags)) { | |
3049 | region.start = res->start - | |
3050 | phb->hose->mem_offset[0] - | |
3051 | phb->ioda.m32_pci_base; | |
3052 | region.end = res->end - | |
3053 | phb->hose->mem_offset[0] - | |
3054 | phb->ioda.m32_pci_base; | |
3055 | index = region.start / phb->ioda.m32_segsize; | |
3056 | ||
3057 | while (index < phb->ioda.total_pe_num && | |
3058 | region.start <= region.end) { | |
3059 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
3060 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3061 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
3062 | if (rc != OPAL_SUCCESS) { | |
3063 | pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", | |
3064 | __func__, rc, index, pe->pe_number); | |
3065 | break; | |
3066 | } | |
3067 | ||
3068 | region.start += phb->ioda.m32_segsize; | |
3069 | index++; | |
3070 | } | |
3071 | } | |
3072 | } | |
3073 | ||
11685bec GS |
3074 | /* |
3075 | * This function is supposed to be called on basis of PE from top | |
3076 | * to bottom style. So the the I/O or MMIO segment assigned to | |
3077 | * parent PE could be overrided by its child PEs if necessary. | |
3078 | */ | |
23e79425 | 3079 | static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) |
11685bec | 3080 | { |
69d733e7 | 3081 | struct pci_dev *pdev; |
23e79425 | 3082 | int i; |
11685bec GS |
3083 | |
3084 | /* | |
3085 | * NOTE: We only care PCI bus based PE for now. For PCI | |
3086 | * device based PE, for example SRIOV sensitive VF should | |
3087 | * be figured out later. | |
3088 | */ | |
3089 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
3090 | ||
69d733e7 GS |
3091 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
3092 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
3093 | pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); | |
3094 | ||
3095 | /* | |
3096 | * If the PE contains all subordinate PCI buses, the | |
3097 | * windows of the child bridges should be mapped to | |
3098 | * the PE as well. | |
3099 | */ | |
3100 | if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) | |
3101 | continue; | |
3102 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
3103 | pnv_ioda_setup_pe_res(pe, | |
3104 | &pdev->resource[PCI_BRIDGE_RESOURCES + i]); | |
3105 | } | |
11685bec GS |
3106 | } |
3107 | ||
cad5cef6 | 3108 | static void pnv_pci_ioda_setup_seg(void) |
11685bec GS |
3109 | { |
3110 | struct pci_controller *tmp, *hose; | |
3111 | struct pnv_phb *phb; | |
3112 | struct pnv_ioda_pe *pe; | |
3113 | ||
3114 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3115 | phb = hose->private_data; | |
5d2aa710 AP |
3116 | |
3117 | /* NPU PHB does not support IO or MMIO segmentation */ | |
3118 | if (phb->type == PNV_PHB_NPU) | |
3119 | continue; | |
3120 | ||
11685bec | 3121 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
23e79425 | 3122 | pnv_ioda_setup_pe_seg(pe); |
11685bec GS |
3123 | } |
3124 | } | |
3125 | } | |
3126 | ||
cad5cef6 | 3127 | static void pnv_pci_ioda_setup_DMA(void) |
13395c48 GS |
3128 | { |
3129 | struct pci_controller *hose, *tmp; | |
db1266c8 | 3130 | struct pnv_phb *phb; |
13395c48 GS |
3131 | |
3132 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3133 | pnv_ioda_setup_dma(hose->private_data); | |
db1266c8 GS |
3134 | |
3135 | /* Mark the PHB initialization done */ | |
3136 | phb = hose->private_data; | |
3137 | phb->initialized = 1; | |
13395c48 GS |
3138 | } |
3139 | } | |
3140 | ||
37c367f2 GS |
3141 | static void pnv_pci_ioda_create_dbgfs(void) |
3142 | { | |
3143 | #ifdef CONFIG_DEBUG_FS | |
3144 | struct pci_controller *hose, *tmp; | |
3145 | struct pnv_phb *phb; | |
3146 | char name[16]; | |
3147 | ||
3148 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3149 | phb = hose->private_data; | |
3150 | ||
3151 | sprintf(name, "PCI%04x", hose->global_number); | |
3152 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
3153 | if (!phb->dbgfs) | |
3154 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", | |
3155 | __func__, hose->global_number); | |
3156 | } | |
3157 | #endif /* CONFIG_DEBUG_FS */ | |
3158 | } | |
3159 | ||
5d2aa710 AP |
3160 | static void pnv_npu_ioda_fixup(void) |
3161 | { | |
3162 | bool enable_bypass; | |
3163 | struct pci_controller *hose, *tmp; | |
3164 | struct pnv_phb *phb; | |
3165 | struct pnv_ioda_pe *pe; | |
3166 | ||
3167 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3168 | phb = hose->private_data; | |
3169 | if (phb->type != PNV_PHB_NPU) | |
3170 | continue; | |
3171 | ||
3172 | list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { | |
3173 | enable_bypass = dma_get_mask(&pe->pdev->dev) == | |
3174 | DMA_BIT_MASK(64); | |
3175 | pnv_npu_init_dma_pe(pe); | |
3176 | pnv_npu_dma_set_bypass(pe, enable_bypass); | |
3177 | } | |
3178 | } | |
3179 | } | |
3180 | ||
cad5cef6 | 3181 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
3182 | { |
3183 | pnv_pci_ioda_setup_PEs(); | |
11685bec | 3184 | pnv_pci_ioda_setup_seg(); |
13395c48 | 3185 | pnv_pci_ioda_setup_DMA(); |
e9cc17d4 | 3186 | |
37c367f2 GS |
3187 | pnv_pci_ioda_create_dbgfs(); |
3188 | ||
e9cc17d4 | 3189 | #ifdef CONFIG_EEH |
e9cc17d4 | 3190 | eeh_init(); |
dadcd6d6 | 3191 | eeh_addr_cache_build(); |
e9cc17d4 | 3192 | #endif |
5d2aa710 AP |
3193 | |
3194 | /* Link NPU IODA tables to their PCI devices. */ | |
3195 | pnv_npu_ioda_fixup(); | |
fb446ad0 GS |
3196 | } |
3197 | ||
271fd03a GS |
3198 | /* |
3199 | * Returns the alignment for I/O or memory windows for P2P | |
3200 | * bridges. That actually depends on how PEs are segmented. | |
3201 | * For now, we return I/O or M32 segment size for PE sensitive | |
3202 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
3203 | * 1MiB for memory) will be returned. | |
3204 | * | |
3205 | * The current PCI bus might be put into one PE, which was | |
3206 | * create against the parent PCI bridge. For that case, we | |
3207 | * needn't enlarge the alignment so that we can save some | |
3208 | * resources. | |
3209 | */ | |
3210 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
3211 | unsigned long type) | |
3212 | { | |
3213 | struct pci_dev *bridge; | |
3214 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3215 | struct pnv_phb *phb = hose->private_data; | |
3216 | int num_pci_bridges = 0; | |
3217 | ||
3218 | bridge = bus->self; | |
3219 | while (bridge) { | |
3220 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
3221 | num_pci_bridges++; | |
3222 | if (num_pci_bridges >= 2) | |
3223 | return 1; | |
3224 | } | |
3225 | ||
3226 | bridge = bridge->bus->self; | |
3227 | } | |
3228 | ||
262af557 GC |
3229 | /* We fail back to M32 if M64 isn't supported */ |
3230 | if (phb->ioda.m64_segsize && | |
3231 | pnv_pci_is_mem_pref_64(type)) | |
3232 | return phb->ioda.m64_segsize; | |
271fd03a GS |
3233 | if (type & IORESOURCE_MEM) |
3234 | return phb->ioda.m32_segsize; | |
3235 | ||
3236 | return phb->ioda.io_segsize; | |
3237 | } | |
3238 | ||
5350ab3f WY |
3239 | #ifdef CONFIG_PCI_IOV |
3240 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, | |
3241 | int resno) | |
3242 | { | |
ee8222fe WY |
3243 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
3244 | struct pnv_phb *phb = hose->private_data; | |
5350ab3f | 3245 | struct pci_dn *pdn = pci_get_pdn(pdev); |
7fbe7a93 | 3246 | resource_size_t align; |
5350ab3f | 3247 | |
7fbe7a93 WY |
3248 | /* |
3249 | * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the | |
3250 | * SR-IOV. While from hardware perspective, the range mapped by M64 | |
3251 | * BAR should be size aligned. | |
3252 | * | |
ee8222fe WY |
3253 | * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra |
3254 | * powernv-specific hardware restriction is gone. But if just use the | |
3255 | * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with | |
3256 | * in one segment of M64 #15, which introduces the PE conflict between | |
3257 | * PF and VF. Based on this, the minimum alignment of an IOV BAR is | |
3258 | * m64_segsize. | |
3259 | * | |
7fbe7a93 WY |
3260 | * This function returns the total IOV BAR size if M64 BAR is in |
3261 | * Shared PE mode or just VF BAR size if not. | |
ee8222fe WY |
3262 | * If the M64 BAR is in Single PE mode, return the VF BAR size or |
3263 | * M64 segment size if IOV BAR size is less. | |
7fbe7a93 | 3264 | */ |
5350ab3f | 3265 | align = pci_iov_resource_size(pdev, resno); |
7fbe7a93 WY |
3266 | if (!pdn->vfs_expanded) |
3267 | return align; | |
ee8222fe WY |
3268 | if (pdn->m64_single_mode) |
3269 | return max(align, (resource_size_t)phb->ioda.m64_segsize); | |
5350ab3f | 3270 | |
7fbe7a93 | 3271 | return pdn->vfs_expanded * align; |
5350ab3f WY |
3272 | } |
3273 | #endif /* CONFIG_PCI_IOV */ | |
3274 | ||
184cd4a3 BH |
3275 | /* Prevent enabling devices for which we couldn't properly |
3276 | * assign a PE | |
3277 | */ | |
c88c2a18 | 3278 | static bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 3279 | { |
db1266c8 GS |
3280 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
3281 | struct pnv_phb *phb = hose->private_data; | |
3282 | struct pci_dn *pdn; | |
184cd4a3 | 3283 | |
db1266c8 GS |
3284 | /* The function is probably called while the PEs have |
3285 | * not be created yet. For example, resource reassignment | |
3286 | * during PCI probe period. We just skip the check if | |
3287 | * PEs isn't ready. | |
3288 | */ | |
3289 | if (!phb->initialized) | |
c88c2a18 | 3290 | return true; |
db1266c8 | 3291 | |
b72c1f65 | 3292 | pdn = pci_get_pdn(dev); |
184cd4a3 | 3293 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
c88c2a18 | 3294 | return false; |
db1266c8 | 3295 | |
c88c2a18 | 3296 | return true; |
184cd4a3 BH |
3297 | } |
3298 | ||
7a8e6bbf | 3299 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
73ed148a | 3300 | { |
7a8e6bbf MN |
3301 | struct pnv_phb *phb = hose->private_data; |
3302 | ||
d1a85eee | 3303 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
73ed148a BH |
3304 | OPAL_ASSERT_RESET); |
3305 | } | |
3306 | ||
92ae0353 | 3307 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
cb4224c5 GS |
3308 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
3309 | .dma_bus_setup = pnv_pci_dma_bus_setup, | |
92ae0353 | 3310 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3311 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3312 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
92ae0353 | 3313 | #endif |
cb4224c5 GS |
3314 | .enable_device_hook = pnv_pci_enable_device_hook, |
3315 | .window_alignment = pnv_pci_window_alignment, | |
3316 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3317 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, | |
3318 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, | |
3319 | .shutdown = pnv_pci_ioda_shutdown, | |
92ae0353 DA |
3320 | }; |
3321 | ||
5d2aa710 | 3322 | static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { |
cb4224c5 | 3323 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
5d2aa710 | 3324 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3325 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3326 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
5d2aa710 | 3327 | #endif |
cb4224c5 GS |
3328 | .enable_device_hook = pnv_pci_enable_device_hook, |
3329 | .window_alignment = pnv_pci_window_alignment, | |
3330 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3331 | .dma_set_mask = pnv_npu_dma_set_mask, | |
3332 | .shutdown = pnv_pci_ioda_shutdown, | |
5d2aa710 AP |
3333 | }; |
3334 | ||
e51df2c1 AB |
3335 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
3336 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
3337 | { |
3338 | struct pci_controller *hose; | |
184cd4a3 | 3339 | struct pnv_phb *phb; |
93289d8c | 3340 | unsigned long size, m64map_off, m32map_off, pemap_off, iomap_off = 0; |
c681b93c | 3341 | const __be64 *prop64; |
3a1a4661 | 3342 | const __be32 *prop32; |
f1b7cc3e | 3343 | int len; |
3fa23ff8 | 3344 | unsigned int segno; |
184cd4a3 BH |
3345 | u64 phb_id; |
3346 | void *aux; | |
3347 | long rc; | |
3348 | ||
58d714ec | 3349 | pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); |
184cd4a3 BH |
3350 | |
3351 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
3352 | if (!prop64) { | |
3353 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
3354 | return; | |
3355 | } | |
3356 | phb_id = be64_to_cpup(prop64); | |
3357 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
3358 | ||
e39f223f | 3359 | phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); |
58d714ec GS |
3360 | |
3361 | /* Allocate PCI controller */ | |
58d714ec GS |
3362 | phb->hose = hose = pcibios_alloc_controller(np); |
3363 | if (!phb->hose) { | |
3364 | pr_err(" Can't allocate PCI controller for %s\n", | |
184cd4a3 | 3365 | np->full_name); |
e39f223f | 3366 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
184cd4a3 BH |
3367 | return; |
3368 | } | |
3369 | ||
3370 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
3371 | prop32 = of_get_property(np, "bus-range", &len); |
3372 | if (prop32 && len == 8) { | |
3a1a4661 BH |
3373 | hose->first_busno = be32_to_cpu(prop32[0]); |
3374 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e GS |
3375 | } else { |
3376 | pr_warn(" Broken <bus-range> on %s\n", np->full_name); | |
3377 | hose->first_busno = 0; | |
3378 | hose->last_busno = 0xff; | |
3379 | } | |
184cd4a3 | 3380 | hose->private_data = phb; |
e9cc17d4 | 3381 | phb->hub_id = hub_id; |
184cd4a3 | 3382 | phb->opal_id = phb_id; |
aa0c033f | 3383 | phb->type = ioda_type; |
781a868f | 3384 | mutex_init(&phb->ioda.pe_alloc_mutex); |
184cd4a3 | 3385 | |
cee72d5b BH |
3386 | /* Detect specific models for error handling */ |
3387 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
3388 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 3389 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 3390 | phb->model = PNV_PHB_MODEL_PHB3; |
5d2aa710 AP |
3391 | else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) |
3392 | phb->model = PNV_PHB_MODEL_NPU; | |
cee72d5b BH |
3393 | else |
3394 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
3395 | ||
aa0c033f | 3396 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 3397 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 3398 | |
aa0c033f | 3399 | /* Get registers */ |
184cd4a3 BH |
3400 | phb->regs = of_iomap(np, 0); |
3401 | if (phb->regs == NULL) | |
3402 | pr_err(" Failed to map registers !\n"); | |
3403 | ||
184cd4a3 | 3404 | /* Initialize more IODA stuff */ |
92b8f137 | 3405 | phb->ioda.total_pe_num = 1; |
aa0c033f | 3406 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 3407 | if (prop32) |
92b8f137 | 3408 | phb->ioda.total_pe_num = be32_to_cpup(prop32); |
36954dc7 GS |
3409 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
3410 | if (prop32) | |
92b8f137 | 3411 | phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); |
262af557 GC |
3412 | |
3413 | /* Parse 64-bit MMIO range */ | |
3414 | pnv_ioda_parse_m64_window(phb); | |
3415 | ||
184cd4a3 | 3416 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 3417 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
3418 | phb->ioda.m32_size += 0x10000; |
3419 | ||
92b8f137 | 3420 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; |
3fd47f06 | 3421 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 | 3422 | phb->ioda.io_size = hose->pci_io_size; |
92b8f137 | 3423 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; |
184cd4a3 BH |
3424 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ |
3425 | ||
c35d2a8c | 3426 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
92b8f137 | 3427 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
93289d8c GS |
3428 | m64map_off = size; |
3429 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); | |
184cd4a3 | 3430 | m32map_off = size; |
92b8f137 | 3431 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
3432 | if (phb->type == PNV_PHB_IODA1) { |
3433 | iomap_off = size; | |
92b8f137 | 3434 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); |
c35d2a8c | 3435 | } |
184cd4a3 | 3436 | pemap_off = size; |
92b8f137 | 3437 | size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); |
e39f223f | 3438 | aux = memblock_virt_alloc(size, 0); |
184cd4a3 | 3439 | phb->ioda.pe_alloc = aux; |
93289d8c | 3440 | phb->ioda.m64_segmap = aux + m64map_off; |
184cd4a3 | 3441 | phb->ioda.m32_segmap = aux + m32map_off; |
93289d8c GS |
3442 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { |
3443 | phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3444 | phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; |
93289d8c | 3445 | } |
3fa23ff8 | 3446 | if (phb->type == PNV_PHB_IODA1) { |
c35d2a8c | 3447 | phb->ioda.io_segmap = aux + iomap_off; |
3fa23ff8 GS |
3448 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) |
3449 | phb->ioda.io_segmap[segno] = IODA_INVALID_PE; | |
3450 | } | |
184cd4a3 | 3451 | phb->ioda.pe_array = aux + pemap_off; |
92b8f137 | 3452 | set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); |
184cd4a3 | 3453 | |
7ebdf956 | 3454 | INIT_LIST_HEAD(&phb->ioda.pe_dma_list); |
184cd4a3 | 3455 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
781a868f | 3456 | mutex_init(&phb->ioda.pe_list_mutex); |
184cd4a3 BH |
3457 | |
3458 | /* Calculate how many 32-bit TCE segments we have */ | |
3459 | phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; | |
3460 | ||
aa0c033f | 3461 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
3462 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
3463 | window_type, | |
3464 | window_num, | |
3465 | starting_real_address, | |
3466 | starting_pci_address, | |
3467 | segment_size); | |
3468 | #endif | |
3469 | ||
262af557 | 3470 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
92b8f137 | 3471 | phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, |
262af557 GC |
3472 | phb->ioda.m32_size, phb->ioda.m32_segsize); |
3473 | if (phb->ioda.m64_size) | |
3474 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", | |
3475 | phb->ioda.m64_size, phb->ioda.m64_segsize); | |
3476 | if (phb->ioda.io_size) | |
3477 | pr_info(" IO: 0x%x [segment=0x%x]\n", | |
3478 | phb->ioda.io_size, phb->ioda.io_segsize); | |
3479 | ||
184cd4a3 | 3480 | |
184cd4a3 | 3481 | phb->hose->ops = &pnv_pci_ops; |
49dec922 GS |
3482 | phb->get_pe_state = pnv_ioda_get_pe_state; |
3483 | phb->freeze_pe = pnv_ioda_freeze_pe; | |
3484 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | |
184cd4a3 | 3485 | |
184cd4a3 BH |
3486 | /* Setup TCEs */ |
3487 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
3488 | ||
3489 | /* Setup MSI support */ | |
3490 | pnv_pci_init_ioda_msis(phb); | |
3491 | ||
c40a4210 GS |
3492 | /* |
3493 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
3494 | * to let the PCI core do resource assignment. It's supposed | |
3495 | * that the PCI core will do correct I/O and MMIO alignment | |
3496 | * for the P2P bridge bars so that each PCI bus (excluding | |
3497 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 3498 | */ |
fb446ad0 | 3499 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
5d2aa710 AP |
3500 | |
3501 | if (phb->type == PNV_PHB_NPU) | |
3502 | hose->controller_ops = pnv_npu_ioda_controller_ops; | |
3503 | else | |
3504 | hose->controller_ops = pnv_pci_ioda_controller_ops; | |
ad30cb99 | 3505 | |
6e628c7d WY |
3506 | #ifdef CONFIG_PCI_IOV |
3507 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; | |
5350ab3f | 3508 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
ad30cb99 ME |
3509 | #endif |
3510 | ||
c40a4210 | 3511 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
3512 | |
3513 | /* Reset IODA tables to a clean state */ | |
d1a85eee | 3514 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
184cd4a3 | 3515 | if (rc) |
f11fe552 | 3516 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
361f2a2a GS |
3517 | |
3518 | /* If we're running in kdump kerenl, the previous kerenl never | |
3519 | * shutdown PCI devices correctly. We already got IODA table | |
3520 | * cleaned out. So we have to issue PHB reset to stop all PCI | |
3521 | * transactions from previous kerenl. | |
3522 | */ | |
3523 | if (is_kdump_kernel()) { | |
3524 | pr_info(" Issue PHB reset ...\n"); | |
cadf364d GS |
3525 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
3526 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); | |
361f2a2a | 3527 | } |
262af557 | 3528 | |
9e9e8935 GS |
3529 | /* Remove M64 resource if we can't configure it successfully */ |
3530 | if (!phb->init_m64 || phb->init_m64(phb)) | |
262af557 | 3531 | hose->mem_resources[1].flags = 0; |
aa0c033f GS |
3532 | } |
3533 | ||
67975005 | 3534 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 3535 | { |
e9cc17d4 | 3536 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
3537 | } |
3538 | ||
5d2aa710 AP |
3539 | void __init pnv_pci_init_npu_phb(struct device_node *np) |
3540 | { | |
3541 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); | |
3542 | } | |
3543 | ||
184cd4a3 BH |
3544 | void __init pnv_pci_init_ioda_hub(struct device_node *np) |
3545 | { | |
3546 | struct device_node *phbn; | |
c681b93c | 3547 | const __be64 *prop64; |
184cd4a3 BH |
3548 | u64 hub_id; |
3549 | ||
3550 | pr_info("Probing IODA IO-Hub %s\n", np->full_name); | |
3551 | ||
3552 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
3553 | if (!prop64) { | |
3554 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
3555 | return; | |
3556 | } | |
3557 | hub_id = be64_to_cpup(prop64); | |
3558 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
3559 | ||
3560 | /* Count child PHBs */ | |
3561 | for_each_child_of_node(np, phbn) { | |
3562 | /* Look for IODA1 PHBs */ | |
3563 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 3564 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
3565 | } |
3566 | } |