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powerpc/powernv: Change NPU PE# assignment
[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / powernv / pci-ioda.c
CommitLineData
184cd4a3
BH		 1/*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
cee72d5b 12#undef DEBUG
184cd4a3
BH		 13
14#include <linux/kernel.h>
15#include <linux/pci.h>
361f2a2a 16#include <linux/crash_dump.h>
37c367f2 17#include <linux/debugfs.h>
184cd4a3
BH		 18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/msi.h>
cd15b048 25#include <linux/memblock.h>
ac9a5889 26#include <linux/iommu.h>
e57080f1 27#include <linux/rculist.h>
4793d65d 28#include <linux/sizes.h>
184cd4a3
BH		 29
30#include <asm/sections.h>
31#include <asm/io.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/machdep.h>
fb1b55d6 35#include <asm/msi_bitmap.h>
184cd4a3
BH		 36#include <asm/ppc-pci.h>
37#include <asm/opal.h>
38#include <asm/iommu.h>
39#include <asm/tce.h>
137436c9 40#include <asm/xics.h>
37c367f2 41#include <asm/debug.h>
262af557 42#include <asm/firmware.h>
80c49c7e 43#include <asm/pnv-pci.h>
aca6913f 44#include <asm/mmzone.h>
80c49c7e 45
ec249dd8 46#include <misc/cxl-base.h>
184cd4a3
BH		 47
48#include "powernv.h"
49#include "pci.h"
50
781a868f
WY		 51/* 256M DMA window, 4K TCE pages, 8 bytes TCE */
52#define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
53
bbb845c4
AK		 54#define POWERNV_IOMMU_DEFAULT_LEVELS 1
55#define POWERNV_IOMMU_MAX_LEVELS 5
56
aca6913f
AK		 57static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
58
6d31c2fa
JP		 59static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
60 const char *fmt, ...)
61{
62 struct va_format vaf;
63 va_list args;
64 char pfix[32];
65
66 va_start(args, fmt);
67
68 vaf.fmt = fmt;
69 vaf.va = &args;
70
781a868f 71 if (pe->flags & PNV_IODA_PE_DEV)
6d31c2fa 72 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
781a868f 73 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
6d31c2fa
JP		 74 sprintf(pfix, "%04x:%02x ",
75 pci_domain_nr(pe->pbus), pe->pbus->number);
781a868f
WY		 76#ifdef CONFIG_PCI_IOV
77 else if (pe->flags & PNV_IODA_PE_VF)
78 sprintf(pfix, "%04x:%02x:%2x.%d",
79 pci_domain_nr(pe->parent_dev->bus),
80 (pe->rid & 0xff00) >> 8,
81 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
82#endif /* CONFIG_PCI_IOV*/
6d31c2fa
JP		 83
84 printk("%spci %s: [PE# %.3d] %pV",
85 level, pfix, pe->pe_number, &vaf);
86
87 va_end(args);
88}
184cd4a3 89
6d31c2fa
JP		 90#define pe_err(pe, fmt, ...) \
91 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
92#define pe_warn(pe, fmt, ...) \
93 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
94#define pe_info(pe, fmt, ...) \
95 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
184cd4a3 96
4e287840
TLSC		 97static bool pnv_iommu_bypass_disabled __read_mostly;
98
99static int __init iommu_setup(char *str)
100{
101 if (!str)
102 return -EINVAL;
103
104 while (*str) {
105 if (!strncmp(str, "nobypass", 8)) {
106 pnv_iommu_bypass_disabled = true;
107 pr_info("PowerNV: IOMMU bypass window disabled.\n");
108 break;
109 }
110 str += strcspn(str, ",");
111 if (*str == ',')
112 str++;
113 }
114
115 return 0;
116}
117early_param("iommu", iommu_setup);
118
262af557
GC		 119static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
120{
121 return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
122 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
123}
124
4b82ab18
GS		 125static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
126{
127 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
128 pr_warn("%s: Invalid PE %d on PHB#%x\n",
129 __func__, pe_no, phb->hose->global_number);
130 return;
131 }
132
e9dc4d7f
GS		 133 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
134 pr_debug("%s: PE %d was reserved on PHB#%x\n",
135 __func__, pe_no, phb->hose->global_number);
4b82ab18
GS		 136
137 phb->ioda.pe_array[pe_no].phb = phb;
138 phb->ioda.pe_array[pe_no].pe_number = pe_no;
139}
140
cad5cef6 141static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
184cd4a3
BH		 142{
143 unsigned long pe;
144
145 do {
146 pe = find_next_zero_bit(phb->ioda.pe_alloc,
147 phb->ioda.total_pe, 0);
148 if (pe >= phb->ioda.total_pe)
149 return IODA_INVALID_PE;
150 } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
151
4cce9550 152 phb->ioda.pe_array[pe].phb = phb;
184cd4a3
BH		 153 phb->ioda.pe_array[pe].pe_number = pe;
154 return pe;
155}
156
cad5cef6 157static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
184cd4a3
BH		 158{
159 WARN_ON(phb->ioda.pe_array[pe].pdev);
160
161 memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
162 clear_bit(pe, phb->ioda.pe_alloc);
163}
164
262af557
GC		 165/* The default M64 BAR is shared by all PEs */
166static int pnv_ioda2_init_m64(struct pnv_phb *phb)
167{
168 const char *desc;
169 struct resource *r;
170 s64 rc;
171
172 /* Configure the default M64 BAR */
173 rc = opal_pci_set_phb_mem_window(phb->opal_id,
174 OPAL_M64_WINDOW_TYPE,
175 phb->ioda.m64_bar_idx,
176 phb->ioda.m64_base,
177 0, /* unused */
178 phb->ioda.m64_size);
179 if (rc != OPAL_SUCCESS) {
180 desc = "configuring";
181 goto fail;
182 }
183
184 /* Enable the default M64 BAR */
185 rc = opal_pci_phb_mmio_enable(phb->opal_id,
186 OPAL_M64_WINDOW_TYPE,
187 phb->ioda.m64_bar_idx,
188 OPAL_ENABLE_M64_SPLIT);
189 if (rc != OPAL_SUCCESS) {
190 desc = "enabling";
191 goto fail;
192 }
193
194 /* Mark the M64 BAR assigned */
195 set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
196
197 /*
198 * Strip off the segment used by the reserved PE, which is
199 * expected to be 0 or last one of PE capabicity.
200 */
201 r = &phb->hose->mem_resources[1];
202 if (phb->ioda.reserved_pe == 0)
203 r->start += phb->ioda.m64_segsize;
204 else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
205 r->end -= phb->ioda.m64_segsize;
206 else
207 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
208 phb->ioda.reserved_pe);
209
210 return 0;
211
212fail:
213 pr_warn(" Failure %lld %s M64 BAR#%d\n",
214 rc, desc, phb->ioda.m64_bar_idx);
215 opal_pci_phb_mmio_enable(phb->opal_id,
216 OPAL_M64_WINDOW_TYPE,
217 phb->ioda.m64_bar_idx,
218 OPAL_DISABLE_M64);
219 return -EIO;
220}
221
96a2f92b
GS		 222static void pnv_ioda2_reserve_dev_m64_pe(struct pci_dev *pdev,
223 unsigned long *pe_bitmap)
262af557 224{
96a2f92b
GS		 225 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
226 struct pnv_phb *phb = hose->private_data;
262af557 227 struct resource *r;
96a2f92b
GS		 228 resource_size_t base, sgsz, start, end;
229 int segno, i;
230
231 base = phb->ioda.m64_base;
232 sgsz = phb->ioda.m64_segsize;
233 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
234 r = &pdev->resource[i];
235 if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
236 continue;
262af557 237
96a2f92b
GS		 238 start = _ALIGN_DOWN(r->start - base, sgsz);
239 end = _ALIGN_UP(r->end - base, sgsz);
240 for (segno = start / sgsz; segno < end / sgsz; segno++) {
241 if (pe_bitmap)
242 set_bit(segno, pe_bitmap);
243 else
244 pnv_ioda_reserve_pe(phb, segno);
262af557
GC		 245 }
246 }
247}
248
96a2f92b
GS		 249static void pnv_ioda2_reserve_m64_pe(struct pci_bus *bus,
250 unsigned long *pe_bitmap,
251 bool all)
262af557 252{
262af557 253 struct pci_dev *pdev;
96a2f92b
GS		 254
255 list_for_each_entry(pdev, &bus->devices, bus_list) {
256 pnv_ioda2_reserve_dev_m64_pe(pdev, pe_bitmap);
257
258 if (all && pdev->subordinate)
259 pnv_ioda2_reserve_m64_pe(pdev->subordinate,
260 pe_bitmap, all);
261 }
262}
263
26ba248d 264static int pnv_ioda2_pick_m64_pe(struct pci_bus *bus, bool all)
262af557 265{
26ba248d
GS		 266 struct pci_controller *hose = pci_bus_to_host(bus);
267 struct pnv_phb *phb = hose->private_data;
262af557
GC		 268 struct pnv_ioda_pe *master_pe, *pe;
269 unsigned long size, *pe_alloc;
26ba248d 270 int i;
262af557
GC		 271
272 /* Root bus shouldn't use M64 */
273 if (pci_is_root_bus(bus))
274 return IODA_INVALID_PE;
275
262af557
GC		 276 /* Allocate bitmap */
277 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
278 pe_alloc = kzalloc(size, GFP_KERNEL);
279 if (!pe_alloc) {
280 pr_warn("%s: Out of memory !\n",
281 __func__);
282 return IODA_INVALID_PE;
283 }
284
26ba248d
GS		 285 /* Figure out reserved PE numbers by the PE */
286 pnv_ioda2_reserve_m64_pe(bus, pe_alloc, all);
262af557
GC		 287
288 /*
289 * the current bus might not own M64 window and that's all
290 * contributed by its child buses. For the case, we needn't
291 * pick M64 dependent PE#.
292 */
293 if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
294 kfree(pe_alloc);
295 return IODA_INVALID_PE;
296 }
297
298 /*
299 * Figure out the master PE and put all slave PEs to master
300 * PE's list to form compound PE.
301 */
262af557
GC		 302 master_pe = NULL;
303 i = -1;
304 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
305 phb->ioda.total_pe) {
306 pe = &phb->ioda.pe_array[i];
262af557
GC		 307
308 if (!master_pe) {
309 pe->flags |= PNV_IODA_PE_MASTER;
310 INIT_LIST_HEAD(&pe->slaves);
311 master_pe = pe;
312 } else {
313 pe->flags |= PNV_IODA_PE_SLAVE;
314 pe->master = master_pe;
315 list_add_tail(&pe->list, &master_pe->slaves);
316 }
317 }
318
319 kfree(pe_alloc);
320 return master_pe->pe_number;
321}
322
323static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
324{
325 struct pci_controller *hose = phb->hose;
326 struct device_node *dn = hose->dn;
327 struct resource *res;
328 const u32 *r;
329 u64 pci_addr;
330
1665c4a8
GS		 331 /* FIXME: Support M64 for P7IOC */
332 if (phb->type != PNV_PHB_IODA2) {
333 pr_info(" Not support M64 window\n");
334 return;
335 }
336
e4d54f71 337 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
262af557
GC		 338 pr_info(" Firmware too old to support M64 window\n");
339 return;
340 }
341
342 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
343 if (!r) {
344 pr_info(" No <ibm,opal-m64-window> on %s\n",
345 dn->full_name);
346 return;
347 }
348
262af557 349 res = &hose->mem_resources[1];
e80c4e7c 350 res->name = dn->full_name;
262af557
GC		 351 res->start = of_translate_address(dn, r + 2);
352 res->end = res->start + of_read_number(r + 4, 2) - 1;
353 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
354 pci_addr = of_read_number(r, 2);
355 hose->mem_offset[1] = res->start - pci_addr;
356
357 phb->ioda.m64_size = resource_size(res);
358 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
359 phb->ioda.m64_base = pci_addr;
360
e9863e68
WY		 361 pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
362 res->start, res->end, pci_addr);
363
262af557
GC		 364 /* Use last M64 BAR to cover M64 window */
365 phb->ioda.m64_bar_idx = 15;
366 phb->init_m64 = pnv_ioda2_init_m64;
5ef73567 367 phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
262af557
GC		 368 phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
369}
370
49dec922
GS		 371static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
372{
373 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
374 struct pnv_ioda_pe *slave;
375 s64 rc;
376
377 /* Fetch master PE */
378 if (pe->flags & PNV_IODA_PE_SLAVE) {
379 pe = pe->master;
ec8e4e9d
GS		 380 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
381 return;
382
49dec922
GS		 383 pe_no = pe->pe_number;
384 }
385
386 /* Freeze master PE */
387 rc = opal_pci_eeh_freeze_set(phb->opal_id,
388 pe_no,
389 OPAL_EEH_ACTION_SET_FREEZE_ALL);
390 if (rc != OPAL_SUCCESS) {
391 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
392 __func__, rc, phb->hose->global_number, pe_no);
393 return;
394 }
395
396 /* Freeze slave PEs */
397 if (!(pe->flags & PNV_IODA_PE_MASTER))
398 return;
399
400 list_for_each_entry(slave, &pe->slaves, list) {
401 rc = opal_pci_eeh_freeze_set(phb->opal_id,
402 slave->pe_number,
403 OPAL_EEH_ACTION_SET_FREEZE_ALL);
404 if (rc != OPAL_SUCCESS)
405 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
406 __func__, rc, phb->hose->global_number,
407 slave->pe_number);
408 }
409}
410
e51df2c1 411static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
49dec922
GS		 412{
413 struct pnv_ioda_pe *pe, *slave;
414 s64 rc;
415
416 /* Find master PE */
417 pe = &phb->ioda.pe_array[pe_no];
418 if (pe->flags & PNV_IODA_PE_SLAVE) {
419 pe = pe->master;
420 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
421 pe_no = pe->pe_number;
422 }
423
424 /* Clear frozen state for master PE */
425 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
426 if (rc != OPAL_SUCCESS) {
427 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
428 __func__, rc, opt, phb->hose->global_number, pe_no);
429 return -EIO;
430 }
431
432 if (!(pe->flags & PNV_IODA_PE_MASTER))
433 return 0;
434
435 /* Clear frozen state for slave PEs */
436 list_for_each_entry(slave, &pe->slaves, list) {
437 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
438 slave->pe_number,
439 opt);
440 if (rc != OPAL_SUCCESS) {
441 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
442 __func__, rc, opt, phb->hose->global_number,
443 slave->pe_number);
444 return -EIO;
445 }
446 }
447
448 return 0;
449}
450
451static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
452{
453 struct pnv_ioda_pe *slave, *pe;
454 u8 fstate, state;
455 __be16 pcierr;
456 s64 rc;
457
458 /* Sanity check on PE number */
459 if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
460 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
461
462 /*
463 * Fetch the master PE and the PE instance might be
464 * not initialized yet.
465 */
466 pe = &phb->ioda.pe_array[pe_no];
467 if (pe->flags & PNV_IODA_PE_SLAVE) {
468 pe = pe->master;
469 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
470 pe_no = pe->pe_number;
471 }
472
473 /* Check the master PE */
474 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
475 &state, &pcierr, NULL);
476 if (rc != OPAL_SUCCESS) {
477 pr_warn("%s: Failure %lld getting "
478 "PHB#%x-PE#%x state\n",
479 __func__, rc,
480 phb->hose->global_number, pe_no);
481 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
482 }
483
484 /* Check the slave PE */
485 if (!(pe->flags & PNV_IODA_PE_MASTER))
486 return state;
487
488 list_for_each_entry(slave, &pe->slaves, list) {
489 rc = opal_pci_eeh_freeze_status(phb->opal_id,
490 slave->pe_number,
491 &fstate,
492 &pcierr,
493 NULL);
494 if (rc != OPAL_SUCCESS) {
495 pr_warn("%s: Failure %lld getting "
496 "PHB#%x-PE#%x state\n",
497 __func__, rc,
498 phb->hose->global_number, slave->pe_number);
499 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
500 }
501
502 /*
503 * Override the result based on the ascending
504 * priority.
505 */
506 if (fstate > state)
507 state = fstate;
508 }
509
510 return state;
511}
512
184cd4a3
BH		 513/* Currently those 2 are only used when MSIs are enabled, this will change
514 * but in the meantime, we need to protect them to avoid warnings
515 */
516#ifdef CONFIG_PCI_MSI
cad5cef6 517static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
184cd4a3
BH		 518{
519 struct pci_controller *hose = pci_bus_to_host(dev->bus);
520 struct pnv_phb *phb = hose->private_data;
b72c1f65 521 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 522
523 if (!pdn)
524 return NULL;
525 if (pdn->pe_number == IODA_INVALID_PE)
526 return NULL;
527 return &phb->ioda.pe_array[pdn->pe_number];
528}
184cd4a3
BH		 529#endif /* CONFIG_PCI_MSI */
530
b131a842
GS		 531static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
532 struct pnv_ioda_pe *parent,
533 struct pnv_ioda_pe *child,
534 bool is_add)
535{
536 const char *desc = is_add ? "adding" : "removing";
537 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
538 OPAL_REMOVE_PE_FROM_DOMAIN;
539 struct pnv_ioda_pe *slave;
540 long rc;
541
542 /* Parent PE affects child PE */
543 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
544 child->pe_number, op);
545 if (rc != OPAL_SUCCESS) {
546 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
547 rc, desc);
548 return -ENXIO;
549 }
550
551 if (!(child->flags & PNV_IODA_PE_MASTER))
552 return 0;
553
554 /* Compound case: parent PE affects slave PEs */
555 list_for_each_entry(slave, &child->slaves, list) {
556 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
557 slave->pe_number, op);
558 if (rc != OPAL_SUCCESS) {
559 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
560 rc, desc);
561 return -ENXIO;
562 }
563 }
564
565 return 0;
566}
567
568static int pnv_ioda_set_peltv(struct pnv_phb *phb,
569 struct pnv_ioda_pe *pe,
570 bool is_add)
571{
572 struct pnv_ioda_pe *slave;
781a868f 573 struct pci_dev *pdev = NULL;
b131a842
GS		 574 int ret;
575
576 /*
577 * Clear PE frozen state. If it's master PE, we need
578 * clear slave PE frozen state as well.
579 */
580 if (is_add) {
581 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
582 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
583 if (pe->flags & PNV_IODA_PE_MASTER) {
584 list_for_each_entry(slave, &pe->slaves, list)
585 opal_pci_eeh_freeze_clear(phb->opal_id,
586 slave->pe_number,
587 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
588 }
589 }
590
591 /*
592 * Associate PE in PELT. We need add the PE into the
593 * corresponding PELT-V as well. Otherwise, the error
594 * originated from the PE might contribute to other
595 * PEs.
596 */
597 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
598 if (ret)
599 return ret;
600
601 /* For compound PEs, any one affects all of them */
602 if (pe->flags & PNV_IODA_PE_MASTER) {
603 list_for_each_entry(slave, &pe->slaves, list) {
604 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
605 if (ret)
606 return ret;
607 }
608 }
609
610 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
611 pdev = pe->pbus->self;
781a868f 612 else if (pe->flags & PNV_IODA_PE_DEV)
b131a842 613 pdev = pe->pdev->bus->self;
781a868f
WY		 614#ifdef CONFIG_PCI_IOV
615 else if (pe->flags & PNV_IODA_PE_VF)
283e2d8a 616 pdev = pe->parent_dev;
781a868f 617#endif /* CONFIG_PCI_IOV */
b131a842
GS		 618 while (pdev) {
619 struct pci_dn *pdn = pci_get_pdn(pdev);
620 struct pnv_ioda_pe *parent;
621
622 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
623 parent = &phb->ioda.pe_array[pdn->pe_number];
624 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
625 if (ret)
626 return ret;
627 }
628
629 pdev = pdev->bus->self;
630 }
631
632 return 0;
633}
634
781a868f
WY		 635#ifdef CONFIG_PCI_IOV
636static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
637{
638 struct pci_dev *parent;
639 uint8_t bcomp, dcomp, fcomp;
640 int64_t rc;
641 long rid_end, rid;
642
643 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
644 if (pe->pbus) {
645 int count;
646
647 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
648 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
649 parent = pe->pbus->self;
650 if (pe->flags & PNV_IODA_PE_BUS_ALL)
651 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
652 else
653 count = 1;
654
655 switch(count) {
656 case 1: bcomp = OpalPciBusAll; break;
657 case 2: bcomp = OpalPciBus7Bits; break;
658 case 4: bcomp = OpalPciBus6Bits; break;
659 case 8: bcomp = OpalPciBus5Bits; break;
660 case 16: bcomp = OpalPciBus4Bits; break;
661 case 32: bcomp = OpalPciBus3Bits; break;
662 default:
663 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
664 count);
665 /* Do an exact match only */
666 bcomp = OpalPciBusAll;
667 }
668 rid_end = pe->rid + (count << 8);
669 } else {
670 if (pe->flags & PNV_IODA_PE_VF)
671 parent = pe->parent_dev;
672 else
673 parent = pe->pdev->bus->self;
674 bcomp = OpalPciBusAll;
675 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
676 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
677 rid_end = pe->rid + 1;
678 }
679
680 /* Clear the reverse map */
681 for (rid = pe->rid; rid < rid_end; rid++)
682 phb->ioda.pe_rmap[rid] = 0;
683
684 /* Release from all parents PELT-V */
685 while (parent) {
686 struct pci_dn *pdn = pci_get_pdn(parent);
687 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
688 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
689 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
690 /* XXX What to do in case of error ? */
691 }
692 parent = parent->bus->self;
693 }
694
f951e510 695 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
781a868f
WY		 696 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
697
698 /* Disassociate PE in PELT */
699 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
700 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
701 if (rc)
702 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
703 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
704 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
705 if (rc)
706 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
707
708 pe->pbus = NULL;
709 pe->pdev = NULL;
710 pe->parent_dev = NULL;
711
712 return 0;
713}
714#endif /* CONFIG_PCI_IOV */
715
cad5cef6 716static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
184cd4a3
BH		 717{
718 struct pci_dev *parent;
719 uint8_t bcomp, dcomp, fcomp;
720 long rc, rid_end, rid;
721
722 /* Bus validation ? */
723 if (pe->pbus) {
724 int count;
725
726 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
727 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
728 parent = pe->pbus->self;
fb446ad0
GS		 729 if (pe->flags & PNV_IODA_PE_BUS_ALL)
730 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
731 else
732 count = 1;
733
184cd4a3
BH		 734 switch(count) {
735 case 1: bcomp = OpalPciBusAll; break;
736 case 2: bcomp = OpalPciBus7Bits; break;
737 case 4: bcomp = OpalPciBus6Bits; break;
738 case 8: bcomp = OpalPciBus5Bits; break;
739 case 16: bcomp = OpalPciBus4Bits; break;
740 case 32: bcomp = OpalPciBus3Bits; break;
741 default:
781a868f
WY		 742 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
743 count);
184cd4a3
BH		 744 /* Do an exact match only */
745 bcomp = OpalPciBusAll;
746 }
747 rid_end = pe->rid + (count << 8);
748 } else {
781a868f
WY		 749#ifdef CONFIG_PCI_IOV
750 if (pe->flags & PNV_IODA_PE_VF)
751 parent = pe->parent_dev;
752 else
753#endif /* CONFIG_PCI_IOV */
754 parent = pe->pdev->bus->self;
184cd4a3
BH		 755 bcomp = OpalPciBusAll;
756 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
757 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
758 rid_end = pe->rid + 1;
759 }
760
631ad691
GS		 761 /*
762 * Associate PE in PELT. We need add the PE into the
763 * corresponding PELT-V as well. Otherwise, the error
764 * originated from the PE might contribute to other
765 * PEs.
766 */
184cd4a3
BH		 767 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
768 bcomp, dcomp, fcomp, OPAL_MAP_PE);
769 if (rc) {
770 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
771 return -ENXIO;
772 }
631ad691 773
5d2aa710
AP		 774 /*
775 * Configure PELTV. NPUs don't have a PELTV table so skip
776 * configuration on them.
777 */
778 if (phb->type != PNV_PHB_NPU)
779 pnv_ioda_set_peltv(phb, pe, true);
184cd4a3 780
184cd4a3
BH		 781 /* Setup reverse map */
782 for (rid = pe->rid; rid < rid_end; rid++)
783 phb->ioda.pe_rmap[rid] = pe->pe_number;
784
785 /* Setup one MVTs on IODA1 */
4773f76b
GS		 786 if (phb->type != PNV_PHB_IODA1) {
787 pe->mve_number = 0;
788 goto out;
789 }
790
791 pe->mve_number = pe->pe_number;
792 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
793 if (rc != OPAL_SUCCESS) {
794 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
795 rc, pe->mve_number);
796 pe->mve_number = -1;
797 } else {
798 rc = opal_pci_set_mve_enable(phb->opal_id,
799 pe->mve_number, OPAL_ENABLE_MVE);
184cd4a3 800 if (rc) {
4773f76b 801 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
184cd4a3
BH		 802 rc, pe->mve_number);
803 pe->mve_number = -1;
184cd4a3 804 }
4773f76b 805 }
184cd4a3 806
4773f76b 807out:
184cd4a3
BH		 808 return 0;
809}
810
cad5cef6
GKH		 811static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
812 struct pnv_ioda_pe *pe)
184cd4a3
BH		 813{
814 struct pnv_ioda_pe *lpe;
815
7ebdf956 816 list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
184cd4a3 817 if (lpe->dma_weight < pe->dma_weight) {
7ebdf956 818 list_add_tail(&pe->dma_link, &lpe->dma_link);
184cd4a3
BH		 819 return;
820 }
821 }
7ebdf956 822 list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
184cd4a3
BH		 823}
824
825static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
826{
827 /* This is quite simplistic. The "base" weight of a device
828 * is 10. 0 means no DMA is to be accounted for it.
829 */
830
831 /* If it's a bridge, no DMA */
832 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
833 return 0;
834
835 /* Reduce the weight of slow USB controllers */
836 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
837 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
838 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
839 return 3;
840
841 /* Increase the weight of RAID (includes Obsidian) */
842 if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
843 return 15;
844
845 /* Default */
846 return 10;
847}
848
781a868f
WY		 849#ifdef CONFIG_PCI_IOV
850static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
851{
852 struct pci_dn *pdn = pci_get_pdn(dev);
853 int i;
854 struct resource *res, res2;
855 resource_size_t size;
856 u16 num_vfs;
857
858 if (!dev->is_physfn)
859 return -EINVAL;
860
861 /*
862 * "offset" is in VFs. The M64 windows are sized so that when they
863 * are segmented, each segment is the same size as the IOV BAR.
864 * Each segment is in a separate PE, and the high order bits of the
865 * address are the PE number. Therefore, each VF's BAR is in a
866 * separate PE, and changing the IOV BAR start address changes the
867 * range of PEs the VFs are in.
868 */
869 num_vfs = pdn->num_vfs;
870 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
871 res = &dev->resource[i + PCI_IOV_RESOURCES];
872 if (!res->flags || !res->parent)
873 continue;
874
875 if (!pnv_pci_is_mem_pref_64(res->flags))
876 continue;
877
878 /*
879 * The actual IOV BAR range is determined by the start address
880 * and the actual size for num_vfs VFs BAR. This check is to
881 * make sure that after shifting, the range will not overlap
882 * with another device.
883 */
884 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
885 res2.flags = res->flags;
886 res2.start = res->start + (size * offset);
887 res2.end = res2.start + (size * num_vfs) - 1;
888
889 if (res2.end > res->end) {
890 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
891 i, &res2, res, num_vfs, offset);
892 return -EBUSY;
893 }
894 }
895
896 /*
897 * After doing so, there would be a "hole" in the /proc/iomem when
898 * offset is a positive value. It looks like the device return some
899 * mmio back to the system, which actually no one could use it.
900 */
901 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
902 res = &dev->resource[i + PCI_IOV_RESOURCES];
903 if (!res->flags || !res->parent)
904 continue;
905
906 if (!pnv_pci_is_mem_pref_64(res->flags))
907 continue;
908
909 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
910 res2 = *res;
911 res->start += size * offset;
912
74703cc4
WY		 913 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
914 i, &res2, res, (offset > 0) ? "En" : "Dis",
915 num_vfs, offset);
781a868f
WY		 916 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
917 }
918 return 0;
919}
920#endif /* CONFIG_PCI_IOV */
921
cad5cef6 922static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
184cd4a3
BH		 923{
924 struct pci_controller *hose = pci_bus_to_host(dev->bus);
925 struct pnv_phb *phb = hose->private_data;
b72c1f65 926 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 927 struct pnv_ioda_pe *pe;
928 int pe_num;
929
930 if (!pdn) {
931 pr_err("%s: Device tree node not associated properly\n",
932 pci_name(dev));
933 return NULL;
934 }
935 if (pdn->pe_number != IODA_INVALID_PE)
936 return NULL;
937
5d2aa710 938 pe_num = pnv_ioda_alloc_pe(phb);
184cd4a3
BH		 939 if (pe_num == IODA_INVALID_PE) {
940 pr_warning("%s: Not enough PE# available, disabling device\n",
941 pci_name(dev));
942 return NULL;
943 }
944
945 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
946 * pointer in the PE data structure, both should be destroyed at the
947 * same time. However, this needs to be looked at more closely again
948 * once we actually start removing things (Hotplug, SR-IOV, ...)
949 *
950 * At some point we want to remove the PDN completely anyways
951 */
952 pe = &phb->ioda.pe_array[pe_num];
953 pci_dev_get(dev);
954 pdn->pcidev = dev;
955 pdn->pe_number = pe_num;
5d2aa710 956 pe->flags = PNV_IODA_PE_DEV;
184cd4a3
BH		 957 pe->pdev = dev;
958 pe->pbus = NULL;
959 pe->tce32_seg = -1;
960 pe->mve_number = -1;
961 pe->rid = dev->bus->number << 8 | pdn->devfn;
962
963 pe_info(pe, "Associated device to PE\n");
964
965 if (pnv_ioda_configure_pe(phb, pe)) {
966 /* XXX What do we do here ? */
967 if (pe_num)
968 pnv_ioda_free_pe(phb, pe_num);
969 pdn->pe_number = IODA_INVALID_PE;
970 pe->pdev = NULL;
971 pci_dev_put(dev);
972 return NULL;
973 }
974
975 /* Assign a DMA weight to the device */
976 pe->dma_weight = pnv_ioda_dma_weight(dev);
977 if (pe->dma_weight != 0) {
978 phb->ioda.dma_weight += pe->dma_weight;
979 phb->ioda.dma_pe_count++;
980 }
981
982 /* Link the PE */
983 pnv_ioda_link_pe_by_weight(phb, pe);
984
985 return pe;
986}
987
988static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
989{
990 struct pci_dev *dev;
991
992 list_for_each_entry(dev, &bus->devices, bus_list) {
b72c1f65 993 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 994
995 if (pdn == NULL) {
996 pr_warn("%s: No device node associated with device !\n",
997 pci_name(dev));
998 continue;
999 }
94973b24 1000 pdn->pcidev = dev;
184cd4a3
BH		 1001 pdn->pe_number = pe->pe_number;
1002 pe->dma_weight += pnv_ioda_dma_weight(dev);
fb446ad0 1003 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
184cd4a3
BH		 1004 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1005 }
1006}
1007
fb446ad0
GS		 1008/*
1009 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1010 * single PCI bus. Another one that contains the primary PCI bus and its
1011 * subordinate PCI devices and buses. The second type of PE is normally
1012 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1013 */
d1203852 1014static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
184cd4a3 1015{
fb446ad0 1016 struct pci_controller *hose = pci_bus_to_host(bus);
184cd4a3 1017 struct pnv_phb *phb = hose->private_data;
184cd4a3 1018 struct pnv_ioda_pe *pe;
262af557
GC		 1019 int pe_num = IODA_INVALID_PE;
1020
1021 /* Check if PE is determined by M64 */
1022 if (phb->pick_m64_pe)
26ba248d 1023 pe_num = phb->pick_m64_pe(bus, all);
262af557
GC		 1024
1025 /* The PE number isn't pinned by M64 */
1026 if (pe_num == IODA_INVALID_PE)
1027 pe_num = pnv_ioda_alloc_pe(phb);
184cd4a3 1028
184cd4a3 1029 if (pe_num == IODA_INVALID_PE) {
fb446ad0
GS		 1030 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1031 __func__, pci_domain_nr(bus), bus->number);
184cd4a3
BH		 1032 return;
1033 }
1034
1035 pe = &phb->ioda.pe_array[pe_num];
262af557 1036 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
184cd4a3
BH		 1037 pe->pbus = bus;
1038 pe->pdev = NULL;
1039 pe->tce32_seg = -1;
1040 pe->mve_number = -1;
b918c62e 1041 pe->rid = bus->busn_res.start << 8;
184cd4a3
BH		 1042 pe->dma_weight = 0;
1043
fb446ad0
GS		 1044 if (all)
1045 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1046 bus->busn_res.start, bus->busn_res.end, pe_num);
1047 else
1048 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1049 bus->busn_res.start, pe_num);
184cd4a3
BH		 1050
1051 if (pnv_ioda_configure_pe(phb, pe)) {
1052 /* XXX What do we do here ? */
1053 if (pe_num)
1054 pnv_ioda_free_pe(phb, pe_num);
1055 pe->pbus = NULL;
1056 return;
1057 }
1058
1059 /* Associate it with all child devices */
1060 pnv_ioda_setup_same_PE(bus, pe);
1061
7ebdf956
GS		 1062 /* Put PE to the list */
1063 list_add_tail(&pe->list, &phb->ioda.pe_list);
1064
184cd4a3
BH		 1065 /* Account for one DMA PE if at least one DMA capable device exist
1066 * below the bridge
1067 */
1068 if (pe->dma_weight != 0) {
1069 phb->ioda.dma_weight += pe->dma_weight;
1070 phb->ioda.dma_pe_count++;
1071 }
1072
1073 /* Link the PE */
1074 pnv_ioda_link_pe_by_weight(phb, pe);
1075}
1076
b521549a
AP		 1077static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1078{
1079 int pe_num, found_pe = false, rc;
1080 long rid;
1081 struct pnv_ioda_pe *pe;
1082 struct pci_dev *gpu_pdev;
1083 struct pci_dn *npu_pdn;
1084 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1085 struct pnv_phb *phb = hose->private_data;
1086
1087 /*
1088 * Due to a hardware errata PE#0 on the NPU is reserved for
1089 * error handling. This means we only have three PEs remaining
1090 * which need to be assigned to four links, implying some
1091 * links must share PEs.
1092 *
1093 * To achieve this we assign PEs such that NPUs linking the
1094 * same GPU get assigned the same PE.
1095 */
1096 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1097 for (pe_num = 0; pe_num < phb->ioda.total_pe; pe_num++) {
1098 pe = &phb->ioda.pe_array[pe_num];
1099 if (!pe->pdev)
1100 continue;
1101
1102 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1103 /*
1104 * This device has the same peer GPU so should
1105 * be assigned the same PE as the existing
1106 * peer NPU.
1107 */
1108 dev_info(&npu_pdev->dev,
1109 "Associating to existing PE %d\n", pe_num);
1110 pci_dev_get(npu_pdev);
1111 npu_pdn = pci_get_pdn(npu_pdev);
1112 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1113 npu_pdn->pcidev = npu_pdev;
1114 npu_pdn->pe_number = pe_num;
1115 pe->dma_weight += pnv_ioda_dma_weight(npu_pdev);
1116 phb->ioda.pe_rmap[rid] = pe->pe_number;
1117
1118 /* Map the PE to this link */
1119 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1120 OpalPciBusAll,
1121 OPAL_COMPARE_RID_DEVICE_NUMBER,
1122 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1123 OPAL_MAP_PE);
1124 WARN_ON(rc != OPAL_SUCCESS);
1125 found_pe = true;
1126 break;
1127 }
1128 }
1129
1130 if (!found_pe)
1131 /*
1132 * Could not find an existing PE so allocate a new
1133 * one.
1134 */
1135 return pnv_ioda_setup_dev_PE(npu_pdev);
1136 else
1137 return pe;
1138}
1139
1140static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
5d2aa710 1141{
5d2aa710
AP		 1142 struct pci_dev *pdev;
1143
1144 list_for_each_entry(pdev, &bus->devices, bus_list)
b521549a 1145 pnv_ioda_setup_npu_PE(pdev);
5d2aa710
AP		 1146}
1147
cad5cef6 1148static void pnv_ioda_setup_PEs(struct pci_bus *bus)
184cd4a3
BH		 1149{
1150 struct pci_dev *dev;
fb446ad0 1151
d1203852 1152 pnv_ioda_setup_bus_PE(bus, false);
184cd4a3
BH		 1153
1154 list_for_each_entry(dev, &bus->devices, bus_list) {
fb446ad0
GS		 1155 if (dev->subordinate) {
1156 if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
d1203852 1157 pnv_ioda_setup_bus_PE(dev->subordinate, true);
fb446ad0
GS		 1158 else
1159 pnv_ioda_setup_PEs(dev->subordinate);
1160 }
1161 }
1162}
1163
1164/*
1165 * Configure PEs so that the downstream PCI buses and devices
1166 * could have their associated PE#. Unfortunately, we didn't
1167 * figure out the way to identify the PLX bridge yet. So we
1168 * simply put the PCI bus and the subordinate behind the root
1169 * port to PE# here. The game rule here is expected to be changed
1170 * as soon as we can detected PLX bridge correctly.
1171 */
cad5cef6 1172static void pnv_pci_ioda_setup_PEs(void)
fb446ad0
GS		 1173{
1174 struct pci_controller *hose, *tmp;
262af557 1175 struct pnv_phb *phb;
fb446ad0
GS		 1176
1177 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
262af557
GC		 1178 phb = hose->private_data;
1179
1180 /* M64 layout might affect PE allocation */
5ef73567 1181 if (phb->reserve_m64_pe)
96a2f92b 1182 phb->reserve_m64_pe(hose->bus, NULL, true);
262af557 1183
5d2aa710
AP		 1184 /*
1185 * On NPU PHB, we expect separate PEs for individual PCI
1186 * functions. PCI bus dependent PEs are required for the
1187 * remaining types of PHBs.
1188 */
1189 if (phb->type == PNV_PHB_NPU)
b521549a 1190 pnv_ioda_setup_npu_PEs(hose->bus);
5d2aa710
AP		 1191 else
1192 pnv_ioda_setup_PEs(hose->bus);
184cd4a3
BH		 1193 }
1194}
1195
a8b2f828 1196#ifdef CONFIG_PCI_IOV
781a868f
WY		 1197static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1198{
1199 struct pci_bus *bus;
1200 struct pci_controller *hose;
1201 struct pnv_phb *phb;
1202 struct pci_dn *pdn;
02639b0e 1203 int i, j;
781a868f
WY		 1204
1205 bus = pdev->bus;
1206 hose = pci_bus_to_host(bus);
1207 phb = hose->private_data;
1208 pdn = pci_get_pdn(pdev);
1209
02639b0e
WY		 1210 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1211 for (j = 0; j < M64_PER_IOV; j++) {
1212 if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1213 continue;
1214 opal_pci_phb_mmio_enable(phb->opal_id,
1215 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1216 clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1217 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1218 }
781a868f
WY		 1219
1220 return 0;
1221}
1222
02639b0e 1223static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1224{
1225 struct pci_bus *bus;
1226 struct pci_controller *hose;
1227 struct pnv_phb *phb;
1228 struct pci_dn *pdn;
1229 unsigned int win;
1230 struct resource *res;
02639b0e 1231 int i, j;
781a868f 1232 int64_t rc;
02639b0e
WY		 1233 int total_vfs;
1234 resource_size_t size, start;
1235 int pe_num;
1236 int vf_groups;
1237 int vf_per_group;
781a868f
WY		 1238
1239 bus = pdev->bus;
1240 hose = pci_bus_to_host(bus);
1241 phb = hose->private_data;
1242 pdn = pci_get_pdn(pdev);
02639b0e 1243 total_vfs = pci_sriov_get_totalvfs(pdev);
781a868f
WY		 1244
1245 /* Initialize the m64_wins to IODA_INVALID_M64 */
1246 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
02639b0e
WY		 1247 for (j = 0; j < M64_PER_IOV; j++)
1248 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1249
1250 if (pdn->m64_per_iov == M64_PER_IOV) {
1251 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1252 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1253 roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1254 } else {
1255 vf_groups = 1;
1256 vf_per_group = 1;
1257 }
781a868f
WY		 1258
1259 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1260 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1261 if (!res->flags || !res->parent)
1262 continue;
1263
1264 if (!pnv_pci_is_mem_pref_64(res->flags))
1265 continue;
1266
02639b0e
WY		 1267 for (j = 0; j < vf_groups; j++) {
1268 do {
1269 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1270 phb->ioda.m64_bar_idx + 1, 0);
1271
1272 if (win >= phb->ioda.m64_bar_idx + 1)
1273 goto m64_failed;
1274 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1275
1276 pdn->m64_wins[i][j] = win;
1277
1278 if (pdn->m64_per_iov == M64_PER_IOV) {
1279 size = pci_iov_resource_size(pdev,
1280 PCI_IOV_RESOURCES + i);
1281 size = size * vf_per_group;
1282 start = res->start + size * j;
1283 } else {
1284 size = resource_size(res);
1285 start = res->start;
1286 }
1287
1288 /* Map the M64 here */
1289 if (pdn->m64_per_iov == M64_PER_IOV) {
1290 pe_num = pdn->offset + j;
1291 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1292 pe_num, OPAL_M64_WINDOW_TYPE,
1293 pdn->m64_wins[i][j], 0);
1294 }
1295
1296 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1297 OPAL_M64_WINDOW_TYPE,
1298 pdn->m64_wins[i][j],
1299 start,
1300 0, /* unused */
1301 size);
781a868f 1302
781a868f 1303
02639b0e
WY		 1304 if (rc != OPAL_SUCCESS) {
1305 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1306 win, rc);
1307 goto m64_failed;
1308 }
781a868f 1309
02639b0e
WY		 1310 if (pdn->m64_per_iov == M64_PER_IOV)
1311 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1312 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1313 else
1314 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1315 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
781a868f 1316
02639b0e
WY		 1317 if (rc != OPAL_SUCCESS) {
1318 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1319 win, rc);
1320 goto m64_failed;
1321 }
781a868f
WY		 1322 }
1323 }
1324 return 0;
1325
1326m64_failed:
1327 pnv_pci_vf_release_m64(pdev);
1328 return -EBUSY;
1329}
1330
c035e37b
AK		 1331static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1332 int num);
1333static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1334
781a868f
WY		 1335static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1336{
781a868f 1337 struct iommu_table *tbl;
781a868f
WY		 1338 int64_t rc;
1339
b348aa65 1340 tbl = pe->table_group.tables[0];
c035e37b 1341 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
781a868f
WY		 1342 if (rc)
1343 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1344
c035e37b 1345 pnv_pci_ioda2_set_bypass(pe, false);
0eaf4def
AK		 1346 if (pe->table_group.group) {
1347 iommu_group_put(pe->table_group.group);
1348 BUG_ON(pe->table_group.group);
ac9a5889 1349 }
aca6913f 1350 pnv_pci_ioda2_table_free_pages(tbl);
781a868f 1351 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
781a868f
WY		 1352}
1353
02639b0e 1354static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1355{
1356 struct pci_bus *bus;
1357 struct pci_controller *hose;
1358 struct pnv_phb *phb;
1359 struct pnv_ioda_pe *pe, *pe_n;
1360 struct pci_dn *pdn;
02639b0e
WY		 1361 u16 vf_index;
1362 int64_t rc;
781a868f
WY		 1363
1364 bus = pdev->bus;
1365 hose = pci_bus_to_host(bus);
1366 phb = hose->private_data;
02639b0e 1367 pdn = pci_get_pdn(pdev);
781a868f
WY		 1368
1369 if (!pdev->is_physfn)
1370 return;
1371
02639b0e
WY		 1372 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1373 int vf_group;
1374 int vf_per_group;
1375 int vf_index1;
1376
1377 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1378
1379 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1380 for (vf_index = vf_group * vf_per_group;
1381 vf_index < (vf_group + 1) * vf_per_group &&
1382 vf_index < num_vfs;
1383 vf_index++)
1384 for (vf_index1 = vf_group * vf_per_group;
1385 vf_index1 < (vf_group + 1) * vf_per_group &&
1386 vf_index1 < num_vfs;
1387 vf_index1++){
1388
1389 rc = opal_pci_set_peltv(phb->opal_id,
1390 pdn->offset + vf_index,
1391 pdn->offset + vf_index1,
1392 OPAL_REMOVE_PE_FROM_DOMAIN);
1393
1394 if (rc)
1395 dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1396 __func__,
1397 pdn->offset + vf_index1, rc);
1398 }
1399 }
1400
781a868f
WY		 1401 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1402 if (pe->parent_dev != pdev)
1403 continue;
1404
1405 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1406
1407 /* Remove from list */
1408 mutex_lock(&phb->ioda.pe_list_mutex);
1409 list_del(&pe->list);
1410 mutex_unlock(&phb->ioda.pe_list_mutex);
1411
1412 pnv_ioda_deconfigure_pe(phb, pe);
1413
1414 pnv_ioda_free_pe(phb, pe->pe_number);
1415 }
1416}
1417
1418void pnv_pci_sriov_disable(struct pci_dev *pdev)
1419{
1420 struct pci_bus *bus;
1421 struct pci_controller *hose;
1422 struct pnv_phb *phb;
1423 struct pci_dn *pdn;
1424 struct pci_sriov *iov;
1425 u16 num_vfs;
1426
1427 bus = pdev->bus;
1428 hose = pci_bus_to_host(bus);
1429 phb = hose->private_data;
1430 pdn = pci_get_pdn(pdev);
1431 iov = pdev->sriov;
1432 num_vfs = pdn->num_vfs;
1433
1434 /* Release VF PEs */
02639b0e 1435 pnv_ioda_release_vf_PE(pdev, num_vfs);
781a868f
WY		 1436
1437 if (phb->type == PNV_PHB_IODA2) {
02639b0e
WY		 1438 if (pdn->m64_per_iov == 1)
1439 pnv_pci_vf_resource_shift(pdev, -pdn->offset);
781a868f
WY		 1440
1441 /* Release M64 windows */
1442 pnv_pci_vf_release_m64(pdev);
1443
1444 /* Release PE numbers */
1445 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1446 pdn->offset = 0;
1447 }
1448}
1449
1450static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1451 struct pnv_ioda_pe *pe);
1452static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1453{
1454 struct pci_bus *bus;
1455 struct pci_controller *hose;
1456 struct pnv_phb *phb;
1457 struct pnv_ioda_pe *pe;
1458 int pe_num;
1459 u16 vf_index;
1460 struct pci_dn *pdn;
02639b0e 1461 int64_t rc;
781a868f
WY		 1462
1463 bus = pdev->bus;
1464 hose = pci_bus_to_host(bus);
1465 phb = hose->private_data;
1466 pdn = pci_get_pdn(pdev);
1467
1468 if (!pdev->is_physfn)
1469 return;
1470
1471 /* Reserve PE for each VF */
1472 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1473 pe_num = pdn->offset + vf_index;
1474
1475 pe = &phb->ioda.pe_array[pe_num];
1476 pe->pe_number = pe_num;
1477 pe->phb = phb;
1478 pe->flags = PNV_IODA_PE_VF;
1479 pe->pbus = NULL;
1480 pe->parent_dev = pdev;
1481 pe->tce32_seg = -1;
1482 pe->mve_number = -1;
1483 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1484 pci_iov_virtfn_devfn(pdev, vf_index);
1485
1486 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1487 hose->global_number, pdev->bus->number,
1488 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1489 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1490
1491 if (pnv_ioda_configure_pe(phb, pe)) {
1492 /* XXX What do we do here ? */
1493 if (pe_num)
1494 pnv_ioda_free_pe(phb, pe_num);
1495 pe->pdev = NULL;
1496 continue;
1497 }
1498
781a868f
WY		 1499 /* Put PE to the list */
1500 mutex_lock(&phb->ioda.pe_list_mutex);
1501 list_add_tail(&pe->list, &phb->ioda.pe_list);
1502 mutex_unlock(&phb->ioda.pe_list_mutex);
1503
1504 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1505 }
02639b0e
WY		 1506
1507 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1508 int vf_group;
1509 int vf_per_group;
1510 int vf_index1;
1511
1512 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1513
1514 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1515 for (vf_index = vf_group * vf_per_group;
1516 vf_index < (vf_group + 1) * vf_per_group &&
1517 vf_index < num_vfs;
1518 vf_index++) {
1519 for (vf_index1 = vf_group * vf_per_group;
1520 vf_index1 < (vf_group + 1) * vf_per_group &&
1521 vf_index1 < num_vfs;
1522 vf_index1++) {
1523
1524 rc = opal_pci_set_peltv(phb->opal_id,
1525 pdn->offset + vf_index,
1526 pdn->offset + vf_index1,
1527 OPAL_ADD_PE_TO_DOMAIN);
1528
1529 if (rc)
1530 dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1531 __func__,
1532 pdn->offset + vf_index1, rc);
1533 }
1534 }
1535 }
1536 }
781a868f
WY		 1537}
1538
1539int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1540{
1541 struct pci_bus *bus;
1542 struct pci_controller *hose;
1543 struct pnv_phb *phb;
1544 struct pci_dn *pdn;
1545 int ret;
1546
1547 bus = pdev->bus;
1548 hose = pci_bus_to_host(bus);
1549 phb = hose->private_data;
1550 pdn = pci_get_pdn(pdev);
1551
1552 if (phb->type == PNV_PHB_IODA2) {
1553 /* Calculate available PE for required VFs */
1554 mutex_lock(&phb->ioda.pe_alloc_mutex);
1555 pdn->offset = bitmap_find_next_zero_area(
1556 phb->ioda.pe_alloc, phb->ioda.total_pe,
1557 0, num_vfs, 0);
1558 if (pdn->offset >= phb->ioda.total_pe) {
1559 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1560 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1561 pdn->offset = 0;
1562 return -EBUSY;
1563 }
1564 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1565 pdn->num_vfs = num_vfs;
1566 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1567
1568 /* Assign M64 window accordingly */
02639b0e 1569 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
781a868f
WY		 1570 if (ret) {
1571 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1572 goto m64_failed;
1573 }
1574
1575 /*
1576 * When using one M64 BAR to map one IOV BAR, we need to shift
1577 * the IOV BAR according to the PE# allocated to the VFs.
1578 * Otherwise, the PE# for the VF will conflict with others.
1579 */
02639b0e
WY		 1580 if (pdn->m64_per_iov == 1) {
1581 ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1582 if (ret)
1583 goto m64_failed;
1584 }
781a868f
WY		 1585 }
1586
1587 /* Setup VF PEs */
1588 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1589
1590 return 0;
1591
1592m64_failed:
1593 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1594 pdn->offset = 0;
1595
1596 return ret;
1597}
1598
a8b2f828
GS		 1599int pcibios_sriov_disable(struct pci_dev *pdev)
1600{
781a868f
WY		 1601 pnv_pci_sriov_disable(pdev);
1602
a8b2f828
GS		 1603 /* Release PCI data */
1604 remove_dev_pci_data(pdev);
1605 return 0;
1606}
1607
1608int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1609{
1610 /* Allocate PCI data */
1611 add_dev_pci_data(pdev);
781a868f
WY		 1612
1613 pnv_pci_sriov_enable(pdev, num_vfs);
a8b2f828
GS		 1614 return 0;
1615}
1616#endif /* CONFIG_PCI_IOV */
1617
959c9bdd 1618static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
184cd4a3 1619{
b72c1f65 1620 struct pci_dn *pdn = pci_get_pdn(pdev);
959c9bdd 1621 struct pnv_ioda_pe *pe;
184cd4a3 1622
959c9bdd
GS		 1623 /*
1624 * The function can be called while the PE#
1625 * hasn't been assigned. Do nothing for the
1626 * case.
1627 */
1628 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1629 return;
184cd4a3 1630
959c9bdd 1631 pe = &phb->ioda.pe_array[pdn->pe_number];
cd15b048 1632 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
0e1ffef0 1633 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
b348aa65 1634 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
4617082e
AK		 1635 /*
1636 * Note: iommu_add_device() will fail here as
1637 * for physical PE: the device is already added by now;
1638 * for virtual PE: sysfs entries are not ready yet and
1639 * tce_iommu_bus_notifier will add the device to a group later.
1640 */
184cd4a3
BH		 1641}
1642
763d2d8d 1643static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
cd15b048 1644{
763d2d8d
DA		 1645 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1646 struct pnv_phb *phb = hose->private_data;
cd15b048
BH		 1647 struct pci_dn *pdn = pci_get_pdn(pdev);
1648 struct pnv_ioda_pe *pe;
1649 uint64_t top;
1650 bool bypass = false;
5d2aa710
AP		 1651 struct pci_dev *linked_npu_dev;
1652 int i;
cd15b048
BH		 1653
1654 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1655 return -ENODEV;;
1656
1657 pe = &phb->ioda.pe_array[pdn->pe_number];
1658 if (pe->tce_bypass_enabled) {
1659 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1660 bypass = (dma_mask >= top);
1661 }
1662
1663 if (bypass) {
1664 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1665 set_dma_ops(&pdev->dev, &dma_direct_ops);
cd15b048
BH		 1666 } else {
1667 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1668 set_dma_ops(&pdev->dev, &dma_iommu_ops);
cd15b048 1669 }
a32305bf 1670 *pdev->dev.dma_mask = dma_mask;
5d2aa710
AP		 1671
1672 /* Update peer npu devices */
1673 if (pe->flags & PNV_IODA_PE_PEER)
419dbd5e
AP		 1674 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1675 if (!pe->peers[i])
1676 continue;
1677
5d2aa710
AP		 1678 linked_npu_dev = pe->peers[i]->pdev;
1679 if (dma_get_mask(&linked_npu_dev->dev) != dma_mask)
1680 dma_set_mask(&linked_npu_dev->dev, dma_mask);
1681 }
1682
cd15b048
BH		 1683 return 0;
1684}
1685
53522982 1686static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
fe7e85c6 1687{
53522982
AD		 1688 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1689 struct pnv_phb *phb = hose->private_data;
fe7e85c6
GS		 1690 struct pci_dn *pdn = pci_get_pdn(pdev);
1691 struct pnv_ioda_pe *pe;
1692 u64 end, mask;
1693
1694 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1695 return 0;
1696
1697 pe = &phb->ioda.pe_array[pdn->pe_number];
1698 if (!pe->tce_bypass_enabled)
1699 return __dma_get_required_mask(&pdev->dev);
1700
1701
1702 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1703 mask = 1ULL << (fls64(end) - 1);
1704 mask += mask - 1;
1705
1706 return mask;
1707}
1708
dff4a39e 1709static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
ea30e99e 1710 struct pci_bus *bus)
74251fe2
BH		 1711{
1712 struct pci_dev *dev;
1713
1714 list_for_each_entry(dev, &bus->devices, bus_list) {
b348aa65 1715 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
e91c2511 1716 set_dma_offset(&dev->dev, pe->tce_bypass_base);
4617082e 1717 iommu_add_device(&dev->dev);
dff4a39e 1718
5c89a87d 1719 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
ea30e99e 1720 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
74251fe2
BH		 1721 }
1722}
1723
decbda25
AK		 1724static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1725 unsigned long index, unsigned long npages, bool rm)
4cce9550 1726{
0eaf4def
AK		 1727 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1728 &tbl->it_group_list, struct iommu_table_group_link,
1729 next);
1730 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
b348aa65 1731 struct pnv_ioda_pe, table_group);
3ad26e5c 1732 __be64 __iomem *invalidate = rm ?
5780fb04
AK		 1733 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1734 pe->phb->ioda.tce_inval_reg;
4cce9550 1735 unsigned long start, end, inc;
b0376c9b 1736 const unsigned shift = tbl->it_page_shift;
4cce9550 1737
decbda25
AK		 1738 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1739 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1740 npages - 1);
4cce9550
GS		 1741
1742 /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1743 if (tbl->it_busno) {
b0376c9b
AK		 1744 start <<= shift;
1745 end <<= shift;
1746 inc = 128ull << shift;
4cce9550
GS		 1747 start |= tbl->it_busno;
1748 end |= tbl->it_busno;
1749 } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1750 /* p7ioc-style invalidation, 2 TCEs per write */
1751 start |= (1ull << 63);
1752 end |= (1ull << 63);
1753 inc = 16;
1754 } else {
1755 /* Default (older HW) */
1756 inc = 128;
1757 }
1758
1759 end |= inc - 1; /* round up end to be different than start */
1760
1761 mb(); /* Ensure above stores are visible */
1762 while (start <= end) {
8e0a1611 1763 if (rm)
3ad26e5c 1764 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1765 else
3ad26e5c 1766 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1767 start += inc;
1768 }
1769
1770 /*
1771 * The iommu layer will do another mb() for us on build()
1772 * and we don't care on free()
1773 */
1774}
1775
decbda25
AK		 1776static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1777 long npages, unsigned long uaddr,
1778 enum dma_data_direction direction,
1779 struct dma_attrs *attrs)
1780{
1781 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1782 attrs);
1783
1784 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1785 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1786
1787 return ret;
1788}
1789
05c6cfb9
AK		 1790#ifdef CONFIG_IOMMU_API
1791static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1792 unsigned long *hpa, enum dma_data_direction *direction)
1793{
1794 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1795
1796 if (!ret && (tbl->it_type &
1797 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1798 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1799
1800 return ret;
1801}
1802#endif
1803
decbda25
AK		 1804static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1805 long npages)
1806{
1807 pnv_tce_free(tbl, index, npages);
1808
1809 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1810 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1811}
1812
da004c36 1813static struct iommu_table_ops pnv_ioda1_iommu_ops = {
decbda25 1814 .set = pnv_ioda1_tce_build,
05c6cfb9
AK		 1815#ifdef CONFIG_IOMMU_API
1816 .exchange = pnv_ioda1_tce_xchg,
1817#endif
decbda25 1818 .clear = pnv_ioda1_tce_free,
da004c36
AK		 1819 .get = pnv_tce_get,
1820};
1821
5780fb04
AK		 1822static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1823{
1824 /* 01xb - invalidate TCEs that match the specified PE# */
1825 unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1826 struct pnv_phb *phb = pe->phb;
5d2aa710
AP		 1827 struct pnv_ioda_pe *npe;
1828 int i;
5780fb04
AK		 1829
1830 if (!phb->ioda.tce_inval_reg)
1831 return;
1832
1833 mb(); /* Ensure above stores are visible */
1834 __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
5d2aa710
AP		 1835
1836 if (pe->flags & PNV_IODA_PE_PEER)
1837 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1838 npe = pe->peers[i];
1839 if (!npe || npe->phb->type != PNV_PHB_NPU)
1840 continue;
1841
1842 pnv_npu_tce_invalidate_entire(npe);
1843 }
5780fb04
AK		 1844}
1845
e57080f1
AK		 1846static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1847 __be64 __iomem *invalidate, unsigned shift,
1848 unsigned long index, unsigned long npages)
4cce9550
GS		 1849{
1850 unsigned long start, end, inc;
4cce9550
GS		 1851
1852 /* We'll invalidate DMA address in PE scope */
b0376c9b 1853 start = 0x2ull << 60;
e57080f1 1854 start |= (pe_number & 0xFF);
4cce9550
GS		 1855 end = start;
1856
1857 /* Figure out the start, end and step */
decbda25
AK		 1858 start |= (index << shift);
1859 end |= ((index + npages - 1) << shift);
b0376c9b 1860 inc = (0x1ull << shift);
4cce9550
GS		 1861 mb();
1862
1863 while (start <= end) {
8e0a1611 1864 if (rm)
3ad26e5c 1865 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1866 else
3ad26e5c 1867 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1868 start += inc;
1869 }
1870}
1871
e57080f1
AK		 1872static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1873 unsigned long index, unsigned long npages, bool rm)
1874{
1875 struct iommu_table_group_link *tgl;
1876
1877 list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
5d2aa710 1878 struct pnv_ioda_pe *npe;
e57080f1
AK		 1879 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1880 struct pnv_ioda_pe, table_group);
1881 __be64 __iomem *invalidate = rm ?
1882 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1883 pe->phb->ioda.tce_inval_reg;
5d2aa710 1884 int i;
e57080f1
AK		 1885
1886 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1887 invalidate, tbl->it_page_shift,
1888 index, npages);
5d2aa710
AP		 1889
1890 if (pe->flags & PNV_IODA_PE_PEER)
1891 /* Invalidate PEs using the same TCE table */
1892 for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
1893 npe = pe->peers[i];
1894 if (!npe || npe->phb->type != PNV_PHB_NPU)
1895 continue;
1896
1897 pnv_npu_tce_invalidate(npe, tbl, index,
1898 npages, rm);
1899 }
e57080f1
AK		 1900 }
1901}
1902
decbda25
AK		 1903static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1904 long npages, unsigned long uaddr,
1905 enum dma_data_direction direction,
1906 struct dma_attrs *attrs)
4cce9550 1907{
decbda25
AK		 1908 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1909 attrs);
4cce9550 1910
decbda25
AK		 1911 if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1912 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1913
1914 return ret;
1915}
1916
05c6cfb9
AK		 1917#ifdef CONFIG_IOMMU_API
1918static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1919 unsigned long *hpa, enum dma_data_direction *direction)
1920{
1921 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1922
1923 if (!ret && (tbl->it_type &
1924 (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1925 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1926
1927 return ret;
1928}
1929#endif
1930
decbda25
AK		 1931static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1932 long npages)
1933{
1934 pnv_tce_free(tbl, index, npages);
1935
1936 if (tbl->it_type & TCE_PCI_SWINV_FREE)
1937 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
4cce9550
GS		 1938}
1939
4793d65d
AK		 1940static void pnv_ioda2_table_free(struct iommu_table *tbl)
1941{
1942 pnv_pci_ioda2_table_free_pages(tbl);
1943 iommu_free_table(tbl, "pnv");
1944}
1945
da004c36 1946static struct iommu_table_ops pnv_ioda2_iommu_ops = {
decbda25 1947 .set = pnv_ioda2_tce_build,
05c6cfb9
AK		 1948#ifdef CONFIG_IOMMU_API
1949 .exchange = pnv_ioda2_tce_xchg,
1950#endif
decbda25 1951 .clear = pnv_ioda2_tce_free,
da004c36 1952 .get = pnv_tce_get,
4793d65d 1953 .free = pnv_ioda2_table_free,
da004c36
AK		 1954};
1955
cad5cef6
GKH		 1956static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1957 struct pnv_ioda_pe *pe, unsigned int base,
1958 unsigned int segs)
184cd4a3
BH		 1959{
1960
1961 struct page *tce_mem = NULL;
184cd4a3
BH		 1962 struct iommu_table *tbl;
1963 unsigned int i;
1964 int64_t rc;
1965 void *addr;
1966
184cd4a3
BH		 1967 /* XXX FIXME: Handle 64-bit only DMA devices */
1968 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1969 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1970
1971 /* We shouldn't already have a 32-bit DMA associated */
1972 if (WARN_ON(pe->tce32_seg >= 0))
1973 return;
1974
0eaf4def 1975 tbl = pnv_pci_table_alloc(phb->hose->node);
b348aa65
AK		 1976 iommu_register_group(&pe->table_group, phb->hose->global_number,
1977 pe->pe_number);
0eaf4def 1978 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
c5773822 1979
184cd4a3
BH		 1980 /* Grab a 32-bit TCE table */
1981 pe->tce32_seg = base;
1982 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1983 (base << 28), ((base + segs) << 28) - 1);
1984
1985 /* XXX Currently, we allocate one big contiguous table for the
1986 * TCEs. We only really need one chunk per 256M of TCE space
1987 * (ie per segment) but that's an optimization for later, it
1988 * requires some added smarts with our get/put_tce implementation
1989 */
1990 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1991 get_order(TCE32_TABLE_SIZE * segs));
1992 if (!tce_mem) {
1993 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1994 goto fail;
1995 }
1996 addr = page_address(tce_mem);
1997 memset(addr, 0, TCE32_TABLE_SIZE * segs);
1998
1999 /* Configure HW */
2000 for (i = 0; i < segs; i++) {
2001 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2002 pe->pe_number,
2003 base + i, 1,
2004 __pa(addr) + TCE32_TABLE_SIZE * i,
2005 TCE32_TABLE_SIZE, 0x1000);
2006 if (rc) {
2007 pe_err(pe, " Failed to configure 32-bit TCE table,"
2008 " err %ld\n", rc);
2009 goto fail;
2010 }
2011 }
2012
2013 /* Setup linux iommu table */
184cd4a3 2014 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
8fa5d454 2015 base << 28, IOMMU_PAGE_SHIFT_4K);
184cd4a3
BH		 2016
2017 /* OPAL variant of P7IOC SW invalidated TCEs */
5780fb04 2018 if (phb->ioda.tce_inval_reg)
65fd766b
GS		 2019 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
2020 TCE_PCI_SWINV_FREE |
2021 TCE_PCI_SWINV_PAIR);
5780fb04 2022
da004c36 2023 tbl->it_ops = &pnv_ioda1_iommu_ops;
4793d65d
AK		 2024 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2025 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
184cd4a3
BH		 2026 iommu_init_table(tbl, phb->hose->node);
2027
781a868f 2028 if (pe->flags & PNV_IODA_PE_DEV) {
4617082e
AK		 2029 /*
2030 * Setting table base here only for carrying iommu_group
2031 * further down to let iommu_add_device() do the job.
2032 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2033 */
2034 set_iommu_table_base(&pe->pdev->dev, tbl);
2035 iommu_add_device(&pe->pdev->dev);
c5773822 2036 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
ea30e99e 2037 pnv_ioda_setup_bus_dma(pe, pe->pbus);
74251fe2 2038
184cd4a3
BH		 2039 return;
2040 fail:
2041 /* XXX Failure: Try to fallback to 64-bit only ? */
2042 if (pe->tce32_seg >= 0)
2043 pe->tce32_seg = -1;
2044 if (tce_mem)
2045 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
0eaf4def
AK		 2046 if (tbl) {
2047 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2048 iommu_free_table(tbl, "pnv");
2049 }
184cd4a3
BH		 2050}
2051
43cb60ab
AK		 2052static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2053 int num, struct iommu_table *tbl)
2054{
2055 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2056 table_group);
2057 struct pnv_phb *phb = pe->phb;
2058 int64_t rc;
bbb845c4
AK		 2059 const unsigned long size = tbl->it_indirect_levels ?
2060 tbl->it_level_size : tbl->it_size;
43cb60ab
AK		 2061 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2062 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2063
4793d65d 2064 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
43cb60ab
AK		 2065 start_addr, start_addr + win_size - 1,
2066 IOMMU_PAGE_SIZE(tbl));
2067
2068 /*
2069 * Map TCE table through TVT. The TVE index is the PE number
2070 * shifted by 1 bit for 32-bits DMA space.
2071 */
2072 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2073 pe->pe_number,
4793d65d 2074 (pe->pe_number << 1) + num,
bbb845c4 2075 tbl->it_indirect_levels + 1,
43cb60ab 2076 __pa(tbl->it_base),
bbb845c4 2077 size << 3,
43cb60ab
AK		 2078 IOMMU_PAGE_SIZE(tbl));
2079 if (rc) {
2080 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2081 return rc;
2082 }
2083
2084 pnv_pci_link_table_and_group(phb->hose->node, num,
2085 tbl, &pe->table_group);
2086 pnv_pci_ioda2_tce_invalidate_entire(pe);
2087
2088 return 0;
2089}
2090
f87a8864 2091static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
cd15b048 2092{
cd15b048
BH		 2093 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2094 int64_t rc;
2095
2096 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2097 if (enable) {
2098 phys_addr_t top = memblock_end_of_DRAM();
2099
2100 top = roundup_pow_of_two(top);
2101 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2102 pe->pe_number,
2103 window_id,
2104 pe->tce_bypass_base,
2105 top);
2106 } else {
2107 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2108 pe->pe_number,
2109 window_id,
2110 pe->tce_bypass_base,
2111 0);
cd15b048
BH		 2112 }
2113 if (rc)
2114 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2115 else
2116 pe->tce_bypass_enabled = enable;
2117}
2118
4793d65d
AK		 2119static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2120 __u32 page_shift, __u64 window_size, __u32 levels,
2121 struct iommu_table *tbl);
2122
2123static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2124 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2125 struct iommu_table **ptbl)
2126{
2127 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2128 table_group);
2129 int nid = pe->phb->hose->node;
2130 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2131 long ret;
2132 struct iommu_table *tbl;
2133
2134 tbl = pnv_pci_table_alloc(nid);
2135 if (!tbl)
2136 return -ENOMEM;
2137
2138 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2139 bus_offset, page_shift, window_size,
2140 levels, tbl);
2141 if (ret) {
2142 iommu_free_table(tbl, "pnv");
2143 return ret;
2144 }
2145
2146 tbl->it_ops = &pnv_ioda2_iommu_ops;
2147 if (pe->phb->ioda.tce_inval_reg)
2148 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2149
2150 *ptbl = tbl;
2151
2152 return 0;
2153}
2154
46d3e1e1
AK		 2155static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2156{
2157 struct iommu_table *tbl = NULL;
2158 long rc;
2159
fa144869
NA		 2160 /*
2161 * crashkernel= specifies the kdump kernel's maximum memory at
2162 * some offset and there is no guaranteed the result is a power
2163 * of 2, which will cause errors later.
2164 */
2165 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2166
bb005455
NA		 2167 /*
2168 * In memory constrained environments, e.g. kdump kernel, the
2169 * DMA window can be larger than available memory, which will
2170 * cause errors later.
2171 */
fa144869 2172 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
bb005455 2173
46d3e1e1
AK		 2174 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2175 IOMMU_PAGE_SHIFT_4K,
bb005455 2176 window_size,
46d3e1e1
AK		 2177 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2178 if (rc) {
2179 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2180 rc);
2181 return rc;
2182 }
2183
2184 iommu_init_table(tbl, pe->phb->hose->node);
2185
2186 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2187 if (rc) {
2188 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2189 rc);
2190 pnv_ioda2_table_free(tbl);
2191 return rc;
2192 }
2193
2194 if (!pnv_iommu_bypass_disabled)
2195 pnv_pci_ioda2_set_bypass(pe, true);
2196
2197 /* OPAL variant of PHB3 invalidated TCEs */
2198 if (pe->phb->ioda.tce_inval_reg)
2199 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2200
2201 /*
2202 * Setting table base here only for carrying iommu_group
2203 * further down to let iommu_add_device() do the job.
2204 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2205 */
2206 if (pe->flags & PNV_IODA_PE_DEV)
2207 set_iommu_table_base(&pe->pdev->dev, tbl);
2208
2209 return 0;
2210}
2211
b5926430
AK		 2212#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2213static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2214 int num)
2215{
2216 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2217 table_group);
2218 struct pnv_phb *phb = pe->phb;
2219 long ret;
2220
2221 pe_info(pe, "Removing DMA window #%d\n", num);
2222
2223 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2224 (pe->pe_number << 1) + num,
2225 0/* levels */, 0/* table address */,
2226 0/* table size */, 0/* page size */);
2227 if (ret)
2228 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2229 else
2230 pnv_pci_ioda2_tce_invalidate_entire(pe);
2231
2232 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2233
2234 return ret;
2235}
2236#endif
2237
f87a8864 2238#ifdef CONFIG_IOMMU_API
00547193
AK		 2239static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2240 __u64 window_size, __u32 levels)
2241{
2242 unsigned long bytes = 0;
2243 const unsigned window_shift = ilog2(window_size);
2244 unsigned entries_shift = window_shift - page_shift;
2245 unsigned table_shift = entries_shift + 3;
2246 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2247 unsigned long direct_table_size;
2248
2249 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2250 (window_size > memory_hotplug_max()) ||
2251 !is_power_of_2(window_size))
2252 return 0;
2253
2254 /* Calculate a direct table size from window_size and levels */
2255 entries_shift = (entries_shift + levels - 1) / levels;
2256 table_shift = entries_shift + 3;
2257 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2258 direct_table_size = 1UL << table_shift;
2259
2260 for ( ; levels; --levels) {
2261 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2262
2263 tce_table_size /= direct_table_size;
2264 tce_table_size <<= 3;
2265 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2266 }
2267
2268 return bytes;
2269}
2270
f87a8864 2271static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
cd15b048 2272{
f87a8864
AK		 2273 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2274 table_group);
46d3e1e1
AK		 2275 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2276 struct iommu_table *tbl = pe->table_group.tables[0];
cd15b048 2277
f87a8864 2278 pnv_pci_ioda2_set_bypass(pe, false);
46d3e1e1
AK		 2279 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2280 pnv_ioda2_table_free(tbl);
f87a8864 2281}
cd15b048 2282
f87a8864
AK		 2283static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2284{
2285 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2286 table_group);
2287
46d3e1e1 2288 pnv_pci_ioda2_setup_default_config(pe);
cd15b048
BH		 2289}
2290
f87a8864 2291static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
00547193 2292 .get_table_size = pnv_pci_ioda2_get_table_size,
4793d65d
AK		 2293 .create_table = pnv_pci_ioda2_create_table,
2294 .set_window = pnv_pci_ioda2_set_window,
2295 .unset_window = pnv_pci_ioda2_unset_window,
f87a8864
AK		 2296 .take_ownership = pnv_ioda2_take_ownership,
2297 .release_ownership = pnv_ioda2_release_ownership,
2298};
2299#endif
2300
5780fb04
AK		 2301static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2302{
2303 const __be64 *swinvp;
2304
2305 /* OPAL variant of PHB3 invalidated TCEs */
2306 swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2307 if (!swinvp)
2308 return;
2309
2310 phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2311 phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2312}
2313
bbb845c4
AK		 2314static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2315 unsigned levels, unsigned long limit,
3ba3a73e 2316 unsigned long *current_offset, unsigned long *total_allocated)
373f5657
GS		 2317{
2318 struct page *tce_mem = NULL;
bbb845c4 2319 __be64 *addr, *tmp;
aca6913f 2320 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
bbb845c4
AK		 2321 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2322 unsigned entries = 1UL << (shift - 3);
2323 long i;
aca6913f
AK		 2324
2325 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2326 if (!tce_mem) {
2327 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2328 return NULL;
2329 }
2330 addr = page_address(tce_mem);
bbb845c4 2331 memset(addr, 0, allocated);
3ba3a73e 2332 *total_allocated += allocated;
bbb845c4
AK		 2333
2334 --levels;
2335 if (!levels) {
2336 *current_offset += allocated;
2337 return addr;
2338 }
2339
2340 for (i = 0; i < entries; ++i) {
2341 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
3ba3a73e 2342 levels, limit, current_offset, total_allocated);
bbb845c4
AK		 2343 if (!tmp)
2344 break;
2345
2346 addr[i] = cpu_to_be64(__pa(tmp) |
2347 TCE_PCI_READ | TCE_PCI_WRITE);
2348
2349 if (*current_offset >= limit)
2350 break;
2351 }
aca6913f
AK		 2352
2353 return addr;
2354}
2355
bbb845c4
AK		 2356static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2357 unsigned long size, unsigned level);
2358
aca6913f 2359static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
bbb845c4
AK		 2360 __u32 page_shift, __u64 window_size, __u32 levels,
2361 struct iommu_table *tbl)
aca6913f 2362{
373f5657 2363 void *addr;
3ba3a73e 2364 unsigned long offset = 0, level_shift, total_allocated = 0;
aca6913f
AK		 2365 const unsigned window_shift = ilog2(window_size);
2366 unsigned entries_shift = window_shift - page_shift;
2367 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2368 const unsigned long tce_table_size = 1UL << table_shift;
2369
bbb845c4
AK		 2370 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2371 return -EINVAL;
2372
aca6913f
AK		 2373 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2374 return -EINVAL;
2375
bbb845c4
AK		 2376 /* Adjust direct table size from window_size and levels */
2377 entries_shift = (entries_shift + levels - 1) / levels;
2378 level_shift = entries_shift + 3;
2379 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2380
aca6913f 2381 /* Allocate TCE table */
bbb845c4 2382 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
3ba3a73e 2383 levels, tce_table_size, &offset, &total_allocated);
bbb845c4
AK		 2384
2385 /* addr==NULL means that the first level allocation failed */
aca6913f
AK		 2386 if (!addr)
2387 return -ENOMEM;
2388
bbb845c4
AK		 2389 /*
2390 * First level was allocated but some lower level failed as
2391 * we did not allocate as much as we wanted,
2392 * release partially allocated table.
2393 */
2394 if (offset < tce_table_size) {
2395 pnv_pci_ioda2_table_do_free_pages(addr,
2396 1ULL << (level_shift - 3), levels - 1);
2397 return -ENOMEM;
2398 }
2399
aca6913f
AK		 2400 /* Setup linux iommu table */
2401 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2402 page_shift);
bbb845c4
AK		 2403 tbl->it_level_size = 1ULL << (level_shift - 3);
2404 tbl->it_indirect_levels = levels - 1;
3ba3a73e 2405 tbl->it_allocated_size = total_allocated;
aca6913f
AK		 2406
2407 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2408 window_size, tce_table_size, bus_offset);
2409
2410 return 0;
2411}
2412
bbb845c4
AK		 2413static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2414 unsigned long size, unsigned level)
2415{
2416 const unsigned long addr_ul = (unsigned long) addr &
2417 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2418
2419 if (level) {
2420 long i;
2421 u64 *tmp = (u64 *) addr_ul;
2422
2423 for (i = 0; i < size; ++i) {
2424 unsigned long hpa = be64_to_cpu(tmp[i]);
2425
2426 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2427 continue;
2428
2429 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2430 level - 1);
2431 }
2432 }
2433
2434 free_pages(addr_ul, get_order(size << 3));
2435}
2436
aca6913f
AK		 2437static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2438{
bbb845c4
AK		 2439 const unsigned long size = tbl->it_indirect_levels ?
2440 tbl->it_level_size : tbl->it_size;
2441
aca6913f
AK		 2442 if (!tbl->it_size)
2443 return;
2444
bbb845c4
AK		 2445 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2446 tbl->it_indirect_levels);
aca6913f
AK		 2447}
2448
2449static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2450 struct pnv_ioda_pe *pe)
2451{
373f5657
GS		 2452 int64_t rc;
2453
2454 /* We shouldn't already have a 32-bit DMA associated */
2455 if (WARN_ON(pe->tce32_seg >= 0))
2456 return;
2457
f87a8864
AK		 2458 /* TVE #1 is selected by PCI address bit 59 */
2459 pe->tce_bypass_base = 1ull << 59;
2460
b348aa65
AK		 2461 iommu_register_group(&pe->table_group, phb->hose->global_number,
2462 pe->pe_number);
c5773822 2463
373f5657
GS		 2464 /* The PE will reserve all possible 32-bits space */
2465 pe->tce32_seg = 0;
373f5657 2466 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
aca6913f 2467 phb->ioda.m32_pci_base);
373f5657 2468
aca6913f 2469 /* Setup linux iommu table */
4793d65d
AK		 2470 pe->table_group.tce32_start = 0;
2471 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2472 pe->table_group.max_dynamic_windows_supported =
2473 IOMMU_TABLE_GROUP_MAX_TABLES;
2474 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2475 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
e5aad1e6
AK		 2476#ifdef CONFIG_IOMMU_API
2477 pe->table_group.ops = &pnv_pci_ioda2_ops;
2478#endif
2479
46d3e1e1 2480 rc = pnv_pci_ioda2_setup_default_config(pe);
373f5657 2481 if (rc) {
46d3e1e1
AK		 2482 if (pe->tce32_seg >= 0)
2483 pe->tce32_seg = -1;
2484 return;
373f5657
GS		 2485 }
2486
46d3e1e1 2487 if (pe->flags & PNV_IODA_PE_DEV)
4617082e 2488 iommu_add_device(&pe->pdev->dev);
46d3e1e1 2489 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
ea30e99e 2490 pnv_ioda_setup_bus_dma(pe, pe->pbus);
373f5657
GS		 2491}
2492
cad5cef6 2493static void pnv_ioda_setup_dma(struct pnv_phb *phb)
184cd4a3
BH		 2494{
2495 struct pci_controller *hose = phb->hose;
2496 unsigned int residual, remaining, segs, tw, base;
2497 struct pnv_ioda_pe *pe;
2498
2499 /* If we have more PE# than segments available, hand out one
2500 * per PE until we run out and let the rest fail. If not,
2501 * then we assign at least one segment per PE, plus more based
2502 * on the amount of devices under that PE
2503 */
2504 if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2505 residual = 0;
2506 else
2507 residual = phb->ioda.tce32_count -
2508 phb->ioda.dma_pe_count;
2509
2510 pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2511 hose->global_number, phb->ioda.tce32_count);
2512 pr_info("PCI: %d PE# for a total weight of %d\n",
2513 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2514
5780fb04
AK		 2515 pnv_pci_ioda_setup_opal_tce_kill(phb);
2516
184cd4a3
BH		 2517 /* Walk our PE list and configure their DMA segments, hand them
2518 * out one base segment plus any residual segments based on
2519 * weight
2520 */
2521 remaining = phb->ioda.tce32_count;
2522 tw = phb->ioda.dma_weight;
2523 base = 0;
7ebdf956 2524 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
184cd4a3
BH		 2525 if (!pe->dma_weight)
2526 continue;
2527 if (!remaining) {
2528 pe_warn(pe, "No DMA32 resources available\n");
2529 continue;
2530 }
2531 segs = 1;
2532 if (residual) {
2533 segs += ((pe->dma_weight * residual) + (tw / 2)) / tw;
2534 if (segs > remaining)
2535 segs = remaining;
2536 }
373f5657
GS		 2537
2538 /*
2539 * For IODA2 compliant PHB3, we needn't care about the weight.
2540 * The all available 32-bits DMA space will be assigned to
2541 * the specific PE.
2542 */
2543 if (phb->type == PNV_PHB_IODA1) {
2544 pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2545 pe->dma_weight, segs);
2546 pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
5d2aa710 2547 } else if (phb->type == PNV_PHB_IODA2) {
373f5657
GS		 2548 pe_info(pe, "Assign DMA32 space\n");
2549 segs = 0;
2550 pnv_pci_ioda2_setup_dma_pe(phb, pe);
5d2aa710
AP		 2551 } else if (phb->type == PNV_PHB_NPU) {
2552 /*
2553 * We initialise the DMA space for an NPU PHB
2554 * after setup of the PHB is complete as we
2555 * point the NPU TVT to the the same location
2556 * as the PHB3 TVT.
2557 */
373f5657
GS		 2558 }
2559
184cd4a3
BH		 2560 remaining -= segs;
2561 base += segs;
2562 }
2563}
2564
2565#ifdef CONFIG_PCI_MSI
137436c9
GS		 2566static void pnv_ioda2_msi_eoi(struct irq_data *d)
2567{
2568 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2569 struct irq_chip *chip = irq_data_get_irq_chip(d);
2570 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2571 ioda.irq_chip);
2572 int64_t rc;
2573
2574 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2575 WARN_ON_ONCE(rc);
2576
2577 icp_native_eoi(d);
2578}
2579
fd9a1c26
IM		 2580
2581static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2582{
2583 struct irq_data *idata;
2584 struct irq_chip *ichip;
2585
2586 if (phb->type != PNV_PHB_IODA2)
2587 return;
2588
2589 if (!phb->ioda.irq_chip_init) {
2590 /*
2591 * First time we setup an MSI IRQ, we need to setup the
2592 * corresponding IRQ chip to route correctly.
2593 */
2594 idata = irq_get_irq_data(virq);
2595 ichip = irq_data_get_irq_chip(idata);
2596 phb->ioda.irq_chip_init = 1;
2597 phb->ioda.irq_chip = *ichip;
2598 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2599 }
2600 irq_set_chip(virq, &phb->ioda.irq_chip);
2601}
2602
80c49c7e
IM		 2603#ifdef CONFIG_CXL_BASE
2604
6f963ec2 2605struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
80c49c7e
IM		 2606{
2607 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2608
6f963ec2 2609 return of_node_get(hose->dn);
80c49c7e 2610}
6f963ec2 2611EXPORT_SYMBOL(pnv_pci_get_phb_node);
80c49c7e 2612
1212aa1c 2613int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
80c49c7e
IM		 2614{
2615 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2616 struct pnv_phb *phb = hose->private_data;
2617 struct pnv_ioda_pe *pe;
2618 int rc;
2619
2620 pe = pnv_ioda_get_pe(dev);
2621 if (!pe)
2622 return -ENODEV;
2623
2624 pe_info(pe, "Switching PHB to CXL\n");
2625
1212aa1c 2626 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
80c49c7e
IM		 2627 if (rc)
2628 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2629
2630 return rc;
2631}
1212aa1c 2632EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
80c49c7e
IM		 2633
2634/* Find PHB for cxl dev and allocate MSI hwirqs?
2635 * Returns the absolute hardware IRQ number
2636 */
2637int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2638{
2639 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2640 struct pnv_phb *phb = hose->private_data;
2641 int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2642
2643 if (hwirq < 0) {
2644 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2645 return -ENOSPC;
2646 }
2647
2648 return phb->msi_base + hwirq;
2649}
2650EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2651
2652void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2653{
2654 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2655 struct pnv_phb *phb = hose->private_data;
2656
2657 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2658}
2659EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2660
2661void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2662 struct pci_dev *dev)
2663{
2664 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2665 struct pnv_phb *phb = hose->private_data;
2666 int i, hwirq;
2667
2668 for (i = 1; i < CXL_IRQ_RANGES; i++) {
2669 if (!irqs->range[i])
2670 continue;
2671 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
2672 i, irqs->offset[i],
2673 irqs->range[i]);
2674 hwirq = irqs->offset[i] - phb->msi_base;
2675 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2676 irqs->range[i]);
2677 }
2678}
2679EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2680
2681int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2682 struct pci_dev *dev, int num)
2683{
2684 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2685 struct pnv_phb *phb = hose->private_data;
2686 int i, hwirq, try;
2687
2688 memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2689
2690 /* 0 is reserved for the multiplexed PSL DSI interrupt */
2691 for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2692 try = num;
2693 while (try) {
2694 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2695 if (hwirq >= 0)
2696 break;
2697 try /= 2;
2698 }
2699 if (!try)
2700 goto fail;
2701
2702 irqs->offset[i] = phb->msi_base + hwirq;
2703 irqs->range[i] = try;
2704 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
2705 i, irqs->offset[i], irqs->range[i]);
2706 num -= try;
2707 }
2708 if (num)
2709 goto fail;
2710
2711 return 0;
2712fail:
2713 pnv_cxl_release_hwirq_ranges(irqs, dev);
2714 return -ENOSPC;
2715}
2716EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2717
2718int pnv_cxl_get_irq_count(struct pci_dev *dev)
2719{
2720 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2721 struct pnv_phb *phb = hose->private_data;
2722
2723 return phb->msi_bmp.irq_count;
2724}
2725EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2726
2727int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2728 unsigned int virq)
2729{
2730 struct pci_controller *hose = pci_bus_to_host(dev->bus);
2731 struct pnv_phb *phb = hose->private_data;
2732 unsigned int xive_num = hwirq - phb->msi_base;
2733 struct pnv_ioda_pe *pe;
2734 int rc;
2735
2736 if (!(pe = pnv_ioda_get_pe(dev)))
2737 return -ENODEV;
2738
2739 /* Assign XIVE to PE */
2740 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2741 if (rc) {
2742 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2743 "hwirq 0x%x XIVE 0x%x PE\n",
2744 pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2745 return -EIO;
2746 }
2747 set_msi_irq_chip(phb, virq);
2748
2749 return 0;
2750}
2751EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2752#endif
2753
184cd4a3 2754static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
137436c9
GS		 2755 unsigned int hwirq, unsigned int virq,
2756 unsigned int is_64, struct msi_msg *msg)
184cd4a3
BH		 2757{
2758 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2759 unsigned int xive_num = hwirq - phb->msi_base;
3a1a4661 2760 __be32 data;
184cd4a3
BH		 2761 int rc;
2762
2763 /* No PE assigned ? bail out ... no MSI for you ! */
2764 if (pe == NULL)
2765 return -ENXIO;
2766
2767 /* Check if we have an MVE */
2768 if (pe->mve_number < 0)
2769 return -ENXIO;
2770
b72c1f65 2771 /* Force 32-bit MSI on some broken devices */
36074381 2772 if (dev->no_64bit_msi)
b72c1f65
BH		 2773 is_64 = 0;
2774
184cd4a3
BH		 2775 /* Assign XIVE to PE */
2776 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2777 if (rc) {
2778 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2779 pci_name(dev), rc, xive_num);
2780 return -EIO;
2781 }
2782
2783 if (is_64) {
3a1a4661
BH		 2784 __be64 addr64;
2785
184cd4a3
BH		 2786 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2787 &addr64, &data);
2788 if (rc) {
2789 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2790 pci_name(dev), rc);
2791 return -EIO;
2792 }
3a1a4661
BH		 2793 msg->address_hi = be64_to_cpu(addr64) >> 32;
2794 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
184cd4a3 2795 } else {
3a1a4661
BH		 2796 __be32 addr32;
2797
184cd4a3
BH		 2798 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2799 &addr32, &data);
2800 if (rc) {
2801 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2802 pci_name(dev), rc);
2803 return -EIO;
2804 }
2805 msg->address_hi = 0;
3a1a4661 2806 msg->address_lo = be32_to_cpu(addr32);
184cd4a3 2807 }
3a1a4661 2808 msg->data = be32_to_cpu(data);
184cd4a3 2809
fd9a1c26 2810 set_msi_irq_chip(phb, virq);
137436c9 2811
184cd4a3
BH		 2812 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2813 " address=%x_%08x data=%x PE# %d\n",
2814 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2815 msg->address_hi, msg->address_lo, data, pe->pe_number);
2816
2817 return 0;
2818}
2819
2820static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2821{
fb1b55d6 2822 unsigned int count;
184cd4a3
BH		 2823 const __be32 *prop = of_get_property(phb->hose->dn,
2824 "ibm,opal-msi-ranges", NULL);
2825 if (!prop) {
2826 /* BML Fallback */
2827 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2828 }
2829 if (!prop)
2830 return;
2831
2832 phb->msi_base = be32_to_cpup(prop);
fb1b55d6
GS		 2833 count = be32_to_cpup(prop + 1);
2834 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
184cd4a3
BH		 2835 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2836 phb->hose->global_number);
2837 return;
2838 }
fb1b55d6 2839
184cd4a3
BH		 2840 phb->msi_setup = pnv_pci_ioda_msi_setup;
2841 phb->msi32_support = 1;
2842 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
fb1b55d6 2843 count, phb->msi_base);
184cd4a3
BH		 2844}
2845#else
2846static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2847#endif /* CONFIG_PCI_MSI */
2848
6e628c7d
WY		 2849#ifdef CONFIG_PCI_IOV
2850static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2851{
2852 struct pci_controller *hose;
2853 struct pnv_phb *phb;
2854 struct resource *res;
2855 int i;
2856 resource_size_t size;
2857 struct pci_dn *pdn;
5b88ec22 2858 int mul, total_vfs;
6e628c7d
WY		 2859
2860 if (!pdev->is_physfn || pdev->is_added)
2861 return;
2862
2863 hose = pci_bus_to_host(pdev->bus);
2864 phb = hose->private_data;
2865
2866 pdn = pci_get_pdn(pdev);
2867 pdn->vfs_expanded = 0;
2868
5b88ec22
WY		 2869 total_vfs = pci_sriov_get_totalvfs(pdev);
2870 pdn->m64_per_iov = 1;
2871 mul = phb->ioda.total_pe;
2872
2873 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2874 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2875 if (!res->flags || res->parent)
2876 continue;
2877 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2878 dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2879 i, res);
2880 continue;
2881 }
2882
2883 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2884
2885 /* bigger than 64M */
2886 if (size > (1 << 26)) {
2887 dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2888 i, res);
2889 pdn->m64_per_iov = M64_PER_IOV;
2890 mul = roundup_pow_of_two(total_vfs);
2891 break;
2892 }
2893 }
2894
6e628c7d
WY		 2895 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2896 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2897 if (!res->flags || res->parent)
2898 continue;
2899 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2900 dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2901 i, res);
2902 continue;
2903 }
2904
2905 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2906 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
5b88ec22 2907 res->end = res->start + size * mul - 1;
6e628c7d
WY		 2908 dev_dbg(&pdev->dev, " %pR\n", res);
2909 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
5b88ec22 2910 i, res, mul);
6e628c7d 2911 }
5b88ec22 2912 pdn->vfs_expanded = mul;
6e628c7d
WY		 2913}
2914#endif /* CONFIG_PCI_IOV */
2915
11685bec
GS		 2916/*
2917 * This function is supposed to be called on basis of PE from top
2918 * to bottom style. So the the I/O or MMIO segment assigned to
2919 * parent PE could be overrided by its child PEs if necessary.
2920 */
cad5cef6
GKH		 2921static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2922 struct pnv_ioda_pe *pe)
11685bec
GS		 2923{
2924 struct pnv_phb *phb = hose->private_data;
2925 struct pci_bus_region region;
2926 struct resource *res;
2927 int i, index;
2928 int rc;
2929
2930 /*
2931 * NOTE: We only care PCI bus based PE for now. For PCI
2932 * device based PE, for example SRIOV sensitive VF should
2933 * be figured out later.
2934 */
2935 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2936
2937 pci_bus_for_each_resource(pe->pbus, res, i) {
2938 if (!res || !res->flags ||
2939 res->start > res->end)
2940 continue;
2941
2942 if (res->flags & IORESOURCE_IO) {
2943 region.start = res->start - phb->ioda.io_pci_base;
2944 region.end = res->end - phb->ioda.io_pci_base;
2945 index = region.start / phb->ioda.io_segsize;
2946
2947 while (index < phb->ioda.total_pe &&
2948 region.start <= region.end) {
2949 phb->ioda.io_segmap[index] = pe->pe_number;
2950 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2951 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2952 if (rc != OPAL_SUCCESS) {
2953 pr_err("%s: OPAL error %d when mapping IO "
2954 "segment #%d to PE#%d\n",
2955 __func__, rc, index, pe->pe_number);
2956 break;
2957 }
2958
2959 region.start += phb->ioda.io_segsize;
2960 index++;
2961 }
027fa02f
GS		 2962 } else if ((res->flags & IORESOURCE_MEM) &&
2963 !pnv_pci_is_mem_pref_64(res->flags)) {
11685bec 2964 region.start = res->start -
3fd47f06 2965 hose->mem_offset[0] -
11685bec
GS		 2966 phb->ioda.m32_pci_base;
2967 region.end = res->end -
3fd47f06 2968 hose->mem_offset[0] -
11685bec
GS		 2969 phb->ioda.m32_pci_base;
2970 index = region.start / phb->ioda.m32_segsize;
2971
2972 while (index < phb->ioda.total_pe &&
2973 region.start <= region.end) {
2974 phb->ioda.m32_segmap[index] = pe->pe_number;
2975 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2976 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2977 if (rc != OPAL_SUCCESS) {
2978 pr_err("%s: OPAL error %d when mapping M32 "
2979 "segment#%d to PE#%d",
2980 __func__, rc, index, pe->pe_number);
2981 break;
2982 }
2983
2984 region.start += phb->ioda.m32_segsize;
2985 index++;
2986 }
2987 }
2988 }
2989}
2990
cad5cef6 2991static void pnv_pci_ioda_setup_seg(void)
11685bec
GS		 2992{
2993 struct pci_controller *tmp, *hose;
2994 struct pnv_phb *phb;
2995 struct pnv_ioda_pe *pe;
2996
2997 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2998 phb = hose->private_data;
5d2aa710
AP		 2999
3000 /* NPU PHB does not support IO or MMIO segmentation */
3001 if (phb->type == PNV_PHB_NPU)
3002 continue;
3003
11685bec
GS		 3004 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3005 pnv_ioda_setup_pe_seg(hose, pe);
3006 }
3007 }
3008}
3009
cad5cef6 3010static void pnv_pci_ioda_setup_DMA(void)
13395c48
GS		 3011{
3012 struct pci_controller *hose, *tmp;
db1266c8 3013 struct pnv_phb *phb;
13395c48
GS		 3014
3015 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3016 pnv_ioda_setup_dma(hose->private_data);
db1266c8
GS		 3017
3018 /* Mark the PHB initialization done */
3019 phb = hose->private_data;
3020 phb->initialized = 1;
13395c48
GS		 3021 }
3022}
3023
37c367f2
GS		 3024static void pnv_pci_ioda_create_dbgfs(void)
3025{
3026#ifdef CONFIG_DEBUG_FS
3027 struct pci_controller *hose, *tmp;
3028 struct pnv_phb *phb;
3029 char name[16];
3030
3031 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3032 phb = hose->private_data;
3033
3034 sprintf(name, "PCI%04x", hose->global_number);
3035 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3036 if (!phb->dbgfs)
3037 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3038 __func__, hose->global_number);
3039 }
3040#endif /* CONFIG_DEBUG_FS */
3041}
3042
5d2aa710
AP		 3043static void pnv_npu_ioda_fixup(void)
3044{
3045 bool enable_bypass;
3046 struct pci_controller *hose, *tmp;
3047 struct pnv_phb *phb;
3048 struct pnv_ioda_pe *pe;
3049
3050 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3051 phb = hose->private_data;
3052 if (phb->type != PNV_PHB_NPU)
3053 continue;
3054
3055 list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
3056 enable_bypass = dma_get_mask(&pe->pdev->dev) ==
3057 DMA_BIT_MASK(64);
3058 pnv_npu_init_dma_pe(pe);
3059 pnv_npu_dma_set_bypass(pe, enable_bypass);
3060 }
3061 }
3062}
3063
cad5cef6 3064static void pnv_pci_ioda_fixup(void)
fb446ad0
GS		 3065{
3066 pnv_pci_ioda_setup_PEs();
11685bec 3067 pnv_pci_ioda_setup_seg();
13395c48 3068 pnv_pci_ioda_setup_DMA();
e9cc17d4 3069
37c367f2
GS		 3070 pnv_pci_ioda_create_dbgfs();
3071
e9cc17d4 3072#ifdef CONFIG_EEH
e9cc17d4 3073 eeh_init();
dadcd6d6 3074 eeh_addr_cache_build();
e9cc17d4 3075#endif
5d2aa710
AP		 3076
3077 /* Link NPU IODA tables to their PCI devices. */
3078 pnv_npu_ioda_fixup();
fb446ad0
GS		 3079}
3080
271fd03a
GS		 3081/*
3082 * Returns the alignment for I/O or memory windows for P2P
3083 * bridges. That actually depends on how PEs are segmented.
3084 * For now, we return I/O or M32 segment size for PE sensitive
3085 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3086 * 1MiB for memory) will be returned.
3087 *
3088 * The current PCI bus might be put into one PE, which was
3089 * create against the parent PCI bridge. For that case, we
3090 * needn't enlarge the alignment so that we can save some
3091 * resources.
3092 */
3093static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3094 unsigned long type)
3095{
3096 struct pci_dev *bridge;
3097 struct pci_controller *hose = pci_bus_to_host(bus);
3098 struct pnv_phb *phb = hose->private_data;
3099 int num_pci_bridges = 0;
3100
3101 bridge = bus->self;
3102 while (bridge) {
3103 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3104 num_pci_bridges++;
3105 if (num_pci_bridges >= 2)
3106 return 1;
3107 }
3108
3109 bridge = bridge->bus->self;
3110 }
3111
262af557
GC		 3112 /* We fail back to M32 if M64 isn't supported */
3113 if (phb->ioda.m64_segsize &&
3114 pnv_pci_is_mem_pref_64(type))
3115 return phb->ioda.m64_segsize;
271fd03a
GS		 3116 if (type & IORESOURCE_MEM)
3117 return phb->ioda.m32_segsize;
3118
3119 return phb->ioda.io_segsize;
3120}
3121
5350ab3f
WY		 3122#ifdef CONFIG_PCI_IOV
3123static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3124 int resno)
3125{
3126 struct pci_dn *pdn = pci_get_pdn(pdev);
3127 resource_size_t align, iov_align;
3128
3129 iov_align = resource_size(&pdev->resource[resno]);
3130 if (iov_align)
3131 return iov_align;
3132
3133 align = pci_iov_resource_size(pdev, resno);
3134 if (pdn->vfs_expanded)
3135 return pdn->vfs_expanded * align;
3136
3137 return align;
3138}
3139#endif /* CONFIG_PCI_IOV */
3140
184cd4a3
BH		 3141/* Prevent enabling devices for which we couldn't properly
3142 * assign a PE
3143 */
c88c2a18 3144static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
184cd4a3 3145{
db1266c8
GS		 3146 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3147 struct pnv_phb *phb = hose->private_data;
3148 struct pci_dn *pdn;
184cd4a3 3149
db1266c8
GS		 3150 /* The function is probably called while the PEs have
3151 * not be created yet. For example, resource reassignment
3152 * during PCI probe period. We just skip the check if
3153 * PEs isn't ready.
3154 */
3155 if (!phb->initialized)
c88c2a18 3156 return true;
db1266c8 3157
b72c1f65 3158 pdn = pci_get_pdn(dev);
184cd4a3 3159 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
c88c2a18 3160 return false;
db1266c8 3161
c88c2a18 3162 return true;
184cd4a3
BH		 3163}
3164
3165static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3166 u32 devfn)
3167{
3168 return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3169}
3170
7a8e6bbf 3171static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
73ed148a 3172{
7a8e6bbf
MN		 3173 struct pnv_phb *phb = hose->private_data;
3174
d1a85eee 3175 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
73ed148a
BH		 3176 OPAL_ASSERT_RESET);
3177}
3178
92ae0353
DA		 3179static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3180 .dma_dev_setup = pnv_pci_dma_dev_setup,
3181#ifdef CONFIG_PCI_MSI
3182 .setup_msi_irqs = pnv_setup_msi_irqs,
3183 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3184#endif
3185 .enable_device_hook = pnv_pci_enable_device_hook,
3186 .window_alignment = pnv_pci_window_alignment,
3187 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
763d2d8d 3188 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
53522982 3189 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
7a8e6bbf 3190 .shutdown = pnv_pci_ioda_shutdown,
92ae0353
DA		 3191};
3192
5d2aa710
AP		 3193static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3194 .dma_dev_setup = pnv_pci_dma_dev_setup,
3195#ifdef CONFIG_PCI_MSI
3196 .setup_msi_irqs = pnv_setup_msi_irqs,
3197 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3198#endif
3199 .enable_device_hook = pnv_pci_enable_device_hook,
3200 .window_alignment = pnv_pci_window_alignment,
3201 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3202 .dma_set_mask = pnv_npu_dma_set_mask,
3203 .shutdown = pnv_pci_ioda_shutdown,
3204};
3205
e51df2c1
AB		 3206static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3207 u64 hub_id, int ioda_type)
184cd4a3
BH		 3208{
3209 struct pci_controller *hose;
184cd4a3 3210 struct pnv_phb *phb;
8184616f 3211 unsigned long size, m32map_off, pemap_off, iomap_off = 0;
c681b93c 3212 const __be64 *prop64;
3a1a4661 3213 const __be32 *prop32;
f1b7cc3e 3214 int len;
184cd4a3
BH		 3215 u64 phb_id;
3216 void *aux;
3217 long rc;
3218
58d714ec 3219 pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
184cd4a3
BH		 3220
3221 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3222 if (!prop64) {
3223 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3224 return;
3225 }
3226 phb_id = be64_to_cpup(prop64);
3227 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3228
e39f223f 3229 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
58d714ec
GS		 3230
3231 /* Allocate PCI controller */
58d714ec
GS		 3232 phb->hose = hose = pcibios_alloc_controller(np);
3233 if (!phb->hose) {
3234 pr_err(" Can't allocate PCI controller for %s\n",
184cd4a3 3235 np->full_name);
e39f223f 3236 memblock_free(__pa(phb), sizeof(struct pnv_phb));
184cd4a3
BH		 3237 return;
3238 }
3239
3240 spin_lock_init(&phb->lock);
f1b7cc3e
GS		 3241 prop32 = of_get_property(np, "bus-range", &len);
3242 if (prop32 && len == 8) {
3a1a4661
BH		 3243 hose->first_busno = be32_to_cpu(prop32[0]);
3244 hose->last_busno = be32_to_cpu(prop32[1]);
f1b7cc3e
GS		 3245 } else {
3246 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3247 hose->first_busno = 0;
3248 hose->last_busno = 0xff;
3249 }
184cd4a3 3250 hose->private_data = phb;
e9cc17d4 3251 phb->hub_id = hub_id;
184cd4a3 3252 phb->opal_id = phb_id;
aa0c033f 3253 phb->type = ioda_type;
781a868f 3254 mutex_init(&phb->ioda.pe_alloc_mutex);
184cd4a3 3255
cee72d5b
BH		 3256 /* Detect specific models for error handling */
3257 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3258 phb->model = PNV_PHB_MODEL_P7IOC;
f3d40c25 3259 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
aa0c033f 3260 phb->model = PNV_PHB_MODEL_PHB3;
5d2aa710
AP		 3261 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3262 phb->model = PNV_PHB_MODEL_NPU;
cee72d5b
BH		 3263 else
3264 phb->model = PNV_PHB_MODEL_UNKNOWN;
3265
aa0c033f 3266 /* Parse 32-bit and IO ranges (if any) */
2f1ec02e 3267 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
184cd4a3 3268
aa0c033f 3269 /* Get registers */
184cd4a3
BH		 3270 phb->regs = of_iomap(np, 0);
3271 if (phb->regs == NULL)
3272 pr_err(" Failed to map registers !\n");
3273
184cd4a3 3274 /* Initialize more IODA stuff */
36954dc7 3275 phb->ioda.total_pe = 1;
aa0c033f 3276 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
36954dc7 3277 if (prop32)
3a1a4661 3278 phb->ioda.total_pe = be32_to_cpup(prop32);
36954dc7
GS		 3279 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3280 if (prop32)
3281 phb->ioda.reserved_pe = be32_to_cpup(prop32);
262af557
GC		 3282
3283 /* Parse 64-bit MMIO range */
3284 pnv_ioda_parse_m64_window(phb);
3285
184cd4a3 3286 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
aa0c033f 3287 /* FW Has already off top 64k of M32 space (MSI space) */
184cd4a3
BH		 3288 phb->ioda.m32_size += 0x10000;
3289
3290 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3fd47f06 3291 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
184cd4a3
BH		 3292 phb->ioda.io_size = hose->pci_io_size;
3293 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3294 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3295
c35d2a8c 3296 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
184cd4a3
BH		 3297 size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3298 m32map_off = size;
e47747f4 3299 size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
c35d2a8c
GS		 3300 if (phb->type == PNV_PHB_IODA1) {
3301 iomap_off = size;
3302 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3303 }
184cd4a3
BH		 3304 pemap_off = size;
3305 size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
e39f223f 3306 aux = memblock_virt_alloc(size, 0);
184cd4a3
BH		 3307 phb->ioda.pe_alloc = aux;
3308 phb->ioda.m32_segmap = aux + m32map_off;
c35d2a8c
GS		 3309 if (phb->type == PNV_PHB_IODA1)
3310 phb->ioda.io_segmap = aux + iomap_off;
184cd4a3 3311 phb->ioda.pe_array = aux + pemap_off;
36954dc7 3312 set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
184cd4a3 3313
7ebdf956 3314 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
184cd4a3 3315 INIT_LIST_HEAD(&phb->ioda.pe_list);
781a868f 3316 mutex_init(&phb->ioda.pe_list_mutex);
184cd4a3
BH		 3317
3318 /* Calculate how many 32-bit TCE segments we have */
3319 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3320
aa0c033f 3321#if 0 /* We should really do that ... */
184cd4a3
BH		 3322 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3323 window_type,
3324 window_num,
3325 starting_real_address,
3326 starting_pci_address,
3327 segment_size);
3328#endif
3329
262af557
GC		 3330 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3331 phb->ioda.total_pe, phb->ioda.reserved_pe,
3332 phb->ioda.m32_size, phb->ioda.m32_segsize);
3333 if (phb->ioda.m64_size)
3334 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3335 phb->ioda.m64_size, phb->ioda.m64_segsize);
3336 if (phb->ioda.io_size)
3337 pr_info(" IO: 0x%x [segment=0x%x]\n",
3338 phb->ioda.io_size, phb->ioda.io_segsize);
3339
184cd4a3 3340
184cd4a3 3341 phb->hose->ops = &pnv_pci_ops;
49dec922
GS		 3342 phb->get_pe_state = pnv_ioda_get_pe_state;
3343 phb->freeze_pe = pnv_ioda_freeze_pe;
3344 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
184cd4a3
BH		 3345
3346 /* Setup RID -> PE mapping function */
3347 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3348
3349 /* Setup TCEs */
3350 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3351
3352 /* Setup MSI support */
3353 pnv_pci_init_ioda_msis(phb);
3354
c40a4210
GS		 3355 /*
3356 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3357 * to let the PCI core do resource assignment. It's supposed
3358 * that the PCI core will do correct I/O and MMIO alignment
3359 * for the P2P bridge bars so that each PCI bus (excluding
3360 * the child P2P bridges) can form individual PE.
184cd4a3 3361 */
fb446ad0 3362 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
5d2aa710
AP		 3363
3364 if (phb->type == PNV_PHB_NPU)
3365 hose->controller_ops = pnv_npu_ioda_controller_ops;
3366 else
3367 hose->controller_ops = pnv_pci_ioda_controller_ops;
ad30cb99 3368
6e628c7d
WY		 3369#ifdef CONFIG_PCI_IOV
3370 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
5350ab3f 3371 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
ad30cb99
ME		 3372#endif
3373
c40a4210 3374 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
184cd4a3
BH		 3375
3376 /* Reset IODA tables to a clean state */
d1a85eee 3377 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
184cd4a3 3378 if (rc)
f11fe552 3379 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
361f2a2a
GS		 3380
3381 /* If we're running in kdump kerenl, the previous kerenl never
3382 * shutdown PCI devices correctly. We already got IODA table
3383 * cleaned out. So we have to issue PHB reset to stop all PCI
3384 * transactions from previous kerenl.
3385 */
3386 if (is_kdump_kernel()) {
3387 pr_info(" Issue PHB reset ...\n");
cadf364d
GS		 3388 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3389 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
361f2a2a 3390 }
262af557 3391
9e9e8935
GS		 3392 /* Remove M64 resource if we can't configure it successfully */
3393 if (!phb->init_m64 || phb->init_m64(phb))
262af557 3394 hose->mem_resources[1].flags = 0;
aa0c033f
GS		 3395}
3396
67975005 3397void __init pnv_pci_init_ioda2_phb(struct device_node *np)
aa0c033f 3398{
e9cc17d4 3399 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
184cd4a3
BH		 3400}
3401
5d2aa710
AP		 3402void __init pnv_pci_init_npu_phb(struct device_node *np)
3403{
3404 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3405}
3406
184cd4a3
BH		 3407void __init pnv_pci_init_ioda_hub(struct device_node *np)
3408{
3409 struct device_node *phbn;
c681b93c 3410 const __be64 *prop64;
184cd4a3
BH		 3411 u64 hub_id;
3412
3413 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3414
3415 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3416 if (!prop64) {
3417 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3418 return;
3419 }
3420 hub_id = be64_to_cpup(prop64);
3421 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3422
3423 /* Count child PHBs */
3424 for_each_child_of_node(np, phbn) {
3425 /* Look for IODA1 PHBs */
3426 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
e9cc17d4 3427 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
184cd4a3
BH		 3428 }
3429}
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