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CommitLineData
184cd4a3
BH		 1/*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
cee72d5b 12#undef DEBUG
184cd4a3
BH		 13
14#include <linux/kernel.h>
15#include <linux/pci.h>
361f2a2a 16#include <linux/crash_dump.h>
184cd4a3
BH		 17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20#include <linux/bootmem.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/msi.h>
cd15b048 24#include <linux/memblock.h>
ac9a5889 25#include <linux/iommu.h>
e57080f1 26#include <linux/rculist.h>
4793d65d 27#include <linux/sizes.h>
184cd4a3
BH		 28
29#include <asm/sections.h>
30#include <asm/io.h>
31#include <asm/prom.h>
32#include <asm/pci-bridge.h>
33#include <asm/machdep.h>
fb1b55d6 34#include <asm/msi_bitmap.h>
184cd4a3
BH		 35#include <asm/ppc-pci.h>
36#include <asm/opal.h>
37#include <asm/iommu.h>
38#include <asm/tce.h>
137436c9 39#include <asm/xics.h>
7644d581 40#include <asm/debugfs.h>
262af557 41#include <asm/firmware.h>
80c49c7e 42#include <asm/pnv-pci.h>
aca6913f 43#include <asm/mmzone.h>
80c49c7e 44
ec249dd8 45#include <misc/cxl-base.h>
184cd4a3
BH		 46
47#include "powernv.h"
48#include "pci.h"
49
99451551
GS		 50#define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51#define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
acce971c 52#define PNV_IODA1_DMA32_SEGSIZE 0x10000000
781a868f 53
bbb845c4
AK		 54#define POWERNV_IOMMU_DEFAULT_LEVELS 1
55#define POWERNV_IOMMU_MAX_LEVELS 5
56
9497a1c1 57static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
aca6913f
AK		 58static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
59
7d623e42 60void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
6d31c2fa
JP		 61 const char *fmt, ...)
62{
63 struct va_format vaf;
64 va_list args;
65 char pfix[32];
66
67 va_start(args, fmt);
68
69 vaf.fmt = fmt;
70 vaf.va = &args;
71
781a868f 72 if (pe->flags & PNV_IODA_PE_DEV)
6d31c2fa 73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
781a868f 74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
6d31c2fa
JP		 75 sprintf(pfix, "%04x:%02x ",
76 pci_domain_nr(pe->pbus), pe->pbus->number);
781a868f
WY		 77#ifdef CONFIG_PCI_IOV
78 else if (pe->flags & PNV_IODA_PE_VF)
79 sprintf(pfix, "%04x:%02x:%2x.%d",
80 pci_domain_nr(pe->parent_dev->bus),
81 (pe->rid & 0xff00) >> 8,
82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
83#endif /* CONFIG_PCI_IOV*/
6d31c2fa 84
1f52f176 85 printk("%spci %s: [PE# %.2x] %pV",
6d31c2fa
JP		 86 level, pfix, pe->pe_number, &vaf);
87
88 va_end(args);
89}
184cd4a3 90
4e287840
TLSC		 91static bool pnv_iommu_bypass_disabled __read_mostly;
92
93static int __init iommu_setup(char *str)
94{
95 if (!str)
96 return -EINVAL;
97
98 while (*str) {
99 if (!strncmp(str, "nobypass", 8)) {
100 pnv_iommu_bypass_disabled = true;
101 pr_info("PowerNV: IOMMU bypass window disabled.\n");
102 break;
103 }
104 str += strcspn(str, ",");
105 if (*str == ',')
106 str++;
107 }
108
109 return 0;
110}
111early_param("iommu", iommu_setup);
112
5958d19a 113static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
262af557 114{
5958d19a
BH		 115 /*
116 * WARNING: We cannot rely on the resource flags. The Linux PCI
117 * allocation code sometimes decides to put a 64-bit prefetchable
118 * BAR in the 32-bit window, so we have to compare the addresses.
119 *
120 * For simplicity we only test resource start.
121 */
122 return (r->start >= phb->ioda.m64_base &&
123 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
262af557
GC		 124}
125
b79331a5
RC		 126static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
127{
128 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
129
130 return (resource_flags & flags) == flags;
131}
132
1e916772
GS		 133static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
134{
313483dd
GS		 135 s64 rc;
136
1e916772
GS		 137 phb->ioda.pe_array[pe_no].phb = phb;
138 phb->ioda.pe_array[pe_no].pe_number = pe_no;
139
313483dd
GS		 140 /*
141 * Clear the PE frozen state as it might be put into frozen state
142 * in the last PCI remove path. It's not harmful to do so when the
143 * PE is already in unfrozen state.
144 */
145 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
146 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
d4791db5 147 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
1f52f176 148 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
313483dd
GS		 149 __func__, rc, phb->hose->global_number, pe_no);
150
1e916772
GS		 151 return &phb->ioda.pe_array[pe_no];
152}
153
4b82ab18
GS		 154static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
155{
92b8f137 156 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
1f52f176 157 pr_warn("%s: Invalid PE %x on PHB#%x\n",
4b82ab18
GS		 158 __func__, pe_no, phb->hose->global_number);
159 return;
160 }
161
e9dc4d7f 162 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
1f52f176 163 pr_debug("%s: PE %x was reserved on PHB#%x\n",
e9dc4d7f 164 __func__, pe_no, phb->hose->global_number);
4b82ab18 165
1e916772 166 pnv_ioda_init_pe(phb, pe_no);
4b82ab18
GS		 167}
168
1e916772 169static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
184cd4a3 170{
60964816 171 long pe;
184cd4a3 172
9fcd6f4a
GS		 173 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
174 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
175 return pnv_ioda_init_pe(phb, pe);
176 }
184cd4a3 177
9fcd6f4a 178 return NULL;
184cd4a3
BH		 179}
180
1e916772 181static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
184cd4a3 182{
1e916772 183 struct pnv_phb *phb = pe->phb;
caa58f80 184 unsigned int pe_num = pe->pe_number;
1e916772
GS		 185
186 WARN_ON(pe->pdev);
184cd4a3 187
1e916772 188 memset(pe, 0, sizeof(struct pnv_ioda_pe));
caa58f80 189 clear_bit(pe_num, phb->ioda.pe_alloc);
184cd4a3
BH		 190}
191
262af557
GC		 192/* The default M64 BAR is shared by all PEs */
193static int pnv_ioda2_init_m64(struct pnv_phb *phb)
194{
195 const char *desc;
196 struct resource *r;
197 s64 rc;
198
199 /* Configure the default M64 BAR */
200 rc = opal_pci_set_phb_mem_window(phb->opal_id,
201 OPAL_M64_WINDOW_TYPE,
202 phb->ioda.m64_bar_idx,
203 phb->ioda.m64_base,
204 0, /* unused */
205 phb->ioda.m64_size);
206 if (rc != OPAL_SUCCESS) {
207 desc = "configuring";
208 goto fail;
209 }
210
211 /* Enable the default M64 BAR */
212 rc = opal_pci_phb_mmio_enable(phb->opal_id,
213 OPAL_M64_WINDOW_TYPE,
214 phb->ioda.m64_bar_idx,
215 OPAL_ENABLE_M64_SPLIT);
216 if (rc != OPAL_SUCCESS) {
217 desc = "enabling";
218 goto fail;
219 }
220
262af557 221 /*
63803c39
GS		 222 * Exclude the segments for reserved and root bus PE, which
223 * are first or last two PEs.
262af557
GC		 224 */
225 r = &phb->hose->mem_resources[1];
92b8f137 226 if (phb->ioda.reserved_pe_idx == 0)
63803c39 227 r->start += (2 * phb->ioda.m64_segsize);
92b8f137 228 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
63803c39 229 r->end -= (2 * phb->ioda.m64_segsize);
262af557 230 else
1f52f176 231 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
92b8f137 232 phb->ioda.reserved_pe_idx);
262af557
GC		 233
234 return 0;
235
236fail:
237 pr_warn(" Failure %lld %s M64 BAR#%d\n",
238 rc, desc, phb->ioda.m64_bar_idx);
239 opal_pci_phb_mmio_enable(phb->opal_id,
240 OPAL_M64_WINDOW_TYPE,
241 phb->ioda.m64_bar_idx,
242 OPAL_DISABLE_M64);
243 return -EIO;
244}
245
c430670a 246static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
96a2f92b 247 unsigned long *pe_bitmap)
262af557 248{
96a2f92b
GS		 249 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
250 struct pnv_phb *phb = hose->private_data;
262af557 251 struct resource *r;
96a2f92b
GS		 252 resource_size_t base, sgsz, start, end;
253 int segno, i;
254
255 base = phb->ioda.m64_base;
256 sgsz = phb->ioda.m64_segsize;
257 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
258 r = &pdev->resource[i];
5958d19a 259 if (!r->parent || !pnv_pci_is_m64(phb, r))
96a2f92b 260 continue;
262af557 261
96a2f92b
GS		 262 start = _ALIGN_DOWN(r->start - base, sgsz);
263 end = _ALIGN_UP(r->end - base, sgsz);
264 for (segno = start / sgsz; segno < end / sgsz; segno++) {
265 if (pe_bitmap)
266 set_bit(segno, pe_bitmap);
267 else
268 pnv_ioda_reserve_pe(phb, segno);
262af557
GC		 269 }
270 }
271}
272
99451551
GS		 273static int pnv_ioda1_init_m64(struct pnv_phb *phb)
274{
275 struct resource *r;
276 int index;
277
278 /*
279 * There are 16 M64 BARs, each of which has 8 segments. So
280 * there are as many M64 segments as the maximum number of
281 * PEs, which is 128.
282 */
283 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
284 unsigned long base, segsz = phb->ioda.m64_segsize;
285 int64_t rc;
286
287 base = phb->ioda.m64_base +
288 index * PNV_IODA1_M64_SEGS * segsz;
289 rc = opal_pci_set_phb_mem_window(phb->opal_id,
290 OPAL_M64_WINDOW_TYPE, index, base, 0,
291 PNV_IODA1_M64_SEGS * segsz);
292 if (rc != OPAL_SUCCESS) {
1f52f176 293 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
99451551
GS		 294 rc, phb->hose->global_number, index);
295 goto fail;
296 }
297
298 rc = opal_pci_phb_mmio_enable(phb->opal_id,
299 OPAL_M64_WINDOW_TYPE, index,
300 OPAL_ENABLE_M64_SPLIT);
301 if (rc != OPAL_SUCCESS) {
1f52f176 302 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
99451551
GS		 303 rc, phb->hose->global_number, index);
304 goto fail;
305 }
306 }
307
308 /*
63803c39
GS		 309 * Exclude the segments for reserved and root bus PE, which
310 * are first or last two PEs.
99451551
GS		 311 */
312 r = &phb->hose->mem_resources[1];
313 if (phb->ioda.reserved_pe_idx == 0)
63803c39 314 r->start += (2 * phb->ioda.m64_segsize);
99451551 315 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
63803c39 316 r->end -= (2 * phb->ioda.m64_segsize);
99451551 317 else
1f52f176 318 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
99451551
GS		 319 phb->ioda.reserved_pe_idx, phb->hose->global_number);
320
321 return 0;
322
323fail:
324 for ( ; index >= 0; index--)
325 opal_pci_phb_mmio_enable(phb->opal_id,
326 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
327
328 return -EIO;
329}
330
c430670a
GS		 331static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
332 unsigned long *pe_bitmap,
333 bool all)
262af557 334{
262af557 335 struct pci_dev *pdev;
96a2f92b
GS		 336
337 list_for_each_entry(pdev, &bus->devices, bus_list) {
c430670a 338 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
96a2f92b
GS		 339
340 if (all && pdev->subordinate)
c430670a
GS		 341 pnv_ioda_reserve_m64_pe(pdev->subordinate,
342 pe_bitmap, all);
96a2f92b
GS		 343 }
344}
345
1e916772 346static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
262af557 347{
26ba248d
GS		 348 struct pci_controller *hose = pci_bus_to_host(bus);
349 struct pnv_phb *phb = hose->private_data;
262af557
GC		 350 struct pnv_ioda_pe *master_pe, *pe;
351 unsigned long size, *pe_alloc;
26ba248d 352 int i;
262af557
GC		 353
354 /* Root bus shouldn't use M64 */
355 if (pci_is_root_bus(bus))
1e916772 356 return NULL;
262af557 357
262af557 358 /* Allocate bitmap */
92b8f137 359 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
262af557
GC		 360 pe_alloc = kzalloc(size, GFP_KERNEL);
361 if (!pe_alloc) {
362 pr_warn("%s: Out of memory !\n",
363 __func__);
1e916772 364 return NULL;
262af557
GC		 365 }
366
26ba248d 367 /* Figure out reserved PE numbers by the PE */
c430670a 368 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
262af557
GC		 369
370 /*
371 * the current bus might not own M64 window and that's all
372 * contributed by its child buses. For the case, we needn't
373 * pick M64 dependent PE#.
374 */
92b8f137 375 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
262af557 376 kfree(pe_alloc);
1e916772 377 return NULL;
262af557
GC		 378 }
379
380 /*
381 * Figure out the master PE and put all slave PEs to master
382 * PE's list to form compound PE.
383 */
262af557
GC		 384 master_pe = NULL;
385 i = -1;
92b8f137
GS		 386 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
387 phb->ioda.total_pe_num) {
262af557 388 pe = &phb->ioda.pe_array[i];
262af557 389
93289d8c 390 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
262af557
GC		 391 if (!master_pe) {
392 pe->flags |= PNV_IODA_PE_MASTER;
393 INIT_LIST_HEAD(&pe->slaves);
394 master_pe = pe;
395 } else {
396 pe->flags |= PNV_IODA_PE_SLAVE;
397 pe->master = master_pe;
398 list_add_tail(&pe->list, &master_pe->slaves);
399 }
99451551
GS		 400
401 /*
402 * P7IOC supports M64DT, which helps mapping M64 segment
403 * to one particular PE#. However, PHB3 has fixed mapping
404 * between M64 segment and PE#. In order to have same logic
405 * for P7IOC and PHB3, we enforce fixed mapping between M64
406 * segment and PE# on P7IOC.
407 */
408 if (phb->type == PNV_PHB_IODA1) {
409 int64_t rc;
410
411 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
412 pe->pe_number, OPAL_M64_WINDOW_TYPE,
413 pe->pe_number / PNV_IODA1_M64_SEGS,
414 pe->pe_number % PNV_IODA1_M64_SEGS);
415 if (rc != OPAL_SUCCESS)
1f52f176 416 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
99451551
GS		 417 __func__, rc, phb->hose->global_number,
418 pe->pe_number);
419 }
262af557
GC		 420 }
421
422 kfree(pe_alloc);
1e916772 423 return master_pe;
262af557
GC		 424}
425
426static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
427{
428 struct pci_controller *hose = phb->hose;
429 struct device_node *dn = hose->dn;
430 struct resource *res;
a1339faf 431 u32 m64_range[2], i;
0e7736c6 432 const __be32 *r;
262af557
GC		 433 u64 pci_addr;
434
99451551 435 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
1665c4a8
GS		 436 pr_info(" Not support M64 window\n");
437 return;
438 }
439
e4d54f71 440 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
262af557
GC		 441 pr_info(" Firmware too old to support M64 window\n");
442 return;
443 }
444
445 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
446 if (!r) {
447 pr_info(" No <ibm,opal-m64-window> on %s\n",
448 dn->full_name);
449 return;
450 }
451
a1339faf
BH		 452 /*
453 * Find the available M64 BAR range and pickup the last one for
454 * covering the whole 64-bits space. We support only one range.
455 */
456 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
457 m64_range, 2)) {
458 /* In absence of the property, assume 0..15 */
459 m64_range[0] = 0;
460 m64_range[1] = 16;
461 }
462 /* We only support 64 bits in our allocator */
463 if (m64_range[1] > 63) {
464 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
465 __func__, m64_range[1], phb->hose->global_number);
466 m64_range[1] = 63;
467 }
468 /* Empty range, no m64 */
469 if (m64_range[1] <= m64_range[0]) {
470 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
471 __func__, phb->hose->global_number);
472 return;
473 }
474
475 /* Configure M64 informations */
262af557 476 res = &hose->mem_resources[1];
e80c4e7c 477 res->name = dn->full_name;
262af557
GC		 478 res->start = of_translate_address(dn, r + 2);
479 res->end = res->start + of_read_number(r + 4, 2) - 1;
480 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
481 pci_addr = of_read_number(r, 2);
482 hose->mem_offset[1] = res->start - pci_addr;
483
484 phb->ioda.m64_size = resource_size(res);
92b8f137 485 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
262af557
GC		 486 phb->ioda.m64_base = pci_addr;
487
a1339faf
BH		 488 /* This lines up nicely with the display from processing OF ranges */
489 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
490 res->start, res->end, pci_addr, m64_range[0],
491 m64_range[0] + m64_range[1] - 1);
492
493 /* Mark all M64 used up by default */
494 phb->ioda.m64_bar_alloc = (unsigned long)-1;
e9863e68 495
262af557 496 /* Use last M64 BAR to cover M64 window */
a1339faf
BH		 497 m64_range[1]--;
498 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
499
500 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
501
502 /* Mark remaining ones free */
503 for (i = m64_range[0]; i < m64_range[1]; i++)
504 clear_bit(i, &phb->ioda.m64_bar_alloc);
505
506 /*
507 * Setup init functions for M64 based on IODA version, IODA3 uses
508 * the IODA2 code.
509 */
99451551
GS		 510 if (phb->type == PNV_PHB_IODA1)
511 phb->init_m64 = pnv_ioda1_init_m64;
512 else
513 phb->init_m64 = pnv_ioda2_init_m64;
c430670a
GS		 514 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
515 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
262af557
GC		 516}
517
49dec922
GS		 518static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
519{
520 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
521 struct pnv_ioda_pe *slave;
522 s64 rc;
523
524 /* Fetch master PE */
525 if (pe->flags & PNV_IODA_PE_SLAVE) {
526 pe = pe->master;
ec8e4e9d
GS		 527 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
528 return;
529
49dec922
GS		 530 pe_no = pe->pe_number;
531 }
532
533 /* Freeze master PE */
534 rc = opal_pci_eeh_freeze_set(phb->opal_id,
535 pe_no,
536 OPAL_EEH_ACTION_SET_FREEZE_ALL);
537 if (rc != OPAL_SUCCESS) {
538 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
539 __func__, rc, phb->hose->global_number, pe_no);
540 return;
541 }
542
543 /* Freeze slave PEs */
544 if (!(pe->flags & PNV_IODA_PE_MASTER))
545 return;
546
547 list_for_each_entry(slave, &pe->slaves, list) {
548 rc = opal_pci_eeh_freeze_set(phb->opal_id,
549 slave->pe_number,
550 OPAL_EEH_ACTION_SET_FREEZE_ALL);
551 if (rc != OPAL_SUCCESS)
552 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
553 __func__, rc, phb->hose->global_number,
554 slave->pe_number);
555 }
556}
557
e51df2c1 558static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
49dec922
GS		 559{
560 struct pnv_ioda_pe *pe, *slave;
561 s64 rc;
562
563 /* Find master PE */
564 pe = &phb->ioda.pe_array[pe_no];
565 if (pe->flags & PNV_IODA_PE_SLAVE) {
566 pe = pe->master;
567 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
568 pe_no = pe->pe_number;
569 }
570
571 /* Clear frozen state for master PE */
572 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
573 if (rc != OPAL_SUCCESS) {
574 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
575 __func__, rc, opt, phb->hose->global_number, pe_no);
576 return -EIO;
577 }
578
579 if (!(pe->flags & PNV_IODA_PE_MASTER))
580 return 0;
581
582 /* Clear frozen state for slave PEs */
583 list_for_each_entry(slave, &pe->slaves, list) {
584 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
585 slave->pe_number,
586 opt);
587 if (rc != OPAL_SUCCESS) {
588 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
589 __func__, rc, opt, phb->hose->global_number,
590 slave->pe_number);
591 return -EIO;
592 }
593 }
594
595 return 0;
596}
597
598static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
599{
600 struct pnv_ioda_pe *slave, *pe;
601 u8 fstate, state;
602 __be16 pcierr;
603 s64 rc;
604
605 /* Sanity check on PE number */
92b8f137 606 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
49dec922
GS		 607 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
608
609 /*
610 * Fetch the master PE and the PE instance might be
611 * not initialized yet.
612 */
613 pe = &phb->ioda.pe_array[pe_no];
614 if (pe->flags & PNV_IODA_PE_SLAVE) {
615 pe = pe->master;
616 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
617 pe_no = pe->pe_number;
618 }
619
620 /* Check the master PE */
621 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
622 &state, &pcierr, NULL);
623 if (rc != OPAL_SUCCESS) {
624 pr_warn("%s: Failure %lld getting "
625 "PHB#%x-PE#%x state\n",
626 __func__, rc,
627 phb->hose->global_number, pe_no);
628 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
629 }
630
631 /* Check the slave PE */
632 if (!(pe->flags & PNV_IODA_PE_MASTER))
633 return state;
634
635 list_for_each_entry(slave, &pe->slaves, list) {
636 rc = opal_pci_eeh_freeze_status(phb->opal_id,
637 slave->pe_number,
638 &fstate,
639 &pcierr,
640 NULL);
641 if (rc != OPAL_SUCCESS) {
642 pr_warn("%s: Failure %lld getting "
643 "PHB#%x-PE#%x state\n",
644 __func__, rc,
645 phb->hose->global_number, slave->pe_number);
646 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
647 }
648
649 /*
650 * Override the result based on the ascending
651 * priority.
652 */
653 if (fstate > state)
654 state = fstate;
655 }
656
657 return state;
658}
659
184cd4a3
BH		 660/* Currently those 2 are only used when MSIs are enabled, this will change
661 * but in the meantime, we need to protect them to avoid warnings
662 */
663#ifdef CONFIG_PCI_MSI
f456834a 664struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
184cd4a3
BH		 665{
666 struct pci_controller *hose = pci_bus_to_host(dev->bus);
667 struct pnv_phb *phb = hose->private_data;
b72c1f65 668 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 669
670 if (!pdn)
671 return NULL;
672 if (pdn->pe_number == IODA_INVALID_PE)
673 return NULL;
674 return &phb->ioda.pe_array[pdn->pe_number];
675}
184cd4a3
BH		 676#endif /* CONFIG_PCI_MSI */
677
b131a842
GS		 678static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
679 struct pnv_ioda_pe *parent,
680 struct pnv_ioda_pe *child,
681 bool is_add)
682{
683 const char *desc = is_add ? "adding" : "removing";
684 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
685 OPAL_REMOVE_PE_FROM_DOMAIN;
686 struct pnv_ioda_pe *slave;
687 long rc;
688
689 /* Parent PE affects child PE */
690 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
691 child->pe_number, op);
692 if (rc != OPAL_SUCCESS) {
693 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
694 rc, desc);
695 return -ENXIO;
696 }
697
698 if (!(child->flags & PNV_IODA_PE_MASTER))
699 return 0;
700
701 /* Compound case: parent PE affects slave PEs */
702 list_for_each_entry(slave, &child->slaves, list) {
703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704 slave->pe_number, op);
705 if (rc != OPAL_SUCCESS) {
706 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
707 rc, desc);
708 return -ENXIO;
709 }
710 }
711
712 return 0;
713}
714
715static int pnv_ioda_set_peltv(struct pnv_phb *phb,
716 struct pnv_ioda_pe *pe,
717 bool is_add)
718{
719 struct pnv_ioda_pe *slave;
781a868f 720 struct pci_dev *pdev = NULL;
b131a842
GS		 721 int ret;
722
723 /*
724 * Clear PE frozen state. If it's master PE, we need
725 * clear slave PE frozen state as well.
726 */
727 if (is_add) {
728 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
730 if (pe->flags & PNV_IODA_PE_MASTER) {
731 list_for_each_entry(slave, &pe->slaves, list)
732 opal_pci_eeh_freeze_clear(phb->opal_id,
733 slave->pe_number,
734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
735 }
736 }
737
738 /*
739 * Associate PE in PELT. We need add the PE into the
740 * corresponding PELT-V as well. Otherwise, the error
741 * originated from the PE might contribute to other
742 * PEs.
743 */
744 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
745 if (ret)
746 return ret;
747
748 /* For compound PEs, any one affects all of them */
749 if (pe->flags & PNV_IODA_PE_MASTER) {
750 list_for_each_entry(slave, &pe->slaves, list) {
751 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
752 if (ret)
753 return ret;
754 }
755 }
756
757 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
758 pdev = pe->pbus->self;
781a868f 759 else if (pe->flags & PNV_IODA_PE_DEV)
b131a842 760 pdev = pe->pdev->bus->self;
781a868f
WY		 761#ifdef CONFIG_PCI_IOV
762 else if (pe->flags & PNV_IODA_PE_VF)
283e2d8a 763 pdev = pe->parent_dev;
781a868f 764#endif /* CONFIG_PCI_IOV */
b131a842
GS		 765 while (pdev) {
766 struct pci_dn *pdn = pci_get_pdn(pdev);
767 struct pnv_ioda_pe *parent;
768
769 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770 parent = &phb->ioda.pe_array[pdn->pe_number];
771 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
772 if (ret)
773 return ret;
774 }
775
776 pdev = pdev->bus->self;
777 }
778
779 return 0;
780}
781
781a868f
WY		 782static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
783{
784 struct pci_dev *parent;
785 uint8_t bcomp, dcomp, fcomp;
786 int64_t rc;
787 long rid_end, rid;
788
789 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
790 if (pe->pbus) {
791 int count;
792
793 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
794 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
795 parent = pe->pbus->self;
796 if (pe->flags & PNV_IODA_PE_BUS_ALL)
797 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
798 else
799 count = 1;
800
801 switch(count) {
802 case 1: bcomp = OpalPciBusAll; break;
803 case 2: bcomp = OpalPciBus7Bits; break;
804 case 4: bcomp = OpalPciBus6Bits; break;
805 case 8: bcomp = OpalPciBus5Bits; break;
806 case 16: bcomp = OpalPciBus4Bits; break;
807 case 32: bcomp = OpalPciBus3Bits; break;
808 default:
809 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
810 count);
811 /* Do an exact match only */
812 bcomp = OpalPciBusAll;
813 }
814 rid_end = pe->rid + (count << 8);
815 } else {
93e01a50 816#ifdef CONFIG_PCI_IOV
781a868f
WY		 817 if (pe->flags & PNV_IODA_PE_VF)
818 parent = pe->parent_dev;
819 else
93e01a50 820#endif
781a868f
WY		 821 parent = pe->pdev->bus->self;
822 bcomp = OpalPciBusAll;
823 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
824 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
825 rid_end = pe->rid + 1;
826 }
827
828 /* Clear the reverse map */
829 for (rid = pe->rid; rid < rid_end; rid++)
c127562a 830 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
781a868f
WY		 831
832 /* Release from all parents PELT-V */
833 while (parent) {
834 struct pci_dn *pdn = pci_get_pdn(parent);
835 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
836 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
837 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
838 /* XXX What to do in case of error ? */
839 }
840 parent = parent->bus->self;
841 }
842
f951e510 843 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
781a868f
WY		 844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
845
846 /* Disassociate PE in PELT */
847 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
849 if (rc)
850 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
853 if (rc)
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
855
856 pe->pbus = NULL;
857 pe->pdev = NULL;
93e01a50 858#ifdef CONFIG_PCI_IOV
781a868f 859 pe->parent_dev = NULL;
93e01a50 860#endif
781a868f
WY		 861
862 return 0;
863}
781a868f 864
cad5cef6 865static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
184cd4a3
BH		 866{
867 struct pci_dev *parent;
868 uint8_t bcomp, dcomp, fcomp;
869 long rc, rid_end, rid;
870
871 /* Bus validation ? */
872 if (pe->pbus) {
873 int count;
874
875 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
876 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
877 parent = pe->pbus->self;
fb446ad0
GS		 878 if (pe->flags & PNV_IODA_PE_BUS_ALL)
879 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
880 else
881 count = 1;
882
184cd4a3
BH		 883 switch(count) {
884 case 1: bcomp = OpalPciBusAll; break;
885 case 2: bcomp = OpalPciBus7Bits; break;
886 case 4: bcomp = OpalPciBus6Bits; break;
887 case 8: bcomp = OpalPciBus5Bits; break;
888 case 16: bcomp = OpalPciBus4Bits; break;
889 case 32: bcomp = OpalPciBus3Bits; break;
890 default:
781a868f
WY		 891 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
892 count);
184cd4a3
BH		 893 /* Do an exact match only */
894 bcomp = OpalPciBusAll;
895 }
896 rid_end = pe->rid + (count << 8);
897 } else {
781a868f
WY		 898#ifdef CONFIG_PCI_IOV
899 if (pe->flags & PNV_IODA_PE_VF)
900 parent = pe->parent_dev;
901 else
902#endif /* CONFIG_PCI_IOV */
903 parent = pe->pdev->bus->self;
184cd4a3
BH		 904 bcomp = OpalPciBusAll;
905 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
906 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
907 rid_end = pe->rid + 1;
908 }
909
631ad691
GS		 910 /*
911 * Associate PE in PELT. We need add the PE into the
912 * corresponding PELT-V as well. Otherwise, the error
913 * originated from the PE might contribute to other
914 * PEs.
915 */
184cd4a3
BH		 916 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
917 bcomp, dcomp, fcomp, OPAL_MAP_PE);
918 if (rc) {
919 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
920 return -ENXIO;
921 }
631ad691 922
5d2aa710
AP		 923 /*
924 * Configure PELTV. NPUs don't have a PELTV table so skip
925 * configuration on them.
926 */
927 if (phb->type != PNV_PHB_NPU)
928 pnv_ioda_set_peltv(phb, pe, true);
184cd4a3 929
184cd4a3
BH		 930 /* Setup reverse map */
931 for (rid = pe->rid; rid < rid_end; rid++)
932 phb->ioda.pe_rmap[rid] = pe->pe_number;
933
934 /* Setup one MVTs on IODA1 */
4773f76b
GS		 935 if (phb->type != PNV_PHB_IODA1) {
936 pe->mve_number = 0;
937 goto out;
938 }
939
940 pe->mve_number = pe->pe_number;
941 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
942 if (rc != OPAL_SUCCESS) {
1f52f176 943 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
4773f76b
GS		 944 rc, pe->mve_number);
945 pe->mve_number = -1;
946 } else {
947 rc = opal_pci_set_mve_enable(phb->opal_id,
948 pe->mve_number, OPAL_ENABLE_MVE);
184cd4a3 949 if (rc) {
1f52f176 950 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
184cd4a3
BH		 951 rc, pe->mve_number);
952 pe->mve_number = -1;
184cd4a3 953 }
4773f76b 954 }
184cd4a3 955
4773f76b 956out:
184cd4a3
BH		 957 return 0;
958}
959
781a868f
WY		 960#ifdef CONFIG_PCI_IOV
961static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
962{
963 struct pci_dn *pdn = pci_get_pdn(dev);
964 int i;
965 struct resource *res, res2;
966 resource_size_t size;
967 u16 num_vfs;
968
969 if (!dev->is_physfn)
970 return -EINVAL;
971
972 /*
973 * "offset" is in VFs. The M64 windows are sized so that when they
974 * are segmented, each segment is the same size as the IOV BAR.
975 * Each segment is in a separate PE, and the high order bits of the
976 * address are the PE number. Therefore, each VF's BAR is in a
977 * separate PE, and changing the IOV BAR start address changes the
978 * range of PEs the VFs are in.
979 */
980 num_vfs = pdn->num_vfs;
981 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
982 res = &dev->resource[i + PCI_IOV_RESOURCES];
983 if (!res->flags || !res->parent)
984 continue;
985
781a868f
WY		 986 /*
987 * The actual IOV BAR range is determined by the start address
988 * and the actual size for num_vfs VFs BAR. This check is to
989 * make sure that after shifting, the range will not overlap
990 * with another device.
991 */
992 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
993 res2.flags = res->flags;
994 res2.start = res->start + (size * offset);
995 res2.end = res2.start + (size * num_vfs) - 1;
996
997 if (res2.end > res->end) {
998 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999 i, &res2, res, num_vfs, offset);
1000 return -EBUSY;
1001 }
1002 }
1003
1004 /*
1005 * After doing so, there would be a "hole" in the /proc/iomem when
1006 * offset is a positive value. It looks like the device return some
1007 * mmio back to the system, which actually no one could use it.
1008 */
1009 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1010 res = &dev->resource[i + PCI_IOV_RESOURCES];
1011 if (!res->flags || !res->parent)
1012 continue;
1013
781a868f
WY		 1014 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1015 res2 = *res;
1016 res->start += size * offset;
1017
74703cc4
WY		 1018 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1019 i, &res2, res, (offset > 0) ? "En" : "Dis",
1020 num_vfs, offset);
781a868f
WY		 1021 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1022 }
1023 return 0;
1024}
1025#endif /* CONFIG_PCI_IOV */
1026
cad5cef6 1027static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
184cd4a3
BH		 1028{
1029 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1030 struct pnv_phb *phb = hose->private_data;
b72c1f65 1031 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3 1032 struct pnv_ioda_pe *pe;
184cd4a3
BH		 1033
1034 if (!pdn) {
1035 pr_err("%s: Device tree node not associated properly\n",
1036 pci_name(dev));
1037 return NULL;
1038 }
1039 if (pdn->pe_number != IODA_INVALID_PE)
1040 return NULL;
1041
1e916772
GS		 1042 pe = pnv_ioda_alloc_pe(phb);
1043 if (!pe) {
184cd4a3
BH		 1044 pr_warning("%s: Not enough PE# available, disabling device\n",
1045 pci_name(dev));
1046 return NULL;
1047 }
1048
1049 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1050 * pointer in the PE data structure, both should be destroyed at the
1051 * same time. However, this needs to be looked at more closely again
1052 * once we actually start removing things (Hotplug, SR-IOV, ...)
1053 *
1054 * At some point we want to remove the PDN completely anyways
1055 */
184cd4a3
BH		 1056 pci_dev_get(dev);
1057 pdn->pcidev = dev;
1e916772 1058 pdn->pe_number = pe->pe_number;
5d2aa710 1059 pe->flags = PNV_IODA_PE_DEV;
184cd4a3
BH		 1060 pe->pdev = dev;
1061 pe->pbus = NULL;
184cd4a3
BH		 1062 pe->mve_number = -1;
1063 pe->rid = dev->bus->number << 8 | pdn->devfn;
1064
1065 pe_info(pe, "Associated device to PE\n");
1066
1067 if (pnv_ioda_configure_pe(phb, pe)) {
1068 /* XXX What do we do here ? */
1e916772 1069 pnv_ioda_free_pe(pe);
184cd4a3
BH		 1070 pdn->pe_number = IODA_INVALID_PE;
1071 pe->pdev = NULL;
1072 pci_dev_put(dev);
1073 return NULL;
1074 }
1075
1d4e89cf
AK		 1076 /* Put PE to the list */
1077 list_add_tail(&pe->list, &phb->ioda.pe_list);
1078
184cd4a3
BH		 1079 return pe;
1080}
1081
1082static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1083{
1084 struct pci_dev *dev;
1085
1086 list_for_each_entry(dev, &bus->devices, bus_list) {
b72c1f65 1087 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 1088
1089 if (pdn == NULL) {
1090 pr_warn("%s: No device node associated with device !\n",
1091 pci_name(dev));
1092 continue;
1093 }
ccd1c191
GS		 1094
1095 /*
1096 * In partial hotplug case, the PCI device might be still
1097 * associated with the PE and needn't attach it to the PE
1098 * again.
1099 */
1100 if (pdn->pe_number != IODA_INVALID_PE)
1101 continue;
1102
c5f7700b 1103 pe->device_count++;
94973b24 1104 pdn->pcidev = dev;
184cd4a3 1105 pdn->pe_number = pe->pe_number;
fb446ad0 1106 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
184cd4a3
BH		 1107 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1108 }
1109}
1110
fb446ad0
GS		 1111/*
1112 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1113 * single PCI bus. Another one that contains the primary PCI bus and its
1114 * subordinate PCI devices and buses. The second type of PE is normally
1115 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1116 */
1e916772 1117static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
184cd4a3 1118{
fb446ad0 1119 struct pci_controller *hose = pci_bus_to_host(bus);
184cd4a3 1120 struct pnv_phb *phb = hose->private_data;
1e916772 1121 struct pnv_ioda_pe *pe = NULL;
ccd1c191
GS		 1122 unsigned int pe_num;
1123
1124 /*
1125 * In partial hotplug case, the PE instance might be still alive.
1126 * We should reuse it instead of allocating a new one.
1127 */
1128 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1129 if (pe_num != IODA_INVALID_PE) {
1130 pe = &phb->ioda.pe_array[pe_num];
1131 pnv_ioda_setup_same_PE(bus, pe);
1132 return NULL;
1133 }
262af557 1134
63803c39
GS		 1135 /* PE number for root bus should have been reserved */
1136 if (pci_is_root_bus(bus) &&
1137 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1138 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1139
262af557 1140 /* Check if PE is determined by M64 */
63803c39 1141 if (!pe && phb->pick_m64_pe)
1e916772 1142 pe = phb->pick_m64_pe(bus, all);
262af557
GC		 1143
1144 /* The PE number isn't pinned by M64 */
1e916772
GS		 1145 if (!pe)
1146 pe = pnv_ioda_alloc_pe(phb);
184cd4a3 1147
1e916772 1148 if (!pe) {
fb446ad0
GS		 1149 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1150 __func__, pci_domain_nr(bus), bus->number);
1e916772 1151 return NULL;
184cd4a3
BH		 1152 }
1153
262af557 1154 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
184cd4a3
BH		 1155 pe->pbus = bus;
1156 pe->pdev = NULL;
184cd4a3 1157 pe->mve_number = -1;
b918c62e 1158 pe->rid = bus->busn_res.start << 8;
184cd4a3 1159
fb446ad0 1160 if (all)
1f52f176 1161 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1e916772 1162 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
fb446ad0 1163 else
1f52f176 1164 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1e916772 1165 bus->busn_res.start, pe->pe_number);
184cd4a3
BH		 1166
1167 if (pnv_ioda_configure_pe(phb, pe)) {
1168 /* XXX What do we do here ? */
1e916772 1169 pnv_ioda_free_pe(pe);
184cd4a3 1170 pe->pbus = NULL;
1e916772 1171 return NULL;
184cd4a3
BH		 1172 }
1173
1174 /* Associate it with all child devices */
1175 pnv_ioda_setup_same_PE(bus, pe);
1176
7ebdf956
GS		 1177 /* Put PE to the list */
1178 list_add_tail(&pe->list, &phb->ioda.pe_list);
1e916772
GS		 1179
1180 return pe;
184cd4a3
BH		 1181}
1182
b521549a
AP		 1183static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1184{
1185 int pe_num, found_pe = false, rc;
1186 long rid;
1187 struct pnv_ioda_pe *pe;
1188 struct pci_dev *gpu_pdev;
1189 struct pci_dn *npu_pdn;
1190 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1191 struct pnv_phb *phb = hose->private_data;
1192
1193 /*
1194 * Due to a hardware errata PE#0 on the NPU is reserved for
1195 * error handling. This means we only have three PEs remaining
1196 * which need to be assigned to four links, implying some
1197 * links must share PEs.
1198 *
1199 * To achieve this we assign PEs such that NPUs linking the
1200 * same GPU get assigned the same PE.
1201 */
1202 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
92b8f137 1203 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
b521549a
AP		 1204 pe = &phb->ioda.pe_array[pe_num];
1205 if (!pe->pdev)
1206 continue;
1207
1208 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1209 /*
1210 * This device has the same peer GPU so should
1211 * be assigned the same PE as the existing
1212 * peer NPU.
1213 */
1214 dev_info(&npu_pdev->dev,
1f52f176 1215 "Associating to existing PE %x\n", pe_num);
b521549a
AP		 1216 pci_dev_get(npu_pdev);
1217 npu_pdn = pci_get_pdn(npu_pdev);
1218 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1219 npu_pdn->pcidev = npu_pdev;
1220 npu_pdn->pe_number = pe_num;
b521549a
AP		 1221 phb->ioda.pe_rmap[rid] = pe->pe_number;
1222
1223 /* Map the PE to this link */
1224 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1225 OpalPciBusAll,
1226 OPAL_COMPARE_RID_DEVICE_NUMBER,
1227 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1228 OPAL_MAP_PE);
1229 WARN_ON(rc != OPAL_SUCCESS);
1230 found_pe = true;
1231 break;
1232 }
1233 }
1234
1235 if (!found_pe)
1236 /*
1237 * Could not find an existing PE so allocate a new
1238 * one.
1239 */
1240 return pnv_ioda_setup_dev_PE(npu_pdev);
1241 else
1242 return pe;
1243}
1244
1245static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
5d2aa710 1246{
5d2aa710
AP		 1247 struct pci_dev *pdev;
1248
1249 list_for_each_entry(pdev, &bus->devices, bus_list)
b521549a 1250 pnv_ioda_setup_npu_PE(pdev);
5d2aa710
AP		 1251}
1252
cad5cef6 1253static void pnv_pci_ioda_setup_PEs(void)
fb446ad0
GS		 1254{
1255 struct pci_controller *hose, *tmp;
262af557 1256 struct pnv_phb *phb;
fb446ad0
GS		 1257
1258 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
262af557 1259 phb = hose->private_data;
08f48f32
AP		 1260 if (phb->type == PNV_PHB_NPU) {
1261 /* PE#0 is needed for error reporting */
1262 pnv_ioda_reserve_pe(phb, 0);
b521549a 1263 pnv_ioda_setup_npu_PEs(hose->bus);
1ab66d1f
AP		 1264 if (phb->model == PNV_PHB_MODEL_NPU2)
1265 pnv_npu2_init(phb);
ccd1c191 1266 }
184cd4a3
BH		 1267 }
1268}
1269
a8b2f828 1270#ifdef CONFIG_PCI_IOV
ee8222fe 1271static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1272{
1273 struct pci_bus *bus;
1274 struct pci_controller *hose;
1275 struct pnv_phb *phb;
1276 struct pci_dn *pdn;
02639b0e 1277 int i, j;
ee8222fe 1278 int m64_bars;
781a868f
WY		 1279
1280 bus = pdev->bus;
1281 hose = pci_bus_to_host(bus);
1282 phb = hose->private_data;
1283 pdn = pci_get_pdn(pdev);
1284
ee8222fe
WY		 1285 if (pdn->m64_single_mode)
1286 m64_bars = num_vfs;
1287 else
1288 m64_bars = 1;
1289
02639b0e 1290 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
ee8222fe
WY		 1291 for (j = 0; j < m64_bars; j++) {
1292 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
02639b0e
WY		 1293 continue;
1294 opal_pci_phb_mmio_enable(phb->opal_id,
ee8222fe
WY		 1295 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1296 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1297 pdn->m64_map[j][i] = IODA_INVALID_M64;
02639b0e 1298 }
781a868f 1299
ee8222fe 1300 kfree(pdn->m64_map);
781a868f
WY		 1301 return 0;
1302}
1303
02639b0e 1304static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1305{
1306 struct pci_bus *bus;
1307 struct pci_controller *hose;
1308 struct pnv_phb *phb;
1309 struct pci_dn *pdn;
1310 unsigned int win;
1311 struct resource *res;
02639b0e 1312 int i, j;
781a868f 1313 int64_t rc;
02639b0e
WY		 1314 int total_vfs;
1315 resource_size_t size, start;
1316 int pe_num;
ee8222fe 1317 int m64_bars;
781a868f
WY		 1318
1319 bus = pdev->bus;
1320 hose = pci_bus_to_host(bus);
1321 phb = hose->private_data;
1322 pdn = pci_get_pdn(pdev);
02639b0e 1323 total_vfs = pci_sriov_get_totalvfs(pdev);
781a868f 1324
ee8222fe
WY		 1325 if (pdn->m64_single_mode)
1326 m64_bars = num_vfs;
1327 else
1328 m64_bars = 1;
1329
fb37e128
ME		 1330 pdn->m64_map = kmalloc_array(m64_bars,
1331 sizeof(*pdn->m64_map),
1332 GFP_KERNEL);
ee8222fe
WY		 1333 if (!pdn->m64_map)
1334 return -ENOMEM;
1335 /* Initialize the m64_map to IODA_INVALID_M64 */
1336 for (i = 0; i < m64_bars ; i++)
1337 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1338 pdn->m64_map[i][j] = IODA_INVALID_M64;
02639b0e 1339
781a868f
WY		 1340
1341 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1342 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1343 if (!res->flags || !res->parent)
1344 continue;
1345
ee8222fe 1346 for (j = 0; j < m64_bars; j++) {
02639b0e
WY		 1347 do {
1348 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1349 phb->ioda.m64_bar_idx + 1, 0);
1350
1351 if (win >= phb->ioda.m64_bar_idx + 1)
1352 goto m64_failed;
1353 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1354
ee8222fe 1355 pdn->m64_map[j][i] = win;
02639b0e 1356
ee8222fe 1357 if (pdn->m64_single_mode) {
02639b0e
WY		 1358 size = pci_iov_resource_size(pdev,
1359 PCI_IOV_RESOURCES + i);
02639b0e
WY		 1360 start = res->start + size * j;
1361 } else {
1362 size = resource_size(res);
1363 start = res->start;
1364 }
1365
1366 /* Map the M64 here */
ee8222fe 1367 if (pdn->m64_single_mode) {
be283eeb 1368 pe_num = pdn->pe_num_map[j];
02639b0e
WY		 1369 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1370 pe_num, OPAL_M64_WINDOW_TYPE,
ee8222fe 1371 pdn->m64_map[j][i], 0);
02639b0e
WY		 1372 }
1373
1374 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1375 OPAL_M64_WINDOW_TYPE,
ee8222fe 1376 pdn->m64_map[j][i],
02639b0e
WY		 1377 start,
1378 0, /* unused */
1379 size);
781a868f 1380
781a868f 1381
02639b0e
WY		 1382 if (rc != OPAL_SUCCESS) {
1383 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1384 win, rc);
1385 goto m64_failed;
1386 }
781a868f 1387
ee8222fe 1388 if (pdn->m64_single_mode)
02639b0e 1389 rc = opal_pci_phb_mmio_enable(phb->opal_id,
ee8222fe 1390 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
02639b0e
WY		 1391 else
1392 rc = opal_pci_phb_mmio_enable(phb->opal_id,
ee8222fe 1393 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
781a868f 1394
02639b0e
WY		 1395 if (rc != OPAL_SUCCESS) {
1396 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1397 win, rc);
1398 goto m64_failed;
1399 }
781a868f
WY		 1400 }
1401 }
1402 return 0;
1403
1404m64_failed:
ee8222fe 1405 pnv_pci_vf_release_m64(pdev, num_vfs);
781a868f
WY		 1406 return -EBUSY;
1407}
1408
c035e37b
AK		 1409static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1410 int num);
1411static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1412
781a868f
WY		 1413static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1414{
781a868f 1415 struct iommu_table *tbl;
781a868f
WY		 1416 int64_t rc;
1417
b348aa65 1418 tbl = pe->table_group.tables[0];
c035e37b 1419 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
781a868f
WY		 1420 if (rc)
1421 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1422
c035e37b 1423 pnv_pci_ioda2_set_bypass(pe, false);
0eaf4def
AK		 1424 if (pe->table_group.group) {
1425 iommu_group_put(pe->table_group.group);
1426 BUG_ON(pe->table_group.group);
ac9a5889 1427 }
e5afdf9d 1428 iommu_tce_table_put(tbl);
781a868f
WY		 1429}
1430
ee8222fe 1431static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
781a868f
WY		 1432{
1433 struct pci_bus *bus;
1434 struct pci_controller *hose;
1435 struct pnv_phb *phb;
1436 struct pnv_ioda_pe *pe, *pe_n;
1437 struct pci_dn *pdn;
1438
1439 bus = pdev->bus;
1440 hose = pci_bus_to_host(bus);
1441 phb = hose->private_data;
02639b0e 1442 pdn = pci_get_pdn(pdev);
781a868f
WY		 1443
1444 if (!pdev->is_physfn)
1445 return;
1446
781a868f
WY		 1447 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1448 if (pe->parent_dev != pdev)
1449 continue;
1450
1451 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1452
1453 /* Remove from list */
1454 mutex_lock(&phb->ioda.pe_list_mutex);
1455 list_del(&pe->list);
1456 mutex_unlock(&phb->ioda.pe_list_mutex);
1457
1458 pnv_ioda_deconfigure_pe(phb, pe);
1459
1e916772 1460 pnv_ioda_free_pe(pe);
781a868f
WY		 1461 }
1462}
1463
1464void pnv_pci_sriov_disable(struct pci_dev *pdev)
1465{
1466 struct pci_bus *bus;
1467 struct pci_controller *hose;
1468 struct pnv_phb *phb;
1e916772 1469 struct pnv_ioda_pe *pe;
781a868f 1470 struct pci_dn *pdn;
be283eeb 1471 u16 num_vfs, i;
781a868f
WY		 1472
1473 bus = pdev->bus;
1474 hose = pci_bus_to_host(bus);
1475 phb = hose->private_data;
1476 pdn = pci_get_pdn(pdev);
781a868f
WY		 1477 num_vfs = pdn->num_vfs;
1478
1479 /* Release VF PEs */
ee8222fe 1480 pnv_ioda_release_vf_PE(pdev);
781a868f
WY		 1481
1482 if (phb->type == PNV_PHB_IODA2) {
ee8222fe 1483 if (!pdn->m64_single_mode)
be283eeb 1484 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
781a868f
WY		 1485
1486 /* Release M64 windows */
ee8222fe 1487 pnv_pci_vf_release_m64(pdev, num_vfs);
781a868f
WY		 1488
1489 /* Release PE numbers */
be283eeb
WY		 1490 if (pdn->m64_single_mode) {
1491 for (i = 0; i < num_vfs; i++) {
1e916772
GS		 1492 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1493 continue;
1494
1495 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1496 pnv_ioda_free_pe(pe);
be283eeb
WY		 1497 }
1498 } else
1499 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1500 /* Releasing pe_num_map */
1501 kfree(pdn->pe_num_map);
781a868f
WY		 1502 }
1503}
1504
1505static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1506 struct pnv_ioda_pe *pe);
1507static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1508{
1509 struct pci_bus *bus;
1510 struct pci_controller *hose;
1511 struct pnv_phb *phb;
1512 struct pnv_ioda_pe *pe;
1513 int pe_num;
1514 u16 vf_index;
1515 struct pci_dn *pdn;
1516
1517 bus = pdev->bus;
1518 hose = pci_bus_to_host(bus);
1519 phb = hose->private_data;
1520 pdn = pci_get_pdn(pdev);
1521
1522 if (!pdev->is_physfn)
1523 return;
1524
1525 /* Reserve PE for each VF */
1526 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
be283eeb
WY		 1527 if (pdn->m64_single_mode)
1528 pe_num = pdn->pe_num_map[vf_index];
1529 else
1530 pe_num = *pdn->pe_num_map + vf_index;
781a868f
WY		 1531
1532 pe = &phb->ioda.pe_array[pe_num];
1533 pe->pe_number = pe_num;
1534 pe->phb = phb;
1535 pe->flags = PNV_IODA_PE_VF;
1536 pe->pbus = NULL;
1537 pe->parent_dev = pdev;
781a868f
WY		 1538 pe->mve_number = -1;
1539 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1540 pci_iov_virtfn_devfn(pdev, vf_index);
1541
1f52f176 1542 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
781a868f
WY		 1543 hose->global_number, pdev->bus->number,
1544 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1545 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1546
1547 if (pnv_ioda_configure_pe(phb, pe)) {
1548 /* XXX What do we do here ? */
1e916772 1549 pnv_ioda_free_pe(pe);
781a868f
WY		 1550 pe->pdev = NULL;
1551 continue;
1552 }
1553
781a868f
WY		 1554 /* Put PE to the list */
1555 mutex_lock(&phb->ioda.pe_list_mutex);
1556 list_add_tail(&pe->list, &phb->ioda.pe_list);
1557 mutex_unlock(&phb->ioda.pe_list_mutex);
1558
1559 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1560 }
1561}
1562
1563int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1564{
1565 struct pci_bus *bus;
1566 struct pci_controller *hose;
1567 struct pnv_phb *phb;
1e916772 1568 struct pnv_ioda_pe *pe;
781a868f
WY		 1569 struct pci_dn *pdn;
1570 int ret;
be283eeb 1571 u16 i;
781a868f
WY		 1572
1573 bus = pdev->bus;
1574 hose = pci_bus_to_host(bus);
1575 phb = hose->private_data;
1576 pdn = pci_get_pdn(pdev);
1577
1578 if (phb->type == PNV_PHB_IODA2) {
b0331854
WY		 1579 if (!pdn->vfs_expanded) {
1580 dev_info(&pdev->dev, "don't support this SRIOV device"
1581 " with non 64bit-prefetchable IOV BAR\n");
1582 return -ENOSPC;
1583 }
1584
ee8222fe
WY		 1585 /*
1586 * When M64 BARs functions in Single PE mode, the number of VFs
1587 * could be enabled must be less than the number of M64 BARs.
1588 */
1589 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1590 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1591 return -EBUSY;
1592 }
1593
be283eeb
WY		 1594 /* Allocating pe_num_map */
1595 if (pdn->m64_single_mode)
fb37e128
ME		 1596 pdn->pe_num_map = kmalloc_array(num_vfs,
1597 sizeof(*pdn->pe_num_map),
1598 GFP_KERNEL);
be283eeb
WY		 1599 else
1600 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1601
1602 if (!pdn->pe_num_map)
1603 return -ENOMEM;
1604
1605 if (pdn->m64_single_mode)
1606 for (i = 0; i < num_vfs; i++)
1607 pdn->pe_num_map[i] = IODA_INVALID_PE;
1608
781a868f 1609 /* Calculate available PE for required VFs */
be283eeb
WY		 1610 if (pdn->m64_single_mode) {
1611 for (i = 0; i < num_vfs; i++) {
1e916772
GS		 1612 pe = pnv_ioda_alloc_pe(phb);
1613 if (!pe) {
be283eeb
WY		 1614 ret = -EBUSY;
1615 goto m64_failed;
1616 }
1e916772
GS		 1617
1618 pdn->pe_num_map[i] = pe->pe_number;
be283eeb
WY		 1619 }
1620 } else {
1621 mutex_lock(&phb->ioda.pe_alloc_mutex);
1622 *pdn->pe_num_map = bitmap_find_next_zero_area(
92b8f137 1623 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
be283eeb 1624 0, num_vfs, 0);
92b8f137 1625 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
be283eeb
WY		 1626 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1627 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1628 kfree(pdn->pe_num_map);
1629 return -EBUSY;
1630 }
1631 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
781a868f 1632 mutex_unlock(&phb->ioda.pe_alloc_mutex);
781a868f 1633 }
781a868f 1634 pdn->num_vfs = num_vfs;
781a868f
WY		 1635
1636 /* Assign M64 window accordingly */
02639b0e 1637 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
781a868f
WY		 1638 if (ret) {
1639 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1640 goto m64_failed;
1641 }
1642
1643 /*
1644 * When using one M64 BAR to map one IOV BAR, we need to shift
1645 * the IOV BAR according to the PE# allocated to the VFs.
1646 * Otherwise, the PE# for the VF will conflict with others.
1647 */
ee8222fe 1648 if (!pdn->m64_single_mode) {
be283eeb 1649 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
02639b0e
WY		 1650 if (ret)
1651 goto m64_failed;
1652 }
781a868f
WY		 1653 }
1654
1655 /* Setup VF PEs */
1656 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1657
1658 return 0;
1659
1660m64_failed:
be283eeb
WY		 1661 if (pdn->m64_single_mode) {
1662 for (i = 0; i < num_vfs; i++) {
1e916772
GS		 1663 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1664 continue;
1665
1666 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1667 pnv_ioda_free_pe(pe);
be283eeb
WY		 1668 }
1669 } else
1670 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1671
1672 /* Releasing pe_num_map */
1673 kfree(pdn->pe_num_map);
781a868f
WY		 1674
1675 return ret;
1676}
1677
a8b2f828
GS		 1678int pcibios_sriov_disable(struct pci_dev *pdev)
1679{
781a868f
WY		 1680 pnv_pci_sriov_disable(pdev);
1681
a8b2f828
GS		 1682 /* Release PCI data */
1683 remove_dev_pci_data(pdev);
1684 return 0;
1685}
1686
1687int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1688{
1689 /* Allocate PCI data */
1690 add_dev_pci_data(pdev);
781a868f 1691
ee8222fe 1692 return pnv_pci_sriov_enable(pdev, num_vfs);
a8b2f828
GS		 1693}
1694#endif /* CONFIG_PCI_IOV */
1695
959c9bdd 1696static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
184cd4a3 1697{
b72c1f65 1698 struct pci_dn *pdn = pci_get_pdn(pdev);
959c9bdd 1699 struct pnv_ioda_pe *pe;
184cd4a3 1700
959c9bdd
GS		 1701 /*
1702 * The function can be called while the PE#
1703 * hasn't been assigned. Do nothing for the
1704 * case.
1705 */
1706 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1707 return;
184cd4a3 1708
959c9bdd 1709 pe = &phb->ioda.pe_array[pdn->pe_number];
cd15b048 1710 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
0e1ffef0 1711 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
b348aa65 1712 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
4617082e
AK		 1713 /*
1714 * Note: iommu_add_device() will fail here as
1715 * for physical PE: the device is already added by now;
1716 * for virtual PE: sysfs entries are not ready yet and
1717 * tce_iommu_bus_notifier will add the device to a group later.
1718 */
184cd4a3
BH		 1719}
1720
763d2d8d 1721static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
cd15b048 1722{
763d2d8d
DA		 1723 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1724 struct pnv_phb *phb = hose->private_data;
cd15b048
BH		 1725 struct pci_dn *pdn = pci_get_pdn(pdev);
1726 struct pnv_ioda_pe *pe;
1727 uint64_t top;
1728 bool bypass = false;
1729
1730 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1731 return -ENODEV;;
1732
1733 pe = &phb->ioda.pe_array[pdn->pe_number];
1734 if (pe->tce_bypass_enabled) {
1735 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1736 bypass = (dma_mask >= top);
1737 }
1738
1739 if (bypass) {
1740 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1741 set_dma_ops(&pdev->dev, &dma_direct_ops);
cd15b048
BH		 1742 } else {
1743 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1744 set_dma_ops(&pdev->dev, &dma_iommu_ops);
cd15b048 1745 }
a32305bf 1746 *pdev->dev.dma_mask = dma_mask;
5d2aa710
AP		 1747
1748 /* Update peer npu devices */
f9f83456 1749 pnv_npu_try_dma_set_bypass(pdev, bypass);
5d2aa710 1750
cd15b048
BH		 1751 return 0;
1752}
1753
53522982 1754static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
fe7e85c6 1755{
53522982
AD		 1756 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1757 struct pnv_phb *phb = hose->private_data;
fe7e85c6
GS		 1758 struct pci_dn *pdn = pci_get_pdn(pdev);
1759 struct pnv_ioda_pe *pe;
1760 u64 end, mask;
1761
1762 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1763 return 0;
1764
1765 pe = &phb->ioda.pe_array[pdn->pe_number];
1766 if (!pe->tce_bypass_enabled)
1767 return __dma_get_required_mask(&pdev->dev);
1768
1769
1770 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1771 mask = 1ULL << (fls64(end) - 1);
1772 mask += mask - 1;
1773
1774 return mask;
1775}
1776
dff4a39e 1777static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
db08e1d5
AK		 1778 struct pci_bus *bus,
1779 bool add_to_group)
74251fe2
BH		 1780{
1781 struct pci_dev *dev;
1782
1783 list_for_each_entry(dev, &bus->devices, bus_list) {
b348aa65 1784 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
e91c2511 1785 set_dma_offset(&dev->dev, pe->tce_bypass_base);
db08e1d5
AK		 1786 if (add_to_group)
1787 iommu_add_device(&dev->dev);
dff4a39e 1788
5c89a87d 1789 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
db08e1d5
AK		 1790 pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1791 add_to_group);
74251fe2
BH		 1792 }
1793}
1794
fd141d1a
BH		 1795static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1796 bool real_mode)
1797{
1798 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1799 (phb->regs + 0x210);
1800}
1801
a34ab7c3 1802static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
decbda25 1803 unsigned long index, unsigned long npages, bool rm)
4cce9550 1804{
0eaf4def
AK		 1805 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1806 &tbl->it_group_list, struct iommu_table_group_link,
1807 next);
1808 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
b348aa65 1809 struct pnv_ioda_pe, table_group);
fd141d1a 1810 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
4cce9550
GS		 1811 unsigned long start, end, inc;
1812
decbda25
AK		 1813 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1814 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1815 npages - 1);
4cce9550 1816
08acce1c
BH		 1817 /* p7ioc-style invalidation, 2 TCEs per write */
1818 start |= (1ull << 63);
1819 end |= (1ull << 63);
1820 inc = 16;
4cce9550
GS		 1821 end |= inc - 1; /* round up end to be different than start */
1822
1823 mb(); /* Ensure above stores are visible */
1824 while (start <= end) {
8e0a1611 1825 if (rm)
3ad26e5c 1826 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1827 else
3ad26e5c 1828 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1829 start += inc;
1830 }
1831
1832 /*
1833 * The iommu layer will do another mb() for us on build()
1834 * and we don't care on free()
1835 */
1836}
1837
decbda25
AK		 1838static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1839 long npages, unsigned long uaddr,
1840 enum dma_data_direction direction,
00085f1e 1841 unsigned long attrs)
decbda25
AK		 1842{
1843 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1844 attrs);
1845
08acce1c 1846 if (!ret)
a34ab7c3 1847 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
decbda25
AK		 1848
1849 return ret;
1850}
1851
05c6cfb9
AK		 1852#ifdef CONFIG_IOMMU_API
1853static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1854 unsigned long *hpa, enum dma_data_direction *direction)
1855{
1856 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1857
08acce1c 1858 if (!ret)
a34ab7c3 1859 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
05c6cfb9
AK		 1860
1861 return ret;
1862}
a540aa56
AK		 1863
1864static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1865 unsigned long *hpa, enum dma_data_direction *direction)
1866{
1867 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1868
1869 if (!ret)
1870 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
1871
1872 return ret;
1873}
05c6cfb9
AK		 1874#endif
1875
decbda25
AK		 1876static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1877 long npages)
1878{
1879 pnv_tce_free(tbl, index, npages);
1880
08acce1c 1881 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
decbda25
AK		 1882}
1883
da004c36 1884static struct iommu_table_ops pnv_ioda1_iommu_ops = {
decbda25 1885 .set = pnv_ioda1_tce_build,
05c6cfb9
AK		 1886#ifdef CONFIG_IOMMU_API
1887 .exchange = pnv_ioda1_tce_xchg,
a540aa56 1888 .exchange_rm = pnv_ioda1_tce_xchg_rm,
05c6cfb9 1889#endif
decbda25 1890 .clear = pnv_ioda1_tce_free,
da004c36
AK		 1891 .get = pnv_tce_get,
1892};
1893
a34ab7c3
BH		 1894#define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1895#define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1896#define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
bef9253f 1897
a34ab7c3 1898void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
0bbcdb43 1899{
fd141d1a 1900 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
a34ab7c3 1901 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
0bbcdb43
AK		 1902
1903 mb(); /* Ensure previous TCE table stores are visible */
1904 if (rm)
fd141d1a 1905 __raw_rm_writeq(cpu_to_be64(val), invalidate);
0bbcdb43 1906 else
fd141d1a 1907 __raw_writeq(cpu_to_be64(val), invalidate);
0bbcdb43
AK		 1908}
1909
a34ab7c3 1910static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
5780fb04
AK		 1911{
1912 /* 01xb - invalidate TCEs that match the specified PE# */
fd141d1a 1913 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
a34ab7c3 1914 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
5780fb04
AK		 1915
1916 mb(); /* Ensure above stores are visible */
fd141d1a 1917 __raw_writeq(cpu_to_be64(val), invalidate);
5780fb04
AK		 1918}
1919
fd141d1a
BH		 1920static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
1921 unsigned shift, unsigned long index,
1922 unsigned long npages)
4cce9550 1923{
4d902195 1924 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
4cce9550 1925 unsigned long start, end, inc;
4cce9550
GS		 1926
1927 /* We'll invalidate DMA address in PE scope */
a34ab7c3 1928 start = PHB3_TCE_KILL_INVAL_ONE;
fd141d1a 1929 start |= (pe->pe_number & 0xFF);
4cce9550
GS		 1930 end = start;
1931
1932 /* Figure out the start, end and step */
decbda25
AK		 1933 start |= (index << shift);
1934 end |= ((index + npages - 1) << shift);
b0376c9b 1935 inc = (0x1ull << shift);
4cce9550
GS		 1936 mb();
1937
1938 while (start <= end) {
8e0a1611 1939 if (rm)
3ad26e5c 1940 __raw_rm_writeq(cpu_to_be64(start), invalidate);
8e0a1611 1941 else
3ad26e5c 1942 __raw_writeq(cpu_to_be64(start), invalidate);
4cce9550
GS		 1943 start += inc;
1944 }
1945}
1946
f0228c41
BH		 1947static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1948{
1949 struct pnv_phb *phb = pe->phb;
1950
1951 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1952 pnv_pci_phb3_tce_invalidate_pe(pe);
1953 else
1954 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1955 pe->pe_number, 0, 0, 0);
1956}
1957
e57080f1
AK		 1958static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1959 unsigned long index, unsigned long npages, bool rm)
1960{
1961 struct iommu_table_group_link *tgl;
1962
a540aa56 1963 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
e57080f1
AK		 1964 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1965 struct pnv_ioda_pe, table_group);
f0228c41
BH		 1966 struct pnv_phb *phb = pe->phb;
1967 unsigned int shift = tbl->it_page_shift;
1968
616badd2
AP		 1969 /*
1970 * NVLink1 can use the TCE kill register directly as
1971 * it's the same as PHB3. NVLink2 is different and
1972 * should go via the OPAL call.
1973 */
1974 if (phb->model == PNV_PHB_MODEL_NPU) {
0bbcdb43
AK		 1975 /*
1976 * The NVLink hardware does not support TCE kill
1977 * per TCE entry so we have to invalidate
1978 * the entire cache for it.
1979 */
f0228c41 1980 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
85674868
AK		 1981 continue;
1982 }
f0228c41
BH		 1983 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1984 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
1985 index, npages);
f0228c41
BH		 1986 else
1987 opal_pci_tce_kill(phb->opal_id,
1988 OPAL_PCI_TCE_KILL_PAGES,
1989 pe->pe_number, 1u << shift,
1990 index << shift, npages);
e57080f1
AK		 1991 }
1992}
1993
decbda25
AK		 1994static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1995 long npages, unsigned long uaddr,
1996 enum dma_data_direction direction,
00085f1e 1997 unsigned long attrs)
4cce9550 1998{
decbda25
AK		 1999 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2000 attrs);
4cce9550 2001
08acce1c 2002 if (!ret)
decbda25
AK		 2003 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2004
2005 return ret;
2006}
2007
05c6cfb9
AK		 2008#ifdef CONFIG_IOMMU_API
2009static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2010 unsigned long *hpa, enum dma_data_direction *direction)
2011{
2012 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2013
08acce1c 2014 if (!ret)
05c6cfb9
AK		 2015 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2016
2017 return ret;
2018}
a540aa56
AK		 2019
2020static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2021 unsigned long *hpa, enum dma_data_direction *direction)
2022{
2023 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2024
2025 if (!ret)
2026 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2027
2028 return ret;
2029}
05c6cfb9
AK		 2030#endif
2031
decbda25
AK		 2032static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2033 long npages)
2034{
2035 pnv_tce_free(tbl, index, npages);
2036
08acce1c 2037 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
4cce9550
GS		 2038}
2039
4793d65d
AK		 2040static void pnv_ioda2_table_free(struct iommu_table *tbl)
2041{
2042 pnv_pci_ioda2_table_free_pages(tbl);
4793d65d
AK		 2043}
2044
da004c36 2045static struct iommu_table_ops pnv_ioda2_iommu_ops = {
decbda25 2046 .set = pnv_ioda2_tce_build,
05c6cfb9
AK		 2047#ifdef CONFIG_IOMMU_API
2048 .exchange = pnv_ioda2_tce_xchg,
a540aa56 2049 .exchange_rm = pnv_ioda2_tce_xchg_rm,
05c6cfb9 2050#endif
decbda25 2051 .clear = pnv_ioda2_tce_free,
da004c36 2052 .get = pnv_tce_get,
4793d65d 2053 .free = pnv_ioda2_table_free,
da004c36
AK		 2054};
2055
801846d1
GS		 2056static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2057{
2058 unsigned int *weight = (unsigned int *)data;
2059
2060 /* This is quite simplistic. The "base" weight of a device
2061 * is 10. 0 means no DMA is to be accounted for it.
2062 */
2063 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2064 return 0;
2065
2066 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2067 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2068 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2069 *weight += 3;
2070 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2071 *weight += 15;
2072 else
2073 *weight += 10;
2074
2075 return 0;
2076}
2077
2078static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2079{
2080 unsigned int weight = 0;
2081
2082 /* SRIOV VF has same DMA32 weight as its PF */
2083#ifdef CONFIG_PCI_IOV
2084 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2085 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2086 return weight;
2087 }
2088#endif
2089
2090 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2091 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2092 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2093 struct pci_dev *pdev;
2094
2095 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2096 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2097 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2098 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2099 }
2100
2101 return weight;
2102}
2103
b30d936f 2104static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2b923ed1 2105 struct pnv_ioda_pe *pe)
184cd4a3
BH		 2106{
2107
2108 struct page *tce_mem = NULL;
184cd4a3 2109 struct iommu_table *tbl;
2b923ed1
GS		 2110 unsigned int weight, total_weight = 0;
2111 unsigned int tce32_segsz, base, segs, avail, i;
184cd4a3
BH		 2112 int64_t rc;
2113 void *addr;
2114
184cd4a3
BH		 2115 /* XXX FIXME: Handle 64-bit only DMA devices */
2116 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2117 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2b923ed1
GS		 2118 weight = pnv_pci_ioda_pe_dma_weight(pe);
2119 if (!weight)
2120 return;
2121
2122 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2123 &total_weight);
2124 segs = (weight * phb->ioda.dma32_count) / total_weight;
2125 if (!segs)
2126 segs = 1;
184cd4a3 2127
2b923ed1
GS		 2128 /*
2129 * Allocate contiguous DMA32 segments. We begin with the expected
2130 * number of segments. With one more attempt, the number of DMA32
2131 * segments to be allocated is decreased by one until one segment
2132 * is allocated successfully.
2133 */
2134 do {
2135 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2136 for (avail = 0, i = base; i < base + segs; i++) {
2137 if (phb->ioda.dma32_segmap[i] ==
2138 IODA_INVALID_PE)
2139 avail++;
2140 }
2141
2142 if (avail == segs)
2143 goto found;
2144 }
2145 } while (--segs);
2146
2147 if (!segs) {
2148 pe_warn(pe, "No available DMA32 segments\n");
2149 return;
2150 }
2151
2152found:
0eaf4def 2153 tbl = pnv_pci_table_alloc(phb->hose->node);
b348aa65
AK		 2154 iommu_register_group(&pe->table_group, phb->hose->global_number,
2155 pe->pe_number);
0eaf4def 2156 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
c5773822 2157
184cd4a3 2158 /* Grab a 32-bit TCE table */
2b923ed1
GS		 2159 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2160 weight, total_weight, base, segs);
184cd4a3 2161 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
acce971c
GS		 2162 base * PNV_IODA1_DMA32_SEGSIZE,
2163 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
184cd4a3
BH		 2164
2165 /* XXX Currently, we allocate one big contiguous table for the
2166 * TCEs. We only really need one chunk per 256M of TCE space
2167 * (ie per segment) but that's an optimization for later, it
2168 * requires some added smarts with our get/put_tce implementation
acce971c
GS		 2169 *
2170 * Each TCE page is 4KB in size and each TCE entry occupies 8
2171 * bytes
184cd4a3 2172 */
acce971c 2173 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
184cd4a3 2174 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
acce971c 2175 get_order(tce32_segsz * segs));
184cd4a3
BH		 2176 if (!tce_mem) {
2177 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2178 goto fail;
2179 }
2180 addr = page_address(tce_mem);
acce971c 2181 memset(addr, 0, tce32_segsz * segs);
184cd4a3
BH		 2182
2183 /* Configure HW */
2184 for (i = 0; i < segs; i++) {
2185 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2186 pe->pe_number,
2187 base + i, 1,
acce971c
GS		 2188 __pa(addr) + tce32_segsz * i,
2189 tce32_segsz, IOMMU_PAGE_SIZE_4K);
184cd4a3
BH		 2190 if (rc) {
2191 pe_err(pe, " Failed to configure 32-bit TCE table,"
2192 " err %ld\n", rc);
2193 goto fail;
2194 }
2195 }
2196
2b923ed1
GS		 2197 /* Setup DMA32 segment mapping */
2198 for (i = base; i < base + segs; i++)
2199 phb->ioda.dma32_segmap[i] = pe->pe_number;
2200
184cd4a3 2201 /* Setup linux iommu table */
acce971c
GS		 2202 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2203 base * PNV_IODA1_DMA32_SEGSIZE,
2204 IOMMU_PAGE_SHIFT_4K);
184cd4a3 2205
da004c36 2206 tbl->it_ops = &pnv_ioda1_iommu_ops;
4793d65d
AK		 2207 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2208 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
184cd4a3
BH		 2209 iommu_init_table(tbl, phb->hose->node);
2210
781a868f 2211 if (pe->flags & PNV_IODA_PE_DEV) {
4617082e
AK		 2212 /*
2213 * Setting table base here only for carrying iommu_group
2214 * further down to let iommu_add_device() do the job.
2215 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2216 */
2217 set_iommu_table_base(&pe->pdev->dev, tbl);
2218 iommu_add_device(&pe->pdev->dev);
c5773822 2219 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
db08e1d5 2220 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
74251fe2 2221
184cd4a3
BH		 2222 return;
2223 fail:
2224 /* XXX Failure: Try to fallback to 64-bit only ? */
184cd4a3 2225 if (tce_mem)
acce971c 2226 __free_pages(tce_mem, get_order(tce32_segsz * segs));
0eaf4def
AK		 2227 if (tbl) {
2228 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
e5afdf9d 2229 iommu_tce_table_put(tbl);
0eaf4def 2230 }
184cd4a3
BH		 2231}
2232
43cb60ab
AK		 2233static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2234 int num, struct iommu_table *tbl)
2235{
2236 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2237 table_group);
2238 struct pnv_phb *phb = pe->phb;
2239 int64_t rc;
bbb845c4
AK		 2240 const unsigned long size = tbl->it_indirect_levels ?
2241 tbl->it_level_size : tbl->it_size;
43cb60ab
AK		 2242 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2243 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2244
4793d65d 2245 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
43cb60ab
AK		 2246 start_addr, start_addr + win_size - 1,
2247 IOMMU_PAGE_SIZE(tbl));
2248
2249 /*
2250 * Map TCE table through TVT. The TVE index is the PE number
2251 * shifted by 1 bit for 32-bits DMA space.
2252 */
2253 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2254 pe->pe_number,
4793d65d 2255 (pe->pe_number << 1) + num,
bbb845c4 2256 tbl->it_indirect_levels + 1,
43cb60ab 2257 __pa(tbl->it_base),
bbb845c4 2258 size << 3,
43cb60ab
AK		 2259 IOMMU_PAGE_SIZE(tbl));
2260 if (rc) {
2261 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2262 return rc;
2263 }
2264
2265 pnv_pci_link_table_and_group(phb->hose->node, num,
2266 tbl, &pe->table_group);
ed7d9a1d 2267 pnv_pci_ioda2_tce_invalidate_pe(pe);
43cb60ab
AK		 2268
2269 return 0;
2270}
2271
f87a8864 2272static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
cd15b048 2273{
cd15b048
BH		 2274 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2275 int64_t rc;
2276
2277 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2278 if (enable) {
2279 phys_addr_t top = memblock_end_of_DRAM();
2280
2281 top = roundup_pow_of_two(top);
2282 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2283 pe->pe_number,
2284 window_id,
2285 pe->tce_bypass_base,
2286 top);
2287 } else {
2288 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2289 pe->pe_number,
2290 window_id,
2291 pe->tce_bypass_base,
2292 0);
cd15b048
BH		 2293 }
2294 if (rc)
2295 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2296 else
2297 pe->tce_bypass_enabled = enable;
2298}
2299
4793d65d
AK		 2300static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2301 __u32 page_shift, __u64 window_size, __u32 levels,
2302 struct iommu_table *tbl);
2303
2304static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2305 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2306 struct iommu_table **ptbl)
2307{
2308 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2309 table_group);
2310 int nid = pe->phb->hose->node;
2311 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2312 long ret;
2313 struct iommu_table *tbl;
2314
2315 tbl = pnv_pci_table_alloc(nid);
2316 if (!tbl)
2317 return -ENOMEM;
2318
11edf116
AK		 2319 tbl->it_ops = &pnv_ioda2_iommu_ops;
2320
4793d65d
AK		 2321 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2322 bus_offset, page_shift, window_size,
2323 levels, tbl);
2324 if (ret) {
e5afdf9d 2325 iommu_tce_table_put(tbl);
4793d65d
AK		 2326 return ret;
2327 }
2328
4793d65d
AK		 2329 *ptbl = tbl;
2330
2331 return 0;
2332}
2333
46d3e1e1
AK		 2334static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2335{
2336 struct iommu_table *tbl = NULL;
2337 long rc;
2338
fa144869
NA		 2339 /*
2340 * crashkernel= specifies the kdump kernel's maximum memory at
2341 * some offset and there is no guaranteed the result is a power
2342 * of 2, which will cause errors later.
2343 */
2344 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2345
bb005455
NA		 2346 /*
2347 * In memory constrained environments, e.g. kdump kernel, the
2348 * DMA window can be larger than available memory, which will
2349 * cause errors later.
2350 */
fa144869 2351 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
bb005455 2352
46d3e1e1
AK		 2353 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2354 IOMMU_PAGE_SHIFT_4K,
bb005455 2355 window_size,
46d3e1e1
AK		 2356 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2357 if (rc) {
2358 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2359 rc);
2360 return rc;
2361 }
2362
2363 iommu_init_table(tbl, pe->phb->hose->node);
2364
2365 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2366 if (rc) {
2367 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2368 rc);
e5afdf9d 2369 iommu_tce_table_put(tbl);
46d3e1e1
AK		 2370 return rc;
2371 }
2372
2373 if (!pnv_iommu_bypass_disabled)
2374 pnv_pci_ioda2_set_bypass(pe, true);
2375
46d3e1e1
AK		 2376 /*
2377 * Setting table base here only for carrying iommu_group
2378 * further down to let iommu_add_device() do the job.
2379 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2380 */
2381 if (pe->flags & PNV_IODA_PE_DEV)
2382 set_iommu_table_base(&pe->pdev->dev, tbl);
2383
2384 return 0;
2385}
2386
b5926430
AK		 2387#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2388static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2389 int num)
2390{
2391 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2392 table_group);
2393 struct pnv_phb *phb = pe->phb;
2394 long ret;
2395
2396 pe_info(pe, "Removing DMA window #%d\n", num);
2397
2398 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2399 (pe->pe_number << 1) + num,
2400 0/* levels */, 0/* table address */,
2401 0/* table size */, 0/* page size */);
2402 if (ret)
2403 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2404 else
ed7d9a1d 2405 pnv_pci_ioda2_tce_invalidate_pe(pe);
b5926430
AK		 2406
2407 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2408
2409 return ret;
2410}
2411#endif
2412
f87a8864 2413#ifdef CONFIG_IOMMU_API
00547193
AK		 2414static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2415 __u64 window_size, __u32 levels)
2416{
2417 unsigned long bytes = 0;
2418 const unsigned window_shift = ilog2(window_size);
2419 unsigned entries_shift = window_shift - page_shift;
2420 unsigned table_shift = entries_shift + 3;
2421 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2422 unsigned long direct_table_size;
2423
2424 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2425 (window_size > memory_hotplug_max()) ||
2426 !is_power_of_2(window_size))
2427 return 0;
2428
2429 /* Calculate a direct table size from window_size and levels */
2430 entries_shift = (entries_shift + levels - 1) / levels;
2431 table_shift = entries_shift + 3;
2432 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2433 direct_table_size = 1UL << table_shift;
2434
2435 for ( ; levels; --levels) {
2436 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2437
2438 tce_table_size /= direct_table_size;
2439 tce_table_size <<= 3;
2440 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2441 }
2442
2443 return bytes;
2444}
2445
f87a8864 2446static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
cd15b048 2447{
f87a8864
AK		 2448 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2449 table_group);
46d3e1e1
AK		 2450 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2451 struct iommu_table *tbl = pe->table_group.tables[0];
cd15b048 2452
f87a8864 2453 pnv_pci_ioda2_set_bypass(pe, false);
46d3e1e1 2454 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
db08e1d5
AK		 2455 if (pe->pbus)
2456 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
e5afdf9d 2457 iommu_tce_table_put(tbl);
f87a8864 2458}
cd15b048 2459
f87a8864
AK		 2460static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2461{
2462 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2463 table_group);
2464
46d3e1e1 2465 pnv_pci_ioda2_setup_default_config(pe);
db08e1d5
AK		 2466 if (pe->pbus)
2467 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
cd15b048
BH		 2468}
2469
f87a8864 2470static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
00547193 2471 .get_table_size = pnv_pci_ioda2_get_table_size,
4793d65d
AK		 2472 .create_table = pnv_pci_ioda2_create_table,
2473 .set_window = pnv_pci_ioda2_set_window,
2474 .unset_window = pnv_pci_ioda2_unset_window,
f87a8864
AK		 2475 .take_ownership = pnv_ioda2_take_ownership,
2476 .release_ownership = pnv_ioda2_release_ownership,
2477};
b5cb9ab1
AK		 2478
2479static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2480{
2481 struct pci_controller *hose;
2482 struct pnv_phb *phb;
2483 struct pnv_ioda_pe **ptmppe = opaque;
2484 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2485 struct pci_dn *pdn = pci_get_pdn(pdev);
2486
2487 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2488 return 0;
2489
2490 hose = pci_bus_to_host(pdev->bus);
2491 phb = hose->private_data;
2492 if (phb->type != PNV_PHB_NPU)
2493 return 0;
2494
2495 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2496
2497 return 1;
2498}
2499
2500/*
2501 * This returns PE of associated NPU.
2502 * This assumes that NPU is in the same IOMMU group with GPU and there is
2503 * no other PEs.
2504 */
2505static struct pnv_ioda_pe *gpe_table_group_to_npe(
2506 struct iommu_table_group *table_group)
2507{
2508 struct pnv_ioda_pe *npe = NULL;
2509 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2510 gpe_table_group_to_npe_cb);
2511
2512 BUG_ON(!ret || !npe);
2513
2514 return npe;
2515}
2516
2517static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2518 int num, struct iommu_table *tbl)
2519{
2520 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2521
2522 if (ret)
2523 return ret;
2524
2525 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2526 if (ret)
2527 pnv_pci_ioda2_unset_window(table_group, num);
2528
2529 return ret;
2530}
2531
2532static long pnv_pci_ioda2_npu_unset_window(
2533 struct iommu_table_group *table_group,
2534 int num)
2535{
2536 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2537
2538 if (ret)
2539 return ret;
2540
2541 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2542}
2543
2544static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2545{
2546 /*
2547 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2548 * the iommu_table if 32bit DMA is enabled.
2549 */
2550 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2551 pnv_ioda2_take_ownership(table_group);
2552}
2553
2554static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2555 .get_table_size = pnv_pci_ioda2_get_table_size,
2556 .create_table = pnv_pci_ioda2_create_table,
2557 .set_window = pnv_pci_ioda2_npu_set_window,
2558 .unset_window = pnv_pci_ioda2_npu_unset_window,
2559 .take_ownership = pnv_ioda2_npu_take_ownership,
2560 .release_ownership = pnv_ioda2_release_ownership,
2561};
2562
2563static void pnv_pci_ioda_setup_iommu_api(void)
2564{
2565 struct pci_controller *hose, *tmp;
2566 struct pnv_phb *phb;
2567 struct pnv_ioda_pe *pe, *gpe;
2568
2569 /*
2570 * Now we have all PHBs discovered, time to add NPU devices to
2571 * the corresponding IOMMU groups.
2572 */
2573 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2574 phb = hose->private_data;
2575
2576 if (phb->type != PNV_PHB_NPU)
2577 continue;
2578
2579 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2580 gpe = pnv_pci_npu_setup_iommu(pe);
2581 if (gpe)
2582 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2583 }
2584 }
2585}
2586#else /* !CONFIG_IOMMU_API */
2587static void pnv_pci_ioda_setup_iommu_api(void) { };
f87a8864
AK		 2588#endif
2589
bbb845c4
AK		 2590static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2591 unsigned levels, unsigned long limit,
3ba3a73e 2592 unsigned long *current_offset, unsigned long *total_allocated)
373f5657
GS		 2593{
2594 struct page *tce_mem = NULL;
bbb845c4 2595 __be64 *addr, *tmp;
aca6913f 2596 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
bbb845c4
AK		 2597 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2598 unsigned entries = 1UL << (shift - 3);
2599 long i;
aca6913f
AK		 2600
2601 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2602 if (!tce_mem) {
2603 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2604 return NULL;
2605 }
2606 addr = page_address(tce_mem);
bbb845c4 2607 memset(addr, 0, allocated);
3ba3a73e 2608 *total_allocated += allocated;
bbb845c4
AK		 2609
2610 --levels;
2611 if (!levels) {
2612 *current_offset += allocated;
2613 return addr;
2614 }
2615
2616 for (i = 0; i < entries; ++i) {
2617 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
3ba3a73e 2618 levels, limit, current_offset, total_allocated);
bbb845c4
AK		 2619 if (!tmp)
2620 break;
2621
2622 addr[i] = cpu_to_be64(__pa(tmp) |
2623 TCE_PCI_READ | TCE_PCI_WRITE);
2624
2625 if (*current_offset >= limit)
2626 break;
2627 }
aca6913f
AK		 2628
2629 return addr;
2630}
2631
bbb845c4
AK		 2632static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2633 unsigned long size, unsigned level);
2634
aca6913f 2635static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
bbb845c4
AK		 2636 __u32 page_shift, __u64 window_size, __u32 levels,
2637 struct iommu_table *tbl)
aca6913f 2638{
373f5657 2639 void *addr;
3ba3a73e 2640 unsigned long offset = 0, level_shift, total_allocated = 0;
aca6913f
AK		 2641 const unsigned window_shift = ilog2(window_size);
2642 unsigned entries_shift = window_shift - page_shift;
2643 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2644 const unsigned long tce_table_size = 1UL << table_shift;
2645
bbb845c4
AK		 2646 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2647 return -EINVAL;
2648
aca6913f
AK		 2649 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2650 return -EINVAL;
2651
bbb845c4
AK		 2652 /* Adjust direct table size from window_size and levels */
2653 entries_shift = (entries_shift + levels - 1) / levels;
2654 level_shift = entries_shift + 3;
2655 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2656
7aafac11
AK		 2657 if ((level_shift - 3) * levels + page_shift >= 60)
2658 return -EINVAL;
2659
aca6913f 2660 /* Allocate TCE table */
bbb845c4 2661 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
3ba3a73e 2662 levels, tce_table_size, &offset, &total_allocated);
bbb845c4
AK		 2663
2664 /* addr==NULL means that the first level allocation failed */
aca6913f
AK		 2665 if (!addr)
2666 return -ENOMEM;
2667
bbb845c4
AK		 2668 /*
2669 * First level was allocated but some lower level failed as
2670 * we did not allocate as much as we wanted,
2671 * release partially allocated table.
2672 */
2673 if (offset < tce_table_size) {
2674 pnv_pci_ioda2_table_do_free_pages(addr,
2675 1ULL << (level_shift - 3), levels - 1);
2676 return -ENOMEM;
2677 }
2678
aca6913f
AK		 2679 /* Setup linux iommu table */
2680 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2681 page_shift);
bbb845c4
AK		 2682 tbl->it_level_size = 1ULL << (level_shift - 3);
2683 tbl->it_indirect_levels = levels - 1;
3ba3a73e 2684 tbl->it_allocated_size = total_allocated;
aca6913f
AK		 2685
2686 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2687 window_size, tce_table_size, bus_offset);
2688
2689 return 0;
2690}
2691
bbb845c4
AK		 2692static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2693 unsigned long size, unsigned level)
2694{
2695 const unsigned long addr_ul = (unsigned long) addr &
2696 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2697
2698 if (level) {
2699 long i;
2700 u64 *tmp = (u64 *) addr_ul;
2701
2702 for (i = 0; i < size; ++i) {
2703 unsigned long hpa = be64_to_cpu(tmp[i]);
2704
2705 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2706 continue;
2707
2708 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2709 level - 1);
2710 }
2711 }
2712
2713 free_pages(addr_ul, get_order(size << 3));
2714}
2715
aca6913f
AK		 2716static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2717{
bbb845c4
AK		 2718 const unsigned long size = tbl->it_indirect_levels ?
2719 tbl->it_level_size : tbl->it_size;
2720
aca6913f
AK		 2721 if (!tbl->it_size)
2722 return;
2723
bbb845c4
AK		 2724 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2725 tbl->it_indirect_levels);
aca6913f
AK		 2726}
2727
2728static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2729 struct pnv_ioda_pe *pe)
2730{
373f5657
GS		 2731 int64_t rc;
2732
ccd1c191
GS		 2733 if (!pnv_pci_ioda_pe_dma_weight(pe))
2734 return;
2735
f87a8864
AK		 2736 /* TVE #1 is selected by PCI address bit 59 */
2737 pe->tce_bypass_base = 1ull << 59;
2738
b348aa65
AK		 2739 iommu_register_group(&pe->table_group, phb->hose->global_number,
2740 pe->pe_number);
c5773822 2741
373f5657 2742 /* The PE will reserve all possible 32-bits space */
373f5657 2743 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
aca6913f 2744 phb->ioda.m32_pci_base);
373f5657 2745
aca6913f 2746 /* Setup linux iommu table */
4793d65d
AK		 2747 pe->table_group.tce32_start = 0;
2748 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2749 pe->table_group.max_dynamic_windows_supported =
2750 IOMMU_TABLE_GROUP_MAX_TABLES;
2751 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2752 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
e5aad1e6
AK		 2753#ifdef CONFIG_IOMMU_API
2754 pe->table_group.ops = &pnv_pci_ioda2_ops;
2755#endif
2756
46d3e1e1 2757 rc = pnv_pci_ioda2_setup_default_config(pe);
801846d1 2758 if (rc)
46d3e1e1 2759 return;
373f5657 2760
20f13b95 2761 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
db08e1d5 2762 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
373f5657
GS		 2763}
2764
184cd4a3 2765#ifdef CONFIG_PCI_MSI
4ee11c1a 2766int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
137436c9 2767{
137436c9
GS		 2768 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2769 ioda.irq_chip);
4ee11c1a
SW		 2770
2771 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2772}
2773
2774static void pnv_ioda2_msi_eoi(struct irq_data *d)
2775{
137436c9 2776 int64_t rc;
4ee11c1a
SW		 2777 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2778 struct irq_chip *chip = irq_data_get_irq_chip(d);
137436c9 2779
4ee11c1a 2780 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
137436c9
GS		 2781 WARN_ON_ONCE(rc);
2782
2783 icp_native_eoi(d);
2784}
2785
fd9a1c26 2786
f456834a 2787void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
fd9a1c26
IM		 2788{
2789 struct irq_data *idata;
2790 struct irq_chip *ichip;
2791
fb111334
BH		 2792 /* The MSI EOI OPAL call is only needed on PHB3 */
2793 if (phb->model != PNV_PHB_MODEL_PHB3)
fd9a1c26
IM		 2794 return;
2795
2796 if (!phb->ioda.irq_chip_init) {
2797 /*
2798 * First time we setup an MSI IRQ, we need to setup the
2799 * corresponding IRQ chip to route correctly.
2800 */
2801 idata = irq_get_irq_data(virq);
2802 ichip = irq_data_get_irq_chip(idata);
2803 phb->ioda.irq_chip_init = 1;
2804 phb->ioda.irq_chip = *ichip;
2805 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2806 }
2807 irq_set_chip(virq, &phb->ioda.irq_chip);
2808}
2809
4ee11c1a
SW		 2810/*
2811 * Returns true iff chip is something that we could call
2812 * pnv_opal_pci_msi_eoi for.
2813 */
2814bool is_pnv_opal_msi(struct irq_chip *chip)
2815{
2816 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2817}
2818EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2819
184cd4a3 2820static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
137436c9
GS		 2821 unsigned int hwirq, unsigned int virq,
2822 unsigned int is_64, struct msi_msg *msg)
184cd4a3
BH		 2823{
2824 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2825 unsigned int xive_num = hwirq - phb->msi_base;
3a1a4661 2826 __be32 data;
184cd4a3
BH		 2827 int rc;
2828
2829 /* No PE assigned ? bail out ... no MSI for you ! */
2830 if (pe == NULL)
2831 return -ENXIO;
2832
2833 /* Check if we have an MVE */
2834 if (pe->mve_number < 0)
2835 return -ENXIO;
2836
b72c1f65 2837 /* Force 32-bit MSI on some broken devices */
36074381 2838 if (dev->no_64bit_msi)
b72c1f65
BH		 2839 is_64 = 0;
2840
184cd4a3
BH		 2841 /* Assign XIVE to PE */
2842 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2843 if (rc) {
2844 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2845 pci_name(dev), rc, xive_num);
2846 return -EIO;
2847 }
2848
2849 if (is_64) {
3a1a4661
BH		 2850 __be64 addr64;
2851
184cd4a3
BH		 2852 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2853 &addr64, &data);
2854 if (rc) {
2855 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2856 pci_name(dev), rc);
2857 return -EIO;
2858 }
3a1a4661
BH		 2859 msg->address_hi = be64_to_cpu(addr64) >> 32;
2860 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
184cd4a3 2861 } else {
3a1a4661
BH		 2862 __be32 addr32;
2863
184cd4a3
BH		 2864 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2865 &addr32, &data);
2866 if (rc) {
2867 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2868 pci_name(dev), rc);
2869 return -EIO;
2870 }
2871 msg->address_hi = 0;
3a1a4661 2872 msg->address_lo = be32_to_cpu(addr32);
184cd4a3 2873 }
3a1a4661 2874 msg->data = be32_to_cpu(data);
184cd4a3 2875
f456834a 2876 pnv_set_msi_irq_chip(phb, virq);
137436c9 2877
184cd4a3 2878 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
1f52f176 2879 " address=%x_%08x data=%x PE# %x\n",
184cd4a3
BH		 2880 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2881 msg->address_hi, msg->address_lo, data, pe->pe_number);
2882
2883 return 0;
2884}
2885
2886static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2887{
fb1b55d6 2888 unsigned int count;
184cd4a3
BH		 2889 const __be32 *prop = of_get_property(phb->hose->dn,
2890 "ibm,opal-msi-ranges", NULL);
2891 if (!prop) {
2892 /* BML Fallback */
2893 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2894 }
2895 if (!prop)
2896 return;
2897
2898 phb->msi_base = be32_to_cpup(prop);
fb1b55d6
GS		 2899 count = be32_to_cpup(prop + 1);
2900 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
184cd4a3
BH		 2901 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2902 phb->hose->global_number);
2903 return;
2904 }
fb1b55d6 2905
184cd4a3
BH		 2906 phb->msi_setup = pnv_pci_ioda_msi_setup;
2907 phb->msi32_support = 1;
2908 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
fb1b55d6 2909 count, phb->msi_base);
184cd4a3
BH		 2910}
2911#else
2912static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2913#endif /* CONFIG_PCI_MSI */
2914
6e628c7d
WY		 2915#ifdef CONFIG_PCI_IOV
2916static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2917{
f2dd0afe
WY		 2918 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2919 struct pnv_phb *phb = hose->private_data;
2920 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
6e628c7d
WY		 2921 struct resource *res;
2922 int i;
dfcc8d45 2923 resource_size_t size, total_vf_bar_sz;
6e628c7d 2924 struct pci_dn *pdn;
5b88ec22 2925 int mul, total_vfs;
6e628c7d
WY		 2926
2927 if (!pdev->is_physfn || pdev->is_added)
2928 return;
2929
6e628c7d
WY		 2930 pdn = pci_get_pdn(pdev);
2931 pdn->vfs_expanded = 0;
ee8222fe 2932 pdn->m64_single_mode = false;
6e628c7d 2933
5b88ec22 2934 total_vfs = pci_sriov_get_totalvfs(pdev);
92b8f137 2935 mul = phb->ioda.total_pe_num;
dfcc8d45 2936 total_vf_bar_sz = 0;
5b88ec22
WY		 2937
2938 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2939 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2940 if (!res->flags || res->parent)
2941 continue;
b79331a5 2942 if (!pnv_pci_is_m64_flags(res->flags)) {
b0331854
WY		 2943 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2944 " non M64 VF BAR%d: %pR. \n",
5b88ec22 2945 i, res);
b0331854 2946 goto truncate_iov;
5b88ec22
WY		 2947 }
2948
dfcc8d45
WY		 2949 total_vf_bar_sz += pci_iov_resource_size(pdev,
2950 i + PCI_IOV_RESOURCES);
5b88ec22 2951
f2dd0afe
WY		 2952 /*
2953 * If bigger than quarter of M64 segment size, just round up
2954 * power of two.
2955 *
2956 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2957 * with other devices, IOV BAR size is expanded to be
2958 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2959 * segment size , the expanded size would equal to half of the
2960 * whole M64 space size, which will exhaust the M64 Space and
2961 * limit the system flexibility. This is a design decision to
2962 * set the boundary to quarter of the M64 segment size.
2963 */
dfcc8d45 2964 if (total_vf_bar_sz > gate) {
5b88ec22 2965 mul = roundup_pow_of_two(total_vfs);
dfcc8d45
WY		 2966 dev_info(&pdev->dev,
2967 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2968 total_vf_bar_sz, gate, mul);
ee8222fe 2969 pdn->m64_single_mode = true;
5b88ec22
WY		 2970 break;
2971 }
2972 }
2973
6e628c7d
WY		 2974 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2975 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2976 if (!res->flags || res->parent)
2977 continue;
6e628c7d 2978
6e628c7d 2979 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
ee8222fe
WY		 2980 /*
2981 * On PHB3, the minimum size alignment of M64 BAR in single
2982 * mode is 32MB.
2983 */
2984 if (pdn->m64_single_mode && (size < SZ_32M))
2985 goto truncate_iov;
2986 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
5b88ec22 2987 res->end = res->start + size * mul - 1;
6e628c7d
WY		 2988 dev_dbg(&pdev->dev, " %pR\n", res);
2989 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
5b88ec22 2990 i, res, mul);
6e628c7d 2991 }
5b88ec22 2992 pdn->vfs_expanded = mul;
b0331854
WY		 2993
2994 return;
2995
2996truncate_iov:
2997 /* To save MMIO space, IOV BAR is truncated. */
2998 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2999 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3000 res->flags = 0;
3001 res->end = res->start - 1;
3002 }
6e628c7d
WY		 3003}
3004#endif /* CONFIG_PCI_IOV */
3005
23e79425
GS		 3006static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3007 struct resource *res)
3008{
3009 struct pnv_phb *phb = pe->phb;
3010 struct pci_bus_region region;
3011 int index;
3012 int64_t rc;
3013
3014 if (!res || !res->flags || res->start > res->end)
3015 return;
3016
3017 if (res->flags & IORESOURCE_IO) {
3018 region.start = res->start - phb->ioda.io_pci_base;
3019 region.end = res->end - phb->ioda.io_pci_base;
3020 index = region.start / phb->ioda.io_segsize;
3021
3022 while (index < phb->ioda.total_pe_num &&
3023 region.start <= region.end) {
3024 phb->ioda.io_segmap[index] = pe->pe_number;
3025 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3026 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3027 if (rc != OPAL_SUCCESS) {
1f52f176 3028 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
23e79425
GS		 3029 __func__, rc, index, pe->pe_number);
3030 break;
3031 }
3032
3033 region.start += phb->ioda.io_segsize;
3034 index++;
3035 }
3036 } else if ((res->flags & IORESOURCE_MEM) &&
5958d19a 3037 !pnv_pci_is_m64(phb, res)) {
23e79425
GS		 3038 region.start = res->start -
3039 phb->hose->mem_offset[0] -
3040 phb->ioda.m32_pci_base;
3041 region.end = res->end -
3042 phb->hose->mem_offset[0] -
3043 phb->ioda.m32_pci_base;
3044 index = region.start / phb->ioda.m32_segsize;
3045
3046 while (index < phb->ioda.total_pe_num &&
3047 region.start <= region.end) {
3048 phb->ioda.m32_segmap[index] = pe->pe_number;
3049 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3050 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3051 if (rc != OPAL_SUCCESS) {
1f52f176 3052 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
23e79425
GS		 3053 __func__, rc, index, pe->pe_number);
3054 break;
3055 }
3056
3057 region.start += phb->ioda.m32_segsize;
3058 index++;
3059 }
3060 }
3061}
3062
11685bec
GS		 3063/*
3064 * This function is supposed to be called on basis of PE from top
3065 * to bottom style. So the the I/O or MMIO segment assigned to
03671057 3066 * parent PE could be overridden by its child PEs if necessary.
11685bec 3067 */
23e79425 3068static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
11685bec 3069{
69d733e7 3070 struct pci_dev *pdev;
23e79425 3071 int i;
11685bec
GS		 3072
3073 /*
3074 * NOTE: We only care PCI bus based PE for now. For PCI
3075 * device based PE, for example SRIOV sensitive VF should
3076 * be figured out later.
3077 */
3078 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3079
69d733e7
GS		 3080 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3081 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3082 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3083
3084 /*
3085 * If the PE contains all subordinate PCI buses, the
3086 * windows of the child bridges should be mapped to
3087 * the PE as well.
3088 */
3089 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3090 continue;
3091 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3092 pnv_ioda_setup_pe_res(pe,
3093 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3094 }
11685bec
GS		 3095}
3096
98b665da
RC		 3097#ifdef CONFIG_DEBUG_FS
3098static int pnv_pci_diag_data_set(void *data, u64 val)
3099{
3100 struct pci_controller *hose;
3101 struct pnv_phb *phb;
3102 s64 ret;
3103
3104 if (val != 1ULL)
3105 return -EINVAL;
3106
3107 hose = (struct pci_controller *)data;
3108 if (!hose || !hose->private_data)
3109 return -ENODEV;
3110
3111 phb = hose->private_data;
3112
3113 /* Retrieve the diag data from firmware */
3114 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
3115 PNV_PCI_DIAG_BUF_SIZE);
3116 if (ret != OPAL_SUCCESS)
3117 return -EIO;
3118
3119 /* Print the diag data to the kernel log */
3120 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob);
3121 return 0;
3122}
3123
3124DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3125 pnv_pci_diag_data_set, "%llu\n");
3126
3127#endif /* CONFIG_DEBUG_FS */
3128
37c367f2
GS		 3129static void pnv_pci_ioda_create_dbgfs(void)
3130{
3131#ifdef CONFIG_DEBUG_FS
3132 struct pci_controller *hose, *tmp;
3133 struct pnv_phb *phb;
3134 char name[16];
3135
3136 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3137 phb = hose->private_data;
3138
ccd1c191
GS		 3139 /* Notify initialization of PHB done */
3140 phb->initialized = 1;
3141
37c367f2
GS		 3142 sprintf(name, "PCI%04x", hose->global_number);
3143 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
98b665da 3144 if (!phb->dbgfs) {
37c367f2
GS		 3145 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3146 __func__, hose->global_number);
98b665da
RC		 3147 continue;
3148 }
3149
3150 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3151 &pnv_pci_diag_data_fops);
37c367f2
GS		 3152 }
3153#endif /* CONFIG_DEBUG_FS */
3154}
3155
cad5cef6 3156static void pnv_pci_ioda_fixup(void)
fb446ad0
GS		 3157{
3158 pnv_pci_ioda_setup_PEs();
ccd1c191 3159 pnv_pci_ioda_setup_iommu_api();
37c367f2
GS		 3160 pnv_pci_ioda_create_dbgfs();
3161
e9cc17d4 3162#ifdef CONFIG_EEH
e9cc17d4 3163 eeh_init();
dadcd6d6 3164 eeh_addr_cache_build();
e9cc17d4 3165#endif
fb446ad0
GS		 3166}
3167
271fd03a
GS		 3168/*
3169 * Returns the alignment for I/O or memory windows for P2P
3170 * bridges. That actually depends on how PEs are segmented.
3171 * For now, we return I/O or M32 segment size for PE sensitive
3172 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3173 * 1MiB for memory) will be returned.
3174 *
3175 * The current PCI bus might be put into one PE, which was
3176 * create against the parent PCI bridge. For that case, we
3177 * needn't enlarge the alignment so that we can save some
3178 * resources.
3179 */
3180static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3181 unsigned long type)
3182{
3183 struct pci_dev *bridge;
3184 struct pci_controller *hose = pci_bus_to_host(bus);
3185 struct pnv_phb *phb = hose->private_data;
3186 int num_pci_bridges = 0;
3187
3188 bridge = bus->self;
3189 while (bridge) {
3190 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3191 num_pci_bridges++;
3192 if (num_pci_bridges >= 2)
3193 return 1;
3194 }
3195
3196 bridge = bridge->bus->self;
3197 }
3198
5958d19a
BH		 3199 /*
3200 * We fall back to M32 if M64 isn't supported. We enforce the M64
3201 * alignment for any 64-bit resource, PCIe doesn't care and
3202 * bridges only do 64-bit prefetchable anyway.
3203 */
b79331a5 3204 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
262af557 3205 return phb->ioda.m64_segsize;
271fd03a
GS		 3206 if (type & IORESOURCE_MEM)
3207 return phb->ioda.m32_segsize;
3208
3209 return phb->ioda.io_segsize;
3210}
3211
40e2a47e
GS		 3212/*
3213 * We are updating root port or the upstream port of the
3214 * bridge behind the root port with PHB's windows in order
3215 * to accommodate the changes on required resources during
3216 * PCI (slot) hotplug, which is connected to either root
3217 * port or the downstream ports of PCIe switch behind the
3218 * root port.
3219 */
3220static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3221 unsigned long type)
3222{
3223 struct pci_controller *hose = pci_bus_to_host(bus);
3224 struct pnv_phb *phb = hose->private_data;
3225 struct pci_dev *bridge = bus->self;
3226 struct resource *r, *w;
3227 bool msi_region = false;
3228 int i;
3229
3230 /* Check if we need apply fixup to the bridge's windows */
3231 if (!pci_is_root_bus(bridge->bus) &&
3232 !pci_is_root_bus(bridge->bus->self->bus))
3233 return;
3234
3235 /* Fixup the resources */
3236 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3237 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3238 if (!r->flags || !r->parent)
3239 continue;
3240
3241 w = NULL;
3242 if (r->flags & type & IORESOURCE_IO)
3243 w = &hose->io_resource;
5958d19a 3244 else if (pnv_pci_is_m64(phb, r) &&
40e2a47e
GS		 3245 (type & IORESOURCE_PREFETCH) &&
3246 phb->ioda.m64_segsize)
3247 w = &hose->mem_resources[1];
3248 else if (r->flags & type & IORESOURCE_MEM) {
3249 w = &hose->mem_resources[0];
3250 msi_region = true;
3251 }
3252
3253 r->start = w->start;
3254 r->end = w->end;
3255
3256 /* The 64KB 32-bits MSI region shouldn't be included in
3257 * the 32-bits bridge window. Otherwise, we can see strange
3258 * issues. One of them is EEH error observed on Garrison.
3259 *
3260 * Exclude top 1MB region which is the minimal alignment of
3261 * 32-bits bridge window.
3262 */
3263 if (msi_region) {
3264 r->end += 0x10000;
3265 r->end -= 0x100000;
3266 }
3267 }
3268}
3269
ccd1c191
GS		 3270static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3271{
3272 struct pci_controller *hose = pci_bus_to_host(bus);
3273 struct pnv_phb *phb = hose->private_data;
3274 struct pci_dev *bridge = bus->self;
3275 struct pnv_ioda_pe *pe;
3276 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3277
40e2a47e
GS		 3278 /* Extend bridge's windows if necessary */
3279 pnv_pci_fixup_bridge_resources(bus, type);
3280
63803c39
GS		 3281 /* The PE for root bus should be realized before any one else */
3282 if (!phb->ioda.root_pe_populated) {
3283 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3284 if (pe) {
3285 phb->ioda.root_pe_idx = pe->pe_number;
3286 phb->ioda.root_pe_populated = true;
3287 }
3288 }
3289
ccd1c191
GS		 3290 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3291 if (list_empty(&bus->devices))
3292 return;
3293
3294 /* Reserve PEs according to used M64 resources */
3295 if (phb->reserve_m64_pe)
3296 phb->reserve_m64_pe(bus, NULL, all);
3297
3298 /*
3299 * Assign PE. We might run here because of partial hotplug.
3300 * For the case, we just pick up the existing PE and should
3301 * not allocate resources again.
3302 */
3303 pe = pnv_ioda_setup_bus_PE(bus, all);
3304 if (!pe)
3305 return;
3306
3307 pnv_ioda_setup_pe_seg(pe);
3308 switch (phb->type) {
3309 case PNV_PHB_IODA1:
3310 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3311 break;
3312 case PNV_PHB_IODA2:
3313 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3314 break;
3315 default:
1f52f176 3316 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
ccd1c191
GS		 3317 __func__, phb->hose->global_number, phb->type);
3318 }
3319}
3320
5350ab3f
WY		 3321#ifdef CONFIG_PCI_IOV
3322static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3323 int resno)
3324{
ee8222fe
WY		 3325 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3326 struct pnv_phb *phb = hose->private_data;
5350ab3f 3327 struct pci_dn *pdn = pci_get_pdn(pdev);
7fbe7a93 3328 resource_size_t align;
5350ab3f 3329
7fbe7a93
WY		 3330 /*
3331 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3332 * SR-IOV. While from hardware perspective, the range mapped by M64
3333 * BAR should be size aligned.
3334 *
ee8222fe
WY		 3335 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3336 * powernv-specific hardware restriction is gone. But if just use the
3337 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3338 * in one segment of M64 #15, which introduces the PE conflict between
3339 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3340 * m64_segsize.
3341 *
7fbe7a93
WY		 3342 * This function returns the total IOV BAR size if M64 BAR is in
3343 * Shared PE mode or just VF BAR size if not.
ee8222fe
WY		 3344 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3345 * M64 segment size if IOV BAR size is less.
7fbe7a93 3346 */
5350ab3f 3347 align = pci_iov_resource_size(pdev, resno);
7fbe7a93
WY		 3348 if (!pdn->vfs_expanded)
3349 return align;
ee8222fe
WY		 3350 if (pdn->m64_single_mode)
3351 return max(align, (resource_size_t)phb->ioda.m64_segsize);
5350ab3f 3352
7fbe7a93 3353 return pdn->vfs_expanded * align;
5350ab3f
WY		 3354}
3355#endif /* CONFIG_PCI_IOV */
3356
184cd4a3
BH		 3357/* Prevent enabling devices for which we couldn't properly
3358 * assign a PE
3359 */
4361b034 3360bool pnv_pci_enable_device_hook(struct pci_dev *dev)
184cd4a3 3361{
db1266c8
GS		 3362 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3363 struct pnv_phb *phb = hose->private_data;
3364 struct pci_dn *pdn;
184cd4a3 3365
db1266c8
GS		 3366 /* The function is probably called while the PEs have
3367 * not be created yet. For example, resource reassignment
3368 * during PCI probe period. We just skip the check if
3369 * PEs isn't ready.
3370 */
3371 if (!phb->initialized)
c88c2a18 3372 return true;
db1266c8 3373
b72c1f65 3374 pdn = pci_get_pdn(dev);
184cd4a3 3375 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
c88c2a18 3376 return false;
db1266c8 3377
c88c2a18 3378 return true;
184cd4a3
BH		 3379}
3380
c5f7700b
GS		 3381static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3382 int num)
3383{
3384 struct pnv_ioda_pe *pe = container_of(table_group,
3385 struct pnv_ioda_pe, table_group);
3386 struct pnv_phb *phb = pe->phb;
3387 unsigned int idx;
3388 long rc;
3389
3390 pe_info(pe, "Removing DMA window #%d\n", num);
3391 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3392 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3393 continue;
3394
3395 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3396 idx, 0, 0ul, 0ul, 0ul);
3397 if (rc != OPAL_SUCCESS) {
3398 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3399 rc, idx);
3400 return rc;
3401 }
3402
3403 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3404 }
3405
3406 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3407 return OPAL_SUCCESS;
3408}
3409
3410static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3411{
3412 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3413 struct iommu_table *tbl = pe->table_group.tables[0];
3414 int64_t rc;
3415
3416 if (!weight)
3417 return;
3418
3419 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3420 if (rc != OPAL_SUCCESS)
3421 return;
3422
a34ab7c3 3423 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
c5f7700b
GS		 3424 if (pe->table_group.group) {
3425 iommu_group_put(pe->table_group.group);
3426 WARN_ON(pe->table_group.group);
3427 }
3428
3429 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
e5afdf9d 3430 iommu_tce_table_put(tbl);
c5f7700b
GS		 3431}
3432
3433static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3434{
3435 struct iommu_table *tbl = pe->table_group.tables[0];
3436 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3437#ifdef CONFIG_IOMMU_API
3438 int64_t rc;
3439#endif
3440
3441 if (!weight)
3442 return;
3443
3444#ifdef CONFIG_IOMMU_API
3445 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3446 if (rc)
3447 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3448#endif
3449
3450 pnv_pci_ioda2_set_bypass(pe, false);
3451 if (pe->table_group.group) {
3452 iommu_group_put(pe->table_group.group);
3453 WARN_ON(pe->table_group.group);
3454 }
3455
3456 pnv_pci_ioda2_table_free_pages(tbl);
e5afdf9d 3457 iommu_tce_table_put(tbl);
c5f7700b
GS		 3458}
3459
3460static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3461 unsigned short win,
3462 unsigned int *map)
3463{
3464 struct pnv_phb *phb = pe->phb;
3465 int idx;
3466 int64_t rc;
3467
3468 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3469 if (map[idx] != pe->pe_number)
3470 continue;
3471
3472 if (win == OPAL_M64_WINDOW_TYPE)
3473 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3474 phb->ioda.reserved_pe_idx, win,
3475 idx / PNV_IODA1_M64_SEGS,
3476 idx % PNV_IODA1_M64_SEGS);
3477 else
3478 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3479 phb->ioda.reserved_pe_idx, win, 0, idx);
3480
3481 if (rc != OPAL_SUCCESS)
3482 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3483 rc, win, idx);
3484
3485 map[idx] = IODA_INVALID_PE;
3486 }
3487}
3488
3489static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3490{
3491 struct pnv_phb *phb = pe->phb;
3492
3493 if (phb->type == PNV_PHB_IODA1) {
3494 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3495 phb->ioda.io_segmap);
3496 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3497 phb->ioda.m32_segmap);
3498 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3499 phb->ioda.m64_segmap);
3500 } else if (phb->type == PNV_PHB_IODA2) {
3501 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3502 phb->ioda.m32_segmap);
3503 }
3504}
3505
3506static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3507{
3508 struct pnv_phb *phb = pe->phb;
3509 struct pnv_ioda_pe *slave, *tmp;
3510
c5f7700b
GS		 3511 list_del(&pe->list);
3512 switch (phb->type) {
3513 case PNV_PHB_IODA1:
3514 pnv_pci_ioda1_release_pe_dma(pe);
3515 break;
3516 case PNV_PHB_IODA2:
3517 pnv_pci_ioda2_release_pe_dma(pe);
3518 break;
3519 default:
3520 WARN_ON(1);
3521 }
3522
3523 pnv_ioda_release_pe_seg(pe);
3524 pnv_ioda_deconfigure_pe(pe->phb, pe);
b314427a
GS		 3525
3526 /* Release slave PEs in the compound PE */
3527 if (pe->flags & PNV_IODA_PE_MASTER) {
3528 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3529 list_del(&slave->list);
3530 pnv_ioda_free_pe(slave);
3531 }
3532 }
3533
6eaed166
GS		 3534 /*
3535 * The PE for root bus can be removed because of hotplug in EEH
3536 * recovery for fenced PHB error. We need to mark the PE dead so
3537 * that it can be populated again in PCI hot add path. The PE
3538 * shouldn't be destroyed as it's the global reserved resource.
3539 */
3540 if (phb->ioda.root_pe_populated &&
3541 phb->ioda.root_pe_idx == pe->pe_number)
3542 phb->ioda.root_pe_populated = false;
3543 else
3544 pnv_ioda_free_pe(pe);
c5f7700b
GS		 3545}
3546
3547static void pnv_pci_release_device(struct pci_dev *pdev)
3548{
3549 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3550 struct pnv_phb *phb = hose->private_data;
3551 struct pci_dn *pdn = pci_get_pdn(pdev);
3552 struct pnv_ioda_pe *pe;
3553
3554 if (pdev->is_virtfn)
3555 return;
3556
3557 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3558 return;
3559
29bf282d
GS		 3560 /*
3561 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3562 * isn't removed and added afterwards in this scenario. We should
3563 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3564 * device count is decreased on removing devices while failing to
3565 * be increased on adding devices. It leads to unbalanced PE's device
3566 * count and eventually make normal PCI hotplug path broken.
3567 */
c5f7700b 3568 pe = &phb->ioda.pe_array[pdn->pe_number];
29bf282d
GS		 3569 pdn->pe_number = IODA_INVALID_PE;
3570
c5f7700b
GS		 3571 WARN_ON(--pe->device_count < 0);
3572 if (pe->device_count == 0)
3573 pnv_ioda_release_pe(pe);
3574}
3575
7a8e6bbf 3576static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
73ed148a 3577{
7a8e6bbf
MN		 3578 struct pnv_phb *phb = hose->private_data;
3579
d1a85eee 3580 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
73ed148a
BH		 3581 OPAL_ASSERT_RESET);
3582}
3583
92ae0353 3584static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
cb4224c5
GS		 3585 .dma_dev_setup = pnv_pci_dma_dev_setup,
3586 .dma_bus_setup = pnv_pci_dma_bus_setup,
92ae0353 3587#ifdef CONFIG_PCI_MSI
cb4224c5
GS		 3588 .setup_msi_irqs = pnv_setup_msi_irqs,
3589 .teardown_msi_irqs = pnv_teardown_msi_irqs,
92ae0353 3590#endif
cb4224c5 3591 .enable_device_hook = pnv_pci_enable_device_hook,
c5f7700b 3592 .release_device = pnv_pci_release_device,
cb4224c5 3593 .window_alignment = pnv_pci_window_alignment,
ccd1c191 3594 .setup_bridge = pnv_pci_setup_bridge,
cb4224c5
GS		 3595 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3596 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3597 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3598 .shutdown = pnv_pci_ioda_shutdown,
92ae0353
DA		 3599};
3600
f9f83456
AK		 3601static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3602{
3603 dev_err_once(&npdev->dev,
3604 "%s operation unsupported for NVLink devices\n",
3605 __func__);
3606 return -EPERM;
3607}
3608
5d2aa710 3609static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
cb4224c5 3610 .dma_dev_setup = pnv_pci_dma_dev_setup,
5d2aa710 3611#ifdef CONFIG_PCI_MSI
cb4224c5
GS		 3612 .setup_msi_irqs = pnv_setup_msi_irqs,
3613 .teardown_msi_irqs = pnv_teardown_msi_irqs,
5d2aa710 3614#endif
cb4224c5
GS		 3615 .enable_device_hook = pnv_pci_enable_device_hook,
3616 .window_alignment = pnv_pci_window_alignment,
3617 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3618 .dma_set_mask = pnv_npu_dma_set_mask,
3619 .shutdown = pnv_pci_ioda_shutdown,
5d2aa710
AP		 3620};
3621
4361b034
IM		 3622#ifdef CONFIG_CXL_BASE
3623const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3624 .dma_dev_setup = pnv_pci_dma_dev_setup,
3625 .dma_bus_setup = pnv_pci_dma_bus_setup,
a2f67d5e
IM		 3626#ifdef CONFIG_PCI_MSI
3627 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
3628 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
3629#endif
4361b034
IM		 3630 .enable_device_hook = pnv_cxl_enable_device_hook,
3631 .disable_device = pnv_cxl_disable_device,
3632 .release_device = pnv_pci_release_device,
3633 .window_alignment = pnv_pci_window_alignment,
3634 .setup_bridge = pnv_pci_setup_bridge,
3635 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3636 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3637 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3638 .shutdown = pnv_pci_ioda_shutdown,
3639};
3640#endif
3641
e51df2c1
AB		 3642static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3643 u64 hub_id, int ioda_type)
184cd4a3
BH		 3644{
3645 struct pci_controller *hose;
184cd4a3 3646 struct pnv_phb *phb;
2b923ed1
GS		 3647 unsigned long size, m64map_off, m32map_off, pemap_off;
3648 unsigned long iomap_off = 0, dma32map_off = 0;
fd141d1a 3649 struct resource r;
c681b93c 3650 const __be64 *prop64;
3a1a4661 3651 const __be32 *prop32;
f1b7cc3e 3652 int len;
3fa23ff8 3653 unsigned int segno;
184cd4a3
BH		 3654 u64 phb_id;
3655 void *aux;
3656 long rc;
3657
08a45b32
BH		 3658 if (!of_device_is_available(np))
3659 return;
3660
9497a1c1
GS		 3661 pr_info("Initializing %s PHB (%s)\n",
3662 pnv_phb_names[ioda_type], of_node_full_name(np));
184cd4a3
BH		 3663
3664 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3665 if (!prop64) {
3666 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3667 return;
3668 }
3669 phb_id = be64_to_cpup(prop64);
3670 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3671
e39f223f 3672 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
58d714ec
GS		 3673
3674 /* Allocate PCI controller */
58d714ec
GS		 3675 phb->hose = hose = pcibios_alloc_controller(np);
3676 if (!phb->hose) {
3677 pr_err(" Can't allocate PCI controller for %s\n",
184cd4a3 3678 np->full_name);
e39f223f 3679 memblock_free(__pa(phb), sizeof(struct pnv_phb));
184cd4a3
BH		 3680 return;
3681 }
3682
3683 spin_lock_init(&phb->lock);
f1b7cc3e
GS		 3684 prop32 = of_get_property(np, "bus-range", &len);
3685 if (prop32 && len == 8) {
3a1a4661
BH		 3686 hose->first_busno = be32_to_cpu(prop32[0]);
3687 hose->last_busno = be32_to_cpu(prop32[1]);
f1b7cc3e
GS		 3688 } else {
3689 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3690 hose->first_busno = 0;
3691 hose->last_busno = 0xff;
3692 }
184cd4a3 3693 hose->private_data = phb;
e9cc17d4 3694 phb->hub_id = hub_id;
184cd4a3 3695 phb->opal_id = phb_id;
aa0c033f 3696 phb->type = ioda_type;
781a868f 3697 mutex_init(&phb->ioda.pe_alloc_mutex);
184cd4a3 3698
cee72d5b
BH		 3699 /* Detect specific models for error handling */
3700 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3701 phb->model = PNV_PHB_MODEL_P7IOC;
f3d40c25 3702 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
aa0c033f 3703 phb->model = PNV_PHB_MODEL_PHB3;
5d2aa710
AP		 3704 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3705 phb->model = PNV_PHB_MODEL_NPU;
616badd2
AP		 3706 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3707 phb->model = PNV_PHB_MODEL_NPU2;
cee72d5b
BH		 3708 else
3709 phb->model = PNV_PHB_MODEL_UNKNOWN;
3710
aa0c033f 3711 /* Parse 32-bit and IO ranges (if any) */
2f1ec02e 3712 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
184cd4a3 3713
aa0c033f 3714 /* Get registers */
fd141d1a
BH		 3715 if (!of_address_to_resource(np, 0, &r)) {
3716 phb->regs_phys = r.start;
3717 phb->regs = ioremap(r.start, resource_size(&r));
3718 if (phb->regs == NULL)
3719 pr_err(" Failed to map registers !\n");
3720 }
577c8c88 3721
184cd4a3 3722 /* Initialize more IODA stuff */
92b8f137 3723 phb->ioda.total_pe_num = 1;
aa0c033f 3724 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
36954dc7 3725 if (prop32)
92b8f137 3726 phb->ioda.total_pe_num = be32_to_cpup(prop32);
36954dc7
GS		 3727 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3728 if (prop32)
92b8f137 3729 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
262af557 3730
c127562a
GS		 3731 /* Invalidate RID to PE# mapping */
3732 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3733 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3734
262af557
GC		 3735 /* Parse 64-bit MMIO range */
3736 pnv_ioda_parse_m64_window(phb);
3737
184cd4a3 3738 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
aa0c033f 3739 /* FW Has already off top 64k of M32 space (MSI space) */
184cd4a3
BH		 3740 phb->ioda.m32_size += 0x10000;
3741
92b8f137 3742 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3fd47f06 3743 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
184cd4a3 3744 phb->ioda.io_size = hose->pci_io_size;
92b8f137 3745 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
184cd4a3
BH		 3746 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3747
2b923ed1
GS		 3748 /* Calculate how many 32-bit TCE segments we have */
3749 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3750 PNV_IODA1_DMA32_SEGSIZE;
3751
c35d2a8c 3752 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
92a86756
AK		 3753 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3754 sizeof(unsigned long));
93289d8c
GS		 3755 m64map_off = size;
3756 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
184cd4a3 3757 m32map_off = size;
92b8f137 3758 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
c35d2a8c
GS		 3759 if (phb->type == PNV_PHB_IODA1) {
3760 iomap_off = size;
92b8f137 3761 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
2b923ed1
GS		 3762 dma32map_off = size;
3763 size += phb->ioda.dma32_count *
3764 sizeof(phb->ioda.dma32_segmap[0]);
c35d2a8c 3765 }
184cd4a3 3766 pemap_off = size;
92b8f137 3767 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
e39f223f 3768 aux = memblock_virt_alloc(size, 0);
184cd4a3 3769 phb->ioda.pe_alloc = aux;
93289d8c 3770 phb->ioda.m64_segmap = aux + m64map_off;
184cd4a3 3771 phb->ioda.m32_segmap = aux + m32map_off;
93289d8c
GS		 3772 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3773 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3fa23ff8 3774 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
93289d8c 3775 }
3fa23ff8 3776 if (phb->type == PNV_PHB_IODA1) {
c35d2a8c 3777 phb->ioda.io_segmap = aux + iomap_off;
3fa23ff8
GS		 3778 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3779 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
2b923ed1
GS		 3780
3781 phb->ioda.dma32_segmap = aux + dma32map_off;
3782 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3783 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3fa23ff8 3784 }
184cd4a3 3785 phb->ioda.pe_array = aux + pemap_off;
63803c39
GS		 3786
3787 /*
3788 * Choose PE number for root bus, which shouldn't have
3789 * M64 resources consumed by its child devices. To pick
3790 * the PE number adjacent to the reserved one if possible.
3791 */
3792 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3793 if (phb->ioda.reserved_pe_idx == 0) {
3794 phb->ioda.root_pe_idx = 1;
3795 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3796 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3797 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3798 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3799 } else {
3800 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3801 }
184cd4a3
BH		 3802
3803 INIT_LIST_HEAD(&phb->ioda.pe_list);
781a868f 3804 mutex_init(&phb->ioda.pe_list_mutex);
184cd4a3
BH		 3805
3806 /* Calculate how many 32-bit TCE segments we have */
2b923ed1 3807 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
acce971c 3808 PNV_IODA1_DMA32_SEGSIZE;
184cd4a3 3809
aa0c033f 3810#if 0 /* We should really do that ... */
184cd4a3
BH		 3811 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3812 window_type,
3813 window_num,
3814 starting_real_address,
3815 starting_pci_address,
3816 segment_size);
3817#endif
3818
262af557 3819 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
92b8f137 3820 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
262af557
GC		 3821 phb->ioda.m32_size, phb->ioda.m32_segsize);
3822 if (phb->ioda.m64_size)
3823 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3824 phb->ioda.m64_size, phb->ioda.m64_segsize);
3825 if (phb->ioda.io_size)
3826 pr_info(" IO: 0x%x [segment=0x%x]\n",
3827 phb->ioda.io_size, phb->ioda.io_segsize);
3828
184cd4a3 3829
184cd4a3 3830 phb->hose->ops = &pnv_pci_ops;
49dec922
GS		 3831 phb->get_pe_state = pnv_ioda_get_pe_state;
3832 phb->freeze_pe = pnv_ioda_freeze_pe;
3833 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
184cd4a3 3834
184cd4a3
BH		 3835 /* Setup MSI support */
3836 pnv_pci_init_ioda_msis(phb);
3837
c40a4210
GS		 3838 /*
3839 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3840 * to let the PCI core do resource assignment. It's supposed
3841 * that the PCI core will do correct I/O and MMIO alignment
3842 * for the P2P bridge bars so that each PCI bus (excluding
3843 * the child P2P bridges) can form individual PE.
184cd4a3 3844 */
fb446ad0 3845 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
5d2aa710 3846
f9f83456 3847 if (phb->type == PNV_PHB_NPU) {
5d2aa710 3848 hose->controller_ops = pnv_npu_ioda_controller_ops;
f9f83456
AK		 3849 } else {
3850 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
5d2aa710 3851 hose->controller_ops = pnv_pci_ioda_controller_ops;
f9f83456 3852 }
ad30cb99 3853
6e628c7d
WY		 3854#ifdef CONFIG_PCI_IOV
3855 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
5350ab3f 3856 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
ad30cb99
ME		 3857#endif
3858
c40a4210 3859 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
184cd4a3
BH		 3860
3861 /* Reset IODA tables to a clean state */
d1a85eee 3862 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
184cd4a3 3863 if (rc)
f11fe552 3864 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
361f2a2a 3865
6060e9ea
AD		 3866 /*
3867 * If we're running in kdump kernel, the previous kernel never
361f2a2a
GS		 3868 * shutdown PCI devices correctly. We already got IODA table
3869 * cleaned out. So we have to issue PHB reset to stop all PCI
6060e9ea 3870 * transactions from previous kernel.
361f2a2a
GS		 3871 */
3872 if (is_kdump_kernel()) {
3873 pr_info(" Issue PHB reset ...\n");
cadf364d
GS		 3874 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3875 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
361f2a2a 3876 }
262af557 3877
9e9e8935
GS		 3878 /* Remove M64 resource if we can't configure it successfully */
3879 if (!phb->init_m64 || phb->init_m64(phb))
262af557 3880 hose->mem_resources[1].flags = 0;
aa0c033f
GS		 3881}
3882
67975005 3883void __init pnv_pci_init_ioda2_phb(struct device_node *np)
aa0c033f 3884{
e9cc17d4 3885 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
184cd4a3
BH		 3886}
3887
5d2aa710
AP		 3888void __init pnv_pci_init_npu_phb(struct device_node *np)
3889{
3890 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
3891}
3892
184cd4a3
BH		 3893void __init pnv_pci_init_ioda_hub(struct device_node *np)
3894{
3895 struct device_node *phbn;
c681b93c 3896 const __be64 *prop64;
184cd4a3
BH		 3897 u64 hub_id;
3898
3899 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3900
3901 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3902 if (!prop64) {
3903 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3904 return;
3905 }
3906 hub_id = be64_to_cpup(prop64);
3907 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3908
3909 /* Count child PHBs */
3910 for_each_child_of_node(np, phbn) {
3911 /* Look for IODA1 PHBs */
3912 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
e9cc17d4 3913 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
184cd4a3
BH		 3914 }
3915}
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