]>
Commit | Line | Data |
---|---|---|
184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
361f2a2a | 16 | #include <linux/crash_dump.h> |
184cd4a3 BH |
17 | #include <linux/delay.h> |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/msi.h> | |
cd15b048 | 24 | #include <linux/memblock.h> |
ac9a5889 | 25 | #include <linux/iommu.h> |
e57080f1 | 26 | #include <linux/rculist.h> |
4793d65d | 27 | #include <linux/sizes.h> |
184cd4a3 BH |
28 | |
29 | #include <asm/sections.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/prom.h> | |
32 | #include <asm/pci-bridge.h> | |
33 | #include <asm/machdep.h> | |
fb1b55d6 | 34 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
35 | #include <asm/ppc-pci.h> |
36 | #include <asm/opal.h> | |
37 | #include <asm/iommu.h> | |
38 | #include <asm/tce.h> | |
137436c9 | 39 | #include <asm/xics.h> |
7644d581 | 40 | #include <asm/debugfs.h> |
262af557 | 41 | #include <asm/firmware.h> |
80c49c7e | 42 | #include <asm/pnv-pci.h> |
aca6913f | 43 | #include <asm/mmzone.h> |
80c49c7e | 44 | |
ec249dd8 | 45 | #include <misc/cxl-base.h> |
184cd4a3 BH |
46 | |
47 | #include "powernv.h" | |
48 | #include "pci.h" | |
49 | ||
99451551 GS |
50 | #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ |
51 | #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ | |
acce971c | 52 | #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 |
781a868f | 53 | |
bbb845c4 AK |
54 | #define POWERNV_IOMMU_DEFAULT_LEVELS 1 |
55 | #define POWERNV_IOMMU_MAX_LEVELS 5 | |
56 | ||
9497a1c1 | 57 | static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; |
aca6913f AK |
58 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); |
59 | ||
7d623e42 | 60 | void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
6d31c2fa JP |
61 | const char *fmt, ...) |
62 | { | |
63 | struct va_format vaf; | |
64 | va_list args; | |
65 | char pfix[32]; | |
66 | ||
67 | va_start(args, fmt); | |
68 | ||
69 | vaf.fmt = fmt; | |
70 | vaf.va = &args; | |
71 | ||
781a868f | 72 | if (pe->flags & PNV_IODA_PE_DEV) |
6d31c2fa | 73 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
781a868f | 74 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
6d31c2fa JP |
75 | sprintf(pfix, "%04x:%02x ", |
76 | pci_domain_nr(pe->pbus), pe->pbus->number); | |
781a868f WY |
77 | #ifdef CONFIG_PCI_IOV |
78 | else if (pe->flags & PNV_IODA_PE_VF) | |
79 | sprintf(pfix, "%04x:%02x:%2x.%d", | |
80 | pci_domain_nr(pe->parent_dev->bus), | |
81 | (pe->rid & 0xff00) >> 8, | |
82 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); | |
83 | #endif /* CONFIG_PCI_IOV*/ | |
6d31c2fa | 84 | |
1f52f176 | 85 | printk("%spci %s: [PE# %.2x] %pV", |
6d31c2fa JP |
86 | level, pfix, pe->pe_number, &vaf); |
87 | ||
88 | va_end(args); | |
89 | } | |
184cd4a3 | 90 | |
4e287840 TLSC |
91 | static bool pnv_iommu_bypass_disabled __read_mostly; |
92 | ||
93 | static int __init iommu_setup(char *str) | |
94 | { | |
95 | if (!str) | |
96 | return -EINVAL; | |
97 | ||
98 | while (*str) { | |
99 | if (!strncmp(str, "nobypass", 8)) { | |
100 | pnv_iommu_bypass_disabled = true; | |
101 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); | |
102 | break; | |
103 | } | |
104 | str += strcspn(str, ","); | |
105 | if (*str == ',') | |
106 | str++; | |
107 | } | |
108 | ||
109 | return 0; | |
110 | } | |
111 | early_param("iommu", iommu_setup); | |
112 | ||
5958d19a | 113 | static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) |
262af557 | 114 | { |
5958d19a BH |
115 | /* |
116 | * WARNING: We cannot rely on the resource flags. The Linux PCI | |
117 | * allocation code sometimes decides to put a 64-bit prefetchable | |
118 | * BAR in the 32-bit window, so we have to compare the addresses. | |
119 | * | |
120 | * For simplicity we only test resource start. | |
121 | */ | |
122 | return (r->start >= phb->ioda.m64_base && | |
123 | r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); | |
262af557 GC |
124 | } |
125 | ||
b79331a5 RC |
126 | static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) |
127 | { | |
128 | unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
129 | ||
130 | return (resource_flags & flags) == flags; | |
131 | } | |
132 | ||
1e916772 GS |
133 | static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) |
134 | { | |
313483dd GS |
135 | s64 rc; |
136 | ||
1e916772 GS |
137 | phb->ioda.pe_array[pe_no].phb = phb; |
138 | phb->ioda.pe_array[pe_no].pe_number = pe_no; | |
139 | ||
313483dd GS |
140 | /* |
141 | * Clear the PE frozen state as it might be put into frozen state | |
142 | * in the last PCI remove path. It's not harmful to do so when the | |
143 | * PE is already in unfrozen state. | |
144 | */ | |
145 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, | |
146 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
d4791db5 | 147 | if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) |
1f52f176 | 148 | pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", |
313483dd GS |
149 | __func__, rc, phb->hose->global_number, pe_no); |
150 | ||
1e916772 GS |
151 | return &phb->ioda.pe_array[pe_no]; |
152 | } | |
153 | ||
4b82ab18 GS |
154 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
155 | { | |
92b8f137 | 156 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { |
1f52f176 | 157 | pr_warn("%s: Invalid PE %x on PHB#%x\n", |
4b82ab18 GS |
158 | __func__, pe_no, phb->hose->global_number); |
159 | return; | |
160 | } | |
161 | ||
e9dc4d7f | 162 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) |
1f52f176 | 163 | pr_debug("%s: PE %x was reserved on PHB#%x\n", |
e9dc4d7f | 164 | __func__, pe_no, phb->hose->global_number); |
4b82ab18 | 165 | |
1e916772 | 166 | pnv_ioda_init_pe(phb, pe_no); |
4b82ab18 GS |
167 | } |
168 | ||
1e916772 | 169 | static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 | 170 | { |
60964816 | 171 | long pe; |
184cd4a3 | 172 | |
9fcd6f4a GS |
173 | for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { |
174 | if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) | |
175 | return pnv_ioda_init_pe(phb, pe); | |
176 | } | |
184cd4a3 | 177 | |
9fcd6f4a | 178 | return NULL; |
184cd4a3 BH |
179 | } |
180 | ||
1e916772 | 181 | static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) |
184cd4a3 | 182 | { |
1e916772 | 183 | struct pnv_phb *phb = pe->phb; |
caa58f80 | 184 | unsigned int pe_num = pe->pe_number; |
1e916772 GS |
185 | |
186 | WARN_ON(pe->pdev); | |
184cd4a3 | 187 | |
1e916772 | 188 | memset(pe, 0, sizeof(struct pnv_ioda_pe)); |
caa58f80 | 189 | clear_bit(pe_num, phb->ioda.pe_alloc); |
184cd4a3 BH |
190 | } |
191 | ||
262af557 GC |
192 | /* The default M64 BAR is shared by all PEs */ |
193 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) | |
194 | { | |
195 | const char *desc; | |
196 | struct resource *r; | |
197 | s64 rc; | |
198 | ||
199 | /* Configure the default M64 BAR */ | |
200 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
201 | OPAL_M64_WINDOW_TYPE, | |
202 | phb->ioda.m64_bar_idx, | |
203 | phb->ioda.m64_base, | |
204 | 0, /* unused */ | |
205 | phb->ioda.m64_size); | |
206 | if (rc != OPAL_SUCCESS) { | |
207 | desc = "configuring"; | |
208 | goto fail; | |
209 | } | |
210 | ||
211 | /* Enable the default M64 BAR */ | |
212 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
213 | OPAL_M64_WINDOW_TYPE, | |
214 | phb->ioda.m64_bar_idx, | |
215 | OPAL_ENABLE_M64_SPLIT); | |
216 | if (rc != OPAL_SUCCESS) { | |
217 | desc = "enabling"; | |
218 | goto fail; | |
219 | } | |
220 | ||
262af557 | 221 | /* |
63803c39 GS |
222 | * Exclude the segments for reserved and root bus PE, which |
223 | * are first or last two PEs. | |
262af557 GC |
224 | */ |
225 | r = &phb->hose->mem_resources[1]; | |
92b8f137 | 226 | if (phb->ioda.reserved_pe_idx == 0) |
63803c39 | 227 | r->start += (2 * phb->ioda.m64_segsize); |
92b8f137 | 228 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
63803c39 | 229 | r->end -= (2 * phb->ioda.m64_segsize); |
262af557 | 230 | else |
1f52f176 | 231 | pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", |
92b8f137 | 232 | phb->ioda.reserved_pe_idx); |
262af557 GC |
233 | |
234 | return 0; | |
235 | ||
236 | fail: | |
237 | pr_warn(" Failure %lld %s M64 BAR#%d\n", | |
238 | rc, desc, phb->ioda.m64_bar_idx); | |
239 | opal_pci_phb_mmio_enable(phb->opal_id, | |
240 | OPAL_M64_WINDOW_TYPE, | |
241 | phb->ioda.m64_bar_idx, | |
242 | OPAL_DISABLE_M64); | |
243 | return -EIO; | |
244 | } | |
245 | ||
c430670a | 246 | static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, |
96a2f92b | 247 | unsigned long *pe_bitmap) |
262af557 | 248 | { |
96a2f92b GS |
249 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
250 | struct pnv_phb *phb = hose->private_data; | |
262af557 | 251 | struct resource *r; |
96a2f92b GS |
252 | resource_size_t base, sgsz, start, end; |
253 | int segno, i; | |
254 | ||
255 | base = phb->ioda.m64_base; | |
256 | sgsz = phb->ioda.m64_segsize; | |
257 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
258 | r = &pdev->resource[i]; | |
5958d19a | 259 | if (!r->parent || !pnv_pci_is_m64(phb, r)) |
96a2f92b | 260 | continue; |
262af557 | 261 | |
96a2f92b GS |
262 | start = _ALIGN_DOWN(r->start - base, sgsz); |
263 | end = _ALIGN_UP(r->end - base, sgsz); | |
264 | for (segno = start / sgsz; segno < end / sgsz; segno++) { | |
265 | if (pe_bitmap) | |
266 | set_bit(segno, pe_bitmap); | |
267 | else | |
268 | pnv_ioda_reserve_pe(phb, segno); | |
262af557 GC |
269 | } |
270 | } | |
271 | } | |
272 | ||
99451551 GS |
273 | static int pnv_ioda1_init_m64(struct pnv_phb *phb) |
274 | { | |
275 | struct resource *r; | |
276 | int index; | |
277 | ||
278 | /* | |
279 | * There are 16 M64 BARs, each of which has 8 segments. So | |
280 | * there are as many M64 segments as the maximum number of | |
281 | * PEs, which is 128. | |
282 | */ | |
283 | for (index = 0; index < PNV_IODA1_M64_NUM; index++) { | |
284 | unsigned long base, segsz = phb->ioda.m64_segsize; | |
285 | int64_t rc; | |
286 | ||
287 | base = phb->ioda.m64_base + | |
288 | index * PNV_IODA1_M64_SEGS * segsz; | |
289 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
290 | OPAL_M64_WINDOW_TYPE, index, base, 0, | |
291 | PNV_IODA1_M64_SEGS * segsz); | |
292 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 293 | pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", |
99451551 GS |
294 | rc, phb->hose->global_number, index); |
295 | goto fail; | |
296 | } | |
297 | ||
298 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
299 | OPAL_M64_WINDOW_TYPE, index, | |
300 | OPAL_ENABLE_M64_SPLIT); | |
301 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 302 | pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", |
99451551 GS |
303 | rc, phb->hose->global_number, index); |
304 | goto fail; | |
305 | } | |
306 | } | |
307 | ||
308 | /* | |
63803c39 GS |
309 | * Exclude the segments for reserved and root bus PE, which |
310 | * are first or last two PEs. | |
99451551 GS |
311 | */ |
312 | r = &phb->hose->mem_resources[1]; | |
313 | if (phb->ioda.reserved_pe_idx == 0) | |
63803c39 | 314 | r->start += (2 * phb->ioda.m64_segsize); |
99451551 | 315 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
63803c39 | 316 | r->end -= (2 * phb->ioda.m64_segsize); |
99451551 | 317 | else |
1f52f176 | 318 | WARN(1, "Wrong reserved PE#%x on PHB#%x\n", |
99451551 GS |
319 | phb->ioda.reserved_pe_idx, phb->hose->global_number); |
320 | ||
321 | return 0; | |
322 | ||
323 | fail: | |
324 | for ( ; index >= 0; index--) | |
325 | opal_pci_phb_mmio_enable(phb->opal_id, | |
326 | OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); | |
327 | ||
328 | return -EIO; | |
329 | } | |
330 | ||
c430670a GS |
331 | static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, |
332 | unsigned long *pe_bitmap, | |
333 | bool all) | |
262af557 | 334 | { |
262af557 | 335 | struct pci_dev *pdev; |
96a2f92b GS |
336 | |
337 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
c430670a | 338 | pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); |
96a2f92b GS |
339 | |
340 | if (all && pdev->subordinate) | |
c430670a GS |
341 | pnv_ioda_reserve_m64_pe(pdev->subordinate, |
342 | pe_bitmap, all); | |
96a2f92b GS |
343 | } |
344 | } | |
345 | ||
1e916772 | 346 | static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) |
262af557 | 347 | { |
26ba248d GS |
348 | struct pci_controller *hose = pci_bus_to_host(bus); |
349 | struct pnv_phb *phb = hose->private_data; | |
262af557 GC |
350 | struct pnv_ioda_pe *master_pe, *pe; |
351 | unsigned long size, *pe_alloc; | |
26ba248d | 352 | int i; |
262af557 GC |
353 | |
354 | /* Root bus shouldn't use M64 */ | |
355 | if (pci_is_root_bus(bus)) | |
1e916772 | 356 | return NULL; |
262af557 | 357 | |
262af557 | 358 | /* Allocate bitmap */ |
92b8f137 | 359 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
262af557 GC |
360 | pe_alloc = kzalloc(size, GFP_KERNEL); |
361 | if (!pe_alloc) { | |
362 | pr_warn("%s: Out of memory !\n", | |
363 | __func__); | |
1e916772 | 364 | return NULL; |
262af557 GC |
365 | } |
366 | ||
26ba248d | 367 | /* Figure out reserved PE numbers by the PE */ |
c430670a | 368 | pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); |
262af557 GC |
369 | |
370 | /* | |
371 | * the current bus might not own M64 window and that's all | |
372 | * contributed by its child buses. For the case, we needn't | |
373 | * pick M64 dependent PE#. | |
374 | */ | |
92b8f137 | 375 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { |
262af557 | 376 | kfree(pe_alloc); |
1e916772 | 377 | return NULL; |
262af557 GC |
378 | } |
379 | ||
380 | /* | |
381 | * Figure out the master PE and put all slave PEs to master | |
382 | * PE's list to form compound PE. | |
383 | */ | |
262af557 GC |
384 | master_pe = NULL; |
385 | i = -1; | |
92b8f137 GS |
386 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < |
387 | phb->ioda.total_pe_num) { | |
262af557 | 388 | pe = &phb->ioda.pe_array[i]; |
262af557 | 389 | |
93289d8c | 390 | phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; |
262af557 GC |
391 | if (!master_pe) { |
392 | pe->flags |= PNV_IODA_PE_MASTER; | |
393 | INIT_LIST_HEAD(&pe->slaves); | |
394 | master_pe = pe; | |
395 | } else { | |
396 | pe->flags |= PNV_IODA_PE_SLAVE; | |
397 | pe->master = master_pe; | |
398 | list_add_tail(&pe->list, &master_pe->slaves); | |
399 | } | |
99451551 GS |
400 | |
401 | /* | |
402 | * P7IOC supports M64DT, which helps mapping M64 segment | |
403 | * to one particular PE#. However, PHB3 has fixed mapping | |
404 | * between M64 segment and PE#. In order to have same logic | |
405 | * for P7IOC and PHB3, we enforce fixed mapping between M64 | |
406 | * segment and PE# on P7IOC. | |
407 | */ | |
408 | if (phb->type == PNV_PHB_IODA1) { | |
409 | int64_t rc; | |
410 | ||
411 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
412 | pe->pe_number, OPAL_M64_WINDOW_TYPE, | |
413 | pe->pe_number / PNV_IODA1_M64_SEGS, | |
414 | pe->pe_number % PNV_IODA1_M64_SEGS); | |
415 | if (rc != OPAL_SUCCESS) | |
1f52f176 | 416 | pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", |
99451551 GS |
417 | __func__, rc, phb->hose->global_number, |
418 | pe->pe_number); | |
419 | } | |
262af557 GC |
420 | } |
421 | ||
422 | kfree(pe_alloc); | |
1e916772 | 423 | return master_pe; |
262af557 GC |
424 | } |
425 | ||
426 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) | |
427 | { | |
428 | struct pci_controller *hose = phb->hose; | |
429 | struct device_node *dn = hose->dn; | |
430 | struct resource *res; | |
a1339faf | 431 | u32 m64_range[2], i; |
0e7736c6 | 432 | const __be32 *r; |
262af557 GC |
433 | u64 pci_addr; |
434 | ||
99451551 | 435 | if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { |
1665c4a8 GS |
436 | pr_info(" Not support M64 window\n"); |
437 | return; | |
438 | } | |
439 | ||
e4d54f71 | 440 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
262af557 GC |
441 | pr_info(" Firmware too old to support M64 window\n"); |
442 | return; | |
443 | } | |
444 | ||
445 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); | |
446 | if (!r) { | |
b7c670d6 RH |
447 | pr_info(" No <ibm,opal-m64-window> on %pOF\n", |
448 | dn); | |
262af557 GC |
449 | return; |
450 | } | |
451 | ||
a1339faf BH |
452 | /* |
453 | * Find the available M64 BAR range and pickup the last one for | |
454 | * covering the whole 64-bits space. We support only one range. | |
455 | */ | |
456 | if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", | |
457 | m64_range, 2)) { | |
458 | /* In absence of the property, assume 0..15 */ | |
459 | m64_range[0] = 0; | |
460 | m64_range[1] = 16; | |
461 | } | |
462 | /* We only support 64 bits in our allocator */ | |
463 | if (m64_range[1] > 63) { | |
464 | pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", | |
465 | __func__, m64_range[1], phb->hose->global_number); | |
466 | m64_range[1] = 63; | |
467 | } | |
468 | /* Empty range, no m64 */ | |
469 | if (m64_range[1] <= m64_range[0]) { | |
470 | pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", | |
471 | __func__, phb->hose->global_number); | |
472 | return; | |
473 | } | |
474 | ||
475 | /* Configure M64 informations */ | |
262af557 | 476 | res = &hose->mem_resources[1]; |
e80c4e7c | 477 | res->name = dn->full_name; |
262af557 GC |
478 | res->start = of_translate_address(dn, r + 2); |
479 | res->end = res->start + of_read_number(r + 4, 2) - 1; | |
480 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
481 | pci_addr = of_read_number(r, 2); | |
482 | hose->mem_offset[1] = res->start - pci_addr; | |
483 | ||
484 | phb->ioda.m64_size = resource_size(res); | |
92b8f137 | 485 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; |
262af557 GC |
486 | phb->ioda.m64_base = pci_addr; |
487 | ||
a1339faf BH |
488 | /* This lines up nicely with the display from processing OF ranges */ |
489 | pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", | |
490 | res->start, res->end, pci_addr, m64_range[0], | |
491 | m64_range[0] + m64_range[1] - 1); | |
492 | ||
493 | /* Mark all M64 used up by default */ | |
494 | phb->ioda.m64_bar_alloc = (unsigned long)-1; | |
e9863e68 | 495 | |
262af557 | 496 | /* Use last M64 BAR to cover M64 window */ |
a1339faf BH |
497 | m64_range[1]--; |
498 | phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; | |
499 | ||
500 | pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); | |
501 | ||
502 | /* Mark remaining ones free */ | |
503 | for (i = m64_range[0]; i < m64_range[1]; i++) | |
504 | clear_bit(i, &phb->ioda.m64_bar_alloc); | |
505 | ||
506 | /* | |
507 | * Setup init functions for M64 based on IODA version, IODA3 uses | |
508 | * the IODA2 code. | |
509 | */ | |
99451551 GS |
510 | if (phb->type == PNV_PHB_IODA1) |
511 | phb->init_m64 = pnv_ioda1_init_m64; | |
512 | else | |
513 | phb->init_m64 = pnv_ioda2_init_m64; | |
c430670a GS |
514 | phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; |
515 | phb->pick_m64_pe = pnv_ioda_pick_m64_pe; | |
262af557 GC |
516 | } |
517 | ||
49dec922 GS |
518 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
519 | { | |
520 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; | |
521 | struct pnv_ioda_pe *slave; | |
522 | s64 rc; | |
523 | ||
524 | /* Fetch master PE */ | |
525 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
526 | pe = pe->master; | |
ec8e4e9d GS |
527 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
528 | return; | |
529 | ||
49dec922 GS |
530 | pe_no = pe->pe_number; |
531 | } | |
532 | ||
533 | /* Freeze master PE */ | |
534 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
535 | pe_no, | |
536 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
537 | if (rc != OPAL_SUCCESS) { | |
538 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
539 | __func__, rc, phb->hose->global_number, pe_no); | |
540 | return; | |
541 | } | |
542 | ||
543 | /* Freeze slave PEs */ | |
544 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
545 | return; | |
546 | ||
547 | list_for_each_entry(slave, &pe->slaves, list) { | |
548 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
549 | slave->pe_number, | |
550 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
551 | if (rc != OPAL_SUCCESS) | |
552 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
553 | __func__, rc, phb->hose->global_number, | |
554 | slave->pe_number); | |
555 | } | |
556 | } | |
557 | ||
e51df2c1 | 558 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
49dec922 GS |
559 | { |
560 | struct pnv_ioda_pe *pe, *slave; | |
561 | s64 rc; | |
562 | ||
563 | /* Find master PE */ | |
564 | pe = &phb->ioda.pe_array[pe_no]; | |
565 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
566 | pe = pe->master; | |
567 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
568 | pe_no = pe->pe_number; | |
569 | } | |
570 | ||
571 | /* Clear frozen state for master PE */ | |
572 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); | |
573 | if (rc != OPAL_SUCCESS) { | |
574 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
575 | __func__, rc, opt, phb->hose->global_number, pe_no); | |
576 | return -EIO; | |
577 | } | |
578 | ||
579 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
580 | return 0; | |
581 | ||
582 | /* Clear frozen state for slave PEs */ | |
583 | list_for_each_entry(slave, &pe->slaves, list) { | |
584 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
585 | slave->pe_number, | |
586 | opt); | |
587 | if (rc != OPAL_SUCCESS) { | |
588 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
589 | __func__, rc, opt, phb->hose->global_number, | |
590 | slave->pe_number); | |
591 | return -EIO; | |
592 | } | |
593 | } | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) | |
599 | { | |
600 | struct pnv_ioda_pe *slave, *pe; | |
601 | u8 fstate, state; | |
602 | __be16 pcierr; | |
603 | s64 rc; | |
604 | ||
605 | /* Sanity check on PE number */ | |
92b8f137 | 606 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) |
49dec922 GS |
607 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; |
608 | ||
609 | /* | |
610 | * Fetch the master PE and the PE instance might be | |
611 | * not initialized yet. | |
612 | */ | |
613 | pe = &phb->ioda.pe_array[pe_no]; | |
614 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
615 | pe = pe->master; | |
616 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
617 | pe_no = pe->pe_number; | |
618 | } | |
619 | ||
620 | /* Check the master PE */ | |
621 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, | |
622 | &state, &pcierr, NULL); | |
623 | if (rc != OPAL_SUCCESS) { | |
624 | pr_warn("%s: Failure %lld getting " | |
625 | "PHB#%x-PE#%x state\n", | |
626 | __func__, rc, | |
627 | phb->hose->global_number, pe_no); | |
628 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
629 | } | |
630 | ||
631 | /* Check the slave PE */ | |
632 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
633 | return state; | |
634 | ||
635 | list_for_each_entry(slave, &pe->slaves, list) { | |
636 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
637 | slave->pe_number, | |
638 | &fstate, | |
639 | &pcierr, | |
640 | NULL); | |
641 | if (rc != OPAL_SUCCESS) { | |
642 | pr_warn("%s: Failure %lld getting " | |
643 | "PHB#%x-PE#%x state\n", | |
644 | __func__, rc, | |
645 | phb->hose->global_number, slave->pe_number); | |
646 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
647 | } | |
648 | ||
649 | /* | |
650 | * Override the result based on the ascending | |
651 | * priority. | |
652 | */ | |
653 | if (fstate > state) | |
654 | state = fstate; | |
655 | } | |
656 | ||
657 | return state; | |
658 | } | |
659 | ||
184cd4a3 BH |
660 | /* Currently those 2 are only used when MSIs are enabled, this will change |
661 | * but in the meantime, we need to protect them to avoid warnings | |
662 | */ | |
663 | #ifdef CONFIG_PCI_MSI | |
f456834a | 664 | struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
665 | { |
666 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
667 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 668 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
669 | |
670 | if (!pdn) | |
671 | return NULL; | |
672 | if (pdn->pe_number == IODA_INVALID_PE) | |
673 | return NULL; | |
674 | return &phb->ioda.pe_array[pdn->pe_number]; | |
675 | } | |
184cd4a3 BH |
676 | #endif /* CONFIG_PCI_MSI */ |
677 | ||
b131a842 GS |
678 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
679 | struct pnv_ioda_pe *parent, | |
680 | struct pnv_ioda_pe *child, | |
681 | bool is_add) | |
682 | { | |
683 | const char *desc = is_add ? "adding" : "removing"; | |
684 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : | |
685 | OPAL_REMOVE_PE_FROM_DOMAIN; | |
686 | struct pnv_ioda_pe *slave; | |
687 | long rc; | |
688 | ||
689 | /* Parent PE affects child PE */ | |
690 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
691 | child->pe_number, op); | |
692 | if (rc != OPAL_SUCCESS) { | |
693 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", | |
694 | rc, desc); | |
695 | return -ENXIO; | |
696 | } | |
697 | ||
698 | if (!(child->flags & PNV_IODA_PE_MASTER)) | |
699 | return 0; | |
700 | ||
701 | /* Compound case: parent PE affects slave PEs */ | |
702 | list_for_each_entry(slave, &child->slaves, list) { | |
703 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
704 | slave->pe_number, op); | |
705 | if (rc != OPAL_SUCCESS) { | |
706 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", | |
707 | rc, desc); | |
708 | return -ENXIO; | |
709 | } | |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
715 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |
716 | struct pnv_ioda_pe *pe, | |
717 | bool is_add) | |
718 | { | |
719 | struct pnv_ioda_pe *slave; | |
781a868f | 720 | struct pci_dev *pdev = NULL; |
b131a842 GS |
721 | int ret; |
722 | ||
723 | /* | |
724 | * Clear PE frozen state. If it's master PE, we need | |
725 | * clear slave PE frozen state as well. | |
726 | */ | |
727 | if (is_add) { | |
728 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, | |
729 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
730 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
731 | list_for_each_entry(slave, &pe->slaves, list) | |
732 | opal_pci_eeh_freeze_clear(phb->opal_id, | |
733 | slave->pe_number, | |
734 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
735 | } | |
736 | } | |
737 | ||
738 | /* | |
739 | * Associate PE in PELT. We need add the PE into the | |
740 | * corresponding PELT-V as well. Otherwise, the error | |
741 | * originated from the PE might contribute to other | |
742 | * PEs. | |
743 | */ | |
744 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
748 | /* For compound PEs, any one affects all of them */ | |
749 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
750 | list_for_each_entry(slave, &pe->slaves, list) { | |
751 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); | |
752 | if (ret) | |
753 | return ret; | |
754 | } | |
755 | } | |
756 | ||
757 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) | |
758 | pdev = pe->pbus->self; | |
781a868f | 759 | else if (pe->flags & PNV_IODA_PE_DEV) |
b131a842 | 760 | pdev = pe->pdev->bus->self; |
781a868f WY |
761 | #ifdef CONFIG_PCI_IOV |
762 | else if (pe->flags & PNV_IODA_PE_VF) | |
283e2d8a | 763 | pdev = pe->parent_dev; |
781a868f | 764 | #endif /* CONFIG_PCI_IOV */ |
b131a842 GS |
765 | while (pdev) { |
766 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
767 | struct pnv_ioda_pe *parent; | |
768 | ||
769 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
770 | parent = &phb->ioda.pe_array[pdn->pe_number]; | |
771 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); | |
772 | if (ret) | |
773 | return ret; | |
774 | } | |
775 | ||
776 | pdev = pdev->bus->self; | |
777 | } | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
781a868f WY |
782 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
783 | { | |
784 | struct pci_dev *parent; | |
785 | uint8_t bcomp, dcomp, fcomp; | |
786 | int64_t rc; | |
787 | long rid_end, rid; | |
788 | ||
789 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ | |
790 | if (pe->pbus) { | |
791 | int count; | |
792 | ||
793 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
794 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
795 | parent = pe->pbus->self; | |
796 | if (pe->flags & PNV_IODA_PE_BUS_ALL) | |
797 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
798 | else | |
799 | count = 1; | |
800 | ||
801 | switch(count) { | |
802 | case 1: bcomp = OpalPciBusAll; break; | |
803 | case 2: bcomp = OpalPciBus7Bits; break; | |
804 | case 4: bcomp = OpalPciBus6Bits; break; | |
805 | case 8: bcomp = OpalPciBus5Bits; break; | |
806 | case 16: bcomp = OpalPciBus4Bits; break; | |
807 | case 32: bcomp = OpalPciBus3Bits; break; | |
808 | default: | |
809 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", | |
810 | count); | |
811 | /* Do an exact match only */ | |
812 | bcomp = OpalPciBusAll; | |
813 | } | |
814 | rid_end = pe->rid + (count << 8); | |
815 | } else { | |
93e01a50 | 816 | #ifdef CONFIG_PCI_IOV |
781a868f WY |
817 | if (pe->flags & PNV_IODA_PE_VF) |
818 | parent = pe->parent_dev; | |
819 | else | |
93e01a50 | 820 | #endif |
781a868f WY |
821 | parent = pe->pdev->bus->self; |
822 | bcomp = OpalPciBusAll; | |
823 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
824 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
825 | rid_end = pe->rid + 1; | |
826 | } | |
827 | ||
828 | /* Clear the reverse map */ | |
829 | for (rid = pe->rid; rid < rid_end; rid++) | |
c127562a | 830 | phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; |
781a868f WY |
831 | |
832 | /* Release from all parents PELT-V */ | |
833 | while (parent) { | |
834 | struct pci_dn *pdn = pci_get_pdn(parent); | |
835 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
836 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
837 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
838 | /* XXX What to do in case of error ? */ | |
839 | } | |
840 | parent = parent->bus->self; | |
841 | } | |
842 | ||
f951e510 | 843 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
781a868f WY |
844 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
845 | ||
846 | /* Disassociate PE in PELT */ | |
847 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
848 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
849 | if (rc) | |
850 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); | |
851 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, | |
852 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); | |
853 | if (rc) | |
854 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
855 | ||
856 | pe->pbus = NULL; | |
857 | pe->pdev = NULL; | |
93e01a50 | 858 | #ifdef CONFIG_PCI_IOV |
781a868f | 859 | pe->parent_dev = NULL; |
93e01a50 | 860 | #endif |
781a868f WY |
861 | |
862 | return 0; | |
863 | } | |
781a868f | 864 | |
cad5cef6 | 865 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
866 | { |
867 | struct pci_dev *parent; | |
868 | uint8_t bcomp, dcomp, fcomp; | |
869 | long rc, rid_end, rid; | |
870 | ||
871 | /* Bus validation ? */ | |
872 | if (pe->pbus) { | |
873 | int count; | |
874 | ||
875 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
876 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
877 | parent = pe->pbus->self; | |
fb446ad0 GS |
878 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
879 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
880 | else | |
881 | count = 1; | |
882 | ||
184cd4a3 BH |
883 | switch(count) { |
884 | case 1: bcomp = OpalPciBusAll; break; | |
885 | case 2: bcomp = OpalPciBus7Bits; break; | |
886 | case 4: bcomp = OpalPciBus6Bits; break; | |
887 | case 8: bcomp = OpalPciBus5Bits; break; | |
888 | case 16: bcomp = OpalPciBus4Bits; break; | |
889 | case 32: bcomp = OpalPciBus3Bits; break; | |
890 | default: | |
781a868f WY |
891 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
892 | count); | |
184cd4a3 BH |
893 | /* Do an exact match only */ |
894 | bcomp = OpalPciBusAll; | |
895 | } | |
896 | rid_end = pe->rid + (count << 8); | |
897 | } else { | |
781a868f WY |
898 | #ifdef CONFIG_PCI_IOV |
899 | if (pe->flags & PNV_IODA_PE_VF) | |
900 | parent = pe->parent_dev; | |
901 | else | |
902 | #endif /* CONFIG_PCI_IOV */ | |
903 | parent = pe->pdev->bus->self; | |
184cd4a3 BH |
904 | bcomp = OpalPciBusAll; |
905 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
906 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
907 | rid_end = pe->rid + 1; | |
908 | } | |
909 | ||
631ad691 GS |
910 | /* |
911 | * Associate PE in PELT. We need add the PE into the | |
912 | * corresponding PELT-V as well. Otherwise, the error | |
913 | * originated from the PE might contribute to other | |
914 | * PEs. | |
915 | */ | |
184cd4a3 BH |
916 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
917 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
918 | if (rc) { | |
919 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
920 | return -ENXIO; | |
921 | } | |
631ad691 | 922 | |
5d2aa710 AP |
923 | /* |
924 | * Configure PELTV. NPUs don't have a PELTV table so skip | |
925 | * configuration on them. | |
926 | */ | |
927 | if (phb->type != PNV_PHB_NPU) | |
928 | pnv_ioda_set_peltv(phb, pe, true); | |
184cd4a3 | 929 | |
184cd4a3 BH |
930 | /* Setup reverse map */ |
931 | for (rid = pe->rid; rid < rid_end; rid++) | |
932 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
933 | ||
934 | /* Setup one MVTs on IODA1 */ | |
4773f76b GS |
935 | if (phb->type != PNV_PHB_IODA1) { |
936 | pe->mve_number = 0; | |
937 | goto out; | |
938 | } | |
939 | ||
940 | pe->mve_number = pe->pe_number; | |
941 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); | |
942 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 943 | pe_err(pe, "OPAL error %ld setting up MVE %x\n", |
4773f76b GS |
944 | rc, pe->mve_number); |
945 | pe->mve_number = -1; | |
946 | } else { | |
947 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
948 | pe->mve_number, OPAL_ENABLE_MVE); | |
184cd4a3 | 949 | if (rc) { |
1f52f176 | 950 | pe_err(pe, "OPAL error %ld enabling MVE %x\n", |
184cd4a3 BH |
951 | rc, pe->mve_number); |
952 | pe->mve_number = -1; | |
184cd4a3 | 953 | } |
4773f76b | 954 | } |
184cd4a3 | 955 | |
4773f76b | 956 | out: |
184cd4a3 BH |
957 | return 0; |
958 | } | |
959 | ||
781a868f WY |
960 | #ifdef CONFIG_PCI_IOV |
961 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) | |
962 | { | |
963 | struct pci_dn *pdn = pci_get_pdn(dev); | |
964 | int i; | |
965 | struct resource *res, res2; | |
966 | resource_size_t size; | |
967 | u16 num_vfs; | |
968 | ||
969 | if (!dev->is_physfn) | |
970 | return -EINVAL; | |
971 | ||
972 | /* | |
973 | * "offset" is in VFs. The M64 windows are sized so that when they | |
974 | * are segmented, each segment is the same size as the IOV BAR. | |
975 | * Each segment is in a separate PE, and the high order bits of the | |
976 | * address are the PE number. Therefore, each VF's BAR is in a | |
977 | * separate PE, and changing the IOV BAR start address changes the | |
978 | * range of PEs the VFs are in. | |
979 | */ | |
980 | num_vfs = pdn->num_vfs; | |
981 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
982 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
983 | if (!res->flags || !res->parent) | |
984 | continue; | |
985 | ||
781a868f WY |
986 | /* |
987 | * The actual IOV BAR range is determined by the start address | |
988 | * and the actual size for num_vfs VFs BAR. This check is to | |
989 | * make sure that after shifting, the range will not overlap | |
990 | * with another device. | |
991 | */ | |
992 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | |
993 | res2.flags = res->flags; | |
994 | res2.start = res->start + (size * offset); | |
995 | res2.end = res2.start + (size * num_vfs) - 1; | |
996 | ||
997 | if (res2.end > res->end) { | |
998 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", | |
999 | i, &res2, res, num_vfs, offset); | |
1000 | return -EBUSY; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | /* | |
d6f934fd AK |
1005 | * Since M64 BAR shares segments among all possible 256 PEs, |
1006 | * we have to shift the beginning of PF IOV BAR to make it start from | |
1007 | * the segment which belongs to the PE number assigned to the first VF. | |
1008 | * This creates a "hole" in the /proc/iomem which could be used for | |
1009 | * allocating other resources so we reserve this area below and | |
1010 | * release when IOV is released. | |
781a868f WY |
1011 | */ |
1012 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1013 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
1014 | if (!res->flags || !res->parent) | |
1015 | continue; | |
1016 | ||
781a868f WY |
1017 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
1018 | res2 = *res; | |
1019 | res->start += size * offset; | |
1020 | ||
74703cc4 WY |
1021 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", |
1022 | i, &res2, res, (offset > 0) ? "En" : "Dis", | |
1023 | num_vfs, offset); | |
d6f934fd AK |
1024 | |
1025 | if (offset < 0) { | |
1026 | devm_release_resource(&dev->dev, &pdn->holes[i]); | |
1027 | memset(&pdn->holes[i], 0, sizeof(pdn->holes[i])); | |
1028 | } | |
1029 | ||
781a868f | 1030 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); |
d6f934fd AK |
1031 | |
1032 | if (offset > 0) { | |
1033 | pdn->holes[i].start = res2.start; | |
1034 | pdn->holes[i].end = res2.start + size * offset - 1; | |
1035 | pdn->holes[i].flags = IORESOURCE_BUS; | |
1036 | pdn->holes[i].name = "pnv_iov_reserved"; | |
1037 | devm_request_resource(&dev->dev, res->parent, | |
1038 | &pdn->holes[i]); | |
1039 | } | |
781a868f WY |
1040 | } |
1041 | return 0; | |
1042 | } | |
1043 | #endif /* CONFIG_PCI_IOV */ | |
1044 | ||
cad5cef6 | 1045 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
1046 | { |
1047 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1048 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 1049 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 | 1050 | struct pnv_ioda_pe *pe; |
184cd4a3 BH |
1051 | |
1052 | if (!pdn) { | |
1053 | pr_err("%s: Device tree node not associated properly\n", | |
1054 | pci_name(dev)); | |
1055 | return NULL; | |
1056 | } | |
1057 | if (pdn->pe_number != IODA_INVALID_PE) | |
1058 | return NULL; | |
1059 | ||
1e916772 GS |
1060 | pe = pnv_ioda_alloc_pe(phb); |
1061 | if (!pe) { | |
184cd4a3 BH |
1062 | pr_warning("%s: Not enough PE# available, disabling device\n", |
1063 | pci_name(dev)); | |
1064 | return NULL; | |
1065 | } | |
1066 | ||
1067 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
1068 | * pointer in the PE data structure, both should be destroyed at the | |
1069 | * same time. However, this needs to be looked at more closely again | |
1070 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
1071 | * | |
1072 | * At some point we want to remove the PDN completely anyways | |
1073 | */ | |
184cd4a3 BH |
1074 | pci_dev_get(dev); |
1075 | pdn->pcidev = dev; | |
1e916772 | 1076 | pdn->pe_number = pe->pe_number; |
5d2aa710 | 1077 | pe->flags = PNV_IODA_PE_DEV; |
184cd4a3 BH |
1078 | pe->pdev = dev; |
1079 | pe->pbus = NULL; | |
184cd4a3 BH |
1080 | pe->mve_number = -1; |
1081 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
1082 | ||
1083 | pe_info(pe, "Associated device to PE\n"); | |
1084 | ||
1085 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1086 | /* XXX What do we do here ? */ | |
1e916772 | 1087 | pnv_ioda_free_pe(pe); |
184cd4a3 BH |
1088 | pdn->pe_number = IODA_INVALID_PE; |
1089 | pe->pdev = NULL; | |
1090 | pci_dev_put(dev); | |
1091 | return NULL; | |
1092 | } | |
1093 | ||
1d4e89cf AK |
1094 | /* Put PE to the list */ |
1095 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1096 | ||
184cd4a3 BH |
1097 | return pe; |
1098 | } | |
1099 | ||
1100 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
1101 | { | |
1102 | struct pci_dev *dev; | |
1103 | ||
1104 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 1105 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1106 | |
1107 | if (pdn == NULL) { | |
1108 | pr_warn("%s: No device node associated with device !\n", | |
1109 | pci_name(dev)); | |
1110 | continue; | |
1111 | } | |
ccd1c191 GS |
1112 | |
1113 | /* | |
1114 | * In partial hotplug case, the PCI device might be still | |
1115 | * associated with the PE and needn't attach it to the PE | |
1116 | * again. | |
1117 | */ | |
1118 | if (pdn->pe_number != IODA_INVALID_PE) | |
1119 | continue; | |
1120 | ||
c5f7700b | 1121 | pe->device_count++; |
94973b24 | 1122 | pdn->pcidev = dev; |
184cd4a3 | 1123 | pdn->pe_number = pe->pe_number; |
fb446ad0 | 1124 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
1125 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
1126 | } | |
1127 | } | |
1128 | ||
fb446ad0 GS |
1129 | /* |
1130 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
1131 | * single PCI bus. Another one that contains the primary PCI bus and its | |
1132 | * subordinate PCI devices and buses. The second type of PE is normally | |
1133 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
1134 | */ | |
1e916772 | 1135 | static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) |
184cd4a3 | 1136 | { |
fb446ad0 | 1137 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 1138 | struct pnv_phb *phb = hose->private_data; |
1e916772 | 1139 | struct pnv_ioda_pe *pe = NULL; |
ccd1c191 GS |
1140 | unsigned int pe_num; |
1141 | ||
1142 | /* | |
1143 | * In partial hotplug case, the PE instance might be still alive. | |
1144 | * We should reuse it instead of allocating a new one. | |
1145 | */ | |
1146 | pe_num = phb->ioda.pe_rmap[bus->number << 8]; | |
1147 | if (pe_num != IODA_INVALID_PE) { | |
1148 | pe = &phb->ioda.pe_array[pe_num]; | |
1149 | pnv_ioda_setup_same_PE(bus, pe); | |
1150 | return NULL; | |
1151 | } | |
262af557 | 1152 | |
63803c39 GS |
1153 | /* PE number for root bus should have been reserved */ |
1154 | if (pci_is_root_bus(bus) && | |
1155 | phb->ioda.root_pe_idx != IODA_INVALID_PE) | |
1156 | pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; | |
1157 | ||
262af557 | 1158 | /* Check if PE is determined by M64 */ |
63803c39 | 1159 | if (!pe && phb->pick_m64_pe) |
1e916772 | 1160 | pe = phb->pick_m64_pe(bus, all); |
262af557 GC |
1161 | |
1162 | /* The PE number isn't pinned by M64 */ | |
1e916772 GS |
1163 | if (!pe) |
1164 | pe = pnv_ioda_alloc_pe(phb); | |
184cd4a3 | 1165 | |
1e916772 | 1166 | if (!pe) { |
fb446ad0 GS |
1167 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
1168 | __func__, pci_domain_nr(bus), bus->number); | |
1e916772 | 1169 | return NULL; |
184cd4a3 BH |
1170 | } |
1171 | ||
262af557 | 1172 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
1173 | pe->pbus = bus; |
1174 | pe->pdev = NULL; | |
184cd4a3 | 1175 | pe->mve_number = -1; |
b918c62e | 1176 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 | 1177 | |
fb446ad0 | 1178 | if (all) |
1f52f176 | 1179 | pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", |
1e916772 | 1180 | bus->busn_res.start, bus->busn_res.end, pe->pe_number); |
fb446ad0 | 1181 | else |
1f52f176 | 1182 | pe_info(pe, "Secondary bus %d associated with PE#%x\n", |
1e916772 | 1183 | bus->busn_res.start, pe->pe_number); |
184cd4a3 BH |
1184 | |
1185 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1186 | /* XXX What do we do here ? */ | |
1e916772 | 1187 | pnv_ioda_free_pe(pe); |
184cd4a3 | 1188 | pe->pbus = NULL; |
1e916772 | 1189 | return NULL; |
184cd4a3 BH |
1190 | } |
1191 | ||
1192 | /* Associate it with all child devices */ | |
1193 | pnv_ioda_setup_same_PE(bus, pe); | |
1194 | ||
7ebdf956 GS |
1195 | /* Put PE to the list */ |
1196 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1e916772 GS |
1197 | |
1198 | return pe; | |
184cd4a3 BH |
1199 | } |
1200 | ||
b521549a AP |
1201 | static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) |
1202 | { | |
1203 | int pe_num, found_pe = false, rc; | |
1204 | long rid; | |
1205 | struct pnv_ioda_pe *pe; | |
1206 | struct pci_dev *gpu_pdev; | |
1207 | struct pci_dn *npu_pdn; | |
1208 | struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); | |
1209 | struct pnv_phb *phb = hose->private_data; | |
1210 | ||
1211 | /* | |
1212 | * Due to a hardware errata PE#0 on the NPU is reserved for | |
1213 | * error handling. This means we only have three PEs remaining | |
1214 | * which need to be assigned to four links, implying some | |
1215 | * links must share PEs. | |
1216 | * | |
1217 | * To achieve this we assign PEs such that NPUs linking the | |
1218 | * same GPU get assigned the same PE. | |
1219 | */ | |
1220 | gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); | |
92b8f137 | 1221 | for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { |
b521549a AP |
1222 | pe = &phb->ioda.pe_array[pe_num]; |
1223 | if (!pe->pdev) | |
1224 | continue; | |
1225 | ||
1226 | if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { | |
1227 | /* | |
1228 | * This device has the same peer GPU so should | |
1229 | * be assigned the same PE as the existing | |
1230 | * peer NPU. | |
1231 | */ | |
1232 | dev_info(&npu_pdev->dev, | |
1f52f176 | 1233 | "Associating to existing PE %x\n", pe_num); |
b521549a AP |
1234 | pci_dev_get(npu_pdev); |
1235 | npu_pdn = pci_get_pdn(npu_pdev); | |
1236 | rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; | |
1237 | npu_pdn->pcidev = npu_pdev; | |
1238 | npu_pdn->pe_number = pe_num; | |
b521549a AP |
1239 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
1240 | ||
1241 | /* Map the PE to this link */ | |
1242 | rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, | |
1243 | OpalPciBusAll, | |
1244 | OPAL_COMPARE_RID_DEVICE_NUMBER, | |
1245 | OPAL_COMPARE_RID_FUNCTION_NUMBER, | |
1246 | OPAL_MAP_PE); | |
1247 | WARN_ON(rc != OPAL_SUCCESS); | |
1248 | found_pe = true; | |
1249 | break; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | if (!found_pe) | |
1254 | /* | |
1255 | * Could not find an existing PE so allocate a new | |
1256 | * one. | |
1257 | */ | |
1258 | return pnv_ioda_setup_dev_PE(npu_pdev); | |
1259 | else | |
1260 | return pe; | |
1261 | } | |
1262 | ||
1263 | static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) | |
5d2aa710 | 1264 | { |
5d2aa710 AP |
1265 | struct pci_dev *pdev; |
1266 | ||
1267 | list_for_each_entry(pdev, &bus->devices, bus_list) | |
b521549a | 1268 | pnv_ioda_setup_npu_PE(pdev); |
5d2aa710 AP |
1269 | } |
1270 | ||
cad5cef6 | 1271 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
1272 | { |
1273 | struct pci_controller *hose, *tmp; | |
262af557 | 1274 | struct pnv_phb *phb; |
fb446ad0 GS |
1275 | |
1276 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
262af557 | 1277 | phb = hose->private_data; |
08f48f32 AP |
1278 | if (phb->type == PNV_PHB_NPU) { |
1279 | /* PE#0 is needed for error reporting */ | |
1280 | pnv_ioda_reserve_pe(phb, 0); | |
b521549a | 1281 | pnv_ioda_setup_npu_PEs(hose->bus); |
1ab66d1f AP |
1282 | if (phb->model == PNV_PHB_MODEL_NPU2) |
1283 | pnv_npu2_init(phb); | |
ccd1c191 | 1284 | } |
184cd4a3 BH |
1285 | } |
1286 | } | |
1287 | ||
a8b2f828 | 1288 | #ifdef CONFIG_PCI_IOV |
ee8222fe | 1289 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1290 | { |
1291 | struct pci_bus *bus; | |
1292 | struct pci_controller *hose; | |
1293 | struct pnv_phb *phb; | |
1294 | struct pci_dn *pdn; | |
02639b0e | 1295 | int i, j; |
ee8222fe | 1296 | int m64_bars; |
781a868f WY |
1297 | |
1298 | bus = pdev->bus; | |
1299 | hose = pci_bus_to_host(bus); | |
1300 | phb = hose->private_data; | |
1301 | pdn = pci_get_pdn(pdev); | |
1302 | ||
ee8222fe WY |
1303 | if (pdn->m64_single_mode) |
1304 | m64_bars = num_vfs; | |
1305 | else | |
1306 | m64_bars = 1; | |
1307 | ||
02639b0e | 1308 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
ee8222fe WY |
1309 | for (j = 0; j < m64_bars; j++) { |
1310 | if (pdn->m64_map[j][i] == IODA_INVALID_M64) | |
02639b0e WY |
1311 | continue; |
1312 | opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe WY |
1313 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); |
1314 | clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); | |
1315 | pdn->m64_map[j][i] = IODA_INVALID_M64; | |
02639b0e | 1316 | } |
781a868f | 1317 | |
ee8222fe | 1318 | kfree(pdn->m64_map); |
781a868f WY |
1319 | return 0; |
1320 | } | |
1321 | ||
02639b0e | 1322 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1323 | { |
1324 | struct pci_bus *bus; | |
1325 | struct pci_controller *hose; | |
1326 | struct pnv_phb *phb; | |
1327 | struct pci_dn *pdn; | |
1328 | unsigned int win; | |
1329 | struct resource *res; | |
02639b0e | 1330 | int i, j; |
781a868f | 1331 | int64_t rc; |
02639b0e WY |
1332 | int total_vfs; |
1333 | resource_size_t size, start; | |
1334 | int pe_num; | |
ee8222fe | 1335 | int m64_bars; |
781a868f WY |
1336 | |
1337 | bus = pdev->bus; | |
1338 | hose = pci_bus_to_host(bus); | |
1339 | phb = hose->private_data; | |
1340 | pdn = pci_get_pdn(pdev); | |
02639b0e | 1341 | total_vfs = pci_sriov_get_totalvfs(pdev); |
781a868f | 1342 | |
ee8222fe WY |
1343 | if (pdn->m64_single_mode) |
1344 | m64_bars = num_vfs; | |
1345 | else | |
1346 | m64_bars = 1; | |
1347 | ||
fb37e128 ME |
1348 | pdn->m64_map = kmalloc_array(m64_bars, |
1349 | sizeof(*pdn->m64_map), | |
1350 | GFP_KERNEL); | |
ee8222fe WY |
1351 | if (!pdn->m64_map) |
1352 | return -ENOMEM; | |
1353 | /* Initialize the m64_map to IODA_INVALID_M64 */ | |
1354 | for (i = 0; i < m64_bars ; i++) | |
1355 | for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) | |
1356 | pdn->m64_map[i][j] = IODA_INVALID_M64; | |
02639b0e | 1357 | |
781a868f WY |
1358 | |
1359 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1360 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
1361 | if (!res->flags || !res->parent) | |
1362 | continue; | |
1363 | ||
ee8222fe | 1364 | for (j = 0; j < m64_bars; j++) { |
02639b0e WY |
1365 | do { |
1366 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, | |
1367 | phb->ioda.m64_bar_idx + 1, 0); | |
1368 | ||
1369 | if (win >= phb->ioda.m64_bar_idx + 1) | |
1370 | goto m64_failed; | |
1371 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); | |
1372 | ||
ee8222fe | 1373 | pdn->m64_map[j][i] = win; |
02639b0e | 1374 | |
ee8222fe | 1375 | if (pdn->m64_single_mode) { |
02639b0e WY |
1376 | size = pci_iov_resource_size(pdev, |
1377 | PCI_IOV_RESOURCES + i); | |
02639b0e WY |
1378 | start = res->start + size * j; |
1379 | } else { | |
1380 | size = resource_size(res); | |
1381 | start = res->start; | |
1382 | } | |
1383 | ||
1384 | /* Map the M64 here */ | |
ee8222fe | 1385 | if (pdn->m64_single_mode) { |
be283eeb | 1386 | pe_num = pdn->pe_num_map[j]; |
02639b0e WY |
1387 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
1388 | pe_num, OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1389 | pdn->m64_map[j][i], 0); |
02639b0e WY |
1390 | } |
1391 | ||
1392 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
1393 | OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1394 | pdn->m64_map[j][i], |
02639b0e WY |
1395 | start, |
1396 | 0, /* unused */ | |
1397 | size); | |
781a868f | 1398 | |
781a868f | 1399 | |
02639b0e WY |
1400 | if (rc != OPAL_SUCCESS) { |
1401 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", | |
1402 | win, rc); | |
1403 | goto m64_failed; | |
1404 | } | |
781a868f | 1405 | |
ee8222fe | 1406 | if (pdn->m64_single_mode) |
02639b0e | 1407 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
ee8222fe | 1408 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); |
02639b0e WY |
1409 | else |
1410 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe | 1411 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); |
781a868f | 1412 | |
02639b0e WY |
1413 | if (rc != OPAL_SUCCESS) { |
1414 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", | |
1415 | win, rc); | |
1416 | goto m64_failed; | |
1417 | } | |
781a868f WY |
1418 | } |
1419 | } | |
1420 | return 0; | |
1421 | ||
1422 | m64_failed: | |
ee8222fe | 1423 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1424 | return -EBUSY; |
1425 | } | |
1426 | ||
c035e37b AK |
1427 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
1428 | int num); | |
c035e37b | 1429 | |
781a868f WY |
1430 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) |
1431 | { | |
781a868f | 1432 | struct iommu_table *tbl; |
781a868f WY |
1433 | int64_t rc; |
1434 | ||
b348aa65 | 1435 | tbl = pe->table_group.tables[0]; |
c035e37b | 1436 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
781a868f WY |
1437 | if (rc) |
1438 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
1439 | ||
c035e37b | 1440 | pnv_pci_ioda2_set_bypass(pe, false); |
0eaf4def AK |
1441 | if (pe->table_group.group) { |
1442 | iommu_group_put(pe->table_group.group); | |
1443 | BUG_ON(pe->table_group.group); | |
ac9a5889 | 1444 | } |
e5afdf9d | 1445 | iommu_tce_table_put(tbl); |
781a868f WY |
1446 | } |
1447 | ||
ee8222fe | 1448 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) |
781a868f WY |
1449 | { |
1450 | struct pci_bus *bus; | |
1451 | struct pci_controller *hose; | |
1452 | struct pnv_phb *phb; | |
1453 | struct pnv_ioda_pe *pe, *pe_n; | |
1454 | struct pci_dn *pdn; | |
1455 | ||
1456 | bus = pdev->bus; | |
1457 | hose = pci_bus_to_host(bus); | |
1458 | phb = hose->private_data; | |
02639b0e | 1459 | pdn = pci_get_pdn(pdev); |
781a868f WY |
1460 | |
1461 | if (!pdev->is_physfn) | |
1462 | return; | |
1463 | ||
781a868f WY |
1464 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
1465 | if (pe->parent_dev != pdev) | |
1466 | continue; | |
1467 | ||
1468 | pnv_pci_ioda2_release_dma_pe(pdev, pe); | |
1469 | ||
1470 | /* Remove from list */ | |
1471 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1472 | list_del(&pe->list); | |
1473 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1474 | ||
1475 | pnv_ioda_deconfigure_pe(phb, pe); | |
1476 | ||
1e916772 | 1477 | pnv_ioda_free_pe(pe); |
781a868f WY |
1478 | } |
1479 | } | |
1480 | ||
1481 | void pnv_pci_sriov_disable(struct pci_dev *pdev) | |
1482 | { | |
1483 | struct pci_bus *bus; | |
1484 | struct pci_controller *hose; | |
1485 | struct pnv_phb *phb; | |
1e916772 | 1486 | struct pnv_ioda_pe *pe; |
781a868f | 1487 | struct pci_dn *pdn; |
be283eeb | 1488 | u16 num_vfs, i; |
781a868f WY |
1489 | |
1490 | bus = pdev->bus; | |
1491 | hose = pci_bus_to_host(bus); | |
1492 | phb = hose->private_data; | |
1493 | pdn = pci_get_pdn(pdev); | |
781a868f WY |
1494 | num_vfs = pdn->num_vfs; |
1495 | ||
1496 | /* Release VF PEs */ | |
ee8222fe | 1497 | pnv_ioda_release_vf_PE(pdev); |
781a868f WY |
1498 | |
1499 | if (phb->type == PNV_PHB_IODA2) { | |
ee8222fe | 1500 | if (!pdn->m64_single_mode) |
be283eeb | 1501 | pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); |
781a868f WY |
1502 | |
1503 | /* Release M64 windows */ | |
ee8222fe | 1504 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1505 | |
1506 | /* Release PE numbers */ | |
be283eeb WY |
1507 | if (pdn->m64_single_mode) { |
1508 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1509 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
1510 | continue; | |
1511 | ||
1512 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; | |
1513 | pnv_ioda_free_pe(pe); | |
be283eeb WY |
1514 | } |
1515 | } else | |
1516 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1517 | /* Releasing pe_num_map */ | |
1518 | kfree(pdn->pe_num_map); | |
781a868f WY |
1519 | } |
1520 | } | |
1521 | ||
1522 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
1523 | struct pnv_ioda_pe *pe); | |
1524 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) | |
1525 | { | |
1526 | struct pci_bus *bus; | |
1527 | struct pci_controller *hose; | |
1528 | struct pnv_phb *phb; | |
1529 | struct pnv_ioda_pe *pe; | |
1530 | int pe_num; | |
1531 | u16 vf_index; | |
1532 | struct pci_dn *pdn; | |
1533 | ||
1534 | bus = pdev->bus; | |
1535 | hose = pci_bus_to_host(bus); | |
1536 | phb = hose->private_data; | |
1537 | pdn = pci_get_pdn(pdev); | |
1538 | ||
1539 | if (!pdev->is_physfn) | |
1540 | return; | |
1541 | ||
1542 | /* Reserve PE for each VF */ | |
1543 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { | |
be283eeb WY |
1544 | if (pdn->m64_single_mode) |
1545 | pe_num = pdn->pe_num_map[vf_index]; | |
1546 | else | |
1547 | pe_num = *pdn->pe_num_map + vf_index; | |
781a868f WY |
1548 | |
1549 | pe = &phb->ioda.pe_array[pe_num]; | |
1550 | pe->pe_number = pe_num; | |
1551 | pe->phb = phb; | |
1552 | pe->flags = PNV_IODA_PE_VF; | |
1553 | pe->pbus = NULL; | |
1554 | pe->parent_dev = pdev; | |
781a868f WY |
1555 | pe->mve_number = -1; |
1556 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | | |
1557 | pci_iov_virtfn_devfn(pdev, vf_index); | |
1558 | ||
1f52f176 | 1559 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", |
781a868f WY |
1560 | hose->global_number, pdev->bus->number, |
1561 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), | |
1562 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); | |
1563 | ||
1564 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1565 | /* XXX What do we do here ? */ | |
1e916772 | 1566 | pnv_ioda_free_pe(pe); |
781a868f WY |
1567 | pe->pdev = NULL; |
1568 | continue; | |
1569 | } | |
1570 | ||
781a868f WY |
1571 | /* Put PE to the list */ |
1572 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1573 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1574 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1575 | ||
1576 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
1577 | } | |
1578 | } | |
1579 | ||
1580 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1581 | { | |
1582 | struct pci_bus *bus; | |
1583 | struct pci_controller *hose; | |
1584 | struct pnv_phb *phb; | |
1e916772 | 1585 | struct pnv_ioda_pe *pe; |
781a868f WY |
1586 | struct pci_dn *pdn; |
1587 | int ret; | |
be283eeb | 1588 | u16 i; |
781a868f WY |
1589 | |
1590 | bus = pdev->bus; | |
1591 | hose = pci_bus_to_host(bus); | |
1592 | phb = hose->private_data; | |
1593 | pdn = pci_get_pdn(pdev); | |
1594 | ||
1595 | if (phb->type == PNV_PHB_IODA2) { | |
b0331854 WY |
1596 | if (!pdn->vfs_expanded) { |
1597 | dev_info(&pdev->dev, "don't support this SRIOV device" | |
1598 | " with non 64bit-prefetchable IOV BAR\n"); | |
1599 | return -ENOSPC; | |
1600 | } | |
1601 | ||
ee8222fe WY |
1602 | /* |
1603 | * When M64 BARs functions in Single PE mode, the number of VFs | |
1604 | * could be enabled must be less than the number of M64 BARs. | |
1605 | */ | |
1606 | if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { | |
1607 | dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); | |
1608 | return -EBUSY; | |
1609 | } | |
1610 | ||
be283eeb WY |
1611 | /* Allocating pe_num_map */ |
1612 | if (pdn->m64_single_mode) | |
fb37e128 ME |
1613 | pdn->pe_num_map = kmalloc_array(num_vfs, |
1614 | sizeof(*pdn->pe_num_map), | |
1615 | GFP_KERNEL); | |
be283eeb WY |
1616 | else |
1617 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); | |
1618 | ||
1619 | if (!pdn->pe_num_map) | |
1620 | return -ENOMEM; | |
1621 | ||
1622 | if (pdn->m64_single_mode) | |
1623 | for (i = 0; i < num_vfs; i++) | |
1624 | pdn->pe_num_map[i] = IODA_INVALID_PE; | |
1625 | ||
781a868f | 1626 | /* Calculate available PE for required VFs */ |
be283eeb WY |
1627 | if (pdn->m64_single_mode) { |
1628 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1629 | pe = pnv_ioda_alloc_pe(phb); |
1630 | if (!pe) { | |
be283eeb WY |
1631 | ret = -EBUSY; |
1632 | goto m64_failed; | |
1633 | } | |
1e916772 GS |
1634 | |
1635 | pdn->pe_num_map[i] = pe->pe_number; | |
be283eeb WY |
1636 | } |
1637 | } else { | |
1638 | mutex_lock(&phb->ioda.pe_alloc_mutex); | |
1639 | *pdn->pe_num_map = bitmap_find_next_zero_area( | |
92b8f137 | 1640 | phb->ioda.pe_alloc, phb->ioda.total_pe_num, |
be283eeb | 1641 | 0, num_vfs, 0); |
92b8f137 | 1642 | if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { |
be283eeb WY |
1643 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
1644 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); | |
1645 | kfree(pdn->pe_num_map); | |
1646 | return -EBUSY; | |
1647 | } | |
1648 | bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
781a868f | 1649 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
781a868f | 1650 | } |
781a868f | 1651 | pdn->num_vfs = num_vfs; |
781a868f WY |
1652 | |
1653 | /* Assign M64 window accordingly */ | |
02639b0e | 1654 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
781a868f WY |
1655 | if (ret) { |
1656 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); | |
1657 | goto m64_failed; | |
1658 | } | |
1659 | ||
1660 | /* | |
1661 | * When using one M64 BAR to map one IOV BAR, we need to shift | |
1662 | * the IOV BAR according to the PE# allocated to the VFs. | |
1663 | * Otherwise, the PE# for the VF will conflict with others. | |
1664 | */ | |
ee8222fe | 1665 | if (!pdn->m64_single_mode) { |
be283eeb | 1666 | ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); |
02639b0e WY |
1667 | if (ret) |
1668 | goto m64_failed; | |
1669 | } | |
781a868f WY |
1670 | } |
1671 | ||
1672 | /* Setup VF PEs */ | |
1673 | pnv_ioda_setup_vf_PE(pdev, num_vfs); | |
1674 | ||
1675 | return 0; | |
1676 | ||
1677 | m64_failed: | |
be283eeb WY |
1678 | if (pdn->m64_single_mode) { |
1679 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1680 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
1681 | continue; | |
1682 | ||
1683 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; | |
1684 | pnv_ioda_free_pe(pe); | |
be283eeb WY |
1685 | } |
1686 | } else | |
1687 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1688 | ||
1689 | /* Releasing pe_num_map */ | |
1690 | kfree(pdn->pe_num_map); | |
781a868f WY |
1691 | |
1692 | return ret; | |
1693 | } | |
1694 | ||
a8b2f828 GS |
1695 | int pcibios_sriov_disable(struct pci_dev *pdev) |
1696 | { | |
781a868f WY |
1697 | pnv_pci_sriov_disable(pdev); |
1698 | ||
a8b2f828 GS |
1699 | /* Release PCI data */ |
1700 | remove_dev_pci_data(pdev); | |
1701 | return 0; | |
1702 | } | |
1703 | ||
1704 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1705 | { | |
1706 | /* Allocate PCI data */ | |
1707 | add_dev_pci_data(pdev); | |
781a868f | 1708 | |
ee8222fe | 1709 | return pnv_pci_sriov_enable(pdev, num_vfs); |
a8b2f828 GS |
1710 | } |
1711 | #endif /* CONFIG_PCI_IOV */ | |
1712 | ||
959c9bdd | 1713 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 1714 | { |
b72c1f65 | 1715 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 1716 | struct pnv_ioda_pe *pe; |
184cd4a3 | 1717 | |
959c9bdd GS |
1718 | /* |
1719 | * The function can be called while the PE# | |
1720 | * hasn't been assigned. Do nothing for the | |
1721 | * case. | |
1722 | */ | |
1723 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
1724 | return; | |
184cd4a3 | 1725 | |
959c9bdd | 1726 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
cd15b048 | 1727 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
0e1ffef0 | 1728 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); |
b348aa65 | 1729 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
4617082e AK |
1730 | /* |
1731 | * Note: iommu_add_device() will fail here as | |
1732 | * for physical PE: the device is already added by now; | |
1733 | * for virtual PE: sysfs entries are not ready yet and | |
1734 | * tce_iommu_bus_notifier will add the device to a group later. | |
1735 | */ | |
184cd4a3 BH |
1736 | } |
1737 | ||
a0f98629 RC |
1738 | static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) |
1739 | { | |
1740 | unsigned short vendor = 0; | |
1741 | struct pci_dev *pdev; | |
1742 | ||
1743 | if (pe->device_count == 1) | |
1744 | return true; | |
1745 | ||
1746 | /* pe->pdev should be set if it's a single device, pe->pbus if not */ | |
1747 | if (!pe->pbus) | |
1748 | return true; | |
1749 | ||
1750 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { | |
1751 | if (!vendor) { | |
1752 | vendor = pdev->vendor; | |
1753 | continue; | |
1754 | } | |
1755 | ||
1756 | if (pdev->vendor != vendor) | |
1757 | return false; | |
1758 | } | |
1759 | ||
1760 | return true; | |
1761 | } | |
1762 | ||
8e3f1b1d RC |
1763 | /* |
1764 | * Reconfigure TVE#0 to be usable as 64-bit DMA space. | |
1765 | * | |
1766 | * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. | |
1767 | * Devices can only access more than that if bit 59 of the PCI address is set | |
1768 | * by hardware, which indicates TVE#1 should be used instead of TVE#0. | |
1769 | * Many PCI devices are not capable of addressing that many bits, and as a | |
1770 | * result are limited to the 4GB of virtual memory made available to 32-bit | |
1771 | * devices in TVE#0. | |
1772 | * | |
1773 | * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit | |
1774 | * devices by configuring the virtual memory past the first 4GB inaccessible | |
1775 | * by 64-bit DMAs. This should only be used by devices that want more than | |
1776 | * 4GB, and only on PEs that have no 32-bit devices. | |
1777 | * | |
1778 | * Currently this will only work on PHB3 (POWER8). | |
1779 | */ | |
1780 | static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) | |
1781 | { | |
1782 | u64 window_size, table_size, tce_count, addr; | |
1783 | struct page *table_pages; | |
1784 | u64 tce_order = 28; /* 256MB TCEs */ | |
1785 | __be64 *tces; | |
1786 | s64 rc; | |
1787 | ||
1788 | /* | |
1789 | * Window size needs to be a power of two, but needs to account for | |
1790 | * shifting memory by the 4GB offset required to skip 32bit space. | |
1791 | */ | |
1792 | window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); | |
1793 | tce_count = window_size >> tce_order; | |
1794 | table_size = tce_count << 3; | |
1795 | ||
1796 | if (table_size < PAGE_SIZE) | |
1797 | table_size = PAGE_SIZE; | |
1798 | ||
1799 | table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, | |
1800 | get_order(table_size)); | |
1801 | if (!table_pages) | |
1802 | goto err; | |
1803 | ||
1804 | tces = page_address(table_pages); | |
1805 | if (!tces) | |
1806 | goto err; | |
1807 | ||
1808 | memset(tces, 0, table_size); | |
1809 | ||
1810 | for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { | |
1811 | tces[(addr + (1ULL << 32)) >> tce_order] = | |
1812 | cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); | |
1813 | } | |
1814 | ||
1815 | rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, | |
1816 | pe->pe_number, | |
1817 | /* reconfigure window 0 */ | |
1818 | (pe->pe_number << 1) + 0, | |
1819 | 1, | |
1820 | __pa(tces), | |
1821 | table_size, | |
1822 | 1 << tce_order); | |
1823 | if (rc == OPAL_SUCCESS) { | |
1824 | pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); | |
1825 | return 0; | |
1826 | } | |
1827 | err: | |
1828 | pe_err(pe, "Error configuring 64-bit DMA bypass\n"); | |
1829 | return -EIO; | |
1830 | } | |
1831 | ||
763d2d8d | 1832 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
cd15b048 | 1833 | { |
763d2d8d DA |
1834 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1835 | struct pnv_phb *phb = hose->private_data; | |
cd15b048 BH |
1836 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1837 | struct pnv_ioda_pe *pe; | |
1838 | uint64_t top; | |
1839 | bool bypass = false; | |
8e3f1b1d | 1840 | s64 rc; |
cd15b048 BH |
1841 | |
1842 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1843 | return -ENODEV;; | |
1844 | ||
1845 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1846 | if (pe->tce_bypass_enabled) { | |
1847 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; | |
1848 | bypass = (dma_mask >= top); | |
1849 | } | |
1850 | ||
1851 | if (bypass) { | |
1852 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); | |
1853 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
cd15b048 | 1854 | } else { |
8e3f1b1d RC |
1855 | /* |
1856 | * If the device can't set the TCE bypass bit but still wants | |
1857 | * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to | |
1858 | * bypass the 32-bit region and be usable for 64-bit DMAs. | |
1859 | * The device needs to be able to address all of this space. | |
1860 | */ | |
1861 | if (dma_mask >> 32 && | |
1862 | dma_mask > (memory_hotplug_max() + (1ULL << 32)) && | |
1863 | pnv_pci_ioda_pe_single_vendor(pe) && | |
1864 | phb->model == PNV_PHB_MODEL_PHB3) { | |
1865 | /* Configure the bypass mode */ | |
1866 | rc = pnv_pci_ioda_dma_64bit_bypass(pe); | |
1867 | if (rc) | |
1868 | return rc; | |
1869 | /* 4GB offset bypasses 32-bit space */ | |
1870 | set_dma_offset(&pdev->dev, (1ULL << 32)); | |
1871 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
253fd51e AP |
1872 | } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { |
1873 | /* | |
1874 | * Fail the request if a DMA mask between 32 and 64 bits | |
1875 | * was requested but couldn't be fulfilled. Ideally we | |
1876 | * would do this for 64-bits but historically we have | |
1877 | * always fallen back to 32-bits. | |
1878 | */ | |
1879 | return -ENOMEM; | |
8e3f1b1d RC |
1880 | } else { |
1881 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | |
1882 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | |
1883 | } | |
cd15b048 | 1884 | } |
a32305bf | 1885 | *pdev->dev.dma_mask = dma_mask; |
5d2aa710 AP |
1886 | |
1887 | /* Update peer npu devices */ | |
f9f83456 | 1888 | pnv_npu_try_dma_set_bypass(pdev, bypass); |
5d2aa710 | 1889 | |
cd15b048 BH |
1890 | return 0; |
1891 | } | |
1892 | ||
53522982 | 1893 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) |
fe7e85c6 | 1894 | { |
53522982 AD |
1895 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1896 | struct pnv_phb *phb = hose->private_data; | |
fe7e85c6 GS |
1897 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1898 | struct pnv_ioda_pe *pe; | |
1899 | u64 end, mask; | |
1900 | ||
1901 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1902 | return 0; | |
1903 | ||
1904 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1905 | if (!pe->tce_bypass_enabled) | |
1906 | return __dma_get_required_mask(&pdev->dev); | |
1907 | ||
1908 | ||
1909 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); | |
1910 | mask = 1ULL << (fls64(end) - 1); | |
1911 | mask += mask - 1; | |
1912 | ||
1913 | return mask; | |
1914 | } | |
1915 | ||
dff4a39e | 1916 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
db08e1d5 AK |
1917 | struct pci_bus *bus, |
1918 | bool add_to_group) | |
74251fe2 BH |
1919 | { |
1920 | struct pci_dev *dev; | |
1921 | ||
1922 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b348aa65 | 1923 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
e91c2511 | 1924 | set_dma_offset(&dev->dev, pe->tce_bypass_base); |
db08e1d5 AK |
1925 | if (add_to_group) |
1926 | iommu_add_device(&dev->dev); | |
dff4a39e | 1927 | |
5c89a87d | 1928 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
db08e1d5 AK |
1929 | pnv_ioda_setup_bus_dma(pe, dev->subordinate, |
1930 | add_to_group); | |
74251fe2 BH |
1931 | } |
1932 | } | |
1933 | ||
fd141d1a BH |
1934 | static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, |
1935 | bool real_mode) | |
1936 | { | |
1937 | return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : | |
1938 | (phb->regs + 0x210); | |
1939 | } | |
1940 | ||
a34ab7c3 | 1941 | static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, |
decbda25 | 1942 | unsigned long index, unsigned long npages, bool rm) |
4cce9550 | 1943 | { |
0eaf4def AK |
1944 | struct iommu_table_group_link *tgl = list_first_entry_or_null( |
1945 | &tbl->it_group_list, struct iommu_table_group_link, | |
1946 | next); | |
1947 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, | |
b348aa65 | 1948 | struct pnv_ioda_pe, table_group); |
fd141d1a | 1949 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
4cce9550 GS |
1950 | unsigned long start, end, inc; |
1951 | ||
decbda25 AK |
1952 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
1953 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + | |
1954 | npages - 1); | |
4cce9550 | 1955 | |
08acce1c BH |
1956 | /* p7ioc-style invalidation, 2 TCEs per write */ |
1957 | start |= (1ull << 63); | |
1958 | end |= (1ull << 63); | |
1959 | inc = 16; | |
4cce9550 GS |
1960 | end |= inc - 1; /* round up end to be different than start */ |
1961 | ||
1962 | mb(); /* Ensure above stores are visible */ | |
1963 | while (start <= end) { | |
8e0a1611 | 1964 | if (rm) |
3ad26e5c | 1965 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1966 | else |
3ad26e5c | 1967 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1968 | start += inc; |
1969 | } | |
1970 | ||
1971 | /* | |
1972 | * The iommu layer will do another mb() for us on build() | |
1973 | * and we don't care on free() | |
1974 | */ | |
1975 | } | |
1976 | ||
decbda25 AK |
1977 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
1978 | long npages, unsigned long uaddr, | |
1979 | enum dma_data_direction direction, | |
00085f1e | 1980 | unsigned long attrs) |
decbda25 AK |
1981 | { |
1982 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, | |
1983 | attrs); | |
1984 | ||
08acce1c | 1985 | if (!ret) |
a34ab7c3 | 1986 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
decbda25 AK |
1987 | |
1988 | return ret; | |
1989 | } | |
1990 | ||
05c6cfb9 AK |
1991 | #ifdef CONFIG_IOMMU_API |
1992 | static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, | |
1993 | unsigned long *hpa, enum dma_data_direction *direction) | |
1994 | { | |
1995 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1996 | ||
08acce1c | 1997 | if (!ret) |
a34ab7c3 | 1998 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); |
05c6cfb9 AK |
1999 | |
2000 | return ret; | |
2001 | } | |
a540aa56 AK |
2002 | |
2003 | static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, | |
2004 | unsigned long *hpa, enum dma_data_direction *direction) | |
2005 | { | |
2006 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
2007 | ||
2008 | if (!ret) | |
2009 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); | |
2010 | ||
2011 | return ret; | |
2012 | } | |
05c6cfb9 AK |
2013 | #endif |
2014 | ||
decbda25 AK |
2015 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, |
2016 | long npages) | |
2017 | { | |
2018 | pnv_tce_free(tbl, index, npages); | |
2019 | ||
08acce1c | 2020 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
decbda25 AK |
2021 | } |
2022 | ||
da004c36 | 2023 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
decbda25 | 2024 | .set = pnv_ioda1_tce_build, |
05c6cfb9 AK |
2025 | #ifdef CONFIG_IOMMU_API |
2026 | .exchange = pnv_ioda1_tce_xchg, | |
a540aa56 | 2027 | .exchange_rm = pnv_ioda1_tce_xchg_rm, |
05c6cfb9 | 2028 | #endif |
decbda25 | 2029 | .clear = pnv_ioda1_tce_free, |
da004c36 AK |
2030 | .get = pnv_tce_get, |
2031 | }; | |
2032 | ||
a34ab7c3 BH |
2033 | #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) |
2034 | #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) | |
2035 | #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) | |
bef9253f | 2036 | |
6b3d12a9 | 2037 | static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
0bbcdb43 | 2038 | { |
fd141d1a | 2039 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); |
a34ab7c3 | 2040 | const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; |
0bbcdb43 AK |
2041 | |
2042 | mb(); /* Ensure previous TCE table stores are visible */ | |
2043 | if (rm) | |
fd141d1a | 2044 | __raw_rm_writeq(cpu_to_be64(val), invalidate); |
0bbcdb43 | 2045 | else |
fd141d1a | 2046 | __raw_writeq(cpu_to_be64(val), invalidate); |
0bbcdb43 AK |
2047 | } |
2048 | ||
a34ab7c3 | 2049 | static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
5780fb04 AK |
2050 | { |
2051 | /* 01xb - invalidate TCEs that match the specified PE# */ | |
fd141d1a | 2052 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); |
a34ab7c3 | 2053 | unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); |
5780fb04 AK |
2054 | |
2055 | mb(); /* Ensure above stores are visible */ | |
fd141d1a | 2056 | __raw_writeq(cpu_to_be64(val), invalidate); |
5780fb04 AK |
2057 | } |
2058 | ||
fd141d1a BH |
2059 | static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, |
2060 | unsigned shift, unsigned long index, | |
2061 | unsigned long npages) | |
4cce9550 | 2062 | { |
4d902195 | 2063 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
4cce9550 | 2064 | unsigned long start, end, inc; |
4cce9550 GS |
2065 | |
2066 | /* We'll invalidate DMA address in PE scope */ | |
a34ab7c3 | 2067 | start = PHB3_TCE_KILL_INVAL_ONE; |
fd141d1a | 2068 | start |= (pe->pe_number & 0xFF); |
4cce9550 GS |
2069 | end = start; |
2070 | ||
2071 | /* Figure out the start, end and step */ | |
decbda25 AK |
2072 | start |= (index << shift); |
2073 | end |= ((index + npages - 1) << shift); | |
b0376c9b | 2074 | inc = (0x1ull << shift); |
4cce9550 GS |
2075 | mb(); |
2076 | ||
2077 | while (start <= end) { | |
8e0a1611 | 2078 | if (rm) |
3ad26e5c | 2079 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 2080 | else |
3ad26e5c | 2081 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
2082 | start += inc; |
2083 | } | |
2084 | } | |
2085 | ||
f0228c41 BH |
2086 | static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
2087 | { | |
2088 | struct pnv_phb *phb = pe->phb; | |
2089 | ||
2090 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) | |
2091 | pnv_pci_phb3_tce_invalidate_pe(pe); | |
2092 | else | |
2093 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, | |
2094 | pe->pe_number, 0, 0, 0); | |
2095 | } | |
2096 | ||
e57080f1 AK |
2097 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
2098 | unsigned long index, unsigned long npages, bool rm) | |
2099 | { | |
2100 | struct iommu_table_group_link *tgl; | |
2101 | ||
a540aa56 | 2102 | list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { |
e57080f1 AK |
2103 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
2104 | struct pnv_ioda_pe, table_group); | |
f0228c41 BH |
2105 | struct pnv_phb *phb = pe->phb; |
2106 | unsigned int shift = tbl->it_page_shift; | |
2107 | ||
616badd2 AP |
2108 | /* |
2109 | * NVLink1 can use the TCE kill register directly as | |
2110 | * it's the same as PHB3. NVLink2 is different and | |
2111 | * should go via the OPAL call. | |
2112 | */ | |
2113 | if (phb->model == PNV_PHB_MODEL_NPU) { | |
0bbcdb43 AK |
2114 | /* |
2115 | * The NVLink hardware does not support TCE kill | |
2116 | * per TCE entry so we have to invalidate | |
2117 | * the entire cache for it. | |
2118 | */ | |
f0228c41 | 2119 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); |
85674868 AK |
2120 | continue; |
2121 | } | |
f0228c41 BH |
2122 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) |
2123 | pnv_pci_phb3_tce_invalidate(pe, rm, shift, | |
2124 | index, npages); | |
f0228c41 BH |
2125 | else |
2126 | opal_pci_tce_kill(phb->opal_id, | |
2127 | OPAL_PCI_TCE_KILL_PAGES, | |
2128 | pe->pe_number, 1u << shift, | |
2129 | index << shift, npages); | |
e57080f1 AK |
2130 | } |
2131 | } | |
2132 | ||
6b3d12a9 AP |
2133 | void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
2134 | { | |
2135 | if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) | |
2136 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); | |
2137 | else | |
2138 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); | |
2139 | } | |
2140 | ||
decbda25 AK |
2141 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
2142 | long npages, unsigned long uaddr, | |
2143 | enum dma_data_direction direction, | |
00085f1e | 2144 | unsigned long attrs) |
4cce9550 | 2145 | { |
decbda25 AK |
2146 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
2147 | attrs); | |
4cce9550 | 2148 | |
08acce1c | 2149 | if (!ret) |
decbda25 AK |
2150 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
2151 | ||
2152 | return ret; | |
2153 | } | |
2154 | ||
05c6cfb9 AK |
2155 | #ifdef CONFIG_IOMMU_API |
2156 | static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, | |
2157 | unsigned long *hpa, enum dma_data_direction *direction) | |
2158 | { | |
2159 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
2160 | ||
08acce1c | 2161 | if (!ret) |
05c6cfb9 AK |
2162 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); |
2163 | ||
2164 | return ret; | |
2165 | } | |
a540aa56 AK |
2166 | |
2167 | static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, | |
2168 | unsigned long *hpa, enum dma_data_direction *direction) | |
2169 | { | |
2170 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
2171 | ||
2172 | if (!ret) | |
2173 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); | |
2174 | ||
2175 | return ret; | |
2176 | } | |
05c6cfb9 AK |
2177 | #endif |
2178 | ||
decbda25 AK |
2179 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, |
2180 | long npages) | |
2181 | { | |
2182 | pnv_tce_free(tbl, index, npages); | |
2183 | ||
08acce1c | 2184 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
4cce9550 GS |
2185 | } |
2186 | ||
4793d65d AK |
2187 | static void pnv_ioda2_table_free(struct iommu_table *tbl) |
2188 | { | |
2189 | pnv_pci_ioda2_table_free_pages(tbl); | |
4793d65d AK |
2190 | } |
2191 | ||
da004c36 | 2192 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
decbda25 | 2193 | .set = pnv_ioda2_tce_build, |
05c6cfb9 AK |
2194 | #ifdef CONFIG_IOMMU_API |
2195 | .exchange = pnv_ioda2_tce_xchg, | |
a540aa56 | 2196 | .exchange_rm = pnv_ioda2_tce_xchg_rm, |
05c6cfb9 | 2197 | #endif |
decbda25 | 2198 | .clear = pnv_ioda2_tce_free, |
da004c36 | 2199 | .get = pnv_tce_get, |
4793d65d | 2200 | .free = pnv_ioda2_table_free, |
da004c36 AK |
2201 | }; |
2202 | ||
801846d1 GS |
2203 | static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) |
2204 | { | |
2205 | unsigned int *weight = (unsigned int *)data; | |
2206 | ||
2207 | /* This is quite simplistic. The "base" weight of a device | |
2208 | * is 10. 0 means no DMA is to be accounted for it. | |
2209 | */ | |
2210 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
2211 | return 0; | |
2212 | ||
2213 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
2214 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
2215 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
2216 | *weight += 3; | |
2217 | else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
2218 | *weight += 15; | |
2219 | else | |
2220 | *weight += 10; | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
2225 | static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) | |
2226 | { | |
2227 | unsigned int weight = 0; | |
2228 | ||
2229 | /* SRIOV VF has same DMA32 weight as its PF */ | |
2230 | #ifdef CONFIG_PCI_IOV | |
2231 | if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { | |
2232 | pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); | |
2233 | return weight; | |
2234 | } | |
2235 | #endif | |
2236 | ||
2237 | if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { | |
2238 | pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); | |
2239 | } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { | |
2240 | struct pci_dev *pdev; | |
2241 | ||
2242 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) | |
2243 | pnv_pci_ioda_dev_dma_weight(pdev, &weight); | |
2244 | } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { | |
2245 | pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); | |
2246 | } | |
2247 | ||
2248 | return weight; | |
2249 | } | |
2250 | ||
b30d936f | 2251 | static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, |
2b923ed1 | 2252 | struct pnv_ioda_pe *pe) |
184cd4a3 BH |
2253 | { |
2254 | ||
2255 | struct page *tce_mem = NULL; | |
184cd4a3 | 2256 | struct iommu_table *tbl; |
2b923ed1 GS |
2257 | unsigned int weight, total_weight = 0; |
2258 | unsigned int tce32_segsz, base, segs, avail, i; | |
184cd4a3 BH |
2259 | int64_t rc; |
2260 | void *addr; | |
2261 | ||
184cd4a3 BH |
2262 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
2263 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
2264 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
2b923ed1 GS |
2265 | weight = pnv_pci_ioda_pe_dma_weight(pe); |
2266 | if (!weight) | |
2267 | return; | |
2268 | ||
2269 | pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, | |
2270 | &total_weight); | |
2271 | segs = (weight * phb->ioda.dma32_count) / total_weight; | |
2272 | if (!segs) | |
2273 | segs = 1; | |
184cd4a3 | 2274 | |
2b923ed1 GS |
2275 | /* |
2276 | * Allocate contiguous DMA32 segments. We begin with the expected | |
2277 | * number of segments. With one more attempt, the number of DMA32 | |
2278 | * segments to be allocated is decreased by one until one segment | |
2279 | * is allocated successfully. | |
2280 | */ | |
2281 | do { | |
2282 | for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { | |
2283 | for (avail = 0, i = base; i < base + segs; i++) { | |
2284 | if (phb->ioda.dma32_segmap[i] == | |
2285 | IODA_INVALID_PE) | |
2286 | avail++; | |
2287 | } | |
2288 | ||
2289 | if (avail == segs) | |
2290 | goto found; | |
2291 | } | |
2292 | } while (--segs); | |
2293 | ||
2294 | if (!segs) { | |
2295 | pe_warn(pe, "No available DMA32 segments\n"); | |
2296 | return; | |
2297 | } | |
2298 | ||
2299 | found: | |
0eaf4def | 2300 | tbl = pnv_pci_table_alloc(phb->hose->node); |
82eae1af AK |
2301 | if (WARN_ON(!tbl)) |
2302 | return; | |
2303 | ||
b348aa65 AK |
2304 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2305 | pe->pe_number); | |
0eaf4def | 2306 | pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); |
c5773822 | 2307 | |
184cd4a3 | 2308 | /* Grab a 32-bit TCE table */ |
2b923ed1 GS |
2309 | pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", |
2310 | weight, total_weight, base, segs); | |
184cd4a3 | 2311 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", |
acce971c GS |
2312 | base * PNV_IODA1_DMA32_SEGSIZE, |
2313 | (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); | |
184cd4a3 BH |
2314 | |
2315 | /* XXX Currently, we allocate one big contiguous table for the | |
2316 | * TCEs. We only really need one chunk per 256M of TCE space | |
2317 | * (ie per segment) but that's an optimization for later, it | |
2318 | * requires some added smarts with our get/put_tce implementation | |
acce971c GS |
2319 | * |
2320 | * Each TCE page is 4KB in size and each TCE entry occupies 8 | |
2321 | * bytes | |
184cd4a3 | 2322 | */ |
acce971c | 2323 | tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); |
184cd4a3 | 2324 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, |
acce971c | 2325 | get_order(tce32_segsz * segs)); |
184cd4a3 BH |
2326 | if (!tce_mem) { |
2327 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
2328 | goto fail; | |
2329 | } | |
2330 | addr = page_address(tce_mem); | |
acce971c | 2331 | memset(addr, 0, tce32_segsz * segs); |
184cd4a3 BH |
2332 | |
2333 | /* Configure HW */ | |
2334 | for (i = 0; i < segs; i++) { | |
2335 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2336 | pe->pe_number, | |
2337 | base + i, 1, | |
acce971c GS |
2338 | __pa(addr) + tce32_segsz * i, |
2339 | tce32_segsz, IOMMU_PAGE_SIZE_4K); | |
184cd4a3 BH |
2340 | if (rc) { |
2341 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
2342 | " err %ld\n", rc); | |
2343 | goto fail; | |
2344 | } | |
2345 | } | |
2346 | ||
2b923ed1 GS |
2347 | /* Setup DMA32 segment mapping */ |
2348 | for (i = base; i < base + segs; i++) | |
2349 | phb->ioda.dma32_segmap[i] = pe->pe_number; | |
2350 | ||
184cd4a3 | 2351 | /* Setup linux iommu table */ |
acce971c GS |
2352 | pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, |
2353 | base * PNV_IODA1_DMA32_SEGSIZE, | |
2354 | IOMMU_PAGE_SHIFT_4K); | |
184cd4a3 | 2355 | |
da004c36 | 2356 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
4793d65d AK |
2357 | pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; |
2358 | pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; | |
184cd4a3 BH |
2359 | iommu_init_table(tbl, phb->hose->node); |
2360 | ||
781a868f | 2361 | if (pe->flags & PNV_IODA_PE_DEV) { |
4617082e AK |
2362 | /* |
2363 | * Setting table base here only for carrying iommu_group | |
2364 | * further down to let iommu_add_device() do the job. | |
2365 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2366 | */ | |
2367 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2368 | iommu_add_device(&pe->pdev->dev); | |
c5773822 | 2369 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
db08e1d5 | 2370 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
74251fe2 | 2371 | |
184cd4a3 BH |
2372 | return; |
2373 | fail: | |
2374 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
184cd4a3 | 2375 | if (tce_mem) |
acce971c | 2376 | __free_pages(tce_mem, get_order(tce32_segsz * segs)); |
0eaf4def AK |
2377 | if (tbl) { |
2378 | pnv_pci_unlink_table_and_group(tbl, &pe->table_group); | |
e5afdf9d | 2379 | iommu_tce_table_put(tbl); |
0eaf4def | 2380 | } |
184cd4a3 BH |
2381 | } |
2382 | ||
43cb60ab AK |
2383 | static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, |
2384 | int num, struct iommu_table *tbl) | |
2385 | { | |
2386 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2387 | table_group); | |
2388 | struct pnv_phb *phb = pe->phb; | |
2389 | int64_t rc; | |
bbb845c4 AK |
2390 | const unsigned long size = tbl->it_indirect_levels ? |
2391 | tbl->it_level_size : tbl->it_size; | |
43cb60ab AK |
2392 | const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
2393 | const __u64 win_size = tbl->it_size << tbl->it_page_shift; | |
2394 | ||
4793d65d | 2395 | pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, |
43cb60ab AK |
2396 | start_addr, start_addr + win_size - 1, |
2397 | IOMMU_PAGE_SIZE(tbl)); | |
2398 | ||
2399 | /* | |
2400 | * Map TCE table through TVT. The TVE index is the PE number | |
2401 | * shifted by 1 bit for 32-bits DMA space. | |
2402 | */ | |
2403 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2404 | pe->pe_number, | |
4793d65d | 2405 | (pe->pe_number << 1) + num, |
bbb845c4 | 2406 | tbl->it_indirect_levels + 1, |
43cb60ab | 2407 | __pa(tbl->it_base), |
bbb845c4 | 2408 | size << 3, |
43cb60ab AK |
2409 | IOMMU_PAGE_SIZE(tbl)); |
2410 | if (rc) { | |
2411 | pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); | |
2412 | return rc; | |
2413 | } | |
2414 | ||
2415 | pnv_pci_link_table_and_group(phb->hose->node, num, | |
2416 | tbl, &pe->table_group); | |
ed7d9a1d | 2417 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
43cb60ab AK |
2418 | |
2419 | return 0; | |
2420 | } | |
2421 | ||
25529100 | 2422 | void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) |
cd15b048 | 2423 | { |
cd15b048 BH |
2424 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
2425 | int64_t rc; | |
2426 | ||
2427 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); | |
2428 | if (enable) { | |
2429 | phys_addr_t top = memblock_end_of_DRAM(); | |
2430 | ||
2431 | top = roundup_pow_of_two(top); | |
2432 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2433 | pe->pe_number, | |
2434 | window_id, | |
2435 | pe->tce_bypass_base, | |
2436 | top); | |
2437 | } else { | |
2438 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2439 | pe->pe_number, | |
2440 | window_id, | |
2441 | pe->tce_bypass_base, | |
2442 | 0); | |
cd15b048 BH |
2443 | } |
2444 | if (rc) | |
2445 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); | |
2446 | else | |
2447 | pe->tce_bypass_enabled = enable; | |
2448 | } | |
2449 | ||
4793d65d AK |
2450 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
2451 | __u32 page_shift, __u64 window_size, __u32 levels, | |
2452 | struct iommu_table *tbl); | |
2453 | ||
2454 | static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, | |
2455 | int num, __u32 page_shift, __u64 window_size, __u32 levels, | |
2456 | struct iommu_table **ptbl) | |
2457 | { | |
2458 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2459 | table_group); | |
2460 | int nid = pe->phb->hose->node; | |
2461 | __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; | |
2462 | long ret; | |
2463 | struct iommu_table *tbl; | |
2464 | ||
2465 | tbl = pnv_pci_table_alloc(nid); | |
2466 | if (!tbl) | |
2467 | return -ENOMEM; | |
2468 | ||
11edf116 AK |
2469 | tbl->it_ops = &pnv_ioda2_iommu_ops; |
2470 | ||
4793d65d AK |
2471 | ret = pnv_pci_ioda2_table_alloc_pages(nid, |
2472 | bus_offset, page_shift, window_size, | |
2473 | levels, tbl); | |
2474 | if (ret) { | |
e5afdf9d | 2475 | iommu_tce_table_put(tbl); |
4793d65d AK |
2476 | return ret; |
2477 | } | |
2478 | ||
4793d65d AK |
2479 | *ptbl = tbl; |
2480 | ||
2481 | return 0; | |
2482 | } | |
2483 | ||
46d3e1e1 AK |
2484 | static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) |
2485 | { | |
2486 | struct iommu_table *tbl = NULL; | |
2487 | long rc; | |
2488 | ||
fa144869 NA |
2489 | /* |
2490 | * crashkernel= specifies the kdump kernel's maximum memory at | |
2491 | * some offset and there is no guaranteed the result is a power | |
2492 | * of 2, which will cause errors later. | |
2493 | */ | |
2494 | const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); | |
2495 | ||
bb005455 NA |
2496 | /* |
2497 | * In memory constrained environments, e.g. kdump kernel, the | |
2498 | * DMA window can be larger than available memory, which will | |
2499 | * cause errors later. | |
2500 | */ | |
fa144869 | 2501 | const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); |
bb005455 | 2502 | |
46d3e1e1 AK |
2503 | rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, |
2504 | IOMMU_PAGE_SHIFT_4K, | |
bb005455 | 2505 | window_size, |
46d3e1e1 AK |
2506 | POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); |
2507 | if (rc) { | |
2508 | pe_err(pe, "Failed to create 32-bit TCE table, err %ld", | |
2509 | rc); | |
2510 | return rc; | |
2511 | } | |
2512 | ||
2513 | iommu_init_table(tbl, pe->phb->hose->node); | |
2514 | ||
2515 | rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); | |
2516 | if (rc) { | |
2517 | pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", | |
2518 | rc); | |
e5afdf9d | 2519 | iommu_tce_table_put(tbl); |
46d3e1e1 AK |
2520 | return rc; |
2521 | } | |
2522 | ||
2523 | if (!pnv_iommu_bypass_disabled) | |
2524 | pnv_pci_ioda2_set_bypass(pe, true); | |
2525 | ||
46d3e1e1 AK |
2526 | /* |
2527 | * Setting table base here only for carrying iommu_group | |
2528 | * further down to let iommu_add_device() do the job. | |
2529 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2530 | */ | |
2531 | if (pe->flags & PNV_IODA_PE_DEV) | |
2532 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2533 | ||
2534 | return 0; | |
2535 | } | |
2536 | ||
b5926430 AK |
2537 | #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) |
2538 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, | |
2539 | int num) | |
2540 | { | |
2541 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2542 | table_group); | |
2543 | struct pnv_phb *phb = pe->phb; | |
2544 | long ret; | |
2545 | ||
2546 | pe_info(pe, "Removing DMA window #%d\n", num); | |
2547 | ||
2548 | ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
2549 | (pe->pe_number << 1) + num, | |
2550 | 0/* levels */, 0/* table address */, | |
2551 | 0/* table size */, 0/* page size */); | |
2552 | if (ret) | |
2553 | pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); | |
2554 | else | |
ed7d9a1d | 2555 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
b5926430 AK |
2556 | |
2557 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); | |
2558 | ||
2559 | return ret; | |
2560 | } | |
2561 | #endif | |
2562 | ||
f87a8864 | 2563 | #ifdef CONFIG_IOMMU_API |
00547193 AK |
2564 | static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, |
2565 | __u64 window_size, __u32 levels) | |
2566 | { | |
2567 | unsigned long bytes = 0; | |
2568 | const unsigned window_shift = ilog2(window_size); | |
2569 | unsigned entries_shift = window_shift - page_shift; | |
2570 | unsigned table_shift = entries_shift + 3; | |
2571 | unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); | |
2572 | unsigned long direct_table_size; | |
2573 | ||
2574 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || | |
2575 | (window_size > memory_hotplug_max()) || | |
2576 | !is_power_of_2(window_size)) | |
2577 | return 0; | |
2578 | ||
2579 | /* Calculate a direct table size from window_size and levels */ | |
2580 | entries_shift = (entries_shift + levels - 1) / levels; | |
2581 | table_shift = entries_shift + 3; | |
2582 | table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); | |
2583 | direct_table_size = 1UL << table_shift; | |
2584 | ||
2585 | for ( ; levels; --levels) { | |
2586 | bytes += _ALIGN_UP(tce_table_size, direct_table_size); | |
2587 | ||
2588 | tce_table_size /= direct_table_size; | |
2589 | tce_table_size <<= 3; | |
e49a6a21 AK |
2590 | tce_table_size = max_t(unsigned long, |
2591 | tce_table_size, direct_table_size); | |
00547193 AK |
2592 | } |
2593 | ||
2594 | return bytes; | |
2595 | } | |
2596 | ||
f87a8864 | 2597 | static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) |
cd15b048 | 2598 | { |
f87a8864 AK |
2599 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
2600 | table_group); | |
46d3e1e1 AK |
2601 | /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ |
2602 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
cd15b048 | 2603 | |
f87a8864 | 2604 | pnv_pci_ioda2_set_bypass(pe, false); |
46d3e1e1 | 2605 | pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
db08e1d5 AK |
2606 | if (pe->pbus) |
2607 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); | |
e5afdf9d | 2608 | iommu_tce_table_put(tbl); |
f87a8864 | 2609 | } |
cd15b048 | 2610 | |
f87a8864 AK |
2611 | static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) |
2612 | { | |
2613 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2614 | table_group); | |
2615 | ||
46d3e1e1 | 2616 | pnv_pci_ioda2_setup_default_config(pe); |
db08e1d5 AK |
2617 | if (pe->pbus) |
2618 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); | |
cd15b048 BH |
2619 | } |
2620 | ||
f87a8864 | 2621 | static struct iommu_table_group_ops pnv_pci_ioda2_ops = { |
00547193 | 2622 | .get_table_size = pnv_pci_ioda2_get_table_size, |
4793d65d AK |
2623 | .create_table = pnv_pci_ioda2_create_table, |
2624 | .set_window = pnv_pci_ioda2_set_window, | |
2625 | .unset_window = pnv_pci_ioda2_unset_window, | |
f87a8864 AK |
2626 | .take_ownership = pnv_ioda2_take_ownership, |
2627 | .release_ownership = pnv_ioda2_release_ownership, | |
2628 | }; | |
b5cb9ab1 AK |
2629 | |
2630 | static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) | |
2631 | { | |
2632 | struct pci_controller *hose; | |
2633 | struct pnv_phb *phb; | |
2634 | struct pnv_ioda_pe **ptmppe = opaque; | |
2635 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
2636 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
2637 | ||
2638 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
2639 | return 0; | |
2640 | ||
2641 | hose = pci_bus_to_host(pdev->bus); | |
2642 | phb = hose->private_data; | |
2643 | if (phb->type != PNV_PHB_NPU) | |
2644 | return 0; | |
2645 | ||
2646 | *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; | |
2647 | ||
2648 | return 1; | |
2649 | } | |
2650 | ||
2651 | /* | |
2652 | * This returns PE of associated NPU. | |
2653 | * This assumes that NPU is in the same IOMMU group with GPU and there is | |
2654 | * no other PEs. | |
2655 | */ | |
2656 | static struct pnv_ioda_pe *gpe_table_group_to_npe( | |
2657 | struct iommu_table_group *table_group) | |
2658 | { | |
2659 | struct pnv_ioda_pe *npe = NULL; | |
2660 | int ret = iommu_group_for_each_dev(table_group->group, &npe, | |
2661 | gpe_table_group_to_npe_cb); | |
2662 | ||
2663 | BUG_ON(!ret || !npe); | |
2664 | ||
2665 | return npe; | |
2666 | } | |
2667 | ||
2668 | static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, | |
2669 | int num, struct iommu_table *tbl) | |
2670 | { | |
2671 | long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); | |
2672 | ||
2673 | if (ret) | |
2674 | return ret; | |
2675 | ||
2676 | ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); | |
2677 | if (ret) | |
2678 | pnv_pci_ioda2_unset_window(table_group, num); | |
2679 | ||
2680 | return ret; | |
2681 | } | |
2682 | ||
2683 | static long pnv_pci_ioda2_npu_unset_window( | |
2684 | struct iommu_table_group *table_group, | |
2685 | int num) | |
2686 | { | |
2687 | long ret = pnv_pci_ioda2_unset_window(table_group, num); | |
2688 | ||
2689 | if (ret) | |
2690 | return ret; | |
2691 | ||
2692 | return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); | |
2693 | } | |
2694 | ||
2695 | static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) | |
2696 | { | |
2697 | /* | |
2698 | * Detach NPU first as pnv_ioda2_take_ownership() will destroy | |
2699 | * the iommu_table if 32bit DMA is enabled. | |
2700 | */ | |
2701 | pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); | |
2702 | pnv_ioda2_take_ownership(table_group); | |
2703 | } | |
2704 | ||
2705 | static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { | |
2706 | .get_table_size = pnv_pci_ioda2_get_table_size, | |
2707 | .create_table = pnv_pci_ioda2_create_table, | |
2708 | .set_window = pnv_pci_ioda2_npu_set_window, | |
2709 | .unset_window = pnv_pci_ioda2_npu_unset_window, | |
2710 | .take_ownership = pnv_ioda2_npu_take_ownership, | |
2711 | .release_ownership = pnv_ioda2_release_ownership, | |
2712 | }; | |
2713 | ||
2714 | static void pnv_pci_ioda_setup_iommu_api(void) | |
2715 | { | |
2716 | struct pci_controller *hose, *tmp; | |
2717 | struct pnv_phb *phb; | |
2718 | struct pnv_ioda_pe *pe, *gpe; | |
2719 | ||
2720 | /* | |
2721 | * Now we have all PHBs discovered, time to add NPU devices to | |
2722 | * the corresponding IOMMU groups. | |
2723 | */ | |
2724 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
2725 | phb = hose->private_data; | |
2726 | ||
2727 | if (phb->type != PNV_PHB_NPU) | |
2728 | continue; | |
2729 | ||
2730 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
2731 | gpe = pnv_pci_npu_setup_iommu(pe); | |
2732 | if (gpe) | |
2733 | gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; | |
2734 | } | |
2735 | } | |
2736 | } | |
2737 | #else /* !CONFIG_IOMMU_API */ | |
2738 | static void pnv_pci_ioda_setup_iommu_api(void) { }; | |
f87a8864 AK |
2739 | #endif |
2740 | ||
bbb845c4 AK |
2741 | static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, |
2742 | unsigned levels, unsigned long limit, | |
3ba3a73e | 2743 | unsigned long *current_offset, unsigned long *total_allocated) |
373f5657 GS |
2744 | { |
2745 | struct page *tce_mem = NULL; | |
bbb845c4 | 2746 | __be64 *addr, *tmp; |
aca6913f | 2747 | unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; |
bbb845c4 AK |
2748 | unsigned long allocated = 1UL << (order + PAGE_SHIFT); |
2749 | unsigned entries = 1UL << (shift - 3); | |
2750 | long i; | |
aca6913f AK |
2751 | |
2752 | tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); | |
2753 | if (!tce_mem) { | |
2754 | pr_err("Failed to allocate a TCE memory, order=%d\n", order); | |
2755 | return NULL; | |
2756 | } | |
2757 | addr = page_address(tce_mem); | |
bbb845c4 | 2758 | memset(addr, 0, allocated); |
3ba3a73e | 2759 | *total_allocated += allocated; |
bbb845c4 AK |
2760 | |
2761 | --levels; | |
2762 | if (!levels) { | |
2763 | *current_offset += allocated; | |
2764 | return addr; | |
2765 | } | |
2766 | ||
2767 | for (i = 0; i < entries; ++i) { | |
2768 | tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, | |
3ba3a73e | 2769 | levels, limit, current_offset, total_allocated); |
bbb845c4 AK |
2770 | if (!tmp) |
2771 | break; | |
2772 | ||
2773 | addr[i] = cpu_to_be64(__pa(tmp) | | |
2774 | TCE_PCI_READ | TCE_PCI_WRITE); | |
2775 | ||
2776 | if (*current_offset >= limit) | |
2777 | break; | |
2778 | } | |
aca6913f AK |
2779 | |
2780 | return addr; | |
2781 | } | |
2782 | ||
bbb845c4 AK |
2783 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2784 | unsigned long size, unsigned level); | |
2785 | ||
aca6913f | 2786 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
bbb845c4 AK |
2787 | __u32 page_shift, __u64 window_size, __u32 levels, |
2788 | struct iommu_table *tbl) | |
aca6913f | 2789 | { |
373f5657 | 2790 | void *addr; |
3ba3a73e | 2791 | unsigned long offset = 0, level_shift, total_allocated = 0; |
aca6913f AK |
2792 | const unsigned window_shift = ilog2(window_size); |
2793 | unsigned entries_shift = window_shift - page_shift; | |
2794 | unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); | |
2795 | const unsigned long tce_table_size = 1UL << table_shift; | |
2796 | ||
bbb845c4 AK |
2797 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) |
2798 | return -EINVAL; | |
2799 | ||
9003a249 | 2800 | if (!is_power_of_2(window_size)) |
aca6913f AK |
2801 | return -EINVAL; |
2802 | ||
bbb845c4 AK |
2803 | /* Adjust direct table size from window_size and levels */ |
2804 | entries_shift = (entries_shift + levels - 1) / levels; | |
2805 | level_shift = entries_shift + 3; | |
2806 | level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); | |
2807 | ||
7aafac11 AK |
2808 | if ((level_shift - 3) * levels + page_shift >= 60) |
2809 | return -EINVAL; | |
2810 | ||
aca6913f | 2811 | /* Allocate TCE table */ |
bbb845c4 | 2812 | addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, |
3ba3a73e | 2813 | levels, tce_table_size, &offset, &total_allocated); |
bbb845c4 AK |
2814 | |
2815 | /* addr==NULL means that the first level allocation failed */ | |
aca6913f AK |
2816 | if (!addr) |
2817 | return -ENOMEM; | |
2818 | ||
bbb845c4 AK |
2819 | /* |
2820 | * First level was allocated but some lower level failed as | |
2821 | * we did not allocate as much as we wanted, | |
2822 | * release partially allocated table. | |
2823 | */ | |
2824 | if (offset < tce_table_size) { | |
2825 | pnv_pci_ioda2_table_do_free_pages(addr, | |
2826 | 1ULL << (level_shift - 3), levels - 1); | |
2827 | return -ENOMEM; | |
2828 | } | |
2829 | ||
aca6913f AK |
2830 | /* Setup linux iommu table */ |
2831 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, | |
2832 | page_shift); | |
bbb845c4 AK |
2833 | tbl->it_level_size = 1ULL << (level_shift - 3); |
2834 | tbl->it_indirect_levels = levels - 1; | |
3ba3a73e | 2835 | tbl->it_allocated_size = total_allocated; |
aca6913f AK |
2836 | |
2837 | pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", | |
2838 | window_size, tce_table_size, bus_offset); | |
2839 | ||
2840 | return 0; | |
2841 | } | |
2842 | ||
bbb845c4 AK |
2843 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2844 | unsigned long size, unsigned level) | |
2845 | { | |
2846 | const unsigned long addr_ul = (unsigned long) addr & | |
2847 | ~(TCE_PCI_READ | TCE_PCI_WRITE); | |
2848 | ||
2849 | if (level) { | |
2850 | long i; | |
2851 | u64 *tmp = (u64 *) addr_ul; | |
2852 | ||
2853 | for (i = 0; i < size; ++i) { | |
2854 | unsigned long hpa = be64_to_cpu(tmp[i]); | |
2855 | ||
2856 | if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) | |
2857 | continue; | |
2858 | ||
2859 | pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, | |
2860 | level - 1); | |
2861 | } | |
2862 | } | |
2863 | ||
2864 | free_pages(addr_ul, get_order(size << 3)); | |
2865 | } | |
2866 | ||
aca6913f AK |
2867 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) |
2868 | { | |
bbb845c4 AK |
2869 | const unsigned long size = tbl->it_indirect_levels ? |
2870 | tbl->it_level_size : tbl->it_size; | |
2871 | ||
aca6913f AK |
2872 | if (!tbl->it_size) |
2873 | return; | |
2874 | ||
bbb845c4 AK |
2875 | pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, |
2876 | tbl->it_indirect_levels); | |
aca6913f AK |
2877 | } |
2878 | ||
2879 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
2880 | struct pnv_ioda_pe *pe) | |
2881 | { | |
373f5657 GS |
2882 | int64_t rc; |
2883 | ||
ccd1c191 GS |
2884 | if (!pnv_pci_ioda_pe_dma_weight(pe)) |
2885 | return; | |
2886 | ||
f87a8864 AK |
2887 | /* TVE #1 is selected by PCI address bit 59 */ |
2888 | pe->tce_bypass_base = 1ull << 59; | |
2889 | ||
b348aa65 AK |
2890 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2891 | pe->pe_number); | |
c5773822 | 2892 | |
373f5657 | 2893 | /* The PE will reserve all possible 32-bits space */ |
373f5657 | 2894 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", |
aca6913f | 2895 | phb->ioda.m32_pci_base); |
373f5657 | 2896 | |
aca6913f | 2897 | /* Setup linux iommu table */ |
4793d65d AK |
2898 | pe->table_group.tce32_start = 0; |
2899 | pe->table_group.tce32_size = phb->ioda.m32_pci_base; | |
2900 | pe->table_group.max_dynamic_windows_supported = | |
2901 | IOMMU_TABLE_GROUP_MAX_TABLES; | |
2902 | pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; | |
2903 | pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; | |
e5aad1e6 AK |
2904 | #ifdef CONFIG_IOMMU_API |
2905 | pe->table_group.ops = &pnv_pci_ioda2_ops; | |
2906 | #endif | |
2907 | ||
46d3e1e1 | 2908 | rc = pnv_pci_ioda2_setup_default_config(pe); |
801846d1 | 2909 | if (rc) |
46d3e1e1 | 2910 | return; |
373f5657 | 2911 | |
20f13b95 | 2912 | if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
db08e1d5 | 2913 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
373f5657 GS |
2914 | } |
2915 | ||
184cd4a3 | 2916 | #ifdef CONFIG_PCI_MSI |
4ee11c1a | 2917 | int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) |
137436c9 | 2918 | { |
137436c9 GS |
2919 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, |
2920 | ioda.irq_chip); | |
4ee11c1a SW |
2921 | |
2922 | return opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
2923 | } | |
2924 | ||
2925 | static void pnv_ioda2_msi_eoi(struct irq_data *d) | |
2926 | { | |
137436c9 | 2927 | int64_t rc; |
4ee11c1a SW |
2928 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); |
2929 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
137436c9 | 2930 | |
4ee11c1a | 2931 | rc = pnv_opal_pci_msi_eoi(chip, hw_irq); |
137436c9 GS |
2932 | WARN_ON_ONCE(rc); |
2933 | ||
2934 | icp_native_eoi(d); | |
2935 | } | |
2936 | ||
fd9a1c26 | 2937 | |
f456834a | 2938 | void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) |
fd9a1c26 IM |
2939 | { |
2940 | struct irq_data *idata; | |
2941 | struct irq_chip *ichip; | |
2942 | ||
fb111334 BH |
2943 | /* The MSI EOI OPAL call is only needed on PHB3 */ |
2944 | if (phb->model != PNV_PHB_MODEL_PHB3) | |
fd9a1c26 IM |
2945 | return; |
2946 | ||
2947 | if (!phb->ioda.irq_chip_init) { | |
2948 | /* | |
2949 | * First time we setup an MSI IRQ, we need to setup the | |
2950 | * corresponding IRQ chip to route correctly. | |
2951 | */ | |
2952 | idata = irq_get_irq_data(virq); | |
2953 | ichip = irq_data_get_irq_chip(idata); | |
2954 | phb->ioda.irq_chip_init = 1; | |
2955 | phb->ioda.irq_chip = *ichip; | |
2956 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
2957 | } | |
2958 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
2959 | } | |
2960 | ||
4ee11c1a SW |
2961 | /* |
2962 | * Returns true iff chip is something that we could call | |
2963 | * pnv_opal_pci_msi_eoi for. | |
2964 | */ | |
2965 | bool is_pnv_opal_msi(struct irq_chip *chip) | |
2966 | { | |
2967 | return chip->irq_eoi == pnv_ioda2_msi_eoi; | |
2968 | } | |
2969 | EXPORT_SYMBOL_GPL(is_pnv_opal_msi); | |
2970 | ||
184cd4a3 | 2971 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
2972 | unsigned int hwirq, unsigned int virq, |
2973 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
2974 | { |
2975 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
2976 | unsigned int xive_num = hwirq - phb->msi_base; | |
3a1a4661 | 2977 | __be32 data; |
184cd4a3 BH |
2978 | int rc; |
2979 | ||
2980 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
2981 | if (pe == NULL) | |
2982 | return -ENXIO; | |
2983 | ||
2984 | /* Check if we have an MVE */ | |
2985 | if (pe->mve_number < 0) | |
2986 | return -ENXIO; | |
2987 | ||
b72c1f65 | 2988 | /* Force 32-bit MSI on some broken devices */ |
36074381 | 2989 | if (dev->no_64bit_msi) |
b72c1f65 BH |
2990 | is_64 = 0; |
2991 | ||
184cd4a3 BH |
2992 | /* Assign XIVE to PE */ |
2993 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2994 | if (rc) { | |
2995 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
2996 | pci_name(dev), rc, xive_num); | |
2997 | return -EIO; | |
2998 | } | |
2999 | ||
3000 | if (is_64) { | |
3a1a4661 BH |
3001 | __be64 addr64; |
3002 | ||
184cd4a3 BH |
3003 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
3004 | &addr64, &data); | |
3005 | if (rc) { | |
3006 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
3007 | pci_name(dev), rc); | |
3008 | return -EIO; | |
3009 | } | |
3a1a4661 BH |
3010 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
3011 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 3012 | } else { |
3a1a4661 BH |
3013 | __be32 addr32; |
3014 | ||
184cd4a3 BH |
3015 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
3016 | &addr32, &data); | |
3017 | if (rc) { | |
3018 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
3019 | pci_name(dev), rc); | |
3020 | return -EIO; | |
3021 | } | |
3022 | msg->address_hi = 0; | |
3a1a4661 | 3023 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 3024 | } |
3a1a4661 | 3025 | msg->data = be32_to_cpu(data); |
184cd4a3 | 3026 | |
f456834a | 3027 | pnv_set_msi_irq_chip(phb, virq); |
137436c9 | 3028 | |
184cd4a3 | 3029 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
1f52f176 | 3030 | " address=%x_%08x data=%x PE# %x\n", |
184cd4a3 BH |
3031 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, |
3032 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
3033 | ||
3034 | return 0; | |
3035 | } | |
3036 | ||
3037 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
3038 | { | |
fb1b55d6 | 3039 | unsigned int count; |
184cd4a3 BH |
3040 | const __be32 *prop = of_get_property(phb->hose->dn, |
3041 | "ibm,opal-msi-ranges", NULL); | |
3042 | if (!prop) { | |
3043 | /* BML Fallback */ | |
3044 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
3045 | } | |
3046 | if (!prop) | |
3047 | return; | |
3048 | ||
3049 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
3050 | count = be32_to_cpup(prop + 1); |
3051 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
3052 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
3053 | phb->hose->global_number); | |
3054 | return; | |
3055 | } | |
fb1b55d6 | 3056 | |
184cd4a3 BH |
3057 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
3058 | phb->msi32_support = 1; | |
3059 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 3060 | count, phb->msi_base); |
184cd4a3 BH |
3061 | } |
3062 | #else | |
3063 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
3064 | #endif /* CONFIG_PCI_MSI */ | |
3065 | ||
6e628c7d WY |
3066 | #ifdef CONFIG_PCI_IOV |
3067 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) | |
3068 | { | |
f2dd0afe WY |
3069 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
3070 | struct pnv_phb *phb = hose->private_data; | |
3071 | const resource_size_t gate = phb->ioda.m64_segsize >> 2; | |
6e628c7d WY |
3072 | struct resource *res; |
3073 | int i; | |
dfcc8d45 | 3074 | resource_size_t size, total_vf_bar_sz; |
6e628c7d | 3075 | struct pci_dn *pdn; |
5b88ec22 | 3076 | int mul, total_vfs; |
6e628c7d WY |
3077 | |
3078 | if (!pdev->is_physfn || pdev->is_added) | |
3079 | return; | |
3080 | ||
6e628c7d WY |
3081 | pdn = pci_get_pdn(pdev); |
3082 | pdn->vfs_expanded = 0; | |
ee8222fe | 3083 | pdn->m64_single_mode = false; |
6e628c7d | 3084 | |
5b88ec22 | 3085 | total_vfs = pci_sriov_get_totalvfs(pdev); |
92b8f137 | 3086 | mul = phb->ioda.total_pe_num; |
dfcc8d45 | 3087 | total_vf_bar_sz = 0; |
5b88ec22 WY |
3088 | |
3089 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
3090 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
3091 | if (!res->flags || res->parent) | |
3092 | continue; | |
b79331a5 | 3093 | if (!pnv_pci_is_m64_flags(res->flags)) { |
b0331854 WY |
3094 | dev_warn(&pdev->dev, "Don't support SR-IOV with" |
3095 | " non M64 VF BAR%d: %pR. \n", | |
5b88ec22 | 3096 | i, res); |
b0331854 | 3097 | goto truncate_iov; |
5b88ec22 WY |
3098 | } |
3099 | ||
dfcc8d45 WY |
3100 | total_vf_bar_sz += pci_iov_resource_size(pdev, |
3101 | i + PCI_IOV_RESOURCES); | |
5b88ec22 | 3102 | |
f2dd0afe WY |
3103 | /* |
3104 | * If bigger than quarter of M64 segment size, just round up | |
3105 | * power of two. | |
3106 | * | |
3107 | * Generally, one M64 BAR maps one IOV BAR. To avoid conflict | |
3108 | * with other devices, IOV BAR size is expanded to be | |
3109 | * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 | |
3110 | * segment size , the expanded size would equal to half of the | |
3111 | * whole M64 space size, which will exhaust the M64 Space and | |
3112 | * limit the system flexibility. This is a design decision to | |
3113 | * set the boundary to quarter of the M64 segment size. | |
3114 | */ | |
dfcc8d45 | 3115 | if (total_vf_bar_sz > gate) { |
5b88ec22 | 3116 | mul = roundup_pow_of_two(total_vfs); |
dfcc8d45 WY |
3117 | dev_info(&pdev->dev, |
3118 | "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", | |
3119 | total_vf_bar_sz, gate, mul); | |
ee8222fe | 3120 | pdn->m64_single_mode = true; |
5b88ec22 WY |
3121 | break; |
3122 | } | |
3123 | } | |
3124 | ||
6e628c7d WY |
3125 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
3126 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
3127 | if (!res->flags || res->parent) | |
3128 | continue; | |
6e628c7d | 3129 | |
6e628c7d | 3130 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); |
ee8222fe WY |
3131 | /* |
3132 | * On PHB3, the minimum size alignment of M64 BAR in single | |
3133 | * mode is 32MB. | |
3134 | */ | |
3135 | if (pdn->m64_single_mode && (size < SZ_32M)) | |
3136 | goto truncate_iov; | |
3137 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); | |
5b88ec22 | 3138 | res->end = res->start + size * mul - 1; |
6e628c7d WY |
3139 | dev_dbg(&pdev->dev, " %pR\n", res); |
3140 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", | |
5b88ec22 | 3141 | i, res, mul); |
6e628c7d | 3142 | } |
5b88ec22 | 3143 | pdn->vfs_expanded = mul; |
b0331854 WY |
3144 | |
3145 | return; | |
3146 | ||
3147 | truncate_iov: | |
3148 | /* To save MMIO space, IOV BAR is truncated. */ | |
3149 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
3150 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
3151 | res->flags = 0; | |
3152 | res->end = res->start - 1; | |
3153 | } | |
6e628c7d WY |
3154 | } |
3155 | #endif /* CONFIG_PCI_IOV */ | |
3156 | ||
23e79425 GS |
3157 | static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, |
3158 | struct resource *res) | |
3159 | { | |
3160 | struct pnv_phb *phb = pe->phb; | |
3161 | struct pci_bus_region region; | |
3162 | int index; | |
3163 | int64_t rc; | |
3164 | ||
3165 | if (!res || !res->flags || res->start > res->end) | |
3166 | return; | |
3167 | ||
3168 | if (res->flags & IORESOURCE_IO) { | |
3169 | region.start = res->start - phb->ioda.io_pci_base; | |
3170 | region.end = res->end - phb->ioda.io_pci_base; | |
3171 | index = region.start / phb->ioda.io_segsize; | |
3172 | ||
3173 | while (index < phb->ioda.total_pe_num && | |
3174 | region.start <= region.end) { | |
3175 | phb->ioda.io_segmap[index] = pe->pe_number; | |
3176 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3177 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
3178 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 3179 | pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", |
23e79425 GS |
3180 | __func__, rc, index, pe->pe_number); |
3181 | break; | |
3182 | } | |
3183 | ||
3184 | region.start += phb->ioda.io_segsize; | |
3185 | index++; | |
3186 | } | |
3187 | } else if ((res->flags & IORESOURCE_MEM) && | |
5958d19a | 3188 | !pnv_pci_is_m64(phb, res)) { |
23e79425 GS |
3189 | region.start = res->start - |
3190 | phb->hose->mem_offset[0] - | |
3191 | phb->ioda.m32_pci_base; | |
3192 | region.end = res->end - | |
3193 | phb->hose->mem_offset[0] - | |
3194 | phb->ioda.m32_pci_base; | |
3195 | index = region.start / phb->ioda.m32_segsize; | |
3196 | ||
3197 | while (index < phb->ioda.total_pe_num && | |
3198 | region.start <= region.end) { | |
3199 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
3200 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3201 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
3202 | if (rc != OPAL_SUCCESS) { | |
1f52f176 | 3203 | pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", |
23e79425 GS |
3204 | __func__, rc, index, pe->pe_number); |
3205 | break; | |
3206 | } | |
3207 | ||
3208 | region.start += phb->ioda.m32_segsize; | |
3209 | index++; | |
3210 | } | |
3211 | } | |
3212 | } | |
3213 | ||
11685bec GS |
3214 | /* |
3215 | * This function is supposed to be called on basis of PE from top | |
3216 | * to bottom style. So the the I/O or MMIO segment assigned to | |
03671057 | 3217 | * parent PE could be overridden by its child PEs if necessary. |
11685bec | 3218 | */ |
23e79425 | 3219 | static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) |
11685bec | 3220 | { |
69d733e7 | 3221 | struct pci_dev *pdev; |
23e79425 | 3222 | int i; |
11685bec GS |
3223 | |
3224 | /* | |
3225 | * NOTE: We only care PCI bus based PE for now. For PCI | |
3226 | * device based PE, for example SRIOV sensitive VF should | |
3227 | * be figured out later. | |
3228 | */ | |
3229 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
3230 | ||
69d733e7 GS |
3231 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
3232 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
3233 | pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); | |
3234 | ||
3235 | /* | |
3236 | * If the PE contains all subordinate PCI buses, the | |
3237 | * windows of the child bridges should be mapped to | |
3238 | * the PE as well. | |
3239 | */ | |
3240 | if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) | |
3241 | continue; | |
3242 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
3243 | pnv_ioda_setup_pe_res(pe, | |
3244 | &pdev->resource[PCI_BRIDGE_RESOURCES + i]); | |
3245 | } | |
11685bec GS |
3246 | } |
3247 | ||
98b665da RC |
3248 | #ifdef CONFIG_DEBUG_FS |
3249 | static int pnv_pci_diag_data_set(void *data, u64 val) | |
3250 | { | |
3251 | struct pci_controller *hose; | |
3252 | struct pnv_phb *phb; | |
3253 | s64 ret; | |
3254 | ||
3255 | if (val != 1ULL) | |
3256 | return -EINVAL; | |
3257 | ||
3258 | hose = (struct pci_controller *)data; | |
3259 | if (!hose || !hose->private_data) | |
3260 | return -ENODEV; | |
3261 | ||
3262 | phb = hose->private_data; | |
3263 | ||
3264 | /* Retrieve the diag data from firmware */ | |
5cb1f8fd RC |
3265 | ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, |
3266 | phb->diag_data_size); | |
98b665da RC |
3267 | if (ret != OPAL_SUCCESS) |
3268 | return -EIO; | |
3269 | ||
3270 | /* Print the diag data to the kernel log */ | |
5cb1f8fd | 3271 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); |
98b665da RC |
3272 | return 0; |
3273 | } | |
3274 | ||
3275 | DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, | |
3276 | pnv_pci_diag_data_set, "%llu\n"); | |
3277 | ||
3278 | #endif /* CONFIG_DEBUG_FS */ | |
3279 | ||
37c367f2 GS |
3280 | static void pnv_pci_ioda_create_dbgfs(void) |
3281 | { | |
3282 | #ifdef CONFIG_DEBUG_FS | |
3283 | struct pci_controller *hose, *tmp; | |
3284 | struct pnv_phb *phb; | |
3285 | char name[16]; | |
3286 | ||
3287 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3288 | phb = hose->private_data; | |
3289 | ||
ccd1c191 GS |
3290 | /* Notify initialization of PHB done */ |
3291 | phb->initialized = 1; | |
3292 | ||
37c367f2 GS |
3293 | sprintf(name, "PCI%04x", hose->global_number); |
3294 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
98b665da | 3295 | if (!phb->dbgfs) { |
37c367f2 GS |
3296 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", |
3297 | __func__, hose->global_number); | |
98b665da RC |
3298 | continue; |
3299 | } | |
3300 | ||
3301 | debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, | |
3302 | &pnv_pci_diag_data_fops); | |
37c367f2 GS |
3303 | } |
3304 | #endif /* CONFIG_DEBUG_FS */ | |
3305 | } | |
3306 | ||
cad5cef6 | 3307 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
3308 | { |
3309 | pnv_pci_ioda_setup_PEs(); | |
ccd1c191 | 3310 | pnv_pci_ioda_setup_iommu_api(); |
37c367f2 GS |
3311 | pnv_pci_ioda_create_dbgfs(); |
3312 | ||
e9cc17d4 | 3313 | #ifdef CONFIG_EEH |
b9fde58d | 3314 | pnv_eeh_post_init(); |
e9cc17d4 | 3315 | #endif |
fb446ad0 GS |
3316 | } |
3317 | ||
271fd03a GS |
3318 | /* |
3319 | * Returns the alignment for I/O or memory windows for P2P | |
3320 | * bridges. That actually depends on how PEs are segmented. | |
3321 | * For now, we return I/O or M32 segment size for PE sensitive | |
3322 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
3323 | * 1MiB for memory) will be returned. | |
3324 | * | |
3325 | * The current PCI bus might be put into one PE, which was | |
3326 | * create against the parent PCI bridge. For that case, we | |
3327 | * needn't enlarge the alignment so that we can save some | |
3328 | * resources. | |
3329 | */ | |
3330 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
3331 | unsigned long type) | |
3332 | { | |
3333 | struct pci_dev *bridge; | |
3334 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3335 | struct pnv_phb *phb = hose->private_data; | |
3336 | int num_pci_bridges = 0; | |
3337 | ||
3338 | bridge = bus->self; | |
3339 | while (bridge) { | |
3340 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
3341 | num_pci_bridges++; | |
3342 | if (num_pci_bridges >= 2) | |
3343 | return 1; | |
3344 | } | |
3345 | ||
3346 | bridge = bridge->bus->self; | |
3347 | } | |
3348 | ||
5958d19a BH |
3349 | /* |
3350 | * We fall back to M32 if M64 isn't supported. We enforce the M64 | |
3351 | * alignment for any 64-bit resource, PCIe doesn't care and | |
3352 | * bridges only do 64-bit prefetchable anyway. | |
3353 | */ | |
b79331a5 | 3354 | if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) |
262af557 | 3355 | return phb->ioda.m64_segsize; |
271fd03a GS |
3356 | if (type & IORESOURCE_MEM) |
3357 | return phb->ioda.m32_segsize; | |
3358 | ||
3359 | return phb->ioda.io_segsize; | |
3360 | } | |
3361 | ||
40e2a47e GS |
3362 | /* |
3363 | * We are updating root port or the upstream port of the | |
3364 | * bridge behind the root port with PHB's windows in order | |
3365 | * to accommodate the changes on required resources during | |
3366 | * PCI (slot) hotplug, which is connected to either root | |
3367 | * port or the downstream ports of PCIe switch behind the | |
3368 | * root port. | |
3369 | */ | |
3370 | static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, | |
3371 | unsigned long type) | |
3372 | { | |
3373 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3374 | struct pnv_phb *phb = hose->private_data; | |
3375 | struct pci_dev *bridge = bus->self; | |
3376 | struct resource *r, *w; | |
3377 | bool msi_region = false; | |
3378 | int i; | |
3379 | ||
3380 | /* Check if we need apply fixup to the bridge's windows */ | |
3381 | if (!pci_is_root_bus(bridge->bus) && | |
3382 | !pci_is_root_bus(bridge->bus->self->bus)) | |
3383 | return; | |
3384 | ||
3385 | /* Fixup the resources */ | |
3386 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { | |
3387 | r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; | |
3388 | if (!r->flags || !r->parent) | |
3389 | continue; | |
3390 | ||
3391 | w = NULL; | |
3392 | if (r->flags & type & IORESOURCE_IO) | |
3393 | w = &hose->io_resource; | |
5958d19a | 3394 | else if (pnv_pci_is_m64(phb, r) && |
40e2a47e GS |
3395 | (type & IORESOURCE_PREFETCH) && |
3396 | phb->ioda.m64_segsize) | |
3397 | w = &hose->mem_resources[1]; | |
3398 | else if (r->flags & type & IORESOURCE_MEM) { | |
3399 | w = &hose->mem_resources[0]; | |
3400 | msi_region = true; | |
3401 | } | |
3402 | ||
3403 | r->start = w->start; | |
3404 | r->end = w->end; | |
3405 | ||
3406 | /* The 64KB 32-bits MSI region shouldn't be included in | |
3407 | * the 32-bits bridge window. Otherwise, we can see strange | |
3408 | * issues. One of them is EEH error observed on Garrison. | |
3409 | * | |
3410 | * Exclude top 1MB region which is the minimal alignment of | |
3411 | * 32-bits bridge window. | |
3412 | */ | |
3413 | if (msi_region) { | |
3414 | r->end += 0x10000; | |
3415 | r->end -= 0x100000; | |
3416 | } | |
3417 | } | |
3418 | } | |
3419 | ||
ccd1c191 GS |
3420 | static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) |
3421 | { | |
3422 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3423 | struct pnv_phb *phb = hose->private_data; | |
3424 | struct pci_dev *bridge = bus->self; | |
3425 | struct pnv_ioda_pe *pe; | |
3426 | bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); | |
3427 | ||
40e2a47e GS |
3428 | /* Extend bridge's windows if necessary */ |
3429 | pnv_pci_fixup_bridge_resources(bus, type); | |
3430 | ||
63803c39 GS |
3431 | /* The PE for root bus should be realized before any one else */ |
3432 | if (!phb->ioda.root_pe_populated) { | |
3433 | pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); | |
3434 | if (pe) { | |
3435 | phb->ioda.root_pe_idx = pe->pe_number; | |
3436 | phb->ioda.root_pe_populated = true; | |
3437 | } | |
3438 | } | |
3439 | ||
ccd1c191 GS |
3440 | /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ |
3441 | if (list_empty(&bus->devices)) | |
3442 | return; | |
3443 | ||
3444 | /* Reserve PEs according to used M64 resources */ | |
3445 | if (phb->reserve_m64_pe) | |
3446 | phb->reserve_m64_pe(bus, NULL, all); | |
3447 | ||
3448 | /* | |
3449 | * Assign PE. We might run here because of partial hotplug. | |
3450 | * For the case, we just pick up the existing PE and should | |
3451 | * not allocate resources again. | |
3452 | */ | |
3453 | pe = pnv_ioda_setup_bus_PE(bus, all); | |
3454 | if (!pe) | |
3455 | return; | |
3456 | ||
3457 | pnv_ioda_setup_pe_seg(pe); | |
3458 | switch (phb->type) { | |
3459 | case PNV_PHB_IODA1: | |
3460 | pnv_pci_ioda1_setup_dma_pe(phb, pe); | |
3461 | break; | |
3462 | case PNV_PHB_IODA2: | |
3463 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
3464 | break; | |
3465 | default: | |
1f52f176 | 3466 | pr_warn("%s: No DMA for PHB#%x (type %d)\n", |
ccd1c191 GS |
3467 | __func__, phb->hose->global_number, phb->type); |
3468 | } | |
3469 | } | |
3470 | ||
38274637 YX |
3471 | static resource_size_t pnv_pci_default_alignment(void) |
3472 | { | |
3473 | return PAGE_SIZE; | |
3474 | } | |
3475 | ||
5350ab3f WY |
3476 | #ifdef CONFIG_PCI_IOV |
3477 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, | |
3478 | int resno) | |
3479 | { | |
ee8222fe WY |
3480 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
3481 | struct pnv_phb *phb = hose->private_data; | |
5350ab3f | 3482 | struct pci_dn *pdn = pci_get_pdn(pdev); |
7fbe7a93 | 3483 | resource_size_t align; |
5350ab3f | 3484 | |
7fbe7a93 WY |
3485 | /* |
3486 | * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the | |
3487 | * SR-IOV. While from hardware perspective, the range mapped by M64 | |
3488 | * BAR should be size aligned. | |
3489 | * | |
ee8222fe WY |
3490 | * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra |
3491 | * powernv-specific hardware restriction is gone. But if just use the | |
3492 | * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with | |
3493 | * in one segment of M64 #15, which introduces the PE conflict between | |
3494 | * PF and VF. Based on this, the minimum alignment of an IOV BAR is | |
3495 | * m64_segsize. | |
3496 | * | |
7fbe7a93 WY |
3497 | * This function returns the total IOV BAR size if M64 BAR is in |
3498 | * Shared PE mode or just VF BAR size if not. | |
ee8222fe WY |
3499 | * If the M64 BAR is in Single PE mode, return the VF BAR size or |
3500 | * M64 segment size if IOV BAR size is less. | |
7fbe7a93 | 3501 | */ |
5350ab3f | 3502 | align = pci_iov_resource_size(pdev, resno); |
7fbe7a93 WY |
3503 | if (!pdn->vfs_expanded) |
3504 | return align; | |
ee8222fe WY |
3505 | if (pdn->m64_single_mode) |
3506 | return max(align, (resource_size_t)phb->ioda.m64_segsize); | |
5350ab3f | 3507 | |
7fbe7a93 | 3508 | return pdn->vfs_expanded * align; |
5350ab3f WY |
3509 | } |
3510 | #endif /* CONFIG_PCI_IOV */ | |
3511 | ||
184cd4a3 BH |
3512 | /* Prevent enabling devices for which we couldn't properly |
3513 | * assign a PE | |
3514 | */ | |
4361b034 | 3515 | bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 3516 | { |
db1266c8 GS |
3517 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
3518 | struct pnv_phb *phb = hose->private_data; | |
3519 | struct pci_dn *pdn; | |
184cd4a3 | 3520 | |
db1266c8 GS |
3521 | /* The function is probably called while the PEs have |
3522 | * not be created yet. For example, resource reassignment | |
3523 | * during PCI probe period. We just skip the check if | |
3524 | * PEs isn't ready. | |
3525 | */ | |
3526 | if (!phb->initialized) | |
c88c2a18 | 3527 | return true; |
db1266c8 | 3528 | |
b72c1f65 | 3529 | pdn = pci_get_pdn(dev); |
184cd4a3 | 3530 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
c88c2a18 | 3531 | return false; |
db1266c8 | 3532 | |
c88c2a18 | 3533 | return true; |
184cd4a3 BH |
3534 | } |
3535 | ||
c5f7700b GS |
3536 | static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, |
3537 | int num) | |
3538 | { | |
3539 | struct pnv_ioda_pe *pe = container_of(table_group, | |
3540 | struct pnv_ioda_pe, table_group); | |
3541 | struct pnv_phb *phb = pe->phb; | |
3542 | unsigned int idx; | |
3543 | long rc; | |
3544 | ||
3545 | pe_info(pe, "Removing DMA window #%d\n", num); | |
3546 | for (idx = 0; idx < phb->ioda.dma32_count; idx++) { | |
3547 | if (phb->ioda.dma32_segmap[idx] != pe->pe_number) | |
3548 | continue; | |
3549 | ||
3550 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
3551 | idx, 0, 0ul, 0ul, 0ul); | |
3552 | if (rc != OPAL_SUCCESS) { | |
3553 | pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", | |
3554 | rc, idx); | |
3555 | return rc; | |
3556 | } | |
3557 | ||
3558 | phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; | |
3559 | } | |
3560 | ||
3561 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); | |
3562 | return OPAL_SUCCESS; | |
3563 | } | |
3564 | ||
3565 | static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) | |
3566 | { | |
3567 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); | |
3568 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
3569 | int64_t rc; | |
3570 | ||
3571 | if (!weight) | |
3572 | return; | |
3573 | ||
3574 | rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); | |
3575 | if (rc != OPAL_SUCCESS) | |
3576 | return; | |
3577 | ||
a34ab7c3 | 3578 | pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); |
c5f7700b GS |
3579 | if (pe->table_group.group) { |
3580 | iommu_group_put(pe->table_group.group); | |
3581 | WARN_ON(pe->table_group.group); | |
3582 | } | |
3583 | ||
3584 | free_pages(tbl->it_base, get_order(tbl->it_size << 3)); | |
e5afdf9d | 3585 | iommu_tce_table_put(tbl); |
c5f7700b GS |
3586 | } |
3587 | ||
3588 | static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) | |
3589 | { | |
3590 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
3591 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); | |
3592 | #ifdef CONFIG_IOMMU_API | |
3593 | int64_t rc; | |
3594 | #endif | |
3595 | ||
3596 | if (!weight) | |
3597 | return; | |
3598 | ||
3599 | #ifdef CONFIG_IOMMU_API | |
3600 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); | |
3601 | if (rc) | |
3602 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
3603 | #endif | |
3604 | ||
3605 | pnv_pci_ioda2_set_bypass(pe, false); | |
3606 | if (pe->table_group.group) { | |
3607 | iommu_group_put(pe->table_group.group); | |
3608 | WARN_ON(pe->table_group.group); | |
3609 | } | |
3610 | ||
3611 | pnv_pci_ioda2_table_free_pages(tbl); | |
e5afdf9d | 3612 | iommu_tce_table_put(tbl); |
c5f7700b GS |
3613 | } |
3614 | ||
3615 | static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, | |
3616 | unsigned short win, | |
3617 | unsigned int *map) | |
3618 | { | |
3619 | struct pnv_phb *phb = pe->phb; | |
3620 | int idx; | |
3621 | int64_t rc; | |
3622 | ||
3623 | for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { | |
3624 | if (map[idx] != pe->pe_number) | |
3625 | continue; | |
3626 | ||
3627 | if (win == OPAL_M64_WINDOW_TYPE) | |
3628 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3629 | phb->ioda.reserved_pe_idx, win, | |
3630 | idx / PNV_IODA1_M64_SEGS, | |
3631 | idx % PNV_IODA1_M64_SEGS); | |
3632 | else | |
3633 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3634 | phb->ioda.reserved_pe_idx, win, 0, idx); | |
3635 | ||
3636 | if (rc != OPAL_SUCCESS) | |
3637 | pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", | |
3638 | rc, win, idx); | |
3639 | ||
3640 | map[idx] = IODA_INVALID_PE; | |
3641 | } | |
3642 | } | |
3643 | ||
3644 | static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) | |
3645 | { | |
3646 | struct pnv_phb *phb = pe->phb; | |
3647 | ||
3648 | if (phb->type == PNV_PHB_IODA1) { | |
3649 | pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, | |
3650 | phb->ioda.io_segmap); | |
3651 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, | |
3652 | phb->ioda.m32_segmap); | |
3653 | pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, | |
3654 | phb->ioda.m64_segmap); | |
3655 | } else if (phb->type == PNV_PHB_IODA2) { | |
3656 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, | |
3657 | phb->ioda.m32_segmap); | |
3658 | } | |
3659 | } | |
3660 | ||
3661 | static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) | |
3662 | { | |
3663 | struct pnv_phb *phb = pe->phb; | |
3664 | struct pnv_ioda_pe *slave, *tmp; | |
3665 | ||
c5f7700b GS |
3666 | list_del(&pe->list); |
3667 | switch (phb->type) { | |
3668 | case PNV_PHB_IODA1: | |
3669 | pnv_pci_ioda1_release_pe_dma(pe); | |
3670 | break; | |
3671 | case PNV_PHB_IODA2: | |
3672 | pnv_pci_ioda2_release_pe_dma(pe); | |
3673 | break; | |
3674 | default: | |
3675 | WARN_ON(1); | |
3676 | } | |
3677 | ||
3678 | pnv_ioda_release_pe_seg(pe); | |
3679 | pnv_ioda_deconfigure_pe(pe->phb, pe); | |
b314427a GS |
3680 | |
3681 | /* Release slave PEs in the compound PE */ | |
3682 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
3683 | list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { | |
3684 | list_del(&slave->list); | |
3685 | pnv_ioda_free_pe(slave); | |
3686 | } | |
3687 | } | |
3688 | ||
6eaed166 GS |
3689 | /* |
3690 | * The PE for root bus can be removed because of hotplug in EEH | |
3691 | * recovery for fenced PHB error. We need to mark the PE dead so | |
3692 | * that it can be populated again in PCI hot add path. The PE | |
3693 | * shouldn't be destroyed as it's the global reserved resource. | |
3694 | */ | |
3695 | if (phb->ioda.root_pe_populated && | |
3696 | phb->ioda.root_pe_idx == pe->pe_number) | |
3697 | phb->ioda.root_pe_populated = false; | |
3698 | else | |
3699 | pnv_ioda_free_pe(pe); | |
c5f7700b GS |
3700 | } |
3701 | ||
3702 | static void pnv_pci_release_device(struct pci_dev *pdev) | |
3703 | { | |
3704 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
3705 | struct pnv_phb *phb = hose->private_data; | |
3706 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
3707 | struct pnv_ioda_pe *pe; | |
3708 | ||
3709 | if (pdev->is_virtfn) | |
3710 | return; | |
3711 | ||
3712 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
3713 | return; | |
3714 | ||
29bf282d GS |
3715 | /* |
3716 | * PCI hotplug can happen as part of EEH error recovery. The @pdn | |
3717 | * isn't removed and added afterwards in this scenario. We should | |
3718 | * set the PE number in @pdn to an invalid one. Otherwise, the PE's | |
3719 | * device count is decreased on removing devices while failing to | |
3720 | * be increased on adding devices. It leads to unbalanced PE's device | |
3721 | * count and eventually make normal PCI hotplug path broken. | |
3722 | */ | |
c5f7700b | 3723 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
29bf282d GS |
3724 | pdn->pe_number = IODA_INVALID_PE; |
3725 | ||
c5f7700b GS |
3726 | WARN_ON(--pe->device_count < 0); |
3727 | if (pe->device_count == 0) | |
3728 | pnv_ioda_release_pe(pe); | |
3729 | } | |
3730 | ||
7a8e6bbf | 3731 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
73ed148a | 3732 | { |
7a8e6bbf MN |
3733 | struct pnv_phb *phb = hose->private_data; |
3734 | ||
d1a85eee | 3735 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
73ed148a BH |
3736 | OPAL_ASSERT_RESET); |
3737 | } | |
3738 | ||
92ae0353 | 3739 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
cb4224c5 GS |
3740 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
3741 | .dma_bus_setup = pnv_pci_dma_bus_setup, | |
92ae0353 | 3742 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3743 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3744 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
92ae0353 | 3745 | #endif |
cb4224c5 | 3746 | .enable_device_hook = pnv_pci_enable_device_hook, |
c5f7700b | 3747 | .release_device = pnv_pci_release_device, |
cb4224c5 | 3748 | .window_alignment = pnv_pci_window_alignment, |
ccd1c191 | 3749 | .setup_bridge = pnv_pci_setup_bridge, |
cb4224c5 GS |
3750 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
3751 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, | |
3752 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, | |
3753 | .shutdown = pnv_pci_ioda_shutdown, | |
92ae0353 DA |
3754 | }; |
3755 | ||
f9f83456 AK |
3756 | static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) |
3757 | { | |
3758 | dev_err_once(&npdev->dev, | |
3759 | "%s operation unsupported for NVLink devices\n", | |
3760 | __func__); | |
3761 | return -EPERM; | |
3762 | } | |
3763 | ||
5d2aa710 | 3764 | static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { |
cb4224c5 | 3765 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
5d2aa710 | 3766 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3767 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3768 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
5d2aa710 | 3769 | #endif |
cb4224c5 GS |
3770 | .enable_device_hook = pnv_pci_enable_device_hook, |
3771 | .window_alignment = pnv_pci_window_alignment, | |
3772 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3773 | .dma_set_mask = pnv_npu_dma_set_mask, | |
3774 | .shutdown = pnv_pci_ioda_shutdown, | |
5d2aa710 AP |
3775 | }; |
3776 | ||
4361b034 IM |
3777 | #ifdef CONFIG_CXL_BASE |
3778 | const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { | |
3779 | .dma_dev_setup = pnv_pci_dma_dev_setup, | |
3780 | .dma_bus_setup = pnv_pci_dma_bus_setup, | |
a2f67d5e IM |
3781 | #ifdef CONFIG_PCI_MSI |
3782 | .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, | |
3783 | .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, | |
3784 | #endif | |
4361b034 IM |
3785 | .enable_device_hook = pnv_cxl_enable_device_hook, |
3786 | .disable_device = pnv_cxl_disable_device, | |
3787 | .release_device = pnv_pci_release_device, | |
3788 | .window_alignment = pnv_pci_window_alignment, | |
3789 | .setup_bridge = pnv_pci_setup_bridge, | |
3790 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3791 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, | |
3792 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, | |
3793 | .shutdown = pnv_pci_ioda_shutdown, | |
3794 | }; | |
3795 | #endif | |
3796 | ||
e51df2c1 AB |
3797 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
3798 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
3799 | { |
3800 | struct pci_controller *hose; | |
184cd4a3 | 3801 | struct pnv_phb *phb; |
2b923ed1 GS |
3802 | unsigned long size, m64map_off, m32map_off, pemap_off; |
3803 | unsigned long iomap_off = 0, dma32map_off = 0; | |
fd141d1a | 3804 | struct resource r; |
c681b93c | 3805 | const __be64 *prop64; |
3a1a4661 | 3806 | const __be32 *prop32; |
f1b7cc3e | 3807 | int len; |
3fa23ff8 | 3808 | unsigned int segno; |
184cd4a3 BH |
3809 | u64 phb_id; |
3810 | void *aux; | |
3811 | long rc; | |
3812 | ||
08a45b32 BH |
3813 | if (!of_device_is_available(np)) |
3814 | return; | |
3815 | ||
b7c670d6 | 3816 | pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); |
184cd4a3 BH |
3817 | |
3818 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
3819 | if (!prop64) { | |
3820 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
3821 | return; | |
3822 | } | |
3823 | phb_id = be64_to_cpup(prop64); | |
3824 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
3825 | ||
e39f223f | 3826 | phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); |
58d714ec GS |
3827 | |
3828 | /* Allocate PCI controller */ | |
58d714ec GS |
3829 | phb->hose = hose = pcibios_alloc_controller(np); |
3830 | if (!phb->hose) { | |
b7c670d6 RH |
3831 | pr_err(" Can't allocate PCI controller for %pOF\n", |
3832 | np); | |
e39f223f | 3833 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
184cd4a3 BH |
3834 | return; |
3835 | } | |
3836 | ||
3837 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
3838 | prop32 = of_get_property(np, "bus-range", &len); |
3839 | if (prop32 && len == 8) { | |
3a1a4661 BH |
3840 | hose->first_busno = be32_to_cpu(prop32[0]); |
3841 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e | 3842 | } else { |
b7c670d6 | 3843 | pr_warn(" Broken <bus-range> on %pOF\n", np); |
f1b7cc3e GS |
3844 | hose->first_busno = 0; |
3845 | hose->last_busno = 0xff; | |
3846 | } | |
184cd4a3 | 3847 | hose->private_data = phb; |
e9cc17d4 | 3848 | phb->hub_id = hub_id; |
184cd4a3 | 3849 | phb->opal_id = phb_id; |
aa0c033f | 3850 | phb->type = ioda_type; |
781a868f | 3851 | mutex_init(&phb->ioda.pe_alloc_mutex); |
184cd4a3 | 3852 | |
cee72d5b BH |
3853 | /* Detect specific models for error handling */ |
3854 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
3855 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 3856 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 3857 | phb->model = PNV_PHB_MODEL_PHB3; |
5d2aa710 AP |
3858 | else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) |
3859 | phb->model = PNV_PHB_MODEL_NPU; | |
616badd2 AP |
3860 | else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) |
3861 | phb->model = PNV_PHB_MODEL_NPU2; | |
cee72d5b BH |
3862 | else |
3863 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
3864 | ||
5cb1f8fd RC |
3865 | /* Initialize diagnostic data buffer */ |
3866 | prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); | |
3867 | if (prop32) | |
3868 | phb->diag_data_size = be32_to_cpup(prop32); | |
3869 | else | |
3870 | phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; | |
3871 | ||
3872 | phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); | |
3873 | ||
aa0c033f | 3874 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 3875 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 3876 | |
aa0c033f | 3877 | /* Get registers */ |
fd141d1a BH |
3878 | if (!of_address_to_resource(np, 0, &r)) { |
3879 | phb->regs_phys = r.start; | |
3880 | phb->regs = ioremap(r.start, resource_size(&r)); | |
3881 | if (phb->regs == NULL) | |
3882 | pr_err(" Failed to map registers !\n"); | |
3883 | } | |
577c8c88 | 3884 | |
184cd4a3 | 3885 | /* Initialize more IODA stuff */ |
92b8f137 | 3886 | phb->ioda.total_pe_num = 1; |
aa0c033f | 3887 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 3888 | if (prop32) |
92b8f137 | 3889 | phb->ioda.total_pe_num = be32_to_cpup(prop32); |
36954dc7 GS |
3890 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
3891 | if (prop32) | |
92b8f137 | 3892 | phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); |
262af557 | 3893 | |
c127562a GS |
3894 | /* Invalidate RID to PE# mapping */ |
3895 | for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) | |
3896 | phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; | |
3897 | ||
262af557 GC |
3898 | /* Parse 64-bit MMIO range */ |
3899 | pnv_ioda_parse_m64_window(phb); | |
3900 | ||
184cd4a3 | 3901 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 3902 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
3903 | phb->ioda.m32_size += 0x10000; |
3904 | ||
92b8f137 | 3905 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; |
3fd47f06 | 3906 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 | 3907 | phb->ioda.io_size = hose->pci_io_size; |
92b8f137 | 3908 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; |
184cd4a3 BH |
3909 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ |
3910 | ||
2b923ed1 GS |
3911 | /* Calculate how many 32-bit TCE segments we have */ |
3912 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / | |
3913 | PNV_IODA1_DMA32_SEGSIZE; | |
3914 | ||
c35d2a8c | 3915 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
92a86756 AK |
3916 | size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, |
3917 | sizeof(unsigned long)); | |
93289d8c GS |
3918 | m64map_off = size; |
3919 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); | |
184cd4a3 | 3920 | m32map_off = size; |
92b8f137 | 3921 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
3922 | if (phb->type == PNV_PHB_IODA1) { |
3923 | iomap_off = size; | |
92b8f137 | 3924 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); |
2b923ed1 GS |
3925 | dma32map_off = size; |
3926 | size += phb->ioda.dma32_count * | |
3927 | sizeof(phb->ioda.dma32_segmap[0]); | |
c35d2a8c | 3928 | } |
184cd4a3 | 3929 | pemap_off = size; |
92b8f137 | 3930 | size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); |
e39f223f | 3931 | aux = memblock_virt_alloc(size, 0); |
184cd4a3 | 3932 | phb->ioda.pe_alloc = aux; |
93289d8c | 3933 | phb->ioda.m64_segmap = aux + m64map_off; |
184cd4a3 | 3934 | phb->ioda.m32_segmap = aux + m32map_off; |
93289d8c GS |
3935 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { |
3936 | phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3937 | phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; |
93289d8c | 3938 | } |
3fa23ff8 | 3939 | if (phb->type == PNV_PHB_IODA1) { |
c35d2a8c | 3940 | phb->ioda.io_segmap = aux + iomap_off; |
3fa23ff8 GS |
3941 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) |
3942 | phb->ioda.io_segmap[segno] = IODA_INVALID_PE; | |
2b923ed1 GS |
3943 | |
3944 | phb->ioda.dma32_segmap = aux + dma32map_off; | |
3945 | for (segno = 0; segno < phb->ioda.dma32_count; segno++) | |
3946 | phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3947 | } |
184cd4a3 | 3948 | phb->ioda.pe_array = aux + pemap_off; |
63803c39 GS |
3949 | |
3950 | /* | |
3951 | * Choose PE number for root bus, which shouldn't have | |
3952 | * M64 resources consumed by its child devices. To pick | |
3953 | * the PE number adjacent to the reserved one if possible. | |
3954 | */ | |
3955 | pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); | |
3956 | if (phb->ioda.reserved_pe_idx == 0) { | |
3957 | phb->ioda.root_pe_idx = 1; | |
3958 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); | |
3959 | } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { | |
3960 | phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; | |
3961 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); | |
3962 | } else { | |
3963 | phb->ioda.root_pe_idx = IODA_INVALID_PE; | |
3964 | } | |
184cd4a3 BH |
3965 | |
3966 | INIT_LIST_HEAD(&phb->ioda.pe_list); | |
781a868f | 3967 | mutex_init(&phb->ioda.pe_list_mutex); |
184cd4a3 BH |
3968 | |
3969 | /* Calculate how many 32-bit TCE segments we have */ | |
2b923ed1 | 3970 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
acce971c | 3971 | PNV_IODA1_DMA32_SEGSIZE; |
184cd4a3 | 3972 | |
aa0c033f | 3973 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
3974 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
3975 | window_type, | |
3976 | window_num, | |
3977 | starting_real_address, | |
3978 | starting_pci_address, | |
3979 | segment_size); | |
3980 | #endif | |
3981 | ||
262af557 | 3982 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
92b8f137 | 3983 | phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, |
262af557 GC |
3984 | phb->ioda.m32_size, phb->ioda.m32_segsize); |
3985 | if (phb->ioda.m64_size) | |
3986 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", | |
3987 | phb->ioda.m64_size, phb->ioda.m64_segsize); | |
3988 | if (phb->ioda.io_size) | |
3989 | pr_info(" IO: 0x%x [segment=0x%x]\n", | |
3990 | phb->ioda.io_size, phb->ioda.io_segsize); | |
3991 | ||
184cd4a3 | 3992 | |
184cd4a3 | 3993 | phb->hose->ops = &pnv_pci_ops; |
49dec922 GS |
3994 | phb->get_pe_state = pnv_ioda_get_pe_state; |
3995 | phb->freeze_pe = pnv_ioda_freeze_pe; | |
3996 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | |
184cd4a3 | 3997 | |
184cd4a3 BH |
3998 | /* Setup MSI support */ |
3999 | pnv_pci_init_ioda_msis(phb); | |
4000 | ||
c40a4210 GS |
4001 | /* |
4002 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
4003 | * to let the PCI core do resource assignment. It's supposed | |
4004 | * that the PCI core will do correct I/O and MMIO alignment | |
4005 | * for the P2P bridge bars so that each PCI bus (excluding | |
4006 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 4007 | */ |
fb446ad0 | 4008 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
5d2aa710 | 4009 | |
f9f83456 | 4010 | if (phb->type == PNV_PHB_NPU) { |
5d2aa710 | 4011 | hose->controller_ops = pnv_npu_ioda_controller_ops; |
f9f83456 AK |
4012 | } else { |
4013 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
5d2aa710 | 4014 | hose->controller_ops = pnv_pci_ioda_controller_ops; |
f9f83456 | 4015 | } |
ad30cb99 | 4016 | |
38274637 YX |
4017 | ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; |
4018 | ||
6e628c7d WY |
4019 | #ifdef CONFIG_PCI_IOV |
4020 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; | |
5350ab3f | 4021 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
ad30cb99 ME |
4022 | #endif |
4023 | ||
c40a4210 | 4024 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
4025 | |
4026 | /* Reset IODA tables to a clean state */ | |
d1a85eee | 4027 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
184cd4a3 | 4028 | if (rc) |
f11fe552 | 4029 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
361f2a2a | 4030 | |
6060e9ea AD |
4031 | /* |
4032 | * If we're running in kdump kernel, the previous kernel never | |
361f2a2a GS |
4033 | * shutdown PCI devices correctly. We already got IODA table |
4034 | * cleaned out. So we have to issue PHB reset to stop all PCI | |
6060e9ea | 4035 | * transactions from previous kernel. |
361f2a2a GS |
4036 | */ |
4037 | if (is_kdump_kernel()) { | |
4038 | pr_info(" Issue PHB reset ...\n"); | |
cadf364d GS |
4039 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
4040 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); | |
361f2a2a | 4041 | } |
262af557 | 4042 | |
9e9e8935 GS |
4043 | /* Remove M64 resource if we can't configure it successfully */ |
4044 | if (!phb->init_m64 || phb->init_m64(phb)) | |
262af557 | 4045 | hose->mem_resources[1].flags = 0; |
aa0c033f GS |
4046 | } |
4047 | ||
67975005 | 4048 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 4049 | { |
e9cc17d4 | 4050 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
4051 | } |
4052 | ||
5d2aa710 AP |
4053 | void __init pnv_pci_init_npu_phb(struct device_node *np) |
4054 | { | |
4055 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); | |
4056 | } | |
4057 | ||
184cd4a3 BH |
4058 | void __init pnv_pci_init_ioda_hub(struct device_node *np) |
4059 | { | |
4060 | struct device_node *phbn; | |
c681b93c | 4061 | const __be64 *prop64; |
184cd4a3 BH |
4062 | u64 hub_id; |
4063 | ||
b7c670d6 | 4064 | pr_info("Probing IODA IO-Hub %pOF\n", np); |
184cd4a3 BH |
4065 | |
4066 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
4067 | if (!prop64) { | |
4068 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
4069 | return; | |
4070 | } | |
4071 | hub_id = be64_to_cpup(prop64); | |
4072 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
4073 | ||
4074 | /* Count child PHBs */ | |
4075 | for_each_child_of_node(np, phbn) { | |
4076 | /* Look for IODA1 PHBs */ | |
4077 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 4078 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
4079 | } |
4080 | } |