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184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
37c367f2 | 16 | #include <linux/debugfs.h> |
184cd4a3 BH |
17 | #include <linux/delay.h> |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/msi.h> | |
24 | ||
25 | #include <asm/sections.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/prom.h> | |
28 | #include <asm/pci-bridge.h> | |
29 | #include <asm/machdep.h> | |
fb1b55d6 | 30 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
31 | #include <asm/ppc-pci.h> |
32 | #include <asm/opal.h> | |
33 | #include <asm/iommu.h> | |
34 | #include <asm/tce.h> | |
137436c9 | 35 | #include <asm/xics.h> |
37c367f2 | 36 | #include <asm/debug.h> |
184cd4a3 BH |
37 | |
38 | #include "powernv.h" | |
39 | #include "pci.h" | |
40 | ||
184cd4a3 BH |
41 | #define define_pe_printk_level(func, kern_level) \ |
42 | static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ | |
43 | { \ | |
44 | struct va_format vaf; \ | |
45 | va_list args; \ | |
490e078d | 46 | char pfix[32]; \ |
184cd4a3 BH |
47 | int r; \ |
48 | \ | |
49 | va_start(args, fmt); \ | |
50 | \ | |
51 | vaf.fmt = fmt; \ | |
52 | vaf.va = &args; \ | |
53 | \ | |
490e078d GS |
54 | if (pe->pdev) \ |
55 | strlcpy(pfix, dev_name(&pe->pdev->dev), \ | |
56 | sizeof(pfix)); \ | |
57 | else \ | |
58 | sprintf(pfix, "%04x:%02x ", \ | |
59 | pci_domain_nr(pe->pbus), \ | |
60 | pe->pbus->number); \ | |
61 | r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ | |
62 | pfix, pe->pe_number, &vaf); \ | |
63 | \ | |
184cd4a3 BH |
64 | va_end(args); \ |
65 | \ | |
66 | return r; \ | |
67 | } \ | |
68 | ||
69 | define_pe_printk_level(pe_err, KERN_ERR); | |
70 | define_pe_printk_level(pe_warn, KERN_WARNING); | |
71 | define_pe_printk_level(pe_info, KERN_INFO); | |
72 | ||
8e0a1611 AK |
73 | /* |
74 | * stdcix is only supposed to be used in hypervisor real mode as per | |
75 | * the architecture spec | |
76 | */ | |
77 | static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) | |
78 | { | |
79 | __asm__ __volatile__("stdcix %0,0,%1" | |
80 | : : "r" (val), "r" (paddr) : "memory"); | |
81 | } | |
82 | ||
cad5cef6 | 83 | static int pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 BH |
84 | { |
85 | unsigned long pe; | |
86 | ||
87 | do { | |
88 | pe = find_next_zero_bit(phb->ioda.pe_alloc, | |
89 | phb->ioda.total_pe, 0); | |
90 | if (pe >= phb->ioda.total_pe) | |
91 | return IODA_INVALID_PE; | |
92 | } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); | |
93 | ||
4cce9550 | 94 | phb->ioda.pe_array[pe].phb = phb; |
184cd4a3 BH |
95 | phb->ioda.pe_array[pe].pe_number = pe; |
96 | return pe; | |
97 | } | |
98 | ||
cad5cef6 | 99 | static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) |
184cd4a3 BH |
100 | { |
101 | WARN_ON(phb->ioda.pe_array[pe].pdev); | |
102 | ||
103 | memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe)); | |
104 | clear_bit(pe, phb->ioda.pe_alloc); | |
105 | } | |
106 | ||
107 | /* Currently those 2 are only used when MSIs are enabled, this will change | |
108 | * but in the meantime, we need to protect them to avoid warnings | |
109 | */ | |
110 | #ifdef CONFIG_PCI_MSI | |
cad5cef6 | 111 | static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
112 | { |
113 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
114 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 115 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
116 | |
117 | if (!pdn) | |
118 | return NULL; | |
119 | if (pdn->pe_number == IODA_INVALID_PE) | |
120 | return NULL; | |
121 | return &phb->ioda.pe_array[pdn->pe_number]; | |
122 | } | |
184cd4a3 BH |
123 | #endif /* CONFIG_PCI_MSI */ |
124 | ||
cad5cef6 | 125 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
126 | { |
127 | struct pci_dev *parent; | |
128 | uint8_t bcomp, dcomp, fcomp; | |
129 | long rc, rid_end, rid; | |
130 | ||
131 | /* Bus validation ? */ | |
132 | if (pe->pbus) { | |
133 | int count; | |
134 | ||
135 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
136 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
137 | parent = pe->pbus->self; | |
fb446ad0 GS |
138 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
139 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
140 | else | |
141 | count = 1; | |
142 | ||
184cd4a3 BH |
143 | switch(count) { |
144 | case 1: bcomp = OpalPciBusAll; break; | |
145 | case 2: bcomp = OpalPciBus7Bits; break; | |
146 | case 4: bcomp = OpalPciBus6Bits; break; | |
147 | case 8: bcomp = OpalPciBus5Bits; break; | |
148 | case 16: bcomp = OpalPciBus4Bits; break; | |
149 | case 32: bcomp = OpalPciBus3Bits; break; | |
150 | default: | |
151 | pr_err("%s: Number of subordinate busses %d" | |
152 | " unsupported\n", | |
153 | pci_name(pe->pbus->self), count); | |
154 | /* Do an exact match only */ | |
155 | bcomp = OpalPciBusAll; | |
156 | } | |
157 | rid_end = pe->rid + (count << 8); | |
158 | } else { | |
159 | parent = pe->pdev->bus->self; | |
160 | bcomp = OpalPciBusAll; | |
161 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
162 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
163 | rid_end = pe->rid + 1; | |
164 | } | |
165 | ||
631ad691 GS |
166 | /* |
167 | * Associate PE in PELT. We need add the PE into the | |
168 | * corresponding PELT-V as well. Otherwise, the error | |
169 | * originated from the PE might contribute to other | |
170 | * PEs. | |
171 | */ | |
184cd4a3 BH |
172 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
173 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
174 | if (rc) { | |
175 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
176 | return -ENXIO; | |
177 | } | |
631ad691 GS |
178 | |
179 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
180 | pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); | |
181 | if (rc) | |
182 | pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc); | |
184cd4a3 BH |
183 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
184 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
185 | ||
186 | /* Add to all parents PELT-V */ | |
187 | while (parent) { | |
b72c1f65 | 188 | struct pci_dn *pdn = pci_get_pdn(parent); |
184cd4a3 BH |
189 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { |
190 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
cee72d5b | 191 | pe->pe_number, OPAL_ADD_PE_TO_DOMAIN); |
184cd4a3 BH |
192 | /* XXX What to do in case of error ? */ |
193 | } | |
194 | parent = parent->bus->self; | |
195 | } | |
196 | /* Setup reverse map */ | |
197 | for (rid = pe->rid; rid < rid_end; rid++) | |
198 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
199 | ||
200 | /* Setup one MVTs on IODA1 */ | |
201 | if (phb->type == PNV_PHB_IODA1) { | |
202 | pe->mve_number = pe->pe_number; | |
203 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, | |
204 | pe->pe_number); | |
205 | if (rc) { | |
206 | pe_err(pe, "OPAL error %ld setting up MVE %d\n", | |
207 | rc, pe->mve_number); | |
208 | pe->mve_number = -1; | |
209 | } else { | |
210 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
cee72d5b | 211 | pe->mve_number, OPAL_ENABLE_MVE); |
184cd4a3 BH |
212 | if (rc) { |
213 | pe_err(pe, "OPAL error %ld enabling MVE %d\n", | |
214 | rc, pe->mve_number); | |
215 | pe->mve_number = -1; | |
216 | } | |
217 | } | |
218 | } else if (phb->type == PNV_PHB_IODA2) | |
219 | pe->mve_number = 0; | |
220 | ||
221 | return 0; | |
222 | } | |
223 | ||
cad5cef6 GKH |
224 | static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, |
225 | struct pnv_ioda_pe *pe) | |
184cd4a3 BH |
226 | { |
227 | struct pnv_ioda_pe *lpe; | |
228 | ||
7ebdf956 | 229 | list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 | 230 | if (lpe->dma_weight < pe->dma_weight) { |
7ebdf956 | 231 | list_add_tail(&pe->dma_link, &lpe->dma_link); |
184cd4a3 BH |
232 | return; |
233 | } | |
234 | } | |
7ebdf956 | 235 | list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list); |
184cd4a3 BH |
236 | } |
237 | ||
238 | static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev) | |
239 | { | |
240 | /* This is quite simplistic. The "base" weight of a device | |
241 | * is 10. 0 means no DMA is to be accounted for it. | |
242 | */ | |
243 | ||
244 | /* If it's a bridge, no DMA */ | |
245 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
246 | return 0; | |
247 | ||
248 | /* Reduce the weight of slow USB controllers */ | |
249 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
250 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
251 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
252 | return 3; | |
253 | ||
254 | /* Increase the weight of RAID (includes Obsidian) */ | |
255 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
256 | return 15; | |
257 | ||
258 | /* Default */ | |
259 | return 10; | |
260 | } | |
261 | ||
fb446ad0 | 262 | #if 0 |
cad5cef6 | 263 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
264 | { |
265 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
266 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 267 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
268 | struct pnv_ioda_pe *pe; |
269 | int pe_num; | |
270 | ||
271 | if (!pdn) { | |
272 | pr_err("%s: Device tree node not associated properly\n", | |
273 | pci_name(dev)); | |
274 | return NULL; | |
275 | } | |
276 | if (pdn->pe_number != IODA_INVALID_PE) | |
277 | return NULL; | |
278 | ||
279 | /* PE#0 has been pre-set */ | |
280 | if (dev->bus->number == 0) | |
281 | pe_num = 0; | |
282 | else | |
283 | pe_num = pnv_ioda_alloc_pe(phb); | |
284 | if (pe_num == IODA_INVALID_PE) { | |
285 | pr_warning("%s: Not enough PE# available, disabling device\n", | |
286 | pci_name(dev)); | |
287 | return NULL; | |
288 | } | |
289 | ||
290 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
291 | * pointer in the PE data structure, both should be destroyed at the | |
292 | * same time. However, this needs to be looked at more closely again | |
293 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
294 | * | |
295 | * At some point we want to remove the PDN completely anyways | |
296 | */ | |
297 | pe = &phb->ioda.pe_array[pe_num]; | |
298 | pci_dev_get(dev); | |
299 | pdn->pcidev = dev; | |
300 | pdn->pe_number = pe_num; | |
301 | pe->pdev = dev; | |
302 | pe->pbus = NULL; | |
303 | pe->tce32_seg = -1; | |
304 | pe->mve_number = -1; | |
305 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
306 | ||
307 | pe_info(pe, "Associated device to PE\n"); | |
308 | ||
309 | if (pnv_ioda_configure_pe(phb, pe)) { | |
310 | /* XXX What do we do here ? */ | |
311 | if (pe_num) | |
312 | pnv_ioda_free_pe(phb, pe_num); | |
313 | pdn->pe_number = IODA_INVALID_PE; | |
314 | pe->pdev = NULL; | |
315 | pci_dev_put(dev); | |
316 | return NULL; | |
317 | } | |
318 | ||
319 | /* Assign a DMA weight to the device */ | |
320 | pe->dma_weight = pnv_ioda_dma_weight(dev); | |
321 | if (pe->dma_weight != 0) { | |
322 | phb->ioda.dma_weight += pe->dma_weight; | |
323 | phb->ioda.dma_pe_count++; | |
324 | } | |
325 | ||
326 | /* Link the PE */ | |
327 | pnv_ioda_link_pe_by_weight(phb, pe); | |
328 | ||
329 | return pe; | |
330 | } | |
fb446ad0 | 331 | #endif /* Useful for SRIOV case */ |
184cd4a3 BH |
332 | |
333 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
334 | { | |
335 | struct pci_dev *dev; | |
336 | ||
337 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 338 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
339 | |
340 | if (pdn == NULL) { | |
341 | pr_warn("%s: No device node associated with device !\n", | |
342 | pci_name(dev)); | |
343 | continue; | |
344 | } | |
345 | pci_dev_get(dev); | |
346 | pdn->pcidev = dev; | |
347 | pdn->pe_number = pe->pe_number; | |
348 | pe->dma_weight += pnv_ioda_dma_weight(dev); | |
fb446ad0 | 349 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
350 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
351 | } | |
352 | } | |
353 | ||
fb446ad0 GS |
354 | /* |
355 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
356 | * single PCI bus. Another one that contains the primary PCI bus and its | |
357 | * subordinate PCI devices and buses. The second type of PE is normally | |
358 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
359 | */ | |
cad5cef6 | 360 | static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) |
184cd4a3 | 361 | { |
fb446ad0 | 362 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 363 | struct pnv_phb *phb = hose->private_data; |
184cd4a3 BH |
364 | struct pnv_ioda_pe *pe; |
365 | int pe_num; | |
366 | ||
184cd4a3 BH |
367 | pe_num = pnv_ioda_alloc_pe(phb); |
368 | if (pe_num == IODA_INVALID_PE) { | |
fb446ad0 GS |
369 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
370 | __func__, pci_domain_nr(bus), bus->number); | |
184cd4a3 BH |
371 | return; |
372 | } | |
373 | ||
374 | pe = &phb->ioda.pe_array[pe_num]; | |
fb446ad0 | 375 | pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
376 | pe->pbus = bus; |
377 | pe->pdev = NULL; | |
378 | pe->tce32_seg = -1; | |
379 | pe->mve_number = -1; | |
b918c62e | 380 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 BH |
381 | pe->dma_weight = 0; |
382 | ||
fb446ad0 GS |
383 | if (all) |
384 | pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", | |
385 | bus->busn_res.start, bus->busn_res.end, pe_num); | |
386 | else | |
387 | pe_info(pe, "Secondary bus %d associated with PE#%d\n", | |
388 | bus->busn_res.start, pe_num); | |
184cd4a3 BH |
389 | |
390 | if (pnv_ioda_configure_pe(phb, pe)) { | |
391 | /* XXX What do we do here ? */ | |
392 | if (pe_num) | |
393 | pnv_ioda_free_pe(phb, pe_num); | |
394 | pe->pbus = NULL; | |
395 | return; | |
396 | } | |
397 | ||
398 | /* Associate it with all child devices */ | |
399 | pnv_ioda_setup_same_PE(bus, pe); | |
400 | ||
7ebdf956 GS |
401 | /* Put PE to the list */ |
402 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
403 | ||
184cd4a3 BH |
404 | /* Account for one DMA PE if at least one DMA capable device exist |
405 | * below the bridge | |
406 | */ | |
407 | if (pe->dma_weight != 0) { | |
408 | phb->ioda.dma_weight += pe->dma_weight; | |
409 | phb->ioda.dma_pe_count++; | |
410 | } | |
411 | ||
412 | /* Link the PE */ | |
413 | pnv_ioda_link_pe_by_weight(phb, pe); | |
414 | } | |
415 | ||
cad5cef6 | 416 | static void pnv_ioda_setup_PEs(struct pci_bus *bus) |
184cd4a3 BH |
417 | { |
418 | struct pci_dev *dev; | |
fb446ad0 GS |
419 | |
420 | pnv_ioda_setup_bus_PE(bus, 0); | |
184cd4a3 BH |
421 | |
422 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
fb446ad0 GS |
423 | if (dev->subordinate) { |
424 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
425 | pnv_ioda_setup_bus_PE(dev->subordinate, 1); | |
426 | else | |
427 | pnv_ioda_setup_PEs(dev->subordinate); | |
428 | } | |
429 | } | |
430 | } | |
431 | ||
432 | /* | |
433 | * Configure PEs so that the downstream PCI buses and devices | |
434 | * could have their associated PE#. Unfortunately, we didn't | |
435 | * figure out the way to identify the PLX bridge yet. So we | |
436 | * simply put the PCI bus and the subordinate behind the root | |
437 | * port to PE# here. The game rule here is expected to be changed | |
438 | * as soon as we can detected PLX bridge correctly. | |
439 | */ | |
cad5cef6 | 440 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
441 | { |
442 | struct pci_controller *hose, *tmp; | |
443 | ||
444 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
445 | pnv_ioda_setup_PEs(hose->bus); | |
184cd4a3 BH |
446 | } |
447 | } | |
448 | ||
959c9bdd | 449 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 450 | { |
b72c1f65 | 451 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 452 | struct pnv_ioda_pe *pe; |
184cd4a3 | 453 | |
959c9bdd GS |
454 | /* |
455 | * The function can be called while the PE# | |
456 | * hasn't been assigned. Do nothing for the | |
457 | * case. | |
458 | */ | |
459 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
460 | return; | |
184cd4a3 | 461 | |
959c9bdd | 462 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
d905c5df | 463 | set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); |
184cd4a3 BH |
464 | } |
465 | ||
74251fe2 BH |
466 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) |
467 | { | |
468 | struct pci_dev *dev; | |
469 | ||
470 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
d905c5df | 471 | set_iommu_table_base_and_group(&dev->dev, &pe->tce32_table); |
74251fe2 BH |
472 | if (dev->subordinate) |
473 | pnv_ioda_setup_bus_dma(pe, dev->subordinate); | |
474 | } | |
475 | } | |
476 | ||
8e0a1611 AK |
477 | static void pnv_pci_ioda1_tce_invalidate(struct pnv_ioda_pe *pe, |
478 | struct iommu_table *tbl, | |
3ad26e5c | 479 | __be64 *startp, __be64 *endp, bool rm) |
4cce9550 | 480 | { |
3ad26e5c BH |
481 | __be64 __iomem *invalidate = rm ? |
482 | (__be64 __iomem *)pe->tce_inval_reg_phys : | |
483 | (__be64 __iomem *)tbl->it_index; | |
4cce9550 GS |
484 | unsigned long start, end, inc; |
485 | ||
486 | start = __pa(startp); | |
487 | end = __pa(endp); | |
488 | ||
489 | /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ | |
490 | if (tbl->it_busno) { | |
491 | start <<= 12; | |
492 | end <<= 12; | |
493 | inc = 128 << 12; | |
494 | start |= tbl->it_busno; | |
495 | end |= tbl->it_busno; | |
496 | } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { | |
497 | /* p7ioc-style invalidation, 2 TCEs per write */ | |
498 | start |= (1ull << 63); | |
499 | end |= (1ull << 63); | |
500 | inc = 16; | |
501 | } else { | |
502 | /* Default (older HW) */ | |
503 | inc = 128; | |
504 | } | |
505 | ||
506 | end |= inc - 1; /* round up end to be different than start */ | |
507 | ||
508 | mb(); /* Ensure above stores are visible */ | |
509 | while (start <= end) { | |
8e0a1611 | 510 | if (rm) |
3ad26e5c | 511 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 512 | else |
3ad26e5c | 513 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
514 | start += inc; |
515 | } | |
516 | ||
517 | /* | |
518 | * The iommu layer will do another mb() for us on build() | |
519 | * and we don't care on free() | |
520 | */ | |
521 | } | |
522 | ||
523 | static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe, | |
524 | struct iommu_table *tbl, | |
3ad26e5c | 525 | __be64 *startp, __be64 *endp, bool rm) |
4cce9550 GS |
526 | { |
527 | unsigned long start, end, inc; | |
3ad26e5c BH |
528 | __be64 __iomem *invalidate = rm ? |
529 | (__be64 __iomem *)pe->tce_inval_reg_phys : | |
530 | (__be64 __iomem *)tbl->it_index; | |
4cce9550 GS |
531 | |
532 | /* We'll invalidate DMA address in PE scope */ | |
533 | start = 0x2ul << 60; | |
534 | start |= (pe->pe_number & 0xFF); | |
535 | end = start; | |
536 | ||
537 | /* Figure out the start, end and step */ | |
538 | inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64)); | |
539 | start |= (inc << 12); | |
540 | inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64)); | |
541 | end |= (inc << 12); | |
542 | inc = (0x1ul << 12); | |
543 | mb(); | |
544 | ||
545 | while (start <= end) { | |
8e0a1611 | 546 | if (rm) |
3ad26e5c | 547 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 548 | else |
3ad26e5c | 549 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
550 | start += inc; |
551 | } | |
552 | } | |
553 | ||
554 | void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, | |
3ad26e5c | 555 | __be64 *startp, __be64 *endp, bool rm) |
4cce9550 GS |
556 | { |
557 | struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, | |
558 | tce32_table); | |
559 | struct pnv_phb *phb = pe->phb; | |
560 | ||
561 | if (phb->type == PNV_PHB_IODA1) | |
8e0a1611 | 562 | pnv_pci_ioda1_tce_invalidate(pe, tbl, startp, endp, rm); |
4cce9550 | 563 | else |
8e0a1611 | 564 | pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp, rm); |
4cce9550 GS |
565 | } |
566 | ||
cad5cef6 GKH |
567 | static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, |
568 | struct pnv_ioda_pe *pe, unsigned int base, | |
569 | unsigned int segs) | |
184cd4a3 BH |
570 | { |
571 | ||
572 | struct page *tce_mem = NULL; | |
573 | const __be64 *swinvp; | |
574 | struct iommu_table *tbl; | |
575 | unsigned int i; | |
576 | int64_t rc; | |
577 | void *addr; | |
578 | ||
579 | /* 256M DMA window, 4K TCE pages, 8 bytes TCE */ | |
580 | #define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8) | |
581 | ||
582 | /* XXX FIXME: Handle 64-bit only DMA devices */ | |
583 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
584 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
585 | ||
586 | /* We shouldn't already have a 32-bit DMA associated */ | |
587 | if (WARN_ON(pe->tce32_seg >= 0)) | |
588 | return; | |
589 | ||
590 | /* Grab a 32-bit TCE table */ | |
591 | pe->tce32_seg = base; | |
592 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", | |
593 | (base << 28), ((base + segs) << 28) - 1); | |
594 | ||
595 | /* XXX Currently, we allocate one big contiguous table for the | |
596 | * TCEs. We only really need one chunk per 256M of TCE space | |
597 | * (ie per segment) but that's an optimization for later, it | |
598 | * requires some added smarts with our get/put_tce implementation | |
599 | */ | |
600 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
601 | get_order(TCE32_TABLE_SIZE * segs)); | |
602 | if (!tce_mem) { | |
603 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
604 | goto fail; | |
605 | } | |
606 | addr = page_address(tce_mem); | |
607 | memset(addr, 0, TCE32_TABLE_SIZE * segs); | |
608 | ||
609 | /* Configure HW */ | |
610 | for (i = 0; i < segs; i++) { | |
611 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
612 | pe->pe_number, | |
613 | base + i, 1, | |
614 | __pa(addr) + TCE32_TABLE_SIZE * i, | |
615 | TCE32_TABLE_SIZE, 0x1000); | |
616 | if (rc) { | |
617 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
618 | " err %ld\n", rc); | |
619 | goto fail; | |
620 | } | |
621 | } | |
622 | ||
623 | /* Setup linux iommu table */ | |
624 | tbl = &pe->tce32_table; | |
625 | pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, | |
626 | base << 28); | |
627 | ||
628 | /* OPAL variant of P7IOC SW invalidated TCEs */ | |
629 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
630 | if (swinvp) { | |
631 | /* We need a couple more fields -- an address and a data | |
632 | * to or. Since the bus is only printed out on table free | |
633 | * errors, and on the first pass the data will be a relative | |
634 | * bus number, print that out instead. | |
635 | */ | |
636 | tbl->it_busno = 0; | |
8e0a1611 AK |
637 | pe->tce_inval_reg_phys = be64_to_cpup(swinvp); |
638 | tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, | |
639 | 8); | |
373f5657 GS |
640 | tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE | |
641 | TCE_PCI_SWINV_PAIR; | |
184cd4a3 BH |
642 | } |
643 | iommu_init_table(tbl, phb->hose->node); | |
4e13c1ac | 644 | iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); |
184cd4a3 | 645 | |
74251fe2 | 646 | if (pe->pdev) |
d905c5df | 647 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); |
74251fe2 BH |
648 | else |
649 | pnv_ioda_setup_bus_dma(pe, pe->pbus); | |
650 | ||
184cd4a3 BH |
651 | return; |
652 | fail: | |
653 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
654 | if (pe->tce32_seg >= 0) | |
655 | pe->tce32_seg = -1; | |
656 | if (tce_mem) | |
657 | __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); | |
658 | } | |
659 | ||
373f5657 GS |
660 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
661 | struct pnv_ioda_pe *pe) | |
662 | { | |
663 | struct page *tce_mem = NULL; | |
664 | void *addr; | |
665 | const __be64 *swinvp; | |
666 | struct iommu_table *tbl; | |
667 | unsigned int tce_table_size, end; | |
668 | int64_t rc; | |
669 | ||
670 | /* We shouldn't already have a 32-bit DMA associated */ | |
671 | if (WARN_ON(pe->tce32_seg >= 0)) | |
672 | return; | |
673 | ||
674 | /* The PE will reserve all possible 32-bits space */ | |
675 | pe->tce32_seg = 0; | |
676 | end = (1 << ilog2(phb->ioda.m32_pci_base)); | |
677 | tce_table_size = (end / 0x1000) * 8; | |
678 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", | |
679 | end); | |
680 | ||
681 | /* Allocate TCE table */ | |
682 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, | |
683 | get_order(tce_table_size)); | |
684 | if (!tce_mem) { | |
685 | pe_err(pe, "Failed to allocate a 32-bit TCE memory\n"); | |
686 | goto fail; | |
687 | } | |
688 | addr = page_address(tce_mem); | |
689 | memset(addr, 0, tce_table_size); | |
690 | ||
691 | /* | |
692 | * Map TCE table through TVT. The TVE index is the PE number | |
693 | * shifted by 1 bit for 32-bits DMA space. | |
694 | */ | |
695 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
696 | pe->pe_number << 1, 1, __pa(addr), | |
697 | tce_table_size, 0x1000); | |
698 | if (rc) { | |
699 | pe_err(pe, "Failed to configure 32-bit TCE table," | |
700 | " err %ld\n", rc); | |
701 | goto fail; | |
702 | } | |
703 | ||
704 | /* Setup linux iommu table */ | |
705 | tbl = &pe->tce32_table; | |
706 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0); | |
707 | ||
708 | /* OPAL variant of PHB3 invalidated TCEs */ | |
709 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
710 | if (swinvp) { | |
711 | /* We need a couple more fields -- an address and a data | |
712 | * to or. Since the bus is only printed out on table free | |
713 | * errors, and on the first pass the data will be a relative | |
714 | * bus number, print that out instead. | |
715 | */ | |
716 | tbl->it_busno = 0; | |
8e0a1611 AK |
717 | pe->tce_inval_reg_phys = be64_to_cpup(swinvp); |
718 | tbl->it_index = (unsigned long)ioremap(pe->tce_inval_reg_phys, | |
719 | 8); | |
373f5657 GS |
720 | tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; |
721 | } | |
722 | iommu_init_table(tbl, phb->hose->node); | |
08607afb | 723 | iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number); |
373f5657 | 724 | |
74251fe2 | 725 | if (pe->pdev) |
d905c5df | 726 | set_iommu_table_base_and_group(&pe->pdev->dev, tbl); |
74251fe2 BH |
727 | else |
728 | pnv_ioda_setup_bus_dma(pe, pe->pbus); | |
729 | ||
373f5657 GS |
730 | return; |
731 | fail: | |
732 | if (pe->tce32_seg >= 0) | |
733 | pe->tce32_seg = -1; | |
734 | if (tce_mem) | |
735 | __free_pages(tce_mem, get_order(tce_table_size)); | |
736 | } | |
737 | ||
cad5cef6 | 738 | static void pnv_ioda_setup_dma(struct pnv_phb *phb) |
184cd4a3 BH |
739 | { |
740 | struct pci_controller *hose = phb->hose; | |
741 | unsigned int residual, remaining, segs, tw, base; | |
742 | struct pnv_ioda_pe *pe; | |
743 | ||
744 | /* If we have more PE# than segments available, hand out one | |
745 | * per PE until we run out and let the rest fail. If not, | |
746 | * then we assign at least one segment per PE, plus more based | |
747 | * on the amount of devices under that PE | |
748 | */ | |
749 | if (phb->ioda.dma_pe_count > phb->ioda.tce32_count) | |
750 | residual = 0; | |
751 | else | |
752 | residual = phb->ioda.tce32_count - | |
753 | phb->ioda.dma_pe_count; | |
754 | ||
755 | pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n", | |
756 | hose->global_number, phb->ioda.tce32_count); | |
757 | pr_info("PCI: %d PE# for a total weight of %d\n", | |
758 | phb->ioda.dma_pe_count, phb->ioda.dma_weight); | |
759 | ||
760 | /* Walk our PE list and configure their DMA segments, hand them | |
761 | * out one base segment plus any residual segments based on | |
762 | * weight | |
763 | */ | |
764 | remaining = phb->ioda.tce32_count; | |
765 | tw = phb->ioda.dma_weight; | |
766 | base = 0; | |
7ebdf956 | 767 | list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { |
184cd4a3 BH |
768 | if (!pe->dma_weight) |
769 | continue; | |
770 | if (!remaining) { | |
771 | pe_warn(pe, "No DMA32 resources available\n"); | |
772 | continue; | |
773 | } | |
774 | segs = 1; | |
775 | if (residual) { | |
776 | segs += ((pe->dma_weight * residual) + (tw / 2)) / tw; | |
777 | if (segs > remaining) | |
778 | segs = remaining; | |
779 | } | |
373f5657 GS |
780 | |
781 | /* | |
782 | * For IODA2 compliant PHB3, we needn't care about the weight. | |
783 | * The all available 32-bits DMA space will be assigned to | |
784 | * the specific PE. | |
785 | */ | |
786 | if (phb->type == PNV_PHB_IODA1) { | |
787 | pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", | |
788 | pe->dma_weight, segs); | |
789 | pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); | |
790 | } else { | |
791 | pe_info(pe, "Assign DMA32 space\n"); | |
792 | segs = 0; | |
793 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
794 | } | |
795 | ||
184cd4a3 BH |
796 | remaining -= segs; |
797 | base += segs; | |
798 | } | |
799 | } | |
800 | ||
801 | #ifdef CONFIG_PCI_MSI | |
137436c9 GS |
802 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
803 | { | |
804 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); | |
805 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
806 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, | |
807 | ioda.irq_chip); | |
808 | int64_t rc; | |
809 | ||
810 | rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
811 | WARN_ON_ONCE(rc); | |
812 | ||
813 | icp_native_eoi(d); | |
814 | } | |
815 | ||
184cd4a3 | 816 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
817 | unsigned int hwirq, unsigned int virq, |
818 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
819 | { |
820 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
b72c1f65 | 821 | struct pci_dn *pdn = pci_get_pdn(dev); |
137436c9 GS |
822 | struct irq_data *idata; |
823 | struct irq_chip *ichip; | |
184cd4a3 | 824 | unsigned int xive_num = hwirq - phb->msi_base; |
3a1a4661 | 825 | __be32 data; |
184cd4a3 BH |
826 | int rc; |
827 | ||
828 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
829 | if (pe == NULL) | |
830 | return -ENXIO; | |
831 | ||
832 | /* Check if we have an MVE */ | |
833 | if (pe->mve_number < 0) | |
834 | return -ENXIO; | |
835 | ||
b72c1f65 BH |
836 | /* Force 32-bit MSI on some broken devices */ |
837 | if (pdn && pdn->force_32bit_msi) | |
838 | is_64 = 0; | |
839 | ||
184cd4a3 BH |
840 | /* Assign XIVE to PE */ |
841 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
842 | if (rc) { | |
843 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
844 | pci_name(dev), rc, xive_num); | |
845 | return -EIO; | |
846 | } | |
847 | ||
848 | if (is_64) { | |
3a1a4661 BH |
849 | __be64 addr64; |
850 | ||
184cd4a3 BH |
851 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
852 | &addr64, &data); | |
853 | if (rc) { | |
854 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
855 | pci_name(dev), rc); | |
856 | return -EIO; | |
857 | } | |
3a1a4661 BH |
858 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
859 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 860 | } else { |
3a1a4661 BH |
861 | __be32 addr32; |
862 | ||
184cd4a3 BH |
863 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
864 | &addr32, &data); | |
865 | if (rc) { | |
866 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
867 | pci_name(dev), rc); | |
868 | return -EIO; | |
869 | } | |
870 | msg->address_hi = 0; | |
3a1a4661 | 871 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 872 | } |
3a1a4661 | 873 | msg->data = be32_to_cpu(data); |
184cd4a3 | 874 | |
137436c9 GS |
875 | /* |
876 | * Change the IRQ chip for the MSI interrupts on PHB3. | |
877 | * The corresponding IRQ chip should be populated for | |
878 | * the first time. | |
879 | */ | |
880 | if (phb->type == PNV_PHB_IODA2) { | |
881 | if (!phb->ioda.irq_chip_init) { | |
882 | idata = irq_get_irq_data(virq); | |
883 | ichip = irq_data_get_irq_chip(idata); | |
884 | phb->ioda.irq_chip_init = 1; | |
885 | phb->ioda.irq_chip = *ichip; | |
886 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
887 | } | |
888 | ||
889 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
890 | } | |
891 | ||
184cd4a3 BH |
892 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
893 | " address=%x_%08x data=%x PE# %d\n", | |
894 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, | |
895 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
901 | { | |
fb1b55d6 | 902 | unsigned int count; |
184cd4a3 BH |
903 | const __be32 *prop = of_get_property(phb->hose->dn, |
904 | "ibm,opal-msi-ranges", NULL); | |
905 | if (!prop) { | |
906 | /* BML Fallback */ | |
907 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
908 | } | |
909 | if (!prop) | |
910 | return; | |
911 | ||
912 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
913 | count = be32_to_cpup(prop + 1); |
914 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
915 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
916 | phb->hose->global_number); | |
917 | return; | |
918 | } | |
fb1b55d6 | 919 | |
184cd4a3 BH |
920 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
921 | phb->msi32_support = 1; | |
922 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 923 | count, phb->msi_base); |
184cd4a3 BH |
924 | } |
925 | #else | |
926 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
927 | #endif /* CONFIG_PCI_MSI */ | |
928 | ||
11685bec GS |
929 | /* |
930 | * This function is supposed to be called on basis of PE from top | |
931 | * to bottom style. So the the I/O or MMIO segment assigned to | |
932 | * parent PE could be overrided by its child PEs if necessary. | |
933 | */ | |
cad5cef6 GKH |
934 | static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, |
935 | struct pnv_ioda_pe *pe) | |
11685bec GS |
936 | { |
937 | struct pnv_phb *phb = hose->private_data; | |
938 | struct pci_bus_region region; | |
939 | struct resource *res; | |
940 | int i, index; | |
941 | int rc; | |
942 | ||
943 | /* | |
944 | * NOTE: We only care PCI bus based PE for now. For PCI | |
945 | * device based PE, for example SRIOV sensitive VF should | |
946 | * be figured out later. | |
947 | */ | |
948 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
949 | ||
950 | pci_bus_for_each_resource(pe->pbus, res, i) { | |
951 | if (!res || !res->flags || | |
952 | res->start > res->end) | |
953 | continue; | |
954 | ||
955 | if (res->flags & IORESOURCE_IO) { | |
956 | region.start = res->start - phb->ioda.io_pci_base; | |
957 | region.end = res->end - phb->ioda.io_pci_base; | |
958 | index = region.start / phb->ioda.io_segsize; | |
959 | ||
960 | while (index < phb->ioda.total_pe && | |
961 | region.start <= region.end) { | |
962 | phb->ioda.io_segmap[index] = pe->pe_number; | |
963 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
964 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
965 | if (rc != OPAL_SUCCESS) { | |
966 | pr_err("%s: OPAL error %d when mapping IO " | |
967 | "segment #%d to PE#%d\n", | |
968 | __func__, rc, index, pe->pe_number); | |
969 | break; | |
970 | } | |
971 | ||
972 | region.start += phb->ioda.io_segsize; | |
973 | index++; | |
974 | } | |
975 | } else if (res->flags & IORESOURCE_MEM) { | |
3fd47f06 BH |
976 | /* WARNING: Assumes M32 is mem region 0 in PHB. We need to |
977 | * harden that algorithm when we start supporting M64 | |
978 | */ | |
11685bec | 979 | region.start = res->start - |
3fd47f06 | 980 | hose->mem_offset[0] - |
11685bec GS |
981 | phb->ioda.m32_pci_base; |
982 | region.end = res->end - | |
3fd47f06 | 983 | hose->mem_offset[0] - |
11685bec GS |
984 | phb->ioda.m32_pci_base; |
985 | index = region.start / phb->ioda.m32_segsize; | |
986 | ||
987 | while (index < phb->ioda.total_pe && | |
988 | region.start <= region.end) { | |
989 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
990 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
991 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
992 | if (rc != OPAL_SUCCESS) { | |
993 | pr_err("%s: OPAL error %d when mapping M32 " | |
994 | "segment#%d to PE#%d", | |
995 | __func__, rc, index, pe->pe_number); | |
996 | break; | |
997 | } | |
998 | ||
999 | region.start += phb->ioda.m32_segsize; | |
1000 | index++; | |
1001 | } | |
1002 | } | |
1003 | } | |
1004 | } | |
1005 | ||
cad5cef6 | 1006 | static void pnv_pci_ioda_setup_seg(void) |
11685bec GS |
1007 | { |
1008 | struct pci_controller *tmp, *hose; | |
1009 | struct pnv_phb *phb; | |
1010 | struct pnv_ioda_pe *pe; | |
1011 | ||
1012 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1013 | phb = hose->private_data; | |
1014 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
1015 | pnv_ioda_setup_pe_seg(hose, pe); | |
1016 | } | |
1017 | } | |
1018 | } | |
1019 | ||
cad5cef6 | 1020 | static void pnv_pci_ioda_setup_DMA(void) |
13395c48 GS |
1021 | { |
1022 | struct pci_controller *hose, *tmp; | |
db1266c8 | 1023 | struct pnv_phb *phb; |
13395c48 GS |
1024 | |
1025 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1026 | pnv_ioda_setup_dma(hose->private_data); | |
db1266c8 GS |
1027 | |
1028 | /* Mark the PHB initialization done */ | |
1029 | phb = hose->private_data; | |
1030 | phb->initialized = 1; | |
13395c48 GS |
1031 | } |
1032 | } | |
1033 | ||
37c367f2 GS |
1034 | static void pnv_pci_ioda_create_dbgfs(void) |
1035 | { | |
1036 | #ifdef CONFIG_DEBUG_FS | |
1037 | struct pci_controller *hose, *tmp; | |
1038 | struct pnv_phb *phb; | |
1039 | char name[16]; | |
1040 | ||
1041 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1042 | phb = hose->private_data; | |
1043 | ||
1044 | sprintf(name, "PCI%04x", hose->global_number); | |
1045 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
1046 | if (!phb->dbgfs) | |
1047 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", | |
1048 | __func__, hose->global_number); | |
1049 | } | |
1050 | #endif /* CONFIG_DEBUG_FS */ | |
1051 | } | |
1052 | ||
cad5cef6 | 1053 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
1054 | { |
1055 | pnv_pci_ioda_setup_PEs(); | |
11685bec | 1056 | pnv_pci_ioda_setup_seg(); |
13395c48 | 1057 | pnv_pci_ioda_setup_DMA(); |
e9cc17d4 | 1058 | |
37c367f2 GS |
1059 | pnv_pci_ioda_create_dbgfs(); |
1060 | ||
e9cc17d4 | 1061 | #ifdef CONFIG_EEH |
88b6d14b | 1062 | eeh_probe_mode_set(EEH_PROBE_MODE_DEV); |
e9cc17d4 GS |
1063 | eeh_addr_cache_build(); |
1064 | eeh_init(); | |
1065 | #endif | |
fb446ad0 GS |
1066 | } |
1067 | ||
271fd03a GS |
1068 | /* |
1069 | * Returns the alignment for I/O or memory windows for P2P | |
1070 | * bridges. That actually depends on how PEs are segmented. | |
1071 | * For now, we return I/O or M32 segment size for PE sensitive | |
1072 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
1073 | * 1MiB for memory) will be returned. | |
1074 | * | |
1075 | * The current PCI bus might be put into one PE, which was | |
1076 | * create against the parent PCI bridge. For that case, we | |
1077 | * needn't enlarge the alignment so that we can save some | |
1078 | * resources. | |
1079 | */ | |
1080 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
1081 | unsigned long type) | |
1082 | { | |
1083 | struct pci_dev *bridge; | |
1084 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1085 | struct pnv_phb *phb = hose->private_data; | |
1086 | int num_pci_bridges = 0; | |
1087 | ||
1088 | bridge = bus->self; | |
1089 | while (bridge) { | |
1090 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
1091 | num_pci_bridges++; | |
1092 | if (num_pci_bridges >= 2) | |
1093 | return 1; | |
1094 | } | |
1095 | ||
1096 | bridge = bridge->bus->self; | |
1097 | } | |
1098 | ||
1099 | /* We need support prefetchable memory window later */ | |
1100 | if (type & IORESOURCE_MEM) | |
1101 | return phb->ioda.m32_segsize; | |
1102 | ||
1103 | return phb->ioda.io_segsize; | |
1104 | } | |
1105 | ||
184cd4a3 BH |
1106 | /* Prevent enabling devices for which we couldn't properly |
1107 | * assign a PE | |
1108 | */ | |
cad5cef6 | 1109 | static int pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 1110 | { |
db1266c8 GS |
1111 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
1112 | struct pnv_phb *phb = hose->private_data; | |
1113 | struct pci_dn *pdn; | |
184cd4a3 | 1114 | |
db1266c8 GS |
1115 | /* The function is probably called while the PEs have |
1116 | * not be created yet. For example, resource reassignment | |
1117 | * during PCI probe period. We just skip the check if | |
1118 | * PEs isn't ready. | |
1119 | */ | |
1120 | if (!phb->initialized) | |
1121 | return 0; | |
1122 | ||
b72c1f65 | 1123 | pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1124 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
1125 | return -EINVAL; | |
db1266c8 | 1126 | |
184cd4a3 BH |
1127 | return 0; |
1128 | } | |
1129 | ||
1130 | static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, | |
1131 | u32 devfn) | |
1132 | { | |
1133 | return phb->ioda.pe_rmap[(bus->number << 8) | devfn]; | |
1134 | } | |
1135 | ||
73ed148a BH |
1136 | static void pnv_pci_ioda_shutdown(struct pnv_phb *phb) |
1137 | { | |
1138 | opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET, | |
1139 | OPAL_ASSERT_RESET); | |
1140 | } | |
1141 | ||
e9cc17d4 GS |
1142 | void __init pnv_pci_init_ioda_phb(struct device_node *np, |
1143 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
1144 | { |
1145 | struct pci_controller *hose; | |
184cd4a3 | 1146 | struct pnv_phb *phb; |
8184616f | 1147 | unsigned long size, m32map_off, pemap_off, iomap_off = 0; |
c681b93c | 1148 | const __be64 *prop64; |
3a1a4661 | 1149 | const __be32 *prop32; |
f1b7cc3e | 1150 | int len; |
184cd4a3 BH |
1151 | u64 phb_id; |
1152 | void *aux; | |
1153 | long rc; | |
1154 | ||
58d714ec | 1155 | pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); |
184cd4a3 BH |
1156 | |
1157 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
1158 | if (!prop64) { | |
1159 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
1160 | return; | |
1161 | } | |
1162 | phb_id = be64_to_cpup(prop64); | |
1163 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
1164 | ||
1165 | phb = alloc_bootmem(sizeof(struct pnv_phb)); | |
58d714ec GS |
1166 | if (!phb) { |
1167 | pr_err(" Out of memory !\n"); | |
1168 | return; | |
184cd4a3 | 1169 | } |
58d714ec GS |
1170 | |
1171 | /* Allocate PCI controller */ | |
1172 | memset(phb, 0, sizeof(struct pnv_phb)); | |
1173 | phb->hose = hose = pcibios_alloc_controller(np); | |
1174 | if (!phb->hose) { | |
1175 | pr_err(" Can't allocate PCI controller for %s\n", | |
184cd4a3 | 1176 | np->full_name); |
58d714ec | 1177 | free_bootmem((unsigned long)phb, sizeof(struct pnv_phb)); |
184cd4a3 BH |
1178 | return; |
1179 | } | |
1180 | ||
1181 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
1182 | prop32 = of_get_property(np, "bus-range", &len); |
1183 | if (prop32 && len == 8) { | |
3a1a4661 BH |
1184 | hose->first_busno = be32_to_cpu(prop32[0]); |
1185 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e GS |
1186 | } else { |
1187 | pr_warn(" Broken <bus-range> on %s\n", np->full_name); | |
1188 | hose->first_busno = 0; | |
1189 | hose->last_busno = 0xff; | |
1190 | } | |
184cd4a3 | 1191 | hose->private_data = phb; |
e9cc17d4 | 1192 | phb->hub_id = hub_id; |
184cd4a3 | 1193 | phb->opal_id = phb_id; |
aa0c033f | 1194 | phb->type = ioda_type; |
184cd4a3 | 1195 | |
cee72d5b BH |
1196 | /* Detect specific models for error handling */ |
1197 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
1198 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 1199 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 1200 | phb->model = PNV_PHB_MODEL_PHB3; |
cee72d5b BH |
1201 | else |
1202 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
1203 | ||
aa0c033f | 1204 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 1205 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 1206 | |
aa0c033f | 1207 | /* Get registers */ |
184cd4a3 BH |
1208 | phb->regs = of_iomap(np, 0); |
1209 | if (phb->regs == NULL) | |
1210 | pr_err(" Failed to map registers !\n"); | |
1211 | ||
184cd4a3 | 1212 | /* Initialize more IODA stuff */ |
36954dc7 | 1213 | phb->ioda.total_pe = 1; |
aa0c033f | 1214 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 1215 | if (prop32) |
3a1a4661 | 1216 | phb->ioda.total_pe = be32_to_cpup(prop32); |
36954dc7 GS |
1217 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
1218 | if (prop32) | |
1219 | phb->ioda.reserved_pe = be32_to_cpup(prop32); | |
184cd4a3 | 1220 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 1221 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
1222 | phb->ioda.m32_size += 0x10000; |
1223 | ||
1224 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe; | |
3fd47f06 | 1225 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 BH |
1226 | phb->ioda.io_size = hose->pci_io_size; |
1227 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe; | |
1228 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ | |
1229 | ||
c35d2a8c | 1230 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
184cd4a3 BH |
1231 | size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long)); |
1232 | m32map_off = size; | |
e47747f4 | 1233 | size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
1234 | if (phb->type == PNV_PHB_IODA1) { |
1235 | iomap_off = size; | |
1236 | size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]); | |
1237 | } | |
184cd4a3 BH |
1238 | pemap_off = size; |
1239 | size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe); | |
1240 | aux = alloc_bootmem(size); | |
1241 | memset(aux, 0, size); | |
1242 | phb->ioda.pe_alloc = aux; | |
1243 | phb->ioda.m32_segmap = aux + m32map_off; | |
c35d2a8c GS |
1244 | if (phb->type == PNV_PHB_IODA1) |
1245 | phb->ioda.io_segmap = aux + iomap_off; | |
184cd4a3 | 1246 | phb->ioda.pe_array = aux + pemap_off; |
36954dc7 | 1247 | set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc); |
184cd4a3 | 1248 | |
7ebdf956 | 1249 | INIT_LIST_HEAD(&phb->ioda.pe_dma_list); |
184cd4a3 BH |
1250 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
1251 | ||
1252 | /* Calculate how many 32-bit TCE segments we have */ | |
1253 | phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; | |
1254 | ||
1255 | /* Clear unusable m64 */ | |
1256 | hose->mem_resources[1].flags = 0; | |
1257 | hose->mem_resources[1].start = 0; | |
1258 | hose->mem_resources[1].end = 0; | |
1259 | hose->mem_resources[2].flags = 0; | |
1260 | hose->mem_resources[2].start = 0; | |
1261 | hose->mem_resources[2].end = 0; | |
1262 | ||
aa0c033f | 1263 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
1264 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
1265 | window_type, | |
1266 | window_num, | |
1267 | starting_real_address, | |
1268 | starting_pci_address, | |
1269 | segment_size); | |
1270 | #endif | |
1271 | ||
36954dc7 GS |
1272 | pr_info(" %d (%d) PE's M32: 0x%x [segment=0x%x]" |
1273 | " IO: 0x%x [segment=0x%x]\n", | |
184cd4a3 | 1274 | phb->ioda.total_pe, |
36954dc7 | 1275 | phb->ioda.reserved_pe, |
184cd4a3 BH |
1276 | phb->ioda.m32_size, phb->ioda.m32_segsize, |
1277 | phb->ioda.io_size, phb->ioda.io_segsize); | |
1278 | ||
184cd4a3 | 1279 | phb->hose->ops = &pnv_pci_ops; |
e9cc17d4 GS |
1280 | #ifdef CONFIG_EEH |
1281 | phb->eeh_ops = &ioda_eeh_ops; | |
1282 | #endif | |
184cd4a3 BH |
1283 | |
1284 | /* Setup RID -> PE mapping function */ | |
1285 | phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; | |
1286 | ||
1287 | /* Setup TCEs */ | |
1288 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
1289 | ||
73ed148a BH |
1290 | /* Setup shutdown function for kexec */ |
1291 | phb->shutdown = pnv_pci_ioda_shutdown; | |
1292 | ||
184cd4a3 BH |
1293 | /* Setup MSI support */ |
1294 | pnv_pci_init_ioda_msis(phb); | |
1295 | ||
c40a4210 GS |
1296 | /* |
1297 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
1298 | * to let the PCI core do resource assignment. It's supposed | |
1299 | * that the PCI core will do correct I/O and MMIO alignment | |
1300 | * for the P2P bridge bars so that each PCI bus (excluding | |
1301 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 1302 | */ |
fb446ad0 | 1303 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
184cd4a3 | 1304 | ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; |
271fd03a | 1305 | ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; |
c40a4210 | 1306 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
1307 | |
1308 | /* Reset IODA tables to a clean state */ | |
f11fe552 | 1309 | rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET); |
184cd4a3 | 1310 | if (rc) |
f11fe552 | 1311 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
aa0c033f GS |
1312 | } |
1313 | ||
67975005 | 1314 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 1315 | { |
e9cc17d4 | 1316 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
1317 | } |
1318 | ||
1319 | void __init pnv_pci_init_ioda_hub(struct device_node *np) | |
1320 | { | |
1321 | struct device_node *phbn; | |
c681b93c | 1322 | const __be64 *prop64; |
184cd4a3 BH |
1323 | u64 hub_id; |
1324 | ||
1325 | pr_info("Probing IODA IO-Hub %s\n", np->full_name); | |
1326 | ||
1327 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
1328 | if (!prop64) { | |
1329 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
1330 | return; | |
1331 | } | |
1332 | hub_id = be64_to_cpup(prop64); | |
1333 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
1334 | ||
1335 | /* Count child PHBs */ | |
1336 | for_each_child_of_node(np, phbn) { | |
1337 | /* Look for IODA1 PHBs */ | |
1338 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 1339 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
1340 | } |
1341 | } |