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[mirror_ubuntu-focal-kernel.git] / arch / powerpc / platforms / powernv / pci-ioda.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
184cd4a3
BH		 2/*
3 * Support PCI/PCIe on PowerNV platforms
4 *
5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
184cd4a3
BH		 6 */
7
cee72d5b 8#undef DEBUG
184cd4a3
BH		 9
10#include <linux/kernel.h>
11#include <linux/pci.h>
361f2a2a 12#include <linux/crash_dump.h>
184cd4a3
BH		 13#include <linux/delay.h>
14#include <linux/string.h>
15#include <linux/init.h>
57c8a661 16#include <linux/memblock.h>
184cd4a3
BH		 17#include <linux/irq.h>
18#include <linux/io.h>
19#include <linux/msi.h>
ac9a5889 20#include <linux/iommu.h>
e57080f1 21#include <linux/rculist.h>
4793d65d 22#include <linux/sizes.h>
184cd4a3
BH		 23
24#include <asm/sections.h>
25#include <asm/io.h>
26#include <asm/prom.h>
27#include <asm/pci-bridge.h>
28#include <asm/machdep.h>
fb1b55d6 29#include <asm/msi_bitmap.h>
184cd4a3
BH		 30#include <asm/ppc-pci.h>
31#include <asm/opal.h>
32#include <asm/iommu.h>
33#include <asm/tce.h>
137436c9 34#include <asm/xics.h>
7644d581 35#include <asm/debugfs.h>
262af557 36#include <asm/firmware.h>
80c49c7e 37#include <asm/pnv-pci.h>
aca6913f 38#include <asm/mmzone.h>
80c49c7e 39
ec249dd8 40#include <misc/cxl-base.h>
184cd4a3
BH		 41
42#include "powernv.h"
43#include "pci.h"
44bda4b7 44#include "../../../../drivers/pci/pci.h"
184cd4a3 45
99451551
GS		 46#define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
47#define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
acce971c 48#define PNV_IODA1_DMA32_SEGSIZE 0x10000000
781a868f 49
7f2c39e9
FB		 50static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
51 "NPU_OCAPI" };
aca6913f 52
c498a4f9
CH		 53static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
54
7d623e42 55void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
6d31c2fa
JP		 56 const char *fmt, ...)
57{
58 struct va_format vaf;
59 va_list args;
60 char pfix[32];
61
62 va_start(args, fmt);
63
64 vaf.fmt = fmt;
65 vaf.va = &args;
66
781a868f 67 if (pe->flags & PNV_IODA_PE_DEV)
6d31c2fa 68 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
781a868f 69 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
6d31c2fa
JP		 70 sprintf(pfix, "%04x:%02x ",
71 pci_domain_nr(pe->pbus), pe->pbus->number);
781a868f
WY		 72#ifdef CONFIG_PCI_IOV
73 else if (pe->flags & PNV_IODA_PE_VF)
74 sprintf(pfix, "%04x:%02x:%2x.%d",
75 pci_domain_nr(pe->parent_dev->bus),
76 (pe->rid & 0xff00) >> 8,
77 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
78#endif /* CONFIG_PCI_IOV*/
6d31c2fa 79
1f52f176 80 printk("%spci %s: [PE# %.2x] %pV",
6d31c2fa
JP		 81 level, pfix, pe->pe_number, &vaf);
82
83 va_end(args);
84}
184cd4a3 85
4e287840 86static bool pnv_iommu_bypass_disabled __read_mostly;
45baee14 87static bool pci_reset_phbs __read_mostly;
4e287840
TLSC		 88
89static int __init iommu_setup(char *str)
90{
91 if (!str)
92 return -EINVAL;
93
94 while (*str) {
95 if (!strncmp(str, "nobypass", 8)) {
96 pnv_iommu_bypass_disabled = true;
97 pr_info("PowerNV: IOMMU bypass window disabled.\n");
98 break;
99 }
100 str += strcspn(str, ",");
101 if (*str == ',')
102 str++;
103 }
104
105 return 0;
106}
107early_param("iommu", iommu_setup);
108
45baee14
GP		 109static int __init pci_reset_phbs_setup(char *str)
110{
111 pci_reset_phbs = true;
112 return 0;
113}
114
115early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
116
5958d19a 117static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
262af557 118{
5958d19a
BH		 119 /*
120 * WARNING: We cannot rely on the resource flags. The Linux PCI
121 * allocation code sometimes decides to put a 64-bit prefetchable
122 * BAR in the 32-bit window, so we have to compare the addresses.
123 *
124 * For simplicity we only test resource start.
125 */
126 return (r->start >= phb->ioda.m64_base &&
127 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
262af557
GC		 128}
129
b79331a5
RC		 130static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
131{
132 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
133
134 return (resource_flags & flags) == flags;
135}
136
1e916772
GS		 137static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
138{
313483dd
GS		 139 s64 rc;
140
1e916772
GS		 141 phb->ioda.pe_array[pe_no].phb = phb;
142 phb->ioda.pe_array[pe_no].pe_number = pe_no;
143
313483dd
GS		 144 /*
145 * Clear the PE frozen state as it might be put into frozen state
146 * in the last PCI remove path. It's not harmful to do so when the
147 * PE is already in unfrozen state.
148 */
149 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
150 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
d4791db5 151 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
1f52f176 152 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
313483dd
GS		 153 __func__, rc, phb->hose->global_number, pe_no);
154
1e916772
GS		 155 return &phb->ioda.pe_array[pe_no];
156}
157
4b82ab18
GS		 158static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
159{
92b8f137 160 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
1f52f176 161 pr_warn("%s: Invalid PE %x on PHB#%x\n",
4b82ab18
GS		 162 __func__, pe_no, phb->hose->global_number);
163 return;
164 }
165
e9dc4d7f 166 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
1f52f176 167 pr_debug("%s: PE %x was reserved on PHB#%x\n",
e9dc4d7f 168 __func__, pe_no, phb->hose->global_number);
4b82ab18 169
1e916772 170 pnv_ioda_init_pe(phb, pe_no);
4b82ab18
GS		 171}
172
1e916772 173static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
184cd4a3 174{
60964816 175 long pe;
184cd4a3 176
9fcd6f4a
GS		 177 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
178 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
179 return pnv_ioda_init_pe(phb, pe);
180 }
184cd4a3 181
9fcd6f4a 182 return NULL;
184cd4a3
BH		 183}
184
1e916772 185static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
184cd4a3 186{
1e916772 187 struct pnv_phb *phb = pe->phb;
caa58f80 188 unsigned int pe_num = pe->pe_number;
1e916772
GS		 189
190 WARN_ON(pe->pdev);
25066f5e 191 WARN_ON(pe->npucomp); /* NPUs for nvlink are not supposed to be freed */
0bd97167 192 kfree(pe->npucomp);
1e916772 193 memset(pe, 0, sizeof(struct pnv_ioda_pe));
caa58f80 194 clear_bit(pe_num, phb->ioda.pe_alloc);
184cd4a3
BH		 195}
196
262af557
GC		 197/* The default M64 BAR is shared by all PEs */
198static int pnv_ioda2_init_m64(struct pnv_phb *phb)
199{
200 const char *desc;
201 struct resource *r;
202 s64 rc;
203
204 /* Configure the default M64 BAR */
205 rc = opal_pci_set_phb_mem_window(phb->opal_id,
206 OPAL_M64_WINDOW_TYPE,
207 phb->ioda.m64_bar_idx,
208 phb->ioda.m64_base,
209 0, /* unused */
210 phb->ioda.m64_size);
211 if (rc != OPAL_SUCCESS) {
212 desc = "configuring";
213 goto fail;
214 }
215
216 /* Enable the default M64 BAR */
217 rc = opal_pci_phb_mmio_enable(phb->opal_id,
218 OPAL_M64_WINDOW_TYPE,
219 phb->ioda.m64_bar_idx,
220 OPAL_ENABLE_M64_SPLIT);
221 if (rc != OPAL_SUCCESS) {
222 desc = "enabling";
223 goto fail;
224 }
225
262af557 226 /*
63803c39
GS		 227 * Exclude the segments for reserved and root bus PE, which
228 * are first or last two PEs.
262af557
GC		 229 */
230 r = &phb->hose->mem_resources[1];
92b8f137 231 if (phb->ioda.reserved_pe_idx == 0)
63803c39 232 r->start += (2 * phb->ioda.m64_segsize);
92b8f137 233 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
63803c39 234 r->end -= (2 * phb->ioda.m64_segsize);
262af557 235 else
1f52f176 236 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
92b8f137 237 phb->ioda.reserved_pe_idx);
262af557
GC		 238
239 return 0;
240
241fail:
242 pr_warn(" Failure %lld %s M64 BAR#%d\n",
243 rc, desc, phb->ioda.m64_bar_idx);
244 opal_pci_phb_mmio_enable(phb->opal_id,
245 OPAL_M64_WINDOW_TYPE,
246 phb->ioda.m64_bar_idx,
247 OPAL_DISABLE_M64);
248 return -EIO;
249}
250
c430670a 251static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
96a2f92b 252 unsigned long *pe_bitmap)
262af557 253{
96a2f92b
GS		 254 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
255 struct pnv_phb *phb = hose->private_data;
262af557 256 struct resource *r;
96a2f92b
GS		 257 resource_size_t base, sgsz, start, end;
258 int segno, i;
259
260 base = phb->ioda.m64_base;
261 sgsz = phb->ioda.m64_segsize;
262 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
263 r = &pdev->resource[i];
5958d19a 264 if (!r->parent || !pnv_pci_is_m64(phb, r))
96a2f92b 265 continue;
262af557 266
96a2f92b
GS		 267 start = _ALIGN_DOWN(r->start - base, sgsz);
268 end = _ALIGN_UP(r->end - base, sgsz);
269 for (segno = start / sgsz; segno < end / sgsz; segno++) {
270 if (pe_bitmap)
271 set_bit(segno, pe_bitmap);
272 else
273 pnv_ioda_reserve_pe(phb, segno);
262af557
GC		 274 }
275 }
276}
277
99451551
GS		 278static int pnv_ioda1_init_m64(struct pnv_phb *phb)
279{
280 struct resource *r;
281 int index;
282
283 /*
284 * There are 16 M64 BARs, each of which has 8 segments. So
285 * there are as many M64 segments as the maximum number of
286 * PEs, which is 128.
287 */
288 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
289 unsigned long base, segsz = phb->ioda.m64_segsize;
290 int64_t rc;
291
292 base = phb->ioda.m64_base +
293 index * PNV_IODA1_M64_SEGS * segsz;
294 rc = opal_pci_set_phb_mem_window(phb->opal_id,
295 OPAL_M64_WINDOW_TYPE, index, base, 0,
296 PNV_IODA1_M64_SEGS * segsz);
297 if (rc != OPAL_SUCCESS) {
1f52f176 298 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
99451551
GS		 299 rc, phb->hose->global_number, index);
300 goto fail;
301 }
302
303 rc = opal_pci_phb_mmio_enable(phb->opal_id,
304 OPAL_M64_WINDOW_TYPE, index,
305 OPAL_ENABLE_M64_SPLIT);
306 if (rc != OPAL_SUCCESS) {
1f52f176 307 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
99451551
GS		 308 rc, phb->hose->global_number, index);
309 goto fail;
310 }
311 }
312
313 /*
63803c39
GS		 314 * Exclude the segments for reserved and root bus PE, which
315 * are first or last two PEs.
99451551
GS		 316 */
317 r = &phb->hose->mem_resources[1];
318 if (phb->ioda.reserved_pe_idx == 0)
63803c39 319 r->start += (2 * phb->ioda.m64_segsize);
99451551 320 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
63803c39 321 r->end -= (2 * phb->ioda.m64_segsize);
99451551 322 else
1f52f176 323 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
99451551
GS		 324 phb->ioda.reserved_pe_idx, phb->hose->global_number);
325
326 return 0;
327
328fail:
329 for ( ; index >= 0; index--)
330 opal_pci_phb_mmio_enable(phb->opal_id,
331 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
332
333 return -EIO;
334}
335
c430670a
GS		 336static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
337 unsigned long *pe_bitmap,
338 bool all)
262af557 339{
262af557 340 struct pci_dev *pdev;
96a2f92b
GS		 341
342 list_for_each_entry(pdev, &bus->devices, bus_list) {
c430670a 343 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
96a2f92b
GS		 344
345 if (all && pdev->subordinate)
c430670a
GS		 346 pnv_ioda_reserve_m64_pe(pdev->subordinate,
347 pe_bitmap, all);
96a2f92b
GS		 348 }
349}
350
1e916772 351static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
262af557 352{
26ba248d
GS		 353 struct pci_controller *hose = pci_bus_to_host(bus);
354 struct pnv_phb *phb = hose->private_data;
262af557
GC		 355 struct pnv_ioda_pe *master_pe, *pe;
356 unsigned long size, *pe_alloc;
26ba248d 357 int i;
262af557
GC		 358
359 /* Root bus shouldn't use M64 */
360 if (pci_is_root_bus(bus))
1e916772 361 return NULL;
262af557 362
262af557 363 /* Allocate bitmap */
92b8f137 364 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
262af557
GC		 365 pe_alloc = kzalloc(size, GFP_KERNEL);
366 if (!pe_alloc) {
367 pr_warn("%s: Out of memory !\n",
368 __func__);
1e916772 369 return NULL;
262af557
GC		 370 }
371
26ba248d 372 /* Figure out reserved PE numbers by the PE */
c430670a 373 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
262af557
GC		 374
375 /*
376 * the current bus might not own M64 window and that's all
377 * contributed by its child buses. For the case, we needn't
378 * pick M64 dependent PE#.
379 */
92b8f137 380 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
262af557 381 kfree(pe_alloc);
1e916772 382 return NULL;
262af557
GC		 383 }
384
385 /*
386 * Figure out the master PE and put all slave PEs to master
387 * PE's list to form compound PE.
388 */
262af557
GC		 389 master_pe = NULL;
390 i = -1;
92b8f137
GS		 391 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
392 phb->ioda.total_pe_num) {
262af557 393 pe = &phb->ioda.pe_array[i];
262af557 394
93289d8c 395 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
262af557
GC		 396 if (!master_pe) {
397 pe->flags |= PNV_IODA_PE_MASTER;
398 INIT_LIST_HEAD(&pe->slaves);
399 master_pe = pe;
400 } else {
401 pe->flags |= PNV_IODA_PE_SLAVE;
402 pe->master = master_pe;
403 list_add_tail(&pe->list, &master_pe->slaves);
404 }
99451551
GS		 405
406 /*
407 * P7IOC supports M64DT, which helps mapping M64 segment
408 * to one particular PE#. However, PHB3 has fixed mapping
409 * between M64 segment and PE#. In order to have same logic
410 * for P7IOC and PHB3, we enforce fixed mapping between M64
411 * segment and PE# on P7IOC.
412 */
413 if (phb->type == PNV_PHB_IODA1) {
414 int64_t rc;
415
416 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
417 pe->pe_number, OPAL_M64_WINDOW_TYPE,
418 pe->pe_number / PNV_IODA1_M64_SEGS,
419 pe->pe_number % PNV_IODA1_M64_SEGS);
420 if (rc != OPAL_SUCCESS)
1f52f176 421 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
99451551
GS		 422 __func__, rc, phb->hose->global_number,
423 pe->pe_number);
424 }
262af557
GC		 425 }
426
427 kfree(pe_alloc);
1e916772 428 return master_pe;
262af557
GC		 429}
430
431static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
432{
433 struct pci_controller *hose = phb->hose;
434 struct device_node *dn = hose->dn;
435 struct resource *res;
a1339faf 436 u32 m64_range[2], i;
0e7736c6 437 const __be32 *r;
262af557
GC		 438 u64 pci_addr;
439
99451551 440 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
1665c4a8
GS		 441 pr_info(" Not support M64 window\n");
442 return;
443 }
444
e4d54f71 445 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
262af557
GC		 446 pr_info(" Firmware too old to support M64 window\n");
447 return;
448 }
449
450 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
451 if (!r) {
b7c670d6
RH		 452 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
453 dn);
262af557
GC		 454 return;
455 }
456
a1339faf
BH		 457 /*
458 * Find the available M64 BAR range and pickup the last one for
459 * covering the whole 64-bits space. We support only one range.
460 */
461 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
462 m64_range, 2)) {
463 /* In absence of the property, assume 0..15 */
464 m64_range[0] = 0;
465 m64_range[1] = 16;
466 }
467 /* We only support 64 bits in our allocator */
468 if (m64_range[1] > 63) {
469 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
470 __func__, m64_range[1], phb->hose->global_number);
471 m64_range[1] = 63;
472 }
473 /* Empty range, no m64 */
474 if (m64_range[1] <= m64_range[0]) {
475 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
476 __func__, phb->hose->global_number);
477 return;
478 }
479
480 /* Configure M64 informations */
262af557 481 res = &hose->mem_resources[1];
e80c4e7c 482 res->name = dn->full_name;
262af557
GC		 483 res->start = of_translate_address(dn, r + 2);
484 res->end = res->start + of_read_number(r + 4, 2) - 1;
485 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
486 pci_addr = of_read_number(r, 2);
487 hose->mem_offset[1] = res->start - pci_addr;
488
489 phb->ioda.m64_size = resource_size(res);
92b8f137 490 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
262af557
GC		 491 phb->ioda.m64_base = pci_addr;
492
a1339faf
BH		 493 /* This lines up nicely with the display from processing OF ranges */
494 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
495 res->start, res->end, pci_addr, m64_range[0],
496 m64_range[0] + m64_range[1] - 1);
497
498 /* Mark all M64 used up by default */
499 phb->ioda.m64_bar_alloc = (unsigned long)-1;
e9863e68 500
262af557 501 /* Use last M64 BAR to cover M64 window */
a1339faf
BH		 502 m64_range[1]--;
503 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
504
505 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
506
507 /* Mark remaining ones free */
508 for (i = m64_range[0]; i < m64_range[1]; i++)
509 clear_bit(i, &phb->ioda.m64_bar_alloc);
510
511 /*
512 * Setup init functions for M64 based on IODA version, IODA3 uses
513 * the IODA2 code.
514 */
99451551
GS		 515 if (phb->type == PNV_PHB_IODA1)
516 phb->init_m64 = pnv_ioda1_init_m64;
517 else
518 phb->init_m64 = pnv_ioda2_init_m64;
262af557
GC		 519}
520
49dec922
GS		 521static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
522{
523 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
524 struct pnv_ioda_pe *slave;
525 s64 rc;
526
527 /* Fetch master PE */
528 if (pe->flags & PNV_IODA_PE_SLAVE) {
529 pe = pe->master;
ec8e4e9d
GS		 530 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
531 return;
532
49dec922
GS		 533 pe_no = pe->pe_number;
534 }
535
536 /* Freeze master PE */
537 rc = opal_pci_eeh_freeze_set(phb->opal_id,
538 pe_no,
539 OPAL_EEH_ACTION_SET_FREEZE_ALL);
540 if (rc != OPAL_SUCCESS) {
541 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
542 __func__, rc, phb->hose->global_number, pe_no);
543 return;
544 }
545
546 /* Freeze slave PEs */
547 if (!(pe->flags & PNV_IODA_PE_MASTER))
548 return;
549
550 list_for_each_entry(slave, &pe->slaves, list) {
551 rc = opal_pci_eeh_freeze_set(phb->opal_id,
552 slave->pe_number,
553 OPAL_EEH_ACTION_SET_FREEZE_ALL);
554 if (rc != OPAL_SUCCESS)
555 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
556 __func__, rc, phb->hose->global_number,
557 slave->pe_number);
558 }
559}
560
e51df2c1 561static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
49dec922
GS		 562{
563 struct pnv_ioda_pe *pe, *slave;
564 s64 rc;
565
566 /* Find master PE */
567 pe = &phb->ioda.pe_array[pe_no];
568 if (pe->flags & PNV_IODA_PE_SLAVE) {
569 pe = pe->master;
570 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
571 pe_no = pe->pe_number;
572 }
573
574 /* Clear frozen state for master PE */
575 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
576 if (rc != OPAL_SUCCESS) {
577 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
578 __func__, rc, opt, phb->hose->global_number, pe_no);
579 return -EIO;
580 }
581
582 if (!(pe->flags & PNV_IODA_PE_MASTER))
583 return 0;
584
585 /* Clear frozen state for slave PEs */
586 list_for_each_entry(slave, &pe->slaves, list) {
587 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
588 slave->pe_number,
589 opt);
590 if (rc != OPAL_SUCCESS) {
591 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
592 __func__, rc, opt, phb->hose->global_number,
593 slave->pe_number);
594 return -EIO;
595 }
596 }
597
598 return 0;
599}
600
601static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
602{
603 struct pnv_ioda_pe *slave, *pe;
c2057701
AK		 604 u8 fstate = 0, state;
605 __be16 pcierr = 0;
49dec922
GS		 606 s64 rc;
607
608 /* Sanity check on PE number */
92b8f137 609 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
49dec922
GS		 610 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
611
612 /*
613 * Fetch the master PE and the PE instance might be
614 * not initialized yet.
615 */
616 pe = &phb->ioda.pe_array[pe_no];
617 if (pe->flags & PNV_IODA_PE_SLAVE) {
618 pe = pe->master;
619 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
620 pe_no = pe->pe_number;
621 }
622
623 /* Check the master PE */
624 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
625 &state, &pcierr, NULL);
626 if (rc != OPAL_SUCCESS) {
627 pr_warn("%s: Failure %lld getting "
628 "PHB#%x-PE#%x state\n",
629 __func__, rc,
630 phb->hose->global_number, pe_no);
631 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
632 }
633
634 /* Check the slave PE */
635 if (!(pe->flags & PNV_IODA_PE_MASTER))
636 return state;
637
638 list_for_each_entry(slave, &pe->slaves, list) {
639 rc = opal_pci_eeh_freeze_status(phb->opal_id,
640 slave->pe_number,
641 &fstate,
642 &pcierr,
643 NULL);
644 if (rc != OPAL_SUCCESS) {
645 pr_warn("%s: Failure %lld getting "
646 "PHB#%x-PE#%x state\n",
647 __func__, rc,
648 phb->hose->global_number, slave->pe_number);
649 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
650 }
651
652 /*
653 * Override the result based on the ascending
654 * priority.
655 */
656 if (fstate > state)
657 state = fstate;
658 }
659
660 return state;
661}
662
f456834a 663struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
184cd4a3
BH		 664{
665 struct pci_controller *hose = pci_bus_to_host(dev->bus);
666 struct pnv_phb *phb = hose->private_data;
b72c1f65 667 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 668
669 if (!pdn)
670 return NULL;
671 if (pdn->pe_number == IODA_INVALID_PE)
672 return NULL;
673 return &phb->ioda.pe_array[pdn->pe_number];
674}
184cd4a3 675
b131a842
GS		 676static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
677 struct pnv_ioda_pe *parent,
678 struct pnv_ioda_pe *child,
679 bool is_add)
680{
681 const char *desc = is_add ? "adding" : "removing";
682 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
683 OPAL_REMOVE_PE_FROM_DOMAIN;
684 struct pnv_ioda_pe *slave;
685 long rc;
686
687 /* Parent PE affects child PE */
688 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
689 child->pe_number, op);
690 if (rc != OPAL_SUCCESS) {
691 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
692 rc, desc);
693 return -ENXIO;
694 }
695
696 if (!(child->flags & PNV_IODA_PE_MASTER))
697 return 0;
698
699 /* Compound case: parent PE affects slave PEs */
700 list_for_each_entry(slave, &child->slaves, list) {
701 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
702 slave->pe_number, op);
703 if (rc != OPAL_SUCCESS) {
704 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
705 rc, desc);
706 return -ENXIO;
707 }
708 }
709
710 return 0;
711}
712
713static int pnv_ioda_set_peltv(struct pnv_phb *phb,
714 struct pnv_ioda_pe *pe,
715 bool is_add)
716{
717 struct pnv_ioda_pe *slave;
781a868f 718 struct pci_dev *pdev = NULL;
b131a842
GS		 719 int ret;
720
721 /*
722 * Clear PE frozen state. If it's master PE, we need
723 * clear slave PE frozen state as well.
724 */
725 if (is_add) {
726 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
727 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
728 if (pe->flags & PNV_IODA_PE_MASTER) {
729 list_for_each_entry(slave, &pe->slaves, list)
730 opal_pci_eeh_freeze_clear(phb->opal_id,
731 slave->pe_number,
732 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
733 }
734 }
735
736 /*
737 * Associate PE in PELT. We need add the PE into the
738 * corresponding PELT-V as well. Otherwise, the error
739 * originated from the PE might contribute to other
740 * PEs.
741 */
742 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
743 if (ret)
744 return ret;
745
746 /* For compound PEs, any one affects all of them */
747 if (pe->flags & PNV_IODA_PE_MASTER) {
748 list_for_each_entry(slave, &pe->slaves, list) {
749 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
750 if (ret)
751 return ret;
752 }
753 }
754
755 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
756 pdev = pe->pbus->self;
781a868f 757 else if (pe->flags & PNV_IODA_PE_DEV)
b131a842 758 pdev = pe->pdev->bus->self;
781a868f
WY		 759#ifdef CONFIG_PCI_IOV
760 else if (pe->flags & PNV_IODA_PE_VF)
283e2d8a 761 pdev = pe->parent_dev;
781a868f 762#endif /* CONFIG_PCI_IOV */
b131a842
GS		 763 while (pdev) {
764 struct pci_dn *pdn = pci_get_pdn(pdev);
765 struct pnv_ioda_pe *parent;
766
767 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
768 parent = &phb->ioda.pe_array[pdn->pe_number];
769 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
770 if (ret)
771 return ret;
772 }
773
774 pdev = pdev->bus->self;
775 }
776
777 return 0;
778}
779
25066f5e
FB		 780static void pnv_ioda_unset_peltv(struct pnv_phb *phb,
781 struct pnv_ioda_pe *pe,
782 struct pci_dev *parent)
783{
784 int64_t rc;
785
786 while (parent) {
787 struct pci_dn *pdn = pci_get_pdn(parent);
788
789 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
790 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
791 pe->pe_number,
792 OPAL_REMOVE_PE_FROM_DOMAIN);
793 /* XXX What to do in case of error ? */
794 }
795 parent = parent->bus->self;
796 }
797
798 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
799 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
800
801 /* Disassociate PE in PELT */
802 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
803 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
804 if (rc)
805 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
806}
807
781a868f
WY		 808static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
809{
810 struct pci_dev *parent;
811 uint8_t bcomp, dcomp, fcomp;
812 int64_t rc;
813 long rid_end, rid;
814
815 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
816 if (pe->pbus) {
817 int count;
818
819 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
820 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
821 parent = pe->pbus->self;
822 if (pe->flags & PNV_IODA_PE_BUS_ALL)
823 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
824 else
825 count = 1;
826
827 switch(count) {
828 case 1: bcomp = OpalPciBusAll; break;
829 case 2: bcomp = OpalPciBus7Bits; break;
830 case 4: bcomp = OpalPciBus6Bits; break;
831 case 8: bcomp = OpalPciBus5Bits; break;
832 case 16: bcomp = OpalPciBus4Bits; break;
833 case 32: bcomp = OpalPciBus3Bits; break;
834 default:
835 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
836 count);
837 /* Do an exact match only */
838 bcomp = OpalPciBusAll;
839 }
840 rid_end = pe->rid + (count << 8);
841 } else {
93e01a50 842#ifdef CONFIG_PCI_IOV
781a868f
WY		 843 if (pe->flags & PNV_IODA_PE_VF)
844 parent = pe->parent_dev;
845 else
93e01a50 846#endif
781a868f
WY		 847 parent = pe->pdev->bus->self;
848 bcomp = OpalPciBusAll;
849 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
850 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
851 rid_end = pe->rid + 1;
852 }
853
854 /* Clear the reverse map */
855 for (rid = pe->rid; rid < rid_end; rid++)
c127562a 856 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
781a868f 857
25066f5e
FB		 858 /*
859 * Release from all parents PELT-V. NPUs don't have a PELTV
860 * table
861 */
862 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
863 pnv_ioda_unset_peltv(phb, pe, parent);
781a868f 864
781a868f
WY		 865 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
866 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
867 if (rc)
1e496391 868 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
781a868f
WY		 869
870 pe->pbus = NULL;
871 pe->pdev = NULL;
93e01a50 872#ifdef CONFIG_PCI_IOV
781a868f 873 pe->parent_dev = NULL;
93e01a50 874#endif
781a868f
WY		 875
876 return 0;
877}
781a868f 878
cad5cef6 879static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
184cd4a3
BH		 880{
881 struct pci_dev *parent;
882 uint8_t bcomp, dcomp, fcomp;
883 long rc, rid_end, rid;
884
885 /* Bus validation ? */
886 if (pe->pbus) {
887 int count;
888
889 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
890 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
891 parent = pe->pbus->self;
fb446ad0
GS		 892 if (pe->flags & PNV_IODA_PE_BUS_ALL)
893 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
894 else
895 count = 1;
896
184cd4a3
BH		 897 switch(count) {
898 case 1: bcomp = OpalPciBusAll; break;
899 case 2: bcomp = OpalPciBus7Bits; break;
900 case 4: bcomp = OpalPciBus6Bits; break;
901 case 8: bcomp = OpalPciBus5Bits; break;
902 case 16: bcomp = OpalPciBus4Bits; break;
903 case 32: bcomp = OpalPciBus3Bits; break;
904 default:
781a868f
WY		 905 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
906 count);
184cd4a3
BH		 907 /* Do an exact match only */
908 bcomp = OpalPciBusAll;
909 }
910 rid_end = pe->rid + (count << 8);
911 } else {
781a868f
WY		 912#ifdef CONFIG_PCI_IOV
913 if (pe->flags & PNV_IODA_PE_VF)
914 parent = pe->parent_dev;
915 else
916#endif /* CONFIG_PCI_IOV */
917 parent = pe->pdev->bus->self;
184cd4a3
BH		 918 bcomp = OpalPciBusAll;
919 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
920 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
921 rid_end = pe->rid + 1;
922 }
923
631ad691
GS		 924 /*
925 * Associate PE in PELT. We need add the PE into the
926 * corresponding PELT-V as well. Otherwise, the error
927 * originated from the PE might contribute to other
928 * PEs.
929 */
184cd4a3
BH		 930 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
931 bcomp, dcomp, fcomp, OPAL_MAP_PE);
932 if (rc) {
933 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
934 return -ENXIO;
935 }
631ad691 936
5d2aa710
AP		 937 /*
938 * Configure PELTV. NPUs don't have a PELTV table so skip
939 * configuration on them.
940 */
7f2c39e9 941 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
5d2aa710 942 pnv_ioda_set_peltv(phb, pe, true);
184cd4a3 943
184cd4a3
BH		 944 /* Setup reverse map */
945 for (rid = pe->rid; rid < rid_end; rid++)
946 phb->ioda.pe_rmap[rid] = pe->pe_number;
947
948 /* Setup one MVTs on IODA1 */
4773f76b
GS		 949 if (phb->type != PNV_PHB_IODA1) {
950 pe->mve_number = 0;
951 goto out;
952 }
953
954 pe->mve_number = pe->pe_number;
955 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
956 if (rc != OPAL_SUCCESS) {
1f52f176 957 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
4773f76b
GS		 958 rc, pe->mve_number);
959 pe->mve_number = -1;
960 } else {
961 rc = opal_pci_set_mve_enable(phb->opal_id,
962 pe->mve_number, OPAL_ENABLE_MVE);
184cd4a3 963 if (rc) {
1f52f176 964 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
184cd4a3
BH		 965 rc, pe->mve_number);
966 pe->mve_number = -1;
184cd4a3 967 }
4773f76b 968 }
184cd4a3 969
4773f76b 970out:
184cd4a3
BH		 971 return 0;
972}
973
781a868f
WY		 974#ifdef CONFIG_PCI_IOV
975static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
976{
977 struct pci_dn *pdn = pci_get_pdn(dev);
978 int i;
979 struct resource *res, res2;
980 resource_size_t size;
981 u16 num_vfs;
982
983 if (!dev->is_physfn)
984 return -EINVAL;
985
986 /*
987 * "offset" is in VFs. The M64 windows are sized so that when they
988 * are segmented, each segment is the same size as the IOV BAR.
989 * Each segment is in a separate PE, and the high order bits of the
990 * address are the PE number. Therefore, each VF's BAR is in a
991 * separate PE, and changing the IOV BAR start address changes the
992 * range of PEs the VFs are in.
993 */
994 num_vfs = pdn->num_vfs;
995 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
996 res = &dev->resource[i + PCI_IOV_RESOURCES];
997 if (!res->flags || !res->parent)
998 continue;
999
781a868f
WY		 1000 /*
1001 * The actual IOV BAR range is determined by the start address
1002 * and the actual size for num_vfs VFs BAR. This check is to
1003 * make sure that after shifting, the range will not overlap
1004 * with another device.
1005 */
1006 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1007 res2.flags = res->flags;
1008 res2.start = res->start + (size * offset);
1009 res2.end = res2.start + (size * num_vfs) - 1;
1010
1011 if (res2.end > res->end) {
1012 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1013 i, &res2, res, num_vfs, offset);
1014 return -EBUSY;
1015 }
1016 }
1017
1018 /*
d6f934fd
AK		 1019 * Since M64 BAR shares segments among all possible 256 PEs,
1020 * we have to shift the beginning of PF IOV BAR to make it start from
1021 * the segment which belongs to the PE number assigned to the first VF.
1022 * This creates a "hole" in the /proc/iomem which could be used for
1023 * allocating other resources so we reserve this area below and
1024 * release when IOV is released.
781a868f
WY		 1025 */
1026 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1027 res = &dev->resource[i + PCI_IOV_RESOURCES];
1028 if (!res->flags || !res->parent)
1029 continue;
1030
781a868f
WY		 1031 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1032 res2 = *res;
1033 res->start += size * offset;
1034
74703cc4
WY		 1035 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1036 i, &res2, res, (offset > 0) ? "En" : "Dis",
1037 num_vfs, offset);
d6f934fd
AK		 1038
1039 if (offset < 0) {
1040 devm_release_resource(&dev->dev, &pdn->holes[i]);
1041 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1042 }
1043
781a868f 1044 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
d6f934fd
AK		 1045
1046 if (offset > 0) {
1047 pdn->holes[i].start = res2.start;
1048 pdn->holes[i].end = res2.start + size * offset - 1;
1049 pdn->holes[i].flags = IORESOURCE_BUS;
1050 pdn->holes[i].name = "pnv_iov_reserved";
1051 devm_request_resource(&dev->dev, res->parent,
1052 &pdn->holes[i]);
1053 }
781a868f
WY		 1054 }
1055 return 0;
1056}
1057#endif /* CONFIG_PCI_IOV */
1058
cad5cef6 1059static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
184cd4a3
BH		 1060{
1061 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1062 struct pnv_phb *phb = hose->private_data;
b72c1f65 1063 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3 1064 struct pnv_ioda_pe *pe;
184cd4a3
BH		 1065
1066 if (!pdn) {
1067 pr_err("%s: Device tree node not associated properly\n",
1068 pci_name(dev));
1069 return NULL;
1070 }
1071 if (pdn->pe_number != IODA_INVALID_PE)
1072 return NULL;
1073
1e916772
GS		 1074 pe = pnv_ioda_alloc_pe(phb);
1075 if (!pe) {
f2c2cbcc
JP		 1076 pr_warn("%s: Not enough PE# available, disabling device\n",
1077 pci_name(dev));
184cd4a3
BH		 1078 return NULL;
1079 }
1080
02b7225f
FB		 1081 /* NOTE: We don't get a reference for the pointer in the PE
1082 * data structure, both the device and PE structures should be
1083 * destroyed at the same time. However, removing nvlink
1084 * devices will need some work.
184cd4a3
BH		 1085 *
1086 * At some point we want to remove the PDN completely anyways
1087 */
1e916772 1088 pdn->pe_number = pe->pe_number;
5d2aa710 1089 pe->flags = PNV_IODA_PE_DEV;
184cd4a3
BH		 1090 pe->pdev = dev;
1091 pe->pbus = NULL;
184cd4a3
BH		 1092 pe->mve_number = -1;
1093 pe->rid = dev->bus->number << 8 | pdn->devfn;
25066f5e 1094 pe->device_count++;
184cd4a3
BH		 1095
1096 pe_info(pe, "Associated device to PE\n");
1097
1098 if (pnv_ioda_configure_pe(phb, pe)) {
1099 /* XXX What do we do here ? */
1e916772 1100 pnv_ioda_free_pe(pe);
184cd4a3
BH		 1101 pdn->pe_number = IODA_INVALID_PE;
1102 pe->pdev = NULL;
184cd4a3
BH		 1103 return NULL;
1104 }
1105
1d4e89cf 1106 /* Put PE to the list */
391677f6 1107 mutex_lock(&phb->ioda.pe_list_mutex);
1d4e89cf 1108 list_add_tail(&pe->list, &phb->ioda.pe_list);
391677f6 1109 mutex_unlock(&phb->ioda.pe_list_mutex);
184cd4a3
BH		 1110 return pe;
1111}
1112
1113static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1114{
1115 struct pci_dev *dev;
1116
1117 list_for_each_entry(dev, &bus->devices, bus_list) {
b72c1f65 1118 struct pci_dn *pdn = pci_get_pdn(dev);
184cd4a3
BH		 1119
1120 if (pdn == NULL) {
1121 pr_warn("%s: No device node associated with device !\n",
1122 pci_name(dev));
1123 continue;
1124 }
ccd1c191
GS		 1125
1126 /*
1127 * In partial hotplug case, the PCI device might be still
1128 * associated with the PE and needn't attach it to the PE
1129 * again.
1130 */
1131 if (pdn->pe_number != IODA_INVALID_PE)
1132 continue;
1133
c5f7700b 1134 pe->device_count++;
184cd4a3 1135 pdn->pe_number = pe->pe_number;
fb446ad0 1136 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
184cd4a3
BH		 1137 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1138 }
1139}
1140
fb446ad0
GS		 1141/*
1142 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1143 * single PCI bus. Another one that contains the primary PCI bus and its
1144 * subordinate PCI devices and buses. The second type of PE is normally
1145 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1146 */
1e916772 1147static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
184cd4a3 1148{
fb446ad0 1149 struct pci_controller *hose = pci_bus_to_host(bus);
184cd4a3 1150 struct pnv_phb *phb = hose->private_data;
1e916772 1151 struct pnv_ioda_pe *pe = NULL;
ccd1c191
GS		 1152 unsigned int pe_num;
1153
1154 /*
1155 * In partial hotplug case, the PE instance might be still alive.
1156 * We should reuse it instead of allocating a new one.
1157 */
1158 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1159 if (pe_num != IODA_INVALID_PE) {
1160 pe = &phb->ioda.pe_array[pe_num];
1161 pnv_ioda_setup_same_PE(bus, pe);
1162 return NULL;
1163 }
262af557 1164
63803c39
GS		 1165 /* PE number for root bus should have been reserved */
1166 if (pci_is_root_bus(bus) &&
1167 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1168 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1169
262af557 1170 /* Check if PE is determined by M64 */
a25de7af
AK		 1171 if (!pe)
1172 pe = pnv_ioda_pick_m64_pe(bus, all);
262af557
GC		 1173
1174 /* The PE number isn't pinned by M64 */
1e916772
GS		 1175 if (!pe)
1176 pe = pnv_ioda_alloc_pe(phb);
184cd4a3 1177
1e916772 1178 if (!pe) {
f2c2cbcc 1179 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
fb446ad0 1180 __func__, pci_domain_nr(bus), bus->number);
1e916772 1181 return NULL;
184cd4a3
BH		 1182 }
1183
262af557 1184 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
184cd4a3
BH		 1185 pe->pbus = bus;
1186 pe->pdev = NULL;
184cd4a3 1187 pe->mve_number = -1;
b918c62e 1188 pe->rid = bus->busn_res.start << 8;
184cd4a3 1189
fb446ad0 1190 if (all)
1e496391
JP		 1191 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1192 &bus->busn_res.start, &bus->busn_res.end,
1193 pe->pe_number);
fb446ad0 1194 else
1e496391
JP		 1195 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1196 &bus->busn_res.start, pe->pe_number);
184cd4a3
BH		 1197
1198 if (pnv_ioda_configure_pe(phb, pe)) {
1199 /* XXX What do we do here ? */
1e916772 1200 pnv_ioda_free_pe(pe);
184cd4a3 1201 pe->pbus = NULL;
1e916772 1202 return NULL;
184cd4a3
BH		 1203 }
1204
1205 /* Associate it with all child devices */
1206 pnv_ioda_setup_same_PE(bus, pe);
1207
7ebdf956
GS		 1208 /* Put PE to the list */
1209 list_add_tail(&pe->list, &phb->ioda.pe_list);
1e916772
GS		 1210
1211 return pe;
184cd4a3
BH		 1212}
1213
b521549a
AP		 1214static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1215{
1216 int pe_num, found_pe = false, rc;
1217 long rid;
1218 struct pnv_ioda_pe *pe;
1219 struct pci_dev *gpu_pdev;
1220 struct pci_dn *npu_pdn;
1221 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1222 struct pnv_phb *phb = hose->private_data;
1223
02b7225f
FB		 1224 /*
1225 * Intentionally leak a reference on the npu device (for
1226 * nvlink only; this is not an opencapi path) to make sure it
1227 * never goes away, as it's been the case all along and some
1228 * work is needed otherwise.
1229 */
1230 pci_dev_get(npu_pdev);
1231
b521549a
AP		 1232 /*
1233 * Due to a hardware errata PE#0 on the NPU is reserved for
1234 * error handling. This means we only have three PEs remaining
1235 * which need to be assigned to four links, implying some
1236 * links must share PEs.
1237 *
1238 * To achieve this we assign PEs such that NPUs linking the
1239 * same GPU get assigned the same PE.
1240 */
1241 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
92b8f137 1242 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
b521549a
AP		 1243 pe = &phb->ioda.pe_array[pe_num];
1244 if (!pe->pdev)
1245 continue;
1246
1247 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1248 /*
1249 * This device has the same peer GPU so should
1250 * be assigned the same PE as the existing
1251 * peer NPU.
1252 */
1253 dev_info(&npu_pdev->dev,
1f52f176 1254 "Associating to existing PE %x\n", pe_num);
b521549a
AP		 1255 npu_pdn = pci_get_pdn(npu_pdev);
1256 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
b521549a 1257 npu_pdn->pe_number = pe_num;
b521549a 1258 phb->ioda.pe_rmap[rid] = pe->pe_number;
25066f5e 1259 pe->device_count++;
b521549a
AP		 1260
1261 /* Map the PE to this link */
1262 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1263 OpalPciBusAll,
1264 OPAL_COMPARE_RID_DEVICE_NUMBER,
1265 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1266 OPAL_MAP_PE);
1267 WARN_ON(rc != OPAL_SUCCESS);
1268 found_pe = true;
1269 break;
1270 }
1271 }
1272
1273 if (!found_pe)
1274 /*
1275 * Could not find an existing PE so allocate a new
1276 * one.
1277 */
1278 return pnv_ioda_setup_dev_PE(npu_pdev);
1279 else
1280 return pe;
1281}
1282
1283static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
5d2aa710 1284{
5d2aa710
AP		 1285 struct pci_dev *pdev;
1286
1287 list_for_each_entry(pdev, &bus->devices, bus_list)
b521549a 1288 pnv_ioda_setup_npu_PE(pdev);
5d2aa710
AP		 1289}
1290
cad5cef6 1291static void pnv_pci_ioda_setup_PEs(void)
fb446ad0 1292{
0e759bd7 1293 struct pci_controller *hose;
262af557 1294 struct pnv_phb *phb;
0e759bd7 1295 struct pnv_ioda_pe *pe;
fb446ad0 1296
0e759bd7 1297 list_for_each_entry(hose, &hose_list, list_node) {
262af557 1298 phb = hose->private_data;
7f2c39e9 1299 if (phb->type == PNV_PHB_NPU_NVLINK) {
08f48f32
AP		 1300 /* PE#0 is needed for error reporting */
1301 pnv_ioda_reserve_pe(phb, 0);
b521549a 1302 pnv_ioda_setup_npu_PEs(hose->bus);
1ab66d1f 1303 if (phb->model == PNV_PHB_MODEL_NPU2)
0e759bd7 1304 WARN_ON_ONCE(pnv_npu2_init(hose));
ccd1c191 1305 }
184cd4a3 1306 }
0e759bd7
AK		 1307 list_for_each_entry(hose, &hose_list, list_node) {
1308 phb = hose->private_data;
1309 if (phb->type != PNV_PHB_IODA2)
1310 continue;
1311
1312 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1313 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1314 }
184cd4a3
BH		 1315}
1316
a8b2f828 1317#ifdef CONFIG_PCI_IOV
ee8222fe 1318static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1319{
1320 struct pci_bus *bus;
1321 struct pci_controller *hose;
1322 struct pnv_phb *phb;
1323 struct pci_dn *pdn;
02639b0e 1324 int i, j;
ee8222fe 1325 int m64_bars;
781a868f
WY		 1326
1327 bus = pdev->bus;
1328 hose = pci_bus_to_host(bus);
1329 phb = hose->private_data;
1330 pdn = pci_get_pdn(pdev);
1331
ee8222fe
WY		 1332 if (pdn->m64_single_mode)
1333 m64_bars = num_vfs;
1334 else
1335 m64_bars = 1;
1336
02639b0e 1337 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
ee8222fe
WY		 1338 for (j = 0; j < m64_bars; j++) {
1339 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
02639b0e
WY		 1340 continue;
1341 opal_pci_phb_mmio_enable(phb->opal_id,
ee8222fe
WY		 1342 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1343 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1344 pdn->m64_map[j][i] = IODA_INVALID_M64;
02639b0e 1345 }
781a868f 1346
ee8222fe 1347 kfree(pdn->m64_map);
781a868f
WY		 1348 return 0;
1349}
1350
02639b0e 1351static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
781a868f
WY		 1352{
1353 struct pci_bus *bus;
1354 struct pci_controller *hose;
1355 struct pnv_phb *phb;
1356 struct pci_dn *pdn;
1357 unsigned int win;
1358 struct resource *res;
02639b0e 1359 int i, j;
781a868f 1360 int64_t rc;
02639b0e
WY		 1361 int total_vfs;
1362 resource_size_t size, start;
1363 int pe_num;
ee8222fe 1364 int m64_bars;
781a868f
WY		 1365
1366 bus = pdev->bus;
1367 hose = pci_bus_to_host(bus);
1368 phb = hose->private_data;
1369 pdn = pci_get_pdn(pdev);
02639b0e 1370 total_vfs = pci_sriov_get_totalvfs(pdev);
781a868f 1371
ee8222fe
WY		 1372 if (pdn->m64_single_mode)
1373 m64_bars = num_vfs;
1374 else
1375 m64_bars = 1;
1376
fb37e128
ME		 1377 pdn->m64_map = kmalloc_array(m64_bars,
1378 sizeof(*pdn->m64_map),
1379 GFP_KERNEL);
ee8222fe
WY		 1380 if (!pdn->m64_map)
1381 return -ENOMEM;
1382 /* Initialize the m64_map to IODA_INVALID_M64 */
1383 for (i = 0; i < m64_bars ; i++)
1384 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1385 pdn->m64_map[i][j] = IODA_INVALID_M64;
02639b0e 1386
781a868f
WY		 1387
1388 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1389 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1390 if (!res->flags || !res->parent)
1391 continue;
1392
ee8222fe 1393 for (j = 0; j < m64_bars; j++) {
02639b0e
WY		 1394 do {
1395 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1396 phb->ioda.m64_bar_idx + 1, 0);
1397
1398 if (win >= phb->ioda.m64_bar_idx + 1)
1399 goto m64_failed;
1400 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1401
ee8222fe 1402 pdn->m64_map[j][i] = win;
02639b0e 1403
ee8222fe 1404 if (pdn->m64_single_mode) {
02639b0e
WY		 1405 size = pci_iov_resource_size(pdev,
1406 PCI_IOV_RESOURCES + i);
02639b0e
WY		 1407 start = res->start + size * j;
1408 } else {
1409 size = resource_size(res);
1410 start = res->start;
1411 }
1412
1413 /* Map the M64 here */
ee8222fe 1414 if (pdn->m64_single_mode) {
be283eeb 1415 pe_num = pdn->pe_num_map[j];
02639b0e
WY		 1416 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1417 pe_num, OPAL_M64_WINDOW_TYPE,
ee8222fe 1418 pdn->m64_map[j][i], 0);
02639b0e
WY		 1419 }
1420
1421 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1422 OPAL_M64_WINDOW_TYPE,
ee8222fe 1423 pdn->m64_map[j][i],
02639b0e
WY		 1424 start,
1425 0, /* unused */
1426 size);
781a868f 1427
781a868f 1428
02639b0e
WY		 1429 if (rc != OPAL_SUCCESS) {
1430 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1431 win, rc);
1432 goto m64_failed;
1433 }
781a868f 1434
ee8222fe 1435 if (pdn->m64_single_mode)
02639b0e 1436 rc = opal_pci_phb_mmio_enable(phb->opal_id,
ee8222fe 1437 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
02639b0e
WY		 1438 else
1439 rc = opal_pci_phb_mmio_enable(phb->opal_id,
ee8222fe 1440 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
781a868f 1441
02639b0e
WY		 1442 if (rc != OPAL_SUCCESS) {
1443 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1444 win, rc);
1445 goto m64_failed;
1446 }
781a868f
WY		 1447 }
1448 }
1449 return 0;
1450
1451m64_failed:
ee8222fe 1452 pnv_pci_vf_release_m64(pdev, num_vfs);
781a868f
WY		 1453 return -EBUSY;
1454}
1455
c035e37b
AK		 1456static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1457 int num);
c035e37b 1458
781a868f
WY		 1459static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1460{
781a868f 1461 struct iommu_table *tbl;
781a868f
WY		 1462 int64_t rc;
1463
b348aa65 1464 tbl = pe->table_group.tables[0];
c035e37b 1465 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
781a868f 1466 if (rc)
1e496391 1467 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
781a868f 1468
c035e37b 1469 pnv_pci_ioda2_set_bypass(pe, false);
0eaf4def
AK		 1470 if (pe->table_group.group) {
1471 iommu_group_put(pe->table_group.group);
1472 BUG_ON(pe->table_group.group);
ac9a5889 1473 }
e5afdf9d 1474 iommu_tce_table_put(tbl);
781a868f
WY		 1475}
1476
ee8222fe 1477static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
781a868f
WY		 1478{
1479 struct pci_bus *bus;
1480 struct pci_controller *hose;
1481 struct pnv_phb *phb;
1482 struct pnv_ioda_pe *pe, *pe_n;
1483 struct pci_dn *pdn;
1484
1485 bus = pdev->bus;
1486 hose = pci_bus_to_host(bus);
1487 phb = hose->private_data;
02639b0e 1488 pdn = pci_get_pdn(pdev);
781a868f
WY		 1489
1490 if (!pdev->is_physfn)
1491 return;
1492
781a868f
WY		 1493 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1494 if (pe->parent_dev != pdev)
1495 continue;
1496
1497 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1498
1499 /* Remove from list */
1500 mutex_lock(&phb->ioda.pe_list_mutex);
1501 list_del(&pe->list);
1502 mutex_unlock(&phb->ioda.pe_list_mutex);
1503
1504 pnv_ioda_deconfigure_pe(phb, pe);
1505
1e916772 1506 pnv_ioda_free_pe(pe);
781a868f
WY		 1507 }
1508}
1509
1510void pnv_pci_sriov_disable(struct pci_dev *pdev)
1511{
1512 struct pci_bus *bus;
1513 struct pci_controller *hose;
1514 struct pnv_phb *phb;
1e916772 1515 struct pnv_ioda_pe *pe;
781a868f 1516 struct pci_dn *pdn;
be283eeb 1517 u16 num_vfs, i;
781a868f
WY		 1518
1519 bus = pdev->bus;
1520 hose = pci_bus_to_host(bus);
1521 phb = hose->private_data;
1522 pdn = pci_get_pdn(pdev);
781a868f
WY		 1523 num_vfs = pdn->num_vfs;
1524
1525 /* Release VF PEs */
ee8222fe 1526 pnv_ioda_release_vf_PE(pdev);
781a868f
WY		 1527
1528 if (phb->type == PNV_PHB_IODA2) {
ee8222fe 1529 if (!pdn->m64_single_mode)
be283eeb 1530 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
781a868f
WY		 1531
1532 /* Release M64 windows */
ee8222fe 1533 pnv_pci_vf_release_m64(pdev, num_vfs);
781a868f
WY		 1534
1535 /* Release PE numbers */
be283eeb
WY		 1536 if (pdn->m64_single_mode) {
1537 for (i = 0; i < num_vfs; i++) {
1e916772
GS		 1538 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1539 continue;
1540
1541 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1542 pnv_ioda_free_pe(pe);
be283eeb
WY		 1543 }
1544 } else
1545 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1546 /* Releasing pe_num_map */
1547 kfree(pdn->pe_num_map);
781a868f
WY		 1548 }
1549}
1550
1551static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1552 struct pnv_ioda_pe *pe);
5eada8a3 1553#ifdef CONFIG_IOMMU_API
0bd97167
AK		 1554static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1555 struct iommu_table_group *table_group, struct pci_bus *bus);
1556
5eada8a3 1557#endif
781a868f
WY		 1558static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1559{
1560 struct pci_bus *bus;
1561 struct pci_controller *hose;
1562 struct pnv_phb *phb;
1563 struct pnv_ioda_pe *pe;
1564 int pe_num;
1565 u16 vf_index;
1566 struct pci_dn *pdn;
1567
1568 bus = pdev->bus;
1569 hose = pci_bus_to_host(bus);
1570 phb = hose->private_data;
1571 pdn = pci_get_pdn(pdev);
1572
1573 if (!pdev->is_physfn)
1574 return;
1575
1576 /* Reserve PE for each VF */
1577 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
67270ad7
OH		 1578 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1579 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1580 struct pci_dn *vf_pdn;
1581
be283eeb
WY		 1582 if (pdn->m64_single_mode)
1583 pe_num = pdn->pe_num_map[vf_index];
1584 else
1585 pe_num = *pdn->pe_num_map + vf_index;
781a868f
WY		 1586
1587 pe = &phb->ioda.pe_array[pe_num];
1588 pe->pe_number = pe_num;
1589 pe->phb = phb;
1590 pe->flags = PNV_IODA_PE_VF;
1591 pe->pbus = NULL;
1592 pe->parent_dev = pdev;
781a868f 1593 pe->mve_number = -1;
67270ad7 1594 pe->rid = (vf_bus << 8) | vf_devfn;
781a868f 1595
1f52f176 1596 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
781a868f 1597 hose->global_number, pdev->bus->number,
67270ad7 1598 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
781a868f
WY		 1599
1600 if (pnv_ioda_configure_pe(phb, pe)) {
1601 /* XXX What do we do here ? */
1e916772 1602 pnv_ioda_free_pe(pe);
781a868f
WY		 1603 pe->pdev = NULL;
1604 continue;
1605 }
1606
781a868f
WY		 1607 /* Put PE to the list */
1608 mutex_lock(&phb->ioda.pe_list_mutex);
1609 list_add_tail(&pe->list, &phb->ioda.pe_list);
1610 mutex_unlock(&phb->ioda.pe_list_mutex);
1611
67270ad7
OH		 1612 /* associate this pe to it's pdn */
1613 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1614 if (vf_pdn->busno == vf_bus &&
1615 vf_pdn->devfn == vf_devfn) {
1616 vf_pdn->pe_number = pe_num;
1617 break;
1618 }
1619 }
1620
781a868f 1621 pnv_pci_ioda2_setup_dma_pe(phb, pe);
5eada8a3 1622#ifdef CONFIG_IOMMU_API
8f5b2734
AK		 1623 iommu_register_group(&pe->table_group,
1624 pe->phb->hose->global_number, pe->pe_number);
0bd97167 1625 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
5eada8a3 1626#endif
781a868f
WY		 1627 }
1628}
1629
1630int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1631{
1632 struct pci_bus *bus;
1633 struct pci_controller *hose;
1634 struct pnv_phb *phb;
1e916772 1635 struct pnv_ioda_pe *pe;
781a868f
WY		 1636 struct pci_dn *pdn;
1637 int ret;
be283eeb 1638 u16 i;
781a868f
WY		 1639
1640 bus = pdev->bus;
1641 hose = pci_bus_to_host(bus);
1642 phb = hose->private_data;
1643 pdn = pci_get_pdn(pdev);
1644
1645 if (phb->type == PNV_PHB_IODA2) {
b0331854
WY		 1646 if (!pdn->vfs_expanded) {
1647 dev_info(&pdev->dev, "don't support this SRIOV device"
1648 " with non 64bit-prefetchable IOV BAR\n");
1649 return -ENOSPC;
1650 }
1651
ee8222fe
WY		 1652 /*
1653 * When M64 BARs functions in Single PE mode, the number of VFs
1654 * could be enabled must be less than the number of M64 BARs.
1655 */
1656 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1657 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1658 return -EBUSY;
1659 }
1660
be283eeb
WY		 1661 /* Allocating pe_num_map */
1662 if (pdn->m64_single_mode)
fb37e128
ME		 1663 pdn->pe_num_map = kmalloc_array(num_vfs,
1664 sizeof(*pdn->pe_num_map),
1665 GFP_KERNEL);
be283eeb
WY		 1666 else
1667 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1668
1669 if (!pdn->pe_num_map)
1670 return -ENOMEM;
1671
1672 if (pdn->m64_single_mode)
1673 for (i = 0; i < num_vfs; i++)
1674 pdn->pe_num_map[i] = IODA_INVALID_PE;
1675
781a868f 1676 /* Calculate available PE for required VFs */
be283eeb
WY		 1677 if (pdn->m64_single_mode) {
1678 for (i = 0; i < num_vfs; i++) {
1e916772
GS		 1679 pe = pnv_ioda_alloc_pe(phb);
1680 if (!pe) {
be283eeb
WY		 1681 ret = -EBUSY;
1682 goto m64_failed;
1683 }
1e916772
GS		 1684
1685 pdn->pe_num_map[i] = pe->pe_number;
be283eeb
WY		 1686 }
1687 } else {
1688 mutex_lock(&phb->ioda.pe_alloc_mutex);
1689 *pdn->pe_num_map = bitmap_find_next_zero_area(
92b8f137 1690 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
be283eeb 1691 0, num_vfs, 0);
92b8f137 1692 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
be283eeb
WY		 1693 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1694 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1695 kfree(pdn->pe_num_map);
1696 return -EBUSY;
1697 }
1698 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
781a868f 1699 mutex_unlock(&phb->ioda.pe_alloc_mutex);
781a868f 1700 }
781a868f 1701 pdn->num_vfs = num_vfs;
781a868f
WY		 1702
1703 /* Assign M64 window accordingly */
02639b0e 1704 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
781a868f
WY		 1705 if (ret) {
1706 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1707 goto m64_failed;
1708 }
1709
1710 /*
1711 * When using one M64 BAR to map one IOV BAR, we need to shift
1712 * the IOV BAR according to the PE# allocated to the VFs.
1713 * Otherwise, the PE# for the VF will conflict with others.
1714 */
ee8222fe 1715 if (!pdn->m64_single_mode) {
be283eeb 1716 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
02639b0e
WY		 1717 if (ret)
1718 goto m64_failed;
1719 }
781a868f
WY		 1720 }
1721
1722 /* Setup VF PEs */
1723 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1724
1725 return 0;
1726
1727m64_failed:
be283eeb
WY		 1728 if (pdn->m64_single_mode) {
1729 for (i = 0; i < num_vfs; i++) {
1e916772
GS		 1730 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1731 continue;
1732
1733 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1734 pnv_ioda_free_pe(pe);
be283eeb
WY		 1735 }
1736 } else
1737 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1738
1739 /* Releasing pe_num_map */
1740 kfree(pdn->pe_num_map);
781a868f
WY		 1741
1742 return ret;
1743}
1744
988fc3ba 1745int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
a8b2f828 1746{
781a868f
WY		 1747 pnv_pci_sriov_disable(pdev);
1748
a8b2f828
GS		 1749 /* Release PCI data */
1750 remove_dev_pci_data(pdev);
1751 return 0;
1752}
1753
988fc3ba 1754int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
a8b2f828
GS		 1755{
1756 /* Allocate PCI data */
1757 add_dev_pci_data(pdev);
781a868f 1758
ee8222fe 1759 return pnv_pci_sriov_enable(pdev, num_vfs);
a8b2f828
GS		 1760}
1761#endif /* CONFIG_PCI_IOV */
1762
959c9bdd 1763static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
184cd4a3 1764{
b72c1f65 1765 struct pci_dn *pdn = pci_get_pdn(pdev);
959c9bdd 1766 struct pnv_ioda_pe *pe;
184cd4a3 1767
959c9bdd
GS		 1768 /*
1769 * The function can be called while the PE#
1770 * hasn't been assigned. Do nothing for the
1771 * case.
1772 */
1773 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1774 return;
184cd4a3 1775
959c9bdd 1776 pe = &phb->ioda.pe_array[pdn->pe_number];
cd15b048 1777 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
0617fc0c 1778 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
b348aa65 1779 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
4617082e
AK		 1780 /*
1781 * Note: iommu_add_device() will fail here as
1782 * for physical PE: the device is already added by now;
1783 * for virtual PE: sysfs entries are not ready yet and
1784 * tce_iommu_bus_notifier will add the device to a group later.
1785 */
184cd4a3
BH		 1786}
1787
8e3f1b1d
RC		 1788/*
1789 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1790 *
1791 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1792 * Devices can only access more than that if bit 59 of the PCI address is set
1793 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1794 * Many PCI devices are not capable of addressing that many bits, and as a
1795 * result are limited to the 4GB of virtual memory made available to 32-bit
1796 * devices in TVE#0.
1797 *
1798 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1799 * devices by configuring the virtual memory past the first 4GB inaccessible
1800 * by 64-bit DMAs. This should only be used by devices that want more than
1801 * 4GB, and only on PEs that have no 32-bit devices.
1802 *
1803 * Currently this will only work on PHB3 (POWER8).
1804 */
1805static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1806{
1807 u64 window_size, table_size, tce_count, addr;
1808 struct page *table_pages;
1809 u64 tce_order = 28; /* 256MB TCEs */
1810 __be64 *tces;
1811 s64 rc;
1812
1813 /*
1814 * Window size needs to be a power of two, but needs to account for
1815 * shifting memory by the 4GB offset required to skip 32bit space.
1816 */
1817 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1818 tce_count = window_size >> tce_order;
1819 table_size = tce_count << 3;
1820
1821 if (table_size < PAGE_SIZE)
1822 table_size = PAGE_SIZE;
1823
1824 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1825 get_order(table_size));
1826 if (!table_pages)
1827 goto err;
1828
1829 tces = page_address(table_pages);
1830 if (!tces)
1831 goto err;
1832
1833 memset(tces, 0, table_size);
1834
1835 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1836 tces[(addr + (1ULL << 32)) >> tce_order] =
1837 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1838 }
1839
1840 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1841 pe->pe_number,
1842 /* reconfigure window 0 */
1843 (pe->pe_number << 1) + 0,
1844 1,
1845 __pa(tces),
1846 table_size,
1847 1 << tce_order);
1848 if (rc == OPAL_SUCCESS) {
1849 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1850 return 0;
1851 }
1852err:
1853 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1854 return -EIO;
1855}
1856
2d6ad41b
CH		 1857static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1858 u64 dma_mask)
cd15b048 1859{
763d2d8d
DA		 1860 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1861 struct pnv_phb *phb = hose->private_data;
cd15b048
BH		 1862 struct pci_dn *pdn = pci_get_pdn(pdev);
1863 struct pnv_ioda_pe *pe;
cd15b048
BH		 1864
1865 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
b511cdd1 1866 return false;
cd15b048
BH		 1867
1868 pe = &phb->ioda.pe_array[pdn->pe_number];
1869 if (pe->tce_bypass_enabled) {
2d6ad41b
CH		 1870 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1871 if (dma_mask >= top)
1872 return true;
cd15b048
BH		 1873 }
1874
2d6ad41b
CH		 1875 /*
1876 * If the device can't set the TCE bypass bit but still wants
1877 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1878 * bypass the 32-bit region and be usable for 64-bit DMAs.
1879 * The device needs to be able to address all of this space.
1880 */
1881 if (dma_mask >> 32 &&
1882 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1883 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1884 (pe->device_count == 1 || !pe->pbus) &&
1885 phb->model == PNV_PHB_MODEL_PHB3) {
1886 /* Configure the bypass mode */
1887 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1888 if (rc)
b511cdd1 1889 return false;
2d6ad41b 1890 /* 4GB offset bypasses 32-bit space */
0617fc0c 1891 pdev->dev.archdata.dma_offset = (1ULL << 32);
2d6ad41b 1892 return true;
cd15b048 1893 }
5d2aa710 1894
2d6ad41b 1895 return false;
fe7e85c6
GS		 1896}
1897
5eada8a3 1898static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
74251fe2
BH		 1899{
1900 struct pci_dev *dev;
1901
1902 list_for_each_entry(dev, &bus->devices, bus_list) {
b348aa65 1903 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
0617fc0c 1904 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
dff4a39e 1905
5c89a87d 1906 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
5eada8a3 1907 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
74251fe2
BH		 1908 }
1909}
1910
fd141d1a
BH		 1911static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1912 bool real_mode)
1913{
1914 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1915 (phb->regs + 0x210);
1916}
1917
a34ab7c3 1918static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
decbda25 1919 unsigned long index, unsigned long npages, bool rm)
4cce9550 1920{
0eaf4def
AK		 1921 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1922 &tbl->it_group_list, struct iommu_table_group_link,
1923 next);
1924 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
b348aa65 1925 struct pnv_ioda_pe, table_group);
fd141d1a 1926 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
4cce9550
GS		 1927 unsigned long start, end, inc;
1928
decbda25
AK		 1929 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1930 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1931 npages - 1);
4cce9550 1932
08acce1c
BH		 1933 /* p7ioc-style invalidation, 2 TCEs per write */
1934 start |= (1ull << 63);
1935 end |= (1ull << 63);
1936 inc = 16;
4cce9550
GS		 1937 end |= inc - 1; /* round up end to be different than start */
1938
1939 mb(); /* Ensure above stores are visible */
1940 while (start <= end) {
8e0a1611 1941 if (rm)
001ff2ee 1942 __raw_rm_writeq_be(start, invalidate);
8e0a1611 1943 else
001ff2ee
ME		 1944 __raw_writeq_be(start, invalidate);
1945
4cce9550
GS		 1946 start += inc;
1947 }
1948
1949 /*
1950 * The iommu layer will do another mb() for us on build()
1951 * and we don't care on free()
1952 */
1953}
1954
decbda25
AK		 1955static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1956 long npages, unsigned long uaddr,
1957 enum dma_data_direction direction,
00085f1e 1958 unsigned long attrs)
decbda25
AK		 1959{
1960 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1961 attrs);
1962
08acce1c 1963 if (!ret)
a34ab7c3 1964 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
decbda25
AK		 1965
1966 return ret;
1967}
1968
05c6cfb9 1969#ifdef CONFIG_IOMMU_API
35872480
AK		 1970/* Common for IODA1 and IODA2 */
1971static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1972 unsigned long *hpa, enum dma_data_direction *direction,
1973 bool realmode)
05c6cfb9 1974{
35872480 1975 return pnv_tce_xchg(tbl, index, hpa, direction, !realmode);
a540aa56 1976}
05c6cfb9
AK		 1977#endif
1978
decbda25
AK		 1979static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1980 long npages)
1981{
1982 pnv_tce_free(tbl, index, npages);
1983
08acce1c 1984 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
decbda25
AK		 1985}
1986
da004c36 1987static struct iommu_table_ops pnv_ioda1_iommu_ops = {
decbda25 1988 .set = pnv_ioda1_tce_build,
05c6cfb9 1989#ifdef CONFIG_IOMMU_API
35872480
AK		 1990 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1991 .tce_kill = pnv_pci_p7ioc_tce_invalidate,
090bad39 1992 .useraddrptr = pnv_tce_useraddrptr,
05c6cfb9 1993#endif
decbda25 1994 .clear = pnv_ioda1_tce_free,
da004c36
AK		 1995 .get = pnv_tce_get,
1996};
1997
a34ab7c3
BH		 1998#define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1999#define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
2000#define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
bef9253f 2001
6b3d12a9 2002static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
0bbcdb43 2003{
fd141d1a 2004 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
a34ab7c3 2005 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
0bbcdb43
AK		 2006
2007 mb(); /* Ensure previous TCE table stores are visible */
2008 if (rm)
001ff2ee 2009 __raw_rm_writeq_be(val, invalidate);
0bbcdb43 2010 else
001ff2ee 2011 __raw_writeq_be(val, invalidate);
0bbcdb43
AK		 2012}
2013
a34ab7c3 2014static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
5780fb04
AK		 2015{
2016 /* 01xb - invalidate TCEs that match the specified PE# */
fd141d1a 2017 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
a34ab7c3 2018 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
5780fb04
AK		 2019
2020 mb(); /* Ensure above stores are visible */
001ff2ee 2021 __raw_writeq_be(val, invalidate);
5780fb04
AK		 2022}
2023
fd141d1a
BH		 2024static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2025 unsigned shift, unsigned long index,
2026 unsigned long npages)
4cce9550 2027{
4d902195 2028 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
4cce9550 2029 unsigned long start, end, inc;
4cce9550
GS		 2030
2031 /* We'll invalidate DMA address in PE scope */
a34ab7c3 2032 start = PHB3_TCE_KILL_INVAL_ONE;
fd141d1a 2033 start |= (pe->pe_number & 0xFF);
4cce9550
GS		 2034 end = start;
2035
2036 /* Figure out the start, end and step */
decbda25
AK		 2037 start |= (index << shift);
2038 end |= ((index + npages - 1) << shift);
b0376c9b 2039 inc = (0x1ull << shift);
4cce9550
GS		 2040 mb();
2041
2042 while (start <= end) {
8e0a1611 2043 if (rm)
001ff2ee 2044 __raw_rm_writeq_be(start, invalidate);
8e0a1611 2045 else
001ff2ee 2046 __raw_writeq_be(start, invalidate);
4cce9550
GS		 2047 start += inc;
2048 }
2049}
2050
f0228c41
BH		 2051static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2052{
2053 struct pnv_phb *phb = pe->phb;
2054
2055 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2056 pnv_pci_phb3_tce_invalidate_pe(pe);
2057 else
2058 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2059 pe->pe_number, 0, 0, 0);
2060}
2061
e57080f1
AK		 2062static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2063 unsigned long index, unsigned long npages, bool rm)
2064{
2065 struct iommu_table_group_link *tgl;
2066
a540aa56 2067 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
e57080f1
AK		 2068 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2069 struct pnv_ioda_pe, table_group);
f0228c41
BH		 2070 struct pnv_phb *phb = pe->phb;
2071 unsigned int shift = tbl->it_page_shift;
2072
616badd2
AP		 2073 /*
2074 * NVLink1 can use the TCE kill register directly as
2075 * it's the same as PHB3. NVLink2 is different and
2076 * should go via the OPAL call.
2077 */
2078 if (phb->model == PNV_PHB_MODEL_NPU) {
0bbcdb43
AK		 2079 /*
2080 * The NVLink hardware does not support TCE kill
2081 * per TCE entry so we have to invalidate
2082 * the entire cache for it.
2083 */
f0228c41 2084 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
85674868
AK		 2085 continue;
2086 }
f0228c41
BH		 2087 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2088 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2089 index, npages);
f0228c41
BH		 2090 else
2091 opal_pci_tce_kill(phb->opal_id,
2092 OPAL_PCI_TCE_KILL_PAGES,
2093 pe->pe_number, 1u << shift,
2094 index << shift, npages);
e57080f1
AK		 2095 }
2096}
2097
6b3d12a9
AP		 2098void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2099{
2100 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2101 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2102 else
2103 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2104}
2105
decbda25
AK		 2106static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2107 long npages, unsigned long uaddr,
2108 enum dma_data_direction direction,
00085f1e 2109 unsigned long attrs)
4cce9550 2110{
decbda25
AK		 2111 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2112 attrs);
4cce9550 2113
08acce1c 2114 if (!ret)
decbda25
AK		 2115 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2116
2117 return ret;
2118}
2119
2120static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2121 long npages)
2122{
2123 pnv_tce_free(tbl, index, npages);
2124
08acce1c 2125 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
4cce9550
GS		 2126}
2127
da004c36 2128static struct iommu_table_ops pnv_ioda2_iommu_ops = {
decbda25 2129 .set = pnv_ioda2_tce_build,
05c6cfb9 2130#ifdef CONFIG_IOMMU_API
35872480
AK		 2131 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
2132 .tce_kill = pnv_pci_ioda2_tce_invalidate,
090bad39 2133 .useraddrptr = pnv_tce_useraddrptr,
05c6cfb9 2134#endif
decbda25 2135 .clear = pnv_ioda2_tce_free,
da004c36 2136 .get = pnv_tce_get,
da2bb0da 2137 .free = pnv_pci_ioda2_table_free_pages,
da004c36
AK		 2138};
2139
801846d1
GS		 2140static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2141{
2142 unsigned int *weight = (unsigned int *)data;
2143
2144 /* This is quite simplistic. The "base" weight of a device
2145 * is 10. 0 means no DMA is to be accounted for it.
2146 */
2147 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2148 return 0;
2149
2150 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2151 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2152 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2153 *weight += 3;
2154 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2155 *weight += 15;
2156 else
2157 *weight += 10;
2158
2159 return 0;
2160}
2161
2162static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2163{
2164 unsigned int weight = 0;
2165
2166 /* SRIOV VF has same DMA32 weight as its PF */
2167#ifdef CONFIG_PCI_IOV
2168 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2169 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2170 return weight;
2171 }
2172#endif
2173
2174 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2175 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2176 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2177 struct pci_dev *pdev;
2178
2179 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2180 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2181 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2182 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2183 }
2184
2185 return weight;
2186}
2187
b30d936f 2188static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2b923ed1 2189 struct pnv_ioda_pe *pe)
184cd4a3
BH		 2190{
2191
2192 struct page *tce_mem = NULL;
184cd4a3 2193 struct iommu_table *tbl;
2b923ed1
GS		 2194 unsigned int weight, total_weight = 0;
2195 unsigned int tce32_segsz, base, segs, avail, i;
184cd4a3
BH		 2196 int64_t rc;
2197 void *addr;
2198
184cd4a3
BH		 2199 /* XXX FIXME: Handle 64-bit only DMA devices */
2200 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2201 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2b923ed1
GS		 2202 weight = pnv_pci_ioda_pe_dma_weight(pe);
2203 if (!weight)
2204 return;
2205
2206 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2207 &total_weight);
2208 segs = (weight * phb->ioda.dma32_count) / total_weight;
2209 if (!segs)
2210 segs = 1;
184cd4a3 2211
2b923ed1
GS		 2212 /*
2213 * Allocate contiguous DMA32 segments. We begin with the expected
2214 * number of segments. With one more attempt, the number of DMA32
2215 * segments to be allocated is decreased by one until one segment
2216 * is allocated successfully.
2217 */
2218 do {
2219 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2220 for (avail = 0, i = base; i < base + segs; i++) {
2221 if (phb->ioda.dma32_segmap[i] ==
2222 IODA_INVALID_PE)
2223 avail++;
2224 }
2225
2226 if (avail == segs)
2227 goto found;
2228 }
2229 } while (--segs);
2230
2231 if (!segs) {
2232 pe_warn(pe, "No available DMA32 segments\n");
2233 return;
2234 }
2235
2236found:
0eaf4def 2237 tbl = pnv_pci_table_alloc(phb->hose->node);
82eae1af
AK		 2238 if (WARN_ON(!tbl))
2239 return;
2240
b348aa65
AK		 2241 iommu_register_group(&pe->table_group, phb->hose->global_number,
2242 pe->pe_number);
0eaf4def 2243 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
c5773822 2244
184cd4a3 2245 /* Grab a 32-bit TCE table */
2b923ed1
GS		 2246 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2247 weight, total_weight, base, segs);
184cd4a3 2248 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
acce971c
GS		 2249 base * PNV_IODA1_DMA32_SEGSIZE,
2250 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
184cd4a3
BH		 2251
2252 /* XXX Currently, we allocate one big contiguous table for the
2253 * TCEs. We only really need one chunk per 256M of TCE space
2254 * (ie per segment) but that's an optimization for later, it
2255 * requires some added smarts with our get/put_tce implementation
acce971c
GS		 2256 *
2257 * Each TCE page is 4KB in size and each TCE entry occupies 8
2258 * bytes
184cd4a3 2259 */
acce971c 2260 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
184cd4a3 2261 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
acce971c 2262 get_order(tce32_segsz * segs));
184cd4a3
BH		 2263 if (!tce_mem) {
2264 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2265 goto fail;
2266 }
2267 addr = page_address(tce_mem);
acce971c 2268 memset(addr, 0, tce32_segsz * segs);
184cd4a3
BH		 2269
2270 /* Configure HW */
2271 for (i = 0; i < segs; i++) {
2272 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2273 pe->pe_number,
2274 base + i, 1,
acce971c
GS		 2275 __pa(addr) + tce32_segsz * i,
2276 tce32_segsz, IOMMU_PAGE_SIZE_4K);
184cd4a3 2277 if (rc) {
1e496391
JP		 2278 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
2279 rc);
184cd4a3
BH		 2280 goto fail;
2281 }
2282 }
2283
2b923ed1
GS		 2284 /* Setup DMA32 segment mapping */
2285 for (i = base; i < base + segs; i++)
2286 phb->ioda.dma32_segmap[i] = pe->pe_number;
2287
184cd4a3 2288 /* Setup linux iommu table */
acce971c
GS		 2289 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2290 base * PNV_IODA1_DMA32_SEGSIZE,
2291 IOMMU_PAGE_SHIFT_4K);
184cd4a3 2292
da004c36 2293 tbl->it_ops = &pnv_ioda1_iommu_ops;
4793d65d
AK		 2294 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2295 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
201ed7f3 2296 iommu_init_table(tbl, phb->hose->node, 0, 0);
184cd4a3 2297
f21b0a45 2298 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
5eada8a3 2299 pnv_ioda_setup_bus_dma(pe, pe->pbus);
74251fe2 2300
184cd4a3
BH		 2301 return;
2302 fail:
2303 /* XXX Failure: Try to fallback to 64-bit only ? */
184cd4a3 2304 if (tce_mem)
acce971c 2305 __free_pages(tce_mem, get_order(tce32_segsz * segs));
0eaf4def
AK		 2306 if (tbl) {
2307 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
e5afdf9d 2308 iommu_tce_table_put(tbl);
0eaf4def 2309 }
184cd4a3
BH		 2310}
2311
43cb60ab
AK		 2312static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2313 int num, struct iommu_table *tbl)
2314{
2315 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2316 table_group);
2317 struct pnv_phb *phb = pe->phb;
2318 int64_t rc;
bbb845c4
AK		 2319 const unsigned long size = tbl->it_indirect_levels ?
2320 tbl->it_level_size : tbl->it_size;
43cb60ab
AK		 2321 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2322 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2323
1e496391
JP		 2324 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
2325 num, start_addr, start_addr + win_size - 1,
2326 IOMMU_PAGE_SIZE(tbl));
43cb60ab
AK		 2327
2328 /*
2329 * Map TCE table through TVT. The TVE index is the PE number
2330 * shifted by 1 bit for 32-bits DMA space.
2331 */
2332 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2333 pe->pe_number,
4793d65d 2334 (pe->pe_number << 1) + num,
bbb845c4 2335 tbl->it_indirect_levels + 1,
43cb60ab 2336 __pa(tbl->it_base),
bbb845c4 2337 size << 3,
43cb60ab
AK		 2338 IOMMU_PAGE_SIZE(tbl));
2339 if (rc) {
1e496391 2340 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
43cb60ab
AK		 2341 return rc;
2342 }
2343
2344 pnv_pci_link_table_and_group(phb->hose->node, num,
2345 tbl, &pe->table_group);
ed7d9a1d 2346 pnv_pci_ioda2_tce_invalidate_pe(pe);
43cb60ab
AK		 2347
2348 return 0;
2349}
2350
c498a4f9 2351static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
cd15b048 2352{
cd15b048
BH		 2353 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2354 int64_t rc;
2355
2356 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2357 if (enable) {
2358 phys_addr_t top = memblock_end_of_DRAM();
2359
2360 top = roundup_pow_of_two(top);
2361 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2362 pe->pe_number,
2363 window_id,
2364 pe->tce_bypass_base,
2365 top);
2366 } else {
2367 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2368 pe->pe_number,
2369 window_id,
2370 pe->tce_bypass_base,
2371 0);
cd15b048
BH		 2372 }
2373 if (rc)
2374 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2375 else
2376 pe->tce_bypass_enabled = enable;
2377}
2378
4793d65d
AK		 2379static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2380 int num, __u32 page_shift, __u64 window_size, __u32 levels,
090bad39 2381 bool alloc_userspace_copy, struct iommu_table **ptbl)
4793d65d
AK		 2382{
2383 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2384 table_group);
2385 int nid = pe->phb->hose->node;
2386 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2387 long ret;
2388 struct iommu_table *tbl;
2389
2390 tbl = pnv_pci_table_alloc(nid);
2391 if (!tbl)
2392 return -ENOMEM;
2393
11edf116
AK		 2394 tbl->it_ops = &pnv_ioda2_iommu_ops;
2395
4793d65d
AK		 2396 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2397 bus_offset, page_shift, window_size,
090bad39 2398 levels, alloc_userspace_copy, tbl);
4793d65d 2399 if (ret) {
e5afdf9d 2400 iommu_tce_table_put(tbl);
4793d65d
AK		 2401 return ret;
2402 }
2403
4793d65d
AK		 2404 *ptbl = tbl;
2405
2406 return 0;
2407}
2408
46d3e1e1
AK		 2409static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2410{
2411 struct iommu_table *tbl = NULL;
2412 long rc;
201ed7f3 2413 unsigned long res_start, res_end;
46d3e1e1 2414
fa144869
NA		 2415 /*
2416 * crashkernel= specifies the kdump kernel's maximum memory at
2417 * some offset and there is no guaranteed the result is a power
2418 * of 2, which will cause errors later.
2419 */
2420 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2421
bb005455
NA		 2422 /*
2423 * In memory constrained environments, e.g. kdump kernel, the
2424 * DMA window can be larger than available memory, which will
2425 * cause errors later.
2426 */
201ed7f3 2427 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1);
bb005455 2428
201ed7f3
AK		 2429 /*
2430 * We create the default window as big as we can. The constraint is
2431 * the max order of allocation possible. The TCE table is likely to
2432 * end up being multilevel and with on-demand allocation in place,
2433 * the initial use is not going to be huge as the default window aims
2434 * to support crippled devices (i.e. not fully 64bit DMAble) only.
2435 */
2436 /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
2437 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
2438 /* Each TCE level cannot exceed maxblock so go multilevel if needed */
2439 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
2440 unsigned long tcelevel_order = ilog2(maxblock >> 3);
2441 unsigned int levels = tces_order / tcelevel_order;
2442
2443 if (tces_order % tcelevel_order)
2444 levels += 1;
2445 /*
2446 * We try to stick to default levels (which is >1 at the moment) in
2447 * order to save memory by relying on on-demain TCE level allocation.
2448 */
2449 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
2450
2451 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
2452 window_size, levels, false, &tbl);
46d3e1e1
AK		 2453 if (rc) {
2454 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2455 rc);
2456 return rc;
2457 }
2458
201ed7f3
AK		 2459 /* We use top part of 32bit space for MMIO so exclude it from DMA */
2460 res_start = 0;
2461 res_end = 0;
2462 if (window_size > pe->phb->ioda.m32_pci_base) {
2463 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
2464 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
2465 }
2466 iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end);
46d3e1e1
AK		 2467
2468 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2469 if (rc) {
2470 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2471 rc);
e5afdf9d 2472 iommu_tce_table_put(tbl);
46d3e1e1
AK		 2473 return rc;
2474 }
2475
2476 if (!pnv_iommu_bypass_disabled)
2477 pnv_pci_ioda2_set_bypass(pe, true);
2478
5636427d
AK		 2479 /*
2480 * Set table base for the case of IOMMU DMA use. Usually this is done
2481 * from dma_dev_setup() which is not called when a device is returned
2482 * from VFIO so do it here.
2483 */
2484 if (pe->pdev)
2485 set_iommu_table_base(&pe->pdev->dev, tbl);
2486
46d3e1e1
AK		 2487 return 0;
2488}
2489
b5926430
AK		 2490#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2491static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2492 int num)
2493{
2494 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2495 table_group);
2496 struct pnv_phb *phb = pe->phb;
2497 long ret;
2498
2499 pe_info(pe, "Removing DMA window #%d\n", num);
2500
2501 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2502 (pe->pe_number << 1) + num,
2503 0/* levels */, 0/* table address */,
2504 0/* table size */, 0/* page size */);
2505 if (ret)
2506 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2507 else
ed7d9a1d 2508 pnv_pci_ioda2_tce_invalidate_pe(pe);
b5926430
AK		 2509
2510 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2511
2512 return ret;
2513}
2514#endif
2515
f87a8864 2516#ifdef CONFIG_IOMMU_API
0bd97167 2517unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
00547193
AK		 2518 __u64 window_size, __u32 levels)
2519{
2520 unsigned long bytes = 0;
2521 const unsigned window_shift = ilog2(window_size);
2522 unsigned entries_shift = window_shift - page_shift;
2523 unsigned table_shift = entries_shift + 3;
2524 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2525 unsigned long direct_table_size;
2526
2527 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
00547193
AK		 2528 !is_power_of_2(window_size))
2529 return 0;
2530
2531 /* Calculate a direct table size from window_size and levels */
2532 entries_shift = (entries_shift + levels - 1) / levels;
2533 table_shift = entries_shift + 3;
2534 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2535 direct_table_size = 1UL << table_shift;
2536
2537 for ( ; levels; --levels) {
2538 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2539
2540 tce_table_size /= direct_table_size;
2541 tce_table_size <<= 3;
e49a6a21
AK		 2542 tce_table_size = max_t(unsigned long,
2543 tce_table_size, direct_table_size);
00547193
AK		 2544 }
2545
090bad39
AK		 2546 return bytes + bytes; /* one for HW table, one for userspace copy */
2547}
2548
2549static long pnv_pci_ioda2_create_table_userspace(
2550 struct iommu_table_group *table_group,
2551 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2552 struct iommu_table **ptbl)
2553{
11f5acce 2554 long ret = pnv_pci_ioda2_create_table(table_group,
090bad39 2555 num, page_shift, window_size, levels, true, ptbl);
11f5acce
AK		 2556
2557 if (!ret)
2558 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2559 page_shift, window_size, levels);
2560 return ret;
00547193
AK		 2561}
2562
f87a8864 2563static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
cd15b048 2564{
f87a8864
AK		 2565 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2566 table_group);
46d3e1e1
AK		 2567 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2568 struct iommu_table *tbl = pe->table_group.tables[0];
cd15b048 2569
f87a8864 2570 pnv_pci_ioda2_set_bypass(pe, false);
46d3e1e1 2571 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
db08e1d5 2572 if (pe->pbus)
5eada8a3 2573 pnv_ioda_setup_bus_dma(pe, pe->pbus);
5636427d
AK		 2574 else if (pe->pdev)
2575 set_iommu_table_base(&pe->pdev->dev, NULL);
e5afdf9d 2576 iommu_tce_table_put(tbl);
f87a8864 2577}
cd15b048 2578
f87a8864
AK		 2579static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2580{
2581 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2582 table_group);
2583
46d3e1e1 2584 pnv_pci_ioda2_setup_default_config(pe);
db08e1d5 2585 if (pe->pbus)
5eada8a3 2586 pnv_ioda_setup_bus_dma(pe, pe->pbus);
cd15b048
BH		 2587}
2588
f87a8864 2589static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
00547193 2590 .get_table_size = pnv_pci_ioda2_get_table_size,
090bad39 2591 .create_table = pnv_pci_ioda2_create_table_userspace,
4793d65d
AK		 2592 .set_window = pnv_pci_ioda2_set_window,
2593 .unset_window = pnv_pci_ioda2_unset_window,
f87a8864
AK		 2594 .take_ownership = pnv_ioda2_take_ownership,
2595 .release_ownership = pnv_ioda2_release_ownership,
2596};
b5cb9ab1 2597
5eada8a3 2598static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
0bd97167 2599 struct iommu_table_group *table_group,
5eada8a3
AK		 2600 struct pci_bus *bus)
2601{
2602 struct pci_dev *dev;
2603
2604 list_for_each_entry(dev, &bus->devices, bus_list) {
0bd97167 2605 iommu_add_device(table_group, &dev->dev);
5eada8a3
AK		 2606
2607 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2608 pnv_ioda_setup_bus_iommu_group_add_devices(pe,
0bd97167 2609 table_group, dev->subordinate);
5eada8a3
AK		 2610 }
2611}
2612
0bd97167
AK		 2613static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2614 struct iommu_table_group *table_group, struct pci_bus *bus)
5eada8a3 2615{
5eada8a3 2616
5eada8a3 2617 if (pe->flags & PNV_IODA_PE_DEV)
0bd97167
AK		 2618 iommu_add_device(table_group, &pe->pdev->dev);
2619
2620 if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2621 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2622 bus);
5eada8a3
AK		 2623}
2624
0bd97167
AK		 2625static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2626
b5cb9ab1
AK		 2627static void pnv_pci_ioda_setup_iommu_api(void)
2628{
0bd97167 2629 struct pci_controller *hose;
b5cb9ab1 2630 struct pnv_phb *phb;
0bd97167 2631 struct pnv_ioda_pe *pe;
b5cb9ab1 2632
5eada8a3
AK		 2633 /*
2634 * There are 4 types of PEs:
2635 * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2636 * created from pnv_pci_setup_bridge();
2637 * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2638 * created from pnv_pci_setup_bridge();
2639 * - PNV_IODA_PE_VF: a SRIOV virtual function,
2640 * created from pnv_pcibios_sriov_enable();
2641 * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2642 * created from pnv_pci_ioda_fixup().
2643 *
2644 * Normally a PE is represented by an IOMMU group, however for
2645 * devices with side channels the groups need to be more strict.
2646 */
2647 list_for_each_entry(hose, &hose_list, list_node) {
2648 phb = hose->private_data;
2649
6bca5159
FB		 2650 if (phb->type == PNV_PHB_NPU_NVLINK ||
2651 phb->type == PNV_PHB_NPU_OCAPI)
5eada8a3
AK		 2652 continue;
2653
0bd97167
AK		 2654 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2655 struct iommu_table_group *table_group;
2656
2657 table_group = pnv_try_setup_npu_table_group(pe);
2658 if (!table_group) {
2659 if (!pnv_pci_ioda_pe_dma_weight(pe))
2660 continue;
2661
2662 table_group = &pe->table_group;
2663 iommu_register_group(&pe->table_group,
2664 pe->phb->hose->global_number,
2665 pe->pe_number);
2666 }
2667 pnv_ioda_setup_bus_iommu_group(pe, table_group,
2668 pe->pbus);
2669 }
5eada8a3
AK		 2670 }
2671
b5cb9ab1
AK		 2672 /*
2673 * Now we have all PHBs discovered, time to add NPU devices to
2674 * the corresponding IOMMU groups.
2675 */
0bd97167
AK		 2676 list_for_each_entry(hose, &hose_list, list_node) {
2677 unsigned long pgsizes;
2678
b5cb9ab1
AK		 2679 phb = hose->private_data;
2680
7f2c39e9 2681 if (phb->type != PNV_PHB_NPU_NVLINK)
b5cb9ab1
AK		 2682 continue;
2683
0bd97167 2684 pgsizes = pnv_ioda_parse_tce_sizes(phb);
b5cb9ab1 2685 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
0bd97167
AK		 2686 /*
2687 * IODA2 bridges get this set up from
2688 * pci_controller_ops::setup_bridge but NPU bridges
2689 * do not have this hook defined so we do it here.
2690 */
2691 pe->table_group.pgsizes = pgsizes;
2692 pnv_npu_compound_attach(pe);
b5cb9ab1
AK		 2693 }
2694 }
2695}
2696#else /* !CONFIG_IOMMU_API */
2697static void pnv_pci_ioda_setup_iommu_api(void) { };
f87a8864
AK		 2698#endif
2699
7ef73cd3
AK		 2700static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2701{
2702 struct pci_controller *hose = phb->hose;
2703 struct device_node *dn = hose->dn;
2704 unsigned long mask = 0;
2705 int i, rc, count;
2706 u32 val;
2707
2708 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2709 if (count <= 0) {
2710 mask = SZ_4K | SZ_64K;
2711 /* Add 16M for POWER8 by default */
2712 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2713 !cpu_has_feature(CPU_FTR_ARCH_300))
00c376fd 2714 mask |= SZ_16M | SZ_256M;
7ef73cd3
AK		 2715 return mask;
2716 }
2717
2718 for (i = 0; i < count; i++) {
2719 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2720 i, &val);
2721 if (rc == 0)
2722 mask |= 1ULL << val;
2723 }
2724
2725 return mask;
2726}
2727
aca6913f
AK		 2728static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2729 struct pnv_ioda_pe *pe)
2730{
373f5657
GS		 2731 int64_t rc;
2732
ccd1c191
GS		 2733 if (!pnv_pci_ioda_pe_dma_weight(pe))
2734 return;
2735
f87a8864
AK		 2736 /* TVE #1 is selected by PCI address bit 59 */
2737 pe->tce_bypass_base = 1ull << 59;
2738
373f5657 2739 /* The PE will reserve all possible 32-bits space */
373f5657 2740 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
aca6913f 2741 phb->ioda.m32_pci_base);
373f5657 2742
aca6913f 2743 /* Setup linux iommu table */
4793d65d
AK		 2744 pe->table_group.tce32_start = 0;
2745 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2746 pe->table_group.max_dynamic_windows_supported =
2747 IOMMU_TABLE_GROUP_MAX_TABLES;
2748 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
7ef73cd3 2749 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
e5aad1e6
AK		 2750#ifdef CONFIG_IOMMU_API
2751 pe->table_group.ops = &pnv_pci_ioda2_ops;
2752#endif
2753
46d3e1e1 2754 rc = pnv_pci_ioda2_setup_default_config(pe);
801846d1 2755 if (rc)
46d3e1e1 2756 return;
373f5657 2757
20f13b95 2758 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
5eada8a3 2759 pnv_ioda_setup_bus_dma(pe, pe->pbus);
373f5657
GS		 2760}
2761
4ee11c1a 2762int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
137436c9 2763{
137436c9
GS		 2764 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2765 ioda.irq_chip);
4ee11c1a
SW		 2766
2767 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2768}
2769
2770static void pnv_ioda2_msi_eoi(struct irq_data *d)
2771{
137436c9 2772 int64_t rc;
4ee11c1a
SW		 2773 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2774 struct irq_chip *chip = irq_data_get_irq_chip(d);
137436c9 2775
4ee11c1a 2776 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
137436c9
GS		 2777 WARN_ON_ONCE(rc);
2778
2779 icp_native_eoi(d);
2780}
2781
fd9a1c26 2782
f456834a 2783void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
fd9a1c26
IM		 2784{
2785 struct irq_data *idata;
2786 struct irq_chip *ichip;
2787
fb111334
BH		 2788 /* The MSI EOI OPAL call is only needed on PHB3 */
2789 if (phb->model != PNV_PHB_MODEL_PHB3)
fd9a1c26
IM		 2790 return;
2791
2792 if (!phb->ioda.irq_chip_init) {
2793 /*
2794 * First time we setup an MSI IRQ, we need to setup the
2795 * corresponding IRQ chip to route correctly.
2796 */
2797 idata = irq_get_irq_data(virq);
2798 ichip = irq_data_get_irq_chip(idata);
2799 phb->ioda.irq_chip_init = 1;
2800 phb->ioda.irq_chip = *ichip;
2801 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2802 }
2803 irq_set_chip(virq, &phb->ioda.irq_chip);
2804}
2805
4ee11c1a
SW		 2806/*
2807 * Returns true iff chip is something that we could call
2808 * pnv_opal_pci_msi_eoi for.
2809 */
2810bool is_pnv_opal_msi(struct irq_chip *chip)
2811{
2812 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2813}
2814EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2815
184cd4a3 2816static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
137436c9
GS		 2817 unsigned int hwirq, unsigned int virq,
2818 unsigned int is_64, struct msi_msg *msg)
184cd4a3
BH		 2819{
2820 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2821 unsigned int xive_num = hwirq - phb->msi_base;
3a1a4661 2822 __be32 data;
184cd4a3
BH		 2823 int rc;
2824
2825 /* No PE assigned ? bail out ... no MSI for you ! */
2826 if (pe == NULL)
2827 return -ENXIO;
2828
2829 /* Check if we have an MVE */
2830 if (pe->mve_number < 0)
2831 return -ENXIO;
2832
b72c1f65 2833 /* Force 32-bit MSI on some broken devices */
36074381 2834 if (dev->no_64bit_msi)
b72c1f65
BH		 2835 is_64 = 0;
2836
184cd4a3
BH		 2837 /* Assign XIVE to PE */
2838 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2839 if (rc) {
2840 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2841 pci_name(dev), rc, xive_num);
2842 return -EIO;
2843 }
2844
2845 if (is_64) {
3a1a4661
BH		 2846 __be64 addr64;
2847
184cd4a3
BH		 2848 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2849 &addr64, &data);
2850 if (rc) {
2851 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2852 pci_name(dev), rc);
2853 return -EIO;
2854 }
3a1a4661
BH		 2855 msg->address_hi = be64_to_cpu(addr64) >> 32;
2856 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
184cd4a3 2857 } else {
3a1a4661
BH		 2858 __be32 addr32;
2859
184cd4a3
BH		 2860 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2861 &addr32, &data);
2862 if (rc) {
2863 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2864 pci_name(dev), rc);
2865 return -EIO;
2866 }
2867 msg->address_hi = 0;
3a1a4661 2868 msg->address_lo = be32_to_cpu(addr32);
184cd4a3 2869 }
3a1a4661 2870 msg->data = be32_to_cpu(data);
184cd4a3 2871
f456834a 2872 pnv_set_msi_irq_chip(phb, virq);
137436c9 2873
184cd4a3 2874 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
1f52f176 2875 " address=%x_%08x data=%x PE# %x\n",
184cd4a3
BH		 2876 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2877 msg->address_hi, msg->address_lo, data, pe->pe_number);
2878
2879 return 0;
2880}
2881
2882static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2883{
fb1b55d6 2884 unsigned int count;
184cd4a3
BH		 2885 const __be32 *prop = of_get_property(phb->hose->dn,
2886 "ibm,opal-msi-ranges", NULL);
2887 if (!prop) {
2888 /* BML Fallback */
2889 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2890 }
2891 if (!prop)
2892 return;
2893
2894 phb->msi_base = be32_to_cpup(prop);
fb1b55d6
GS		 2895 count = be32_to_cpup(prop + 1);
2896 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
184cd4a3
BH		 2897 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2898 phb->hose->global_number);
2899 return;
2900 }
fb1b55d6 2901
184cd4a3
BH		 2902 phb->msi_setup = pnv_pci_ioda_msi_setup;
2903 phb->msi32_support = 1;
2904 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
fb1b55d6 2905 count, phb->msi_base);
184cd4a3 2906}
184cd4a3 2907
6e628c7d
WY		 2908#ifdef CONFIG_PCI_IOV
2909static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2910{
f2dd0afe
WY		 2911 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2912 struct pnv_phb *phb = hose->private_data;
2913 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
6e628c7d
WY		 2914 struct resource *res;
2915 int i;
dfcc8d45 2916 resource_size_t size, total_vf_bar_sz;
6e628c7d 2917 struct pci_dn *pdn;
5b88ec22 2918 int mul, total_vfs;
6e628c7d 2919
6e628c7d
WY		 2920 pdn = pci_get_pdn(pdev);
2921 pdn->vfs_expanded = 0;
ee8222fe 2922 pdn->m64_single_mode = false;
6e628c7d 2923
5b88ec22 2924 total_vfs = pci_sriov_get_totalvfs(pdev);
92b8f137 2925 mul = phb->ioda.total_pe_num;
dfcc8d45 2926 total_vf_bar_sz = 0;
5b88ec22
WY		 2927
2928 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2929 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2930 if (!res->flags || res->parent)
2931 continue;
b79331a5 2932 if (!pnv_pci_is_m64_flags(res->flags)) {
b0331854
WY		 2933 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2934 " non M64 VF BAR%d: %pR. \n",
5b88ec22 2935 i, res);
b0331854 2936 goto truncate_iov;
5b88ec22
WY		 2937 }
2938
dfcc8d45
WY		 2939 total_vf_bar_sz += pci_iov_resource_size(pdev,
2940 i + PCI_IOV_RESOURCES);
5b88ec22 2941
f2dd0afe
WY		 2942 /*
2943 * If bigger than quarter of M64 segment size, just round up
2944 * power of two.
2945 *
2946 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2947 * with other devices, IOV BAR size is expanded to be
2948 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2949 * segment size , the expanded size would equal to half of the
2950 * whole M64 space size, which will exhaust the M64 Space and
2951 * limit the system flexibility. This is a design decision to
2952 * set the boundary to quarter of the M64 segment size.
2953 */
dfcc8d45 2954 if (total_vf_bar_sz > gate) {
5b88ec22 2955 mul = roundup_pow_of_two(total_vfs);
dfcc8d45
WY		 2956 dev_info(&pdev->dev,
2957 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2958 total_vf_bar_sz, gate, mul);
ee8222fe 2959 pdn->m64_single_mode = true;
5b88ec22
WY		 2960 break;
2961 }
2962 }
2963
6e628c7d
WY		 2964 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2965 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2966 if (!res->flags || res->parent)
2967 continue;
6e628c7d 2968
6e628c7d 2969 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
ee8222fe
WY		 2970 /*
2971 * On PHB3, the minimum size alignment of M64 BAR in single
2972 * mode is 32MB.
2973 */
2974 if (pdn->m64_single_mode && (size < SZ_32M))
2975 goto truncate_iov;
2976 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
5b88ec22 2977 res->end = res->start + size * mul - 1;
6e628c7d
WY		 2978 dev_dbg(&pdev->dev, " %pR\n", res);
2979 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
5b88ec22 2980 i, res, mul);
6e628c7d 2981 }
5b88ec22 2982 pdn->vfs_expanded = mul;
b0331854
WY		 2983
2984 return;
2985
2986truncate_iov:
2987 /* To save MMIO space, IOV BAR is truncated. */
2988 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2989 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2990 res->flags = 0;
2991 res->end = res->start - 1;
2992 }
6e628c7d 2993}
9fc91252
OH		 2994
2995static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
2996{
2997 if (WARN_ON(pci_dev_is_added(pdev)))
2998 return;
2999
3000 if (pdev->is_virtfn) {
3001 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
3002
3003 /*
3004 * VF PEs are single-device PEs so their pdev pointer needs to
3005 * be set. The pdev doesn't exist when the PE is allocated (in
3006 * (pcibios_sriov_enable()) so we fix it up here.
3007 */
3008 pe->pdev = pdev;
3009 WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
3010 } else if (pdev->is_physfn) {
3011 /*
3012 * For PFs adjust their allocated IOV resources to match what
3013 * the PHB can support using it's M64 BAR table.
3014 */
3015 pnv_pci_ioda_fixup_iov_resources(pdev);
3016 }
3017}
6e628c7d
WY		 3018#endif /* CONFIG_PCI_IOV */
3019
23e79425
GS		 3020static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3021 struct resource *res)
3022{
3023 struct pnv_phb *phb = pe->phb;
3024 struct pci_bus_region region;
3025 int index;
3026 int64_t rc;
3027
3028 if (!res || !res->flags || res->start > res->end)
3029 return;
3030
3031 if (res->flags & IORESOURCE_IO) {
3032 region.start = res->start - phb->ioda.io_pci_base;
3033 region.end = res->end - phb->ioda.io_pci_base;
3034 index = region.start / phb->ioda.io_segsize;
3035
3036 while (index < phb->ioda.total_pe_num &&
3037 region.start <= region.end) {
3038 phb->ioda.io_segmap[index] = pe->pe_number;
3039 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3040 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3041 if (rc != OPAL_SUCCESS) {
1f52f176 3042 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
23e79425
GS		 3043 __func__, rc, index, pe->pe_number);
3044 break;
3045 }
3046
3047 region.start += phb->ioda.io_segsize;
3048 index++;
3049 }
3050 } else if ((res->flags & IORESOURCE_MEM) &&
5958d19a 3051 !pnv_pci_is_m64(phb, res)) {
23e79425
GS		 3052 region.start = res->start -
3053 phb->hose->mem_offset[0] -
3054 phb->ioda.m32_pci_base;
3055 region.end = res->end -
3056 phb->hose->mem_offset[0] -
3057 phb->ioda.m32_pci_base;
3058 index = region.start / phb->ioda.m32_segsize;
3059
3060 while (index < phb->ioda.total_pe_num &&
3061 region.start <= region.end) {
3062 phb->ioda.m32_segmap[index] = pe->pe_number;
3063 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3064 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3065 if (rc != OPAL_SUCCESS) {
1f52f176 3066 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
23e79425
GS		 3067 __func__, rc, index, pe->pe_number);
3068 break;
3069 }
3070
3071 region.start += phb->ioda.m32_segsize;
3072 index++;
3073 }
3074 }
3075}
3076
11685bec
GS		 3077/*
3078 * This function is supposed to be called on basis of PE from top
3079 * to bottom style. So the the I/O or MMIO segment assigned to
03671057 3080 * parent PE could be overridden by its child PEs if necessary.
11685bec 3081 */
23e79425 3082static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
11685bec 3083{
69d733e7 3084 struct pci_dev *pdev;
23e79425 3085 int i;
11685bec
GS		 3086
3087 /*
3088 * NOTE: We only care PCI bus based PE for now. For PCI
3089 * device based PE, for example SRIOV sensitive VF should
3090 * be figured out later.
3091 */
3092 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3093
69d733e7
GS		 3094 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3095 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3096 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3097
3098 /*
3099 * If the PE contains all subordinate PCI buses, the
3100 * windows of the child bridges should be mapped to
3101 * the PE as well.
3102 */
3103 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3104 continue;
3105 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3106 pnv_ioda_setup_pe_res(pe,
3107 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3108 }
11685bec
GS		 3109}
3110
98b665da
RC		 3111#ifdef CONFIG_DEBUG_FS
3112static int pnv_pci_diag_data_set(void *data, u64 val)
3113{
3114 struct pci_controller *hose;
3115 struct pnv_phb *phb;
3116 s64 ret;
3117
3118 if (val != 1ULL)
3119 return -EINVAL;
3120
3121 hose = (struct pci_controller *)data;
3122 if (!hose || !hose->private_data)
3123 return -ENODEV;
3124
3125 phb = hose->private_data;
3126
3127 /* Retrieve the diag data from firmware */
5cb1f8fd
RC		 3128 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3129 phb->diag_data_size);
98b665da
RC		 3130 if (ret != OPAL_SUCCESS)
3131 return -EIO;
3132
3133 /* Print the diag data to the kernel log */
5cb1f8fd 3134 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
98b665da
RC		 3135 return 0;
3136}
3137
3138DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3139 pnv_pci_diag_data_set, "%llu\n");
3140
3141#endif /* CONFIG_DEBUG_FS */
3142
37c367f2
GS		 3143static void pnv_pci_ioda_create_dbgfs(void)
3144{
3145#ifdef CONFIG_DEBUG_FS
3146 struct pci_controller *hose, *tmp;
3147 struct pnv_phb *phb;
3148 char name[16];
3149
3150 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3151 phb = hose->private_data;
3152
ccd1c191
GS		 3153 /* Notify initialization of PHB done */
3154 phb->initialized = 1;
3155
37c367f2
GS		 3156 sprintf(name, "PCI%04x", hose->global_number);
3157 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
98b665da 3158 if (!phb->dbgfs) {
f2c2cbcc 3159 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
37c367f2 3160 __func__, hose->global_number);
98b665da
RC		 3161 continue;
3162 }
3163
3164 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3165 &pnv_pci_diag_data_fops);
37c367f2
GS		 3166 }
3167#endif /* CONFIG_DEBUG_FS */
3168}
3169
db217319
BH		 3170static void pnv_pci_enable_bridge(struct pci_bus *bus)
3171{
3172 struct pci_dev *dev = bus->self;
3173 struct pci_bus *child;
3174
3175 /* Empty bus ? bail */
3176 if (list_empty(&bus->devices))
3177 return;
3178
3179 /*
3180 * If there's a bridge associated with that bus enable it. This works
3181 * around races in the generic code if the enabling is done during
3182 * parallel probing. This can be removed once those races have been
3183 * fixed.
3184 */
3185 if (dev) {
3186 int rc = pci_enable_device(dev);
3187 if (rc)
3188 pci_err(dev, "Error enabling bridge (%d)\n", rc);
3189 pci_set_master(dev);
3190 }
3191
3192 /* Perform the same to child busses */
3193 list_for_each_entry(child, &bus->children, node)
3194 pnv_pci_enable_bridge(child);
3195}
3196
3197static void pnv_pci_enable_bridges(void)
3198{
3199 struct pci_controller *hose;
3200
3201 list_for_each_entry(hose, &hose_list, list_node)
3202 pnv_pci_enable_bridge(hose->bus);
3203}
3204
cad5cef6 3205static void pnv_pci_ioda_fixup(void)
fb446ad0
GS		 3206{
3207 pnv_pci_ioda_setup_PEs();
ccd1c191 3208 pnv_pci_ioda_setup_iommu_api();
37c367f2
GS		 3209 pnv_pci_ioda_create_dbgfs();
3210
db217319
BH		 3211 pnv_pci_enable_bridges();
3212
e9cc17d4 3213#ifdef CONFIG_EEH
b9fde58d 3214 pnv_eeh_post_init();
e9cc17d4 3215#endif
fb446ad0
GS		 3216}
3217
271fd03a
GS		 3218/*
3219 * Returns the alignment for I/O or memory windows for P2P
3220 * bridges. That actually depends on how PEs are segmented.
3221 * For now, we return I/O or M32 segment size for PE sensitive
3222 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3223 * 1MiB for memory) will be returned.
3224 *
3225 * The current PCI bus might be put into one PE, which was
3226 * create against the parent PCI bridge. For that case, we
3227 * needn't enlarge the alignment so that we can save some
3228 * resources.
3229 */
3230static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3231 unsigned long type)
3232{
3233 struct pci_dev *bridge;
3234 struct pci_controller *hose = pci_bus_to_host(bus);
3235 struct pnv_phb *phb = hose->private_data;
3236 int num_pci_bridges = 0;
3237
3238 bridge = bus->self;
3239 while (bridge) {
3240 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3241 num_pci_bridges++;
3242 if (num_pci_bridges >= 2)
3243 return 1;
3244 }
3245
3246 bridge = bridge->bus->self;
3247 }
3248
5958d19a
BH		 3249 /*
3250 * We fall back to M32 if M64 isn't supported. We enforce the M64
3251 * alignment for any 64-bit resource, PCIe doesn't care and
3252 * bridges only do 64-bit prefetchable anyway.
3253 */
b79331a5 3254 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
262af557 3255 return phb->ioda.m64_segsize;
271fd03a
GS		 3256 if (type & IORESOURCE_MEM)
3257 return phb->ioda.m32_segsize;
3258
3259 return phb->ioda.io_segsize;
3260}
3261
40e2a47e
GS		 3262/*
3263 * We are updating root port or the upstream port of the
3264 * bridge behind the root port with PHB's windows in order
3265 * to accommodate the changes on required resources during
3266 * PCI (slot) hotplug, which is connected to either root
3267 * port or the downstream ports of PCIe switch behind the
3268 * root port.
3269 */
3270static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3271 unsigned long type)
3272{
3273 struct pci_controller *hose = pci_bus_to_host(bus);
3274 struct pnv_phb *phb = hose->private_data;
3275 struct pci_dev *bridge = bus->self;
3276 struct resource *r, *w;
3277 bool msi_region = false;
3278 int i;
3279
3280 /* Check if we need apply fixup to the bridge's windows */
3281 if (!pci_is_root_bus(bridge->bus) &&
3282 !pci_is_root_bus(bridge->bus->self->bus))
3283 return;
3284
3285 /* Fixup the resources */
3286 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3287 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3288 if (!r->flags || !r->parent)
3289 continue;
3290
3291 w = NULL;
3292 if (r->flags & type & IORESOURCE_IO)
3293 w = &hose->io_resource;
5958d19a 3294 else if (pnv_pci_is_m64(phb, r) &&
40e2a47e
GS		 3295 (type & IORESOURCE_PREFETCH) &&
3296 phb->ioda.m64_segsize)
3297 w = &hose->mem_resources[1];
3298 else if (r->flags & type & IORESOURCE_MEM) {
3299 w = &hose->mem_resources[0];
3300 msi_region = true;
3301 }
3302
3303 r->start = w->start;
3304 r->end = w->end;
3305
3306 /* The 64KB 32-bits MSI region shouldn't be included in
3307 * the 32-bits bridge window. Otherwise, we can see strange
3308 * issues. One of them is EEH error observed on Garrison.
3309 *
3310 * Exclude top 1MB region which is the minimal alignment of
3311 * 32-bits bridge window.
3312 */
3313 if (msi_region) {
3314 r->end += 0x10000;
3315 r->end -= 0x100000;
3316 }
3317 }
3318}
3319
ccd1c191
GS		 3320static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3321{
3322 struct pci_controller *hose = pci_bus_to_host(bus);
3323 struct pnv_phb *phb = hose->private_data;
3324 struct pci_dev *bridge = bus->self;
3325 struct pnv_ioda_pe *pe;
3326 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3327
40e2a47e
GS		 3328 /* Extend bridge's windows if necessary */
3329 pnv_pci_fixup_bridge_resources(bus, type);
3330
63803c39
GS		 3331 /* The PE for root bus should be realized before any one else */
3332 if (!phb->ioda.root_pe_populated) {
3333 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3334 if (pe) {
3335 phb->ioda.root_pe_idx = pe->pe_number;
3336 phb->ioda.root_pe_populated = true;
3337 }
3338 }
3339
ccd1c191
GS		 3340 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3341 if (list_empty(&bus->devices))
3342 return;
3343
3344 /* Reserve PEs according to used M64 resources */
a25de7af 3345 pnv_ioda_reserve_m64_pe(bus, NULL, all);
ccd1c191
GS		 3346
3347 /*
3348 * Assign PE. We might run here because of partial hotplug.
3349 * For the case, we just pick up the existing PE and should
3350 * not allocate resources again.
3351 */
3352 pe = pnv_ioda_setup_bus_PE(bus, all);
3353 if (!pe)
3354 return;
3355
3356 pnv_ioda_setup_pe_seg(pe);
3357 switch (phb->type) {
3358 case PNV_PHB_IODA1:
3359 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3360 break;
3361 case PNV_PHB_IODA2:
3362 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3363 break;
3364 default:
1f52f176 3365 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
ccd1c191
GS		 3366 __func__, phb->hose->global_number, phb->type);
3367 }
3368}
3369
38274637
YX		 3370static resource_size_t pnv_pci_default_alignment(void)
3371{
3372 return PAGE_SIZE;
3373}
3374
5350ab3f
WY		 3375#ifdef CONFIG_PCI_IOV
3376static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3377 int resno)
3378{
ee8222fe
WY		 3379 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3380 struct pnv_phb *phb = hose->private_data;
5350ab3f 3381 struct pci_dn *pdn = pci_get_pdn(pdev);
7fbe7a93 3382 resource_size_t align;
5350ab3f 3383
7fbe7a93
WY		 3384 /*
3385 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3386 * SR-IOV. While from hardware perspective, the range mapped by M64
3387 * BAR should be size aligned.
3388 *
ee8222fe
WY		 3389 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3390 * powernv-specific hardware restriction is gone. But if just use the
3391 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3392 * in one segment of M64 #15, which introduces the PE conflict between
3393 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3394 * m64_segsize.
3395 *
7fbe7a93
WY		 3396 * This function returns the total IOV BAR size if M64 BAR is in
3397 * Shared PE mode or just VF BAR size if not.
ee8222fe
WY		 3398 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3399 * M64 segment size if IOV BAR size is less.
7fbe7a93 3400 */
5350ab3f 3401 align = pci_iov_resource_size(pdev, resno);
7fbe7a93
WY		 3402 if (!pdn->vfs_expanded)
3403 return align;
ee8222fe
WY		 3404 if (pdn->m64_single_mode)
3405 return max(align, (resource_size_t)phb->ioda.m64_segsize);
5350ab3f 3406
7fbe7a93 3407 return pdn->vfs_expanded * align;
5350ab3f
WY		 3408}
3409#endif /* CONFIG_PCI_IOV */
3410
184cd4a3
BH		 3411/* Prevent enabling devices for which we couldn't properly
3412 * assign a PE
3413 */
8bf6b91a 3414static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
184cd4a3 3415{
db1266c8
GS		 3416 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3417 struct pnv_phb *phb = hose->private_data;
3418 struct pci_dn *pdn;
184cd4a3 3419
db1266c8
GS		 3420 /* The function is probably called while the PEs have
3421 * not be created yet. For example, resource reassignment
3422 * during PCI probe period. We just skip the check if
3423 * PEs isn't ready.
3424 */
3425 if (!phb->initialized)
c88c2a18 3426 return true;
db1266c8 3427
b72c1f65 3428 pdn = pci_get_pdn(dev);
184cd4a3 3429 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
c88c2a18 3430 return false;
db1266c8 3431
c88c2a18 3432 return true;
184cd4a3
BH		 3433}
3434
eb744dac
FB		 3435static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev)
3436{
3437 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3438 struct pnv_phb *phb = hose->private_data;
3439 struct pci_dn *pdn;
3440 struct pnv_ioda_pe *pe;
3441
3442 if (!phb->initialized)
3443 return true;
3444
3445 pdn = pci_get_pdn(dev);
3446 if (!pdn)
3447 return false;
3448
3449 if (pdn->pe_number == IODA_INVALID_PE) {
3450 pe = pnv_ioda_setup_dev_PE(dev);
3451 if (!pe)
3452 return false;
3453 }
3454 return true;
3455}
3456
c5f7700b
GS		 3457static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3458 int num)
3459{
3460 struct pnv_ioda_pe *pe = container_of(table_group,
3461 struct pnv_ioda_pe, table_group);
3462 struct pnv_phb *phb = pe->phb;
3463 unsigned int idx;
3464 long rc;
3465
3466 pe_info(pe, "Removing DMA window #%d\n", num);
3467 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3468 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3469 continue;
3470
3471 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3472 idx, 0, 0ul, 0ul, 0ul);
3473 if (rc != OPAL_SUCCESS) {
3474 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3475 rc, idx);
3476 return rc;
3477 }
3478
3479 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3480 }
3481
3482 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3483 return OPAL_SUCCESS;
3484}
3485
3486static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3487{
3488 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3489 struct iommu_table *tbl = pe->table_group.tables[0];
3490 int64_t rc;
3491
3492 if (!weight)
3493 return;
3494
3495 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3496 if (rc != OPAL_SUCCESS)
3497 return;
3498
a34ab7c3 3499 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
c5f7700b
GS		 3500 if (pe->table_group.group) {
3501 iommu_group_put(pe->table_group.group);
3502 WARN_ON(pe->table_group.group);
3503 }
3504
3505 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
e5afdf9d 3506 iommu_tce_table_put(tbl);
c5f7700b
GS		 3507}
3508
3509static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3510{
3511 struct iommu_table *tbl = pe->table_group.tables[0];
3512 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3513#ifdef CONFIG_IOMMU_API
3514 int64_t rc;
3515#endif
3516
3517 if (!weight)
3518 return;
3519
3520#ifdef CONFIG_IOMMU_API
3521 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3522 if (rc)
1e496391 3523 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
c5f7700b
GS		 3524#endif
3525
3526 pnv_pci_ioda2_set_bypass(pe, false);
3527 if (pe->table_group.group) {
3528 iommu_group_put(pe->table_group.group);
3529 WARN_ON(pe->table_group.group);
3530 }
3531
e5afdf9d 3532 iommu_tce_table_put(tbl);
c5f7700b
GS		 3533}
3534
3535static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3536 unsigned short win,
3537 unsigned int *map)
3538{
3539 struct pnv_phb *phb = pe->phb;
3540 int idx;
3541 int64_t rc;
3542
3543 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3544 if (map[idx] != pe->pe_number)
3545 continue;
3546
3547 if (win == OPAL_M64_WINDOW_TYPE)
3548 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3549 phb->ioda.reserved_pe_idx, win,
3550 idx / PNV_IODA1_M64_SEGS,
3551 idx % PNV_IODA1_M64_SEGS);
3552 else
3553 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3554 phb->ioda.reserved_pe_idx, win, 0, idx);
3555
3556 if (rc != OPAL_SUCCESS)
1e496391 3557 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
c5f7700b
GS		 3558 rc, win, idx);
3559
3560 map[idx] = IODA_INVALID_PE;
3561 }
3562}
3563
3564static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3565{
3566 struct pnv_phb *phb = pe->phb;
3567
3568 if (phb->type == PNV_PHB_IODA1) {
3569 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3570 phb->ioda.io_segmap);
3571 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3572 phb->ioda.m32_segmap);
3573 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3574 phb->ioda.m64_segmap);
3575 } else if (phb->type == PNV_PHB_IODA2) {
3576 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3577 phb->ioda.m32_segmap);
3578 }
3579}
3580
3581static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3582{
3583 struct pnv_phb *phb = pe->phb;
3584 struct pnv_ioda_pe *slave, *tmp;
3585
391677f6 3586 mutex_lock(&phb->ioda.pe_list_mutex);
c5f7700b 3587 list_del(&pe->list);
391677f6
FB		 3588 mutex_unlock(&phb->ioda.pe_list_mutex);
3589
c5f7700b
GS		 3590 switch (phb->type) {
3591 case PNV_PHB_IODA1:
3592 pnv_pci_ioda1_release_pe_dma(pe);
3593 break;
3594 case PNV_PHB_IODA2:
3595 pnv_pci_ioda2_release_pe_dma(pe);
3596 break;
25066f5e
FB		 3597 case PNV_PHB_NPU_OCAPI:
3598 break;
c5f7700b
GS		 3599 default:
3600 WARN_ON(1);
3601 }
3602
3603 pnv_ioda_release_pe_seg(pe);
3604 pnv_ioda_deconfigure_pe(pe->phb, pe);
b314427a
GS		 3605
3606 /* Release slave PEs in the compound PE */
3607 if (pe->flags & PNV_IODA_PE_MASTER) {
3608 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3609 list_del(&slave->list);
3610 pnv_ioda_free_pe(slave);
3611 }
3612 }
3613
6eaed166
GS		 3614 /*
3615 * The PE for root bus can be removed because of hotplug in EEH
3616 * recovery for fenced PHB error. We need to mark the PE dead so
3617 * that it can be populated again in PCI hot add path. The PE
3618 * shouldn't be destroyed as it's the global reserved resource.
3619 */
3620 if (phb->ioda.root_pe_populated &&
3621 phb->ioda.root_pe_idx == pe->pe_number)
3622 phb->ioda.root_pe_populated = false;
3623 else
3624 pnv_ioda_free_pe(pe);
c5f7700b
GS		 3625}
3626
3627static void pnv_pci_release_device(struct pci_dev *pdev)
3628{
3629 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3630 struct pnv_phb *phb = hose->private_data;
3631 struct pci_dn *pdn = pci_get_pdn(pdev);
3632 struct pnv_ioda_pe *pe;
3633
3634 if (pdev->is_virtfn)
3635 return;
3636
3637 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3638 return;
3639
29bf282d
GS		 3640 /*
3641 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3642 * isn't removed and added afterwards in this scenario. We should
3643 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3644 * device count is decreased on removing devices while failing to
3645 * be increased on adding devices. It leads to unbalanced PE's device
3646 * count and eventually make normal PCI hotplug path broken.
3647 */
c5f7700b 3648 pe = &phb->ioda.pe_array[pdn->pe_number];
29bf282d
GS		 3649 pdn->pe_number = IODA_INVALID_PE;
3650
c5f7700b
GS		 3651 WARN_ON(--pe->device_count < 0);
3652 if (pe->device_count == 0)
3653 pnv_ioda_release_pe(pe);
3654}
3655
ab7032e7
AK		 3656static void pnv_npu_disable_device(struct pci_dev *pdev)
3657{
3658 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3659 struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3660
3661 if (eehpe && eeh_ops && eeh_ops->reset)
3662 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3663}
3664
7a8e6bbf 3665static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
73ed148a 3666{
7a8e6bbf
MN		 3667 struct pnv_phb *phb = hose->private_data;
3668
d1a85eee 3669 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
73ed148a
BH		 3670 OPAL_ASSERT_RESET);
3671}
3672
92ae0353 3673static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
cb4224c5
GS		 3674 .dma_dev_setup = pnv_pci_dma_dev_setup,
3675 .dma_bus_setup = pnv_pci_dma_bus_setup,
2d6ad41b 3676 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
cb4224c5
GS		 3677 .setup_msi_irqs = pnv_setup_msi_irqs,
3678 .teardown_msi_irqs = pnv_teardown_msi_irqs,
cb4224c5 3679 .enable_device_hook = pnv_pci_enable_device_hook,
c5f7700b 3680 .release_device = pnv_pci_release_device,
cb4224c5 3681 .window_alignment = pnv_pci_window_alignment,
ccd1c191 3682 .setup_bridge = pnv_pci_setup_bridge,
cb4224c5 3683 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
cb4224c5 3684 .shutdown = pnv_pci_ioda_shutdown,
92ae0353
DA		 3685};
3686
5d2aa710 3687static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
cb4224c5 3688 .dma_dev_setup = pnv_pci_dma_dev_setup,
cb4224c5
GS		 3689 .setup_msi_irqs = pnv_setup_msi_irqs,
3690 .teardown_msi_irqs = pnv_teardown_msi_irqs,
cb4224c5
GS		 3691 .enable_device_hook = pnv_pci_enable_device_hook,
3692 .window_alignment = pnv_pci_window_alignment,
3693 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
cb4224c5 3694 .shutdown = pnv_pci_ioda_shutdown,
ab7032e7 3695 .disable_device = pnv_npu_disable_device,
5d2aa710
AP		 3696};
3697
7f2c39e9 3698static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
eb744dac 3699 .enable_device_hook = pnv_ocapi_enable_device_hook,
25066f5e 3700 .release_device = pnv_pci_release_device,
7f2c39e9
FB		 3701 .window_alignment = pnv_pci_window_alignment,
3702 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3703 .shutdown = pnv_pci_ioda_shutdown,
3704};
3705
e51df2c1
AB		 3706static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3707 u64 hub_id, int ioda_type)
184cd4a3
BH		 3708{
3709 struct pci_controller *hose;
184cd4a3 3710 struct pnv_phb *phb;
2b923ed1
GS		 3711 unsigned long size, m64map_off, m32map_off, pemap_off;
3712 unsigned long iomap_off = 0, dma32map_off = 0;
fd141d1a 3713 struct resource r;
c681b93c 3714 const __be64 *prop64;
3a1a4661 3715 const __be32 *prop32;
f1b7cc3e 3716 int len;
3fa23ff8 3717 unsigned int segno;
184cd4a3
BH		 3718 u64 phb_id;
3719 void *aux;
3720 long rc;
3721
08a45b32
BH		 3722 if (!of_device_is_available(np))
3723 return;
3724
b7c670d6 3725 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
184cd4a3
BH		 3726
3727 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3728 if (!prop64) {
3729 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3730 return;
3731 }
3732 phb_id = be64_to_cpup(prop64);
3733 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3734
7e1c4e27 3735 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
8a7f97b9
MR		 3736 if (!phb)
3737 panic("%s: Failed to allocate %zu bytes\n", __func__,
3738 sizeof(*phb));
58d714ec
GS		 3739
3740 /* Allocate PCI controller */
58d714ec
GS		 3741 phb->hose = hose = pcibios_alloc_controller(np);
3742 if (!phb->hose) {
b7c670d6
RH		 3743 pr_err(" Can't allocate PCI controller for %pOF\n",
3744 np);
e39f223f 3745 memblock_free(__pa(phb), sizeof(struct pnv_phb));
184cd4a3
BH		 3746 return;
3747 }
3748
3749 spin_lock_init(&phb->lock);
f1b7cc3e
GS		 3750 prop32 = of_get_property(np, "bus-range", &len);
3751 if (prop32 && len == 8) {
3a1a4661
BH		 3752 hose->first_busno = be32_to_cpu(prop32[0]);
3753 hose->last_busno = be32_to_cpu(prop32[1]);
f1b7cc3e 3754 } else {
b7c670d6 3755 pr_warn(" Broken <bus-range> on %pOF\n", np);
f1b7cc3e
GS		 3756 hose->first_busno = 0;
3757 hose->last_busno = 0xff;
3758 }
184cd4a3 3759 hose->private_data = phb;
e9cc17d4 3760 phb->hub_id = hub_id;
184cd4a3 3761 phb->opal_id = phb_id;
aa0c033f 3762 phb->type = ioda_type;
781a868f 3763 mutex_init(&phb->ioda.pe_alloc_mutex);
184cd4a3 3764
cee72d5b
BH		 3765 /* Detect specific models for error handling */
3766 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3767 phb->model = PNV_PHB_MODEL_P7IOC;
f3d40c25 3768 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
aa0c033f 3769 phb->model = PNV_PHB_MODEL_PHB3;
5d2aa710
AP		 3770 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3771 phb->model = PNV_PHB_MODEL_NPU;
616badd2
AP		 3772 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3773 phb->model = PNV_PHB_MODEL_NPU2;
cee72d5b
BH		 3774 else
3775 phb->model = PNV_PHB_MODEL_UNKNOWN;
3776
5cb1f8fd
RC		 3777 /* Initialize diagnostic data buffer */
3778 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3779 if (prop32)
3780 phb->diag_data_size = be32_to_cpup(prop32);
3781 else
3782 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3783
7e1c4e27 3784 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
8a7f97b9
MR		 3785 if (!phb->diag_data)
3786 panic("%s: Failed to allocate %u bytes\n", __func__,
3787 phb->diag_data_size);
5cb1f8fd 3788
aa0c033f 3789 /* Parse 32-bit and IO ranges (if any) */
2f1ec02e 3790 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
184cd4a3 3791
aa0c033f 3792 /* Get registers */
fd141d1a
BH		 3793 if (!of_address_to_resource(np, 0, &r)) {
3794 phb->regs_phys = r.start;
3795 phb->regs = ioremap(r.start, resource_size(&r));
3796 if (phb->regs == NULL)
3797 pr_err(" Failed to map registers !\n");
3798 }
577c8c88 3799
184cd4a3 3800 /* Initialize more IODA stuff */
92b8f137 3801 phb->ioda.total_pe_num = 1;
aa0c033f 3802 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
36954dc7 3803 if (prop32)
92b8f137 3804 phb->ioda.total_pe_num = be32_to_cpup(prop32);
36954dc7
GS		 3805 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3806 if (prop32)
92b8f137 3807 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
262af557 3808
c127562a
GS		 3809 /* Invalidate RID to PE# mapping */
3810 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3811 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3812
262af557
GC		 3813 /* Parse 64-bit MMIO range */
3814 pnv_ioda_parse_m64_window(phb);
3815
184cd4a3 3816 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
aa0c033f 3817 /* FW Has already off top 64k of M32 space (MSI space) */
184cd4a3
BH		 3818 phb->ioda.m32_size += 0x10000;
3819
92b8f137 3820 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3fd47f06 3821 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
184cd4a3 3822 phb->ioda.io_size = hose->pci_io_size;
92b8f137 3823 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
184cd4a3
BH		 3824 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3825
2b923ed1
GS		 3826 /* Calculate how many 32-bit TCE segments we have */
3827 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3828 PNV_IODA1_DMA32_SEGSIZE;
3829
c35d2a8c 3830 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
92a86756
AK		 3831 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3832 sizeof(unsigned long));
93289d8c
GS		 3833 m64map_off = size;
3834 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
184cd4a3 3835 m32map_off = size;
92b8f137 3836 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
c35d2a8c
GS		 3837 if (phb->type == PNV_PHB_IODA1) {
3838 iomap_off = size;
92b8f137 3839 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
2b923ed1
GS		 3840 dma32map_off = size;
3841 size += phb->ioda.dma32_count *
3842 sizeof(phb->ioda.dma32_segmap[0]);
c35d2a8c 3843 }
184cd4a3 3844 pemap_off = size;
92b8f137 3845 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
7e1c4e27 3846 aux = memblock_alloc(size, SMP_CACHE_BYTES);
8a7f97b9
MR		 3847 if (!aux)
3848 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
184cd4a3 3849 phb->ioda.pe_alloc = aux;
93289d8c 3850 phb->ioda.m64_segmap = aux + m64map_off;
184cd4a3 3851 phb->ioda.m32_segmap = aux + m32map_off;
93289d8c
GS		 3852 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3853 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3fa23ff8 3854 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
93289d8c 3855 }
3fa23ff8 3856 if (phb->type == PNV_PHB_IODA1) {
c35d2a8c 3857 phb->ioda.io_segmap = aux + iomap_off;
3fa23ff8
GS		 3858 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3859 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
2b923ed1
GS		 3860
3861 phb->ioda.dma32_segmap = aux + dma32map_off;
3862 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3863 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3fa23ff8 3864 }
184cd4a3 3865 phb->ioda.pe_array = aux + pemap_off;
63803c39
GS		 3866
3867 /*
3868 * Choose PE number for root bus, which shouldn't have
3869 * M64 resources consumed by its child devices. To pick
3870 * the PE number adjacent to the reserved one if possible.
3871 */
3872 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3873 if (phb->ioda.reserved_pe_idx == 0) {
3874 phb->ioda.root_pe_idx = 1;
3875 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3876 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3877 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3878 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3879 } else {
3880 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3881 }
184cd4a3
BH		 3882
3883 INIT_LIST_HEAD(&phb->ioda.pe_list);
781a868f 3884 mutex_init(&phb->ioda.pe_list_mutex);
184cd4a3
BH		 3885
3886 /* Calculate how many 32-bit TCE segments we have */
2b923ed1 3887 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
acce971c 3888 PNV_IODA1_DMA32_SEGSIZE;
184cd4a3 3889
aa0c033f 3890#if 0 /* We should really do that ... */
184cd4a3
BH		 3891 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3892 window_type,
3893 window_num,
3894 starting_real_address,
3895 starting_pci_address,
3896 segment_size);
3897#endif
3898
262af557 3899 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
92b8f137 3900 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
262af557
GC		 3901 phb->ioda.m32_size, phb->ioda.m32_segsize);
3902 if (phb->ioda.m64_size)
3903 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3904 phb->ioda.m64_size, phb->ioda.m64_segsize);
3905 if (phb->ioda.io_size)
3906 pr_info(" IO: 0x%x [segment=0x%x]\n",
3907 phb->ioda.io_size, phb->ioda.io_segsize);
3908
184cd4a3 3909
184cd4a3 3910 phb->hose->ops = &pnv_pci_ops;
49dec922
GS		 3911 phb->get_pe_state = pnv_ioda_get_pe_state;
3912 phb->freeze_pe = pnv_ioda_freeze_pe;
3913 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
184cd4a3 3914
184cd4a3
BH		 3915 /* Setup MSI support */
3916 pnv_pci_init_ioda_msis(phb);
3917
c40a4210
GS		 3918 /*
3919 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3920 * to let the PCI core do resource assignment. It's supposed
3921 * that the PCI core will do correct I/O and MMIO alignment
3922 * for the P2P bridge bars so that each PCI bus (excluding
3923 * the child P2P bridges) can form individual PE.
184cd4a3 3924 */
fb446ad0 3925 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
5d2aa710 3926
7f2c39e9
FB		 3927 switch (phb->type) {
3928 case PNV_PHB_NPU_NVLINK:
5d2aa710 3929 hose->controller_ops = pnv_npu_ioda_controller_ops;
7f2c39e9
FB		 3930 break;
3931 case PNV_PHB_NPU_OCAPI:
3932 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3933 break;
3934 default:
f9f83456 3935 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
5d2aa710 3936 hose->controller_ops = pnv_pci_ioda_controller_ops;
f9f83456 3937 }
ad30cb99 3938
38274637
YX		 3939 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3940
6e628c7d 3941#ifdef CONFIG_PCI_IOV
9fc91252 3942 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
5350ab3f 3943 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
988fc3ba
BL		 3944 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3945 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
ad30cb99
ME		 3946#endif
3947
c40a4210 3948 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
184cd4a3
BH		 3949
3950 /* Reset IODA tables to a clean state */
d1a85eee 3951 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
184cd4a3 3952 if (rc)
f2c2cbcc 3953 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
361f2a2a 3954
6060e9ea
AD		 3955 /*
3956 * If we're running in kdump kernel, the previous kernel never
361f2a2a
GS		 3957 * shutdown PCI devices correctly. We already got IODA table
3958 * cleaned out. So we have to issue PHB reset to stop all PCI
45baee14 3959 * transactions from previous kernel. The ppc_pci_reset_phbs
b174b4fb
OH		 3960 * kernel parameter will force this reset too. Additionally,
3961 * if the IODA reset above failed then use a bigger hammer.
3962 * This can happen if we get a PHB fatal error in very early
3963 * boot.
361f2a2a 3964 */
b174b4fb 3965 if (is_kdump_kernel() || pci_reset_phbs || rc) {
361f2a2a 3966 pr_info(" Issue PHB reset ...\n");
cadf364d
GS		 3967 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3968 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
361f2a2a 3969 }
262af557 3970
9e9e8935
GS		 3971 /* Remove M64 resource if we can't configure it successfully */
3972 if (!phb->init_m64 || phb->init_m64(phb))
262af557 3973 hose->mem_resources[1].flags = 0;
aa0c033f
GS		 3974}
3975
67975005 3976void __init pnv_pci_init_ioda2_phb(struct device_node *np)
aa0c033f 3977{
e9cc17d4 3978 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
184cd4a3
BH		 3979}
3980
5d2aa710
AP		 3981void __init pnv_pci_init_npu_phb(struct device_node *np)
3982{
7f2c39e9
FB		 3983 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3984}
3985
3986void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3987{
3988 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
5d2aa710
AP		 3989}
3990
228c2f41
AD		 3991static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3992{
3993 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3994 struct pnv_phb *phb = hose->private_data;
3995
3996 if (!machine_is(powernv))
3997 return;
3998
3999 if (phb->type == PNV_PHB_NPU_OCAPI)
4000 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5d2aa710 4001}
228c2f41 4002DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
5d2aa710 4003
184cd4a3
BH		 4004void __init pnv_pci_init_ioda_hub(struct device_node *np)
4005{
4006 struct device_node *phbn;
c681b93c 4007 const __be64 *prop64;
184cd4a3
BH		 4008 u64 hub_id;
4009
b7c670d6 4010 pr_info("Probing IODA IO-Hub %pOF\n", np);
184cd4a3
BH		 4011
4012 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4013 if (!prop64) {
4014 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4015 return;
4016 }
4017 hub_id = be64_to_cpup(prop64);
4018 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4019
4020 /* Count child PHBs */
4021 for_each_child_of_node(np, phbn) {
4022 /* Look for IODA1 PHBs */
4023 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
e9cc17d4 4024 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
184cd4a3
BH		 4025 }
4026}
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