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61305a96 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Currently supports only P5IOC2 | |
5 | * | |
6 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/init.h> | |
61305a96 BH |
19 | #include <linux/irq.h> |
20 | #include <linux/io.h> | |
c1a2562a | 21 | #include <linux/msi.h> |
4e13c1ac | 22 | #include <linux/iommu.h> |
61305a96 BH |
23 | |
24 | #include <asm/sections.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/prom.h> | |
27 | #include <asm/pci-bridge.h> | |
28 | #include <asm/machdep.h> | |
fb1b55d6 | 29 | #include <asm/msi_bitmap.h> |
61305a96 BH |
30 | #include <asm/ppc-pci.h> |
31 | #include <asm/opal.h> | |
32 | #include <asm/iommu.h> | |
33 | #include <asm/tce.h> | |
f5339277 | 34 | #include <asm/firmware.h> |
be7e7446 GS |
35 | #include <asm/eeh_event.h> |
36 | #include <asm/eeh.h> | |
61305a96 BH |
37 | |
38 | #include "powernv.h" | |
39 | #include "pci.h" | |
40 | ||
82ba129b BH |
41 | /* Delay in usec */ |
42 | #define PCI_RESET_DELAY_US 3000000 | |
61305a96 BH |
43 | |
44 | #define cfg_dbg(fmt...) do { } while(0) | |
45 | //#define cfg_dbg(fmt...) printk(fmt) | |
46 | ||
c1a2562a | 47 | #ifdef CONFIG_PCI_MSI |
c1a2562a BH |
48 | static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) |
49 | { | |
50 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
51 | struct pnv_phb *phb = hose->private_data; | |
52 | struct msi_desc *entry; | |
53 | struct msi_msg msg; | |
fb1b55d6 GS |
54 | int hwirq; |
55 | unsigned int virq; | |
c1a2562a BH |
56 | int rc; |
57 | ||
6b2fd7ef AG |
58 | if (WARN_ON(!phb) || !phb->msi_bmp.bitmap) |
59 | return -ENODEV; | |
60 | ||
36074381 | 61 | if (pdev->no_64bit_msi && !phb->msi32_support) |
c1a2562a BH |
62 | return -ENODEV; |
63 | ||
64 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
65 | if (!entry->msi_attrib.is_64 && !phb->msi32_support) { | |
66 | pr_warn("%s: Supports only 64-bit MSIs\n", | |
67 | pci_name(pdev)); | |
68 | return -ENXIO; | |
69 | } | |
fb1b55d6 GS |
70 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); |
71 | if (hwirq < 0) { | |
c1a2562a BH |
72 | pr_warn("%s: Failed to find a free MSI\n", |
73 | pci_name(pdev)); | |
74 | return -ENOSPC; | |
75 | } | |
fb1b55d6 | 76 | virq = irq_create_mapping(NULL, phb->msi_base + hwirq); |
c1a2562a BH |
77 | if (virq == NO_IRQ) { |
78 | pr_warn("%s: Failed to map MSI to linux irq\n", | |
79 | pci_name(pdev)); | |
fb1b55d6 | 80 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
81 | return -ENOMEM; |
82 | } | |
fb1b55d6 | 83 | rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, |
137436c9 | 84 | virq, entry->msi_attrib.is_64, &msg); |
c1a2562a BH |
85 | if (rc) { |
86 | pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); | |
87 | irq_dispose_mapping(virq); | |
fb1b55d6 | 88 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
89 | return rc; |
90 | } | |
91 | irq_set_msi_desc(virq, entry); | |
83a18912 | 92 | pci_write_msi_msg(virq, &msg); |
c1a2562a BH |
93 | } |
94 | return 0; | |
95 | } | |
96 | ||
97 | static void pnv_teardown_msi_irqs(struct pci_dev *pdev) | |
98 | { | |
99 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
100 | struct pnv_phb *phb = hose->private_data; | |
101 | struct msi_desc *entry; | |
102 | ||
103 | if (WARN_ON(!phb)) | |
104 | return; | |
105 | ||
106 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
107 | if (entry->irq == NO_IRQ) | |
108 | continue; | |
109 | irq_set_msi_desc(entry->irq, NULL); | |
fb1b55d6 GS |
110 | msi_bitmap_free_hwirqs(&phb->msi_bmp, |
111 | virq_to_hw(entry->irq) - phb->msi_base, 1); | |
c1a2562a BH |
112 | irq_dispose_mapping(entry->irq); |
113 | } | |
114 | } | |
115 | #endif /* CONFIG_PCI_MSI */ | |
61305a96 | 116 | |
93aef2a7 GS |
117 | static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, |
118 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 119 | { |
93aef2a7 | 120 | struct OpalIoP7IOCPhbErrorData *data; |
cee72d5b BH |
121 | int i; |
122 | ||
93aef2a7 | 123 | data = (struct OpalIoP7IOCPhbErrorData *)common; |
b34497d1 | 124 | pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", |
f18440fb | 125 | hose->global_number, be32_to_cpu(common->version)); |
93aef2a7 | 126 | |
af87d2fe | 127 | if (data->brdgCtl) |
b34497d1 | 128 | pr_info("brdgCtl: %08x\n", |
f18440fb | 129 | be32_to_cpu(data->brdgCtl)); |
af87d2fe GS |
130 | if (data->portStatusReg || data->rootCmplxStatus || |
131 | data->busAgentStatus) | |
b34497d1 | 132 | pr_info("UtlSts: %08x %08x %08x\n", |
f18440fb GS |
133 | be32_to_cpu(data->portStatusReg), |
134 | be32_to_cpu(data->rootCmplxStatus), | |
135 | be32_to_cpu(data->busAgentStatus)); | |
af87d2fe GS |
136 | if (data->deviceStatus || data->slotStatus || |
137 | data->linkStatus || data->devCmdStatus || | |
138 | data->devSecStatus) | |
b34497d1 | 139 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
f18440fb GS |
140 | be32_to_cpu(data->deviceStatus), |
141 | be32_to_cpu(data->slotStatus), | |
142 | be32_to_cpu(data->linkStatus), | |
143 | be32_to_cpu(data->devCmdStatus), | |
144 | be32_to_cpu(data->devSecStatus)); | |
af87d2fe GS |
145 | if (data->rootErrorStatus || data->uncorrErrorStatus || |
146 | data->corrErrorStatus) | |
b34497d1 | 147 | pr_info("RootErrSts: %08x %08x %08x\n", |
f18440fb GS |
148 | be32_to_cpu(data->rootErrorStatus), |
149 | be32_to_cpu(data->uncorrErrorStatus), | |
150 | be32_to_cpu(data->corrErrorStatus)); | |
af87d2fe GS |
151 | if (data->tlpHdr1 || data->tlpHdr2 || |
152 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 153 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
f18440fb GS |
154 | be32_to_cpu(data->tlpHdr1), |
155 | be32_to_cpu(data->tlpHdr2), | |
156 | be32_to_cpu(data->tlpHdr3), | |
157 | be32_to_cpu(data->tlpHdr4)); | |
af87d2fe GS |
158 | if (data->sourceId || data->errorClass || |
159 | data->correlator) | |
b34497d1 | 160 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
f18440fb GS |
161 | be32_to_cpu(data->sourceId), |
162 | be64_to_cpu(data->errorClass), | |
163 | be64_to_cpu(data->correlator)); | |
af87d2fe | 164 | if (data->p7iocPlssr || data->p7iocCsr) |
b34497d1 | 165 | pr_info("PhbSts: %016llx %016llx\n", |
f18440fb GS |
166 | be64_to_cpu(data->p7iocPlssr), |
167 | be64_to_cpu(data->p7iocCsr)); | |
b34497d1 GS |
168 | if (data->lemFir) |
169 | pr_info("Lem: %016llx %016llx %016llx\n", | |
f18440fb GS |
170 | be64_to_cpu(data->lemFir), |
171 | be64_to_cpu(data->lemErrorMask), | |
172 | be64_to_cpu(data->lemWOF)); | |
b34497d1 GS |
173 | if (data->phbErrorStatus) |
174 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
175 | be64_to_cpu(data->phbErrorStatus), |
176 | be64_to_cpu(data->phbFirstErrorStatus), | |
177 | be64_to_cpu(data->phbErrorLog0), | |
178 | be64_to_cpu(data->phbErrorLog1)); | |
b34497d1 GS |
179 | if (data->mmioErrorStatus) |
180 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
181 | be64_to_cpu(data->mmioErrorStatus), |
182 | be64_to_cpu(data->mmioFirstErrorStatus), | |
183 | be64_to_cpu(data->mmioErrorLog0), | |
184 | be64_to_cpu(data->mmioErrorLog1)); | |
b34497d1 GS |
185 | if (data->dma0ErrorStatus) |
186 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
187 | be64_to_cpu(data->dma0ErrorStatus), |
188 | be64_to_cpu(data->dma0FirstErrorStatus), | |
189 | be64_to_cpu(data->dma0ErrorLog0), | |
190 | be64_to_cpu(data->dma0ErrorLog1)); | |
b34497d1 GS |
191 | if (data->dma1ErrorStatus) |
192 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
193 | be64_to_cpu(data->dma1ErrorStatus), |
194 | be64_to_cpu(data->dma1FirstErrorStatus), | |
195 | be64_to_cpu(data->dma1ErrorLog0), | |
196 | be64_to_cpu(data->dma1ErrorLog1)); | |
cee72d5b BH |
197 | |
198 | for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { | |
199 | if ((data->pestA[i] >> 63) == 0 && | |
200 | (data->pestB[i] >> 63) == 0) | |
201 | continue; | |
93aef2a7 | 202 | |
b34497d1 | 203 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
f18440fb GS |
204 | i, be64_to_cpu(data->pestA[i]), |
205 | be64_to_cpu(data->pestB[i])); | |
cee72d5b BH |
206 | } |
207 | } | |
208 | ||
93aef2a7 GS |
209 | static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, |
210 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 211 | { |
93aef2a7 GS |
212 | struct OpalIoPhb3ErrorData *data; |
213 | int i; | |
214 | ||
215 | data = (struct OpalIoPhb3ErrorData*)common; | |
b34497d1 | 216 | pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", |
ddf0322a | 217 | hose->global_number, be32_to_cpu(common->version)); |
af87d2fe | 218 | if (data->brdgCtl) |
b34497d1 | 219 | pr_info("brdgCtl: %08x\n", |
ddf0322a | 220 | be32_to_cpu(data->brdgCtl)); |
af87d2fe GS |
221 | if (data->portStatusReg || data->rootCmplxStatus || |
222 | data->busAgentStatus) | |
b34497d1 | 223 | pr_info("UtlSts: %08x %08x %08x\n", |
ddf0322a GC |
224 | be32_to_cpu(data->portStatusReg), |
225 | be32_to_cpu(data->rootCmplxStatus), | |
226 | be32_to_cpu(data->busAgentStatus)); | |
af87d2fe GS |
227 | if (data->deviceStatus || data->slotStatus || |
228 | data->linkStatus || data->devCmdStatus || | |
229 | data->devSecStatus) | |
b34497d1 | 230 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
ddf0322a GC |
231 | be32_to_cpu(data->deviceStatus), |
232 | be32_to_cpu(data->slotStatus), | |
233 | be32_to_cpu(data->linkStatus), | |
234 | be32_to_cpu(data->devCmdStatus), | |
235 | be32_to_cpu(data->devSecStatus)); | |
af87d2fe GS |
236 | if (data->rootErrorStatus || data->uncorrErrorStatus || |
237 | data->corrErrorStatus) | |
b34497d1 | 238 | pr_info("RootErrSts: %08x %08x %08x\n", |
ddf0322a GC |
239 | be32_to_cpu(data->rootErrorStatus), |
240 | be32_to_cpu(data->uncorrErrorStatus), | |
241 | be32_to_cpu(data->corrErrorStatus)); | |
af87d2fe GS |
242 | if (data->tlpHdr1 || data->tlpHdr2 || |
243 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 244 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
ddf0322a GC |
245 | be32_to_cpu(data->tlpHdr1), |
246 | be32_to_cpu(data->tlpHdr2), | |
247 | be32_to_cpu(data->tlpHdr3), | |
248 | be32_to_cpu(data->tlpHdr4)); | |
af87d2fe GS |
249 | if (data->sourceId || data->errorClass || |
250 | data->correlator) | |
b34497d1 | 251 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
ddf0322a GC |
252 | be32_to_cpu(data->sourceId), |
253 | be64_to_cpu(data->errorClass), | |
254 | be64_to_cpu(data->correlator)); | |
b34497d1 GS |
255 | if (data->nFir) |
256 | pr_info("nFir: %016llx %016llx %016llx\n", | |
ddf0322a GC |
257 | be64_to_cpu(data->nFir), |
258 | be64_to_cpu(data->nFirMask), | |
259 | be64_to_cpu(data->nFirWOF)); | |
af87d2fe | 260 | if (data->phbPlssr || data->phbCsr) |
b34497d1 | 261 | pr_info("PhbSts: %016llx %016llx\n", |
ddf0322a GC |
262 | be64_to_cpu(data->phbPlssr), |
263 | be64_to_cpu(data->phbCsr)); | |
b34497d1 GS |
264 | if (data->lemFir) |
265 | pr_info("Lem: %016llx %016llx %016llx\n", | |
ddf0322a GC |
266 | be64_to_cpu(data->lemFir), |
267 | be64_to_cpu(data->lemErrorMask), | |
268 | be64_to_cpu(data->lemWOF)); | |
b34497d1 GS |
269 | if (data->phbErrorStatus) |
270 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
271 | be64_to_cpu(data->phbErrorStatus), |
272 | be64_to_cpu(data->phbFirstErrorStatus), | |
273 | be64_to_cpu(data->phbErrorLog0), | |
274 | be64_to_cpu(data->phbErrorLog1)); | |
b34497d1 GS |
275 | if (data->mmioErrorStatus) |
276 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
277 | be64_to_cpu(data->mmioErrorStatus), |
278 | be64_to_cpu(data->mmioFirstErrorStatus), | |
279 | be64_to_cpu(data->mmioErrorLog0), | |
280 | be64_to_cpu(data->mmioErrorLog1)); | |
b34497d1 GS |
281 | if (data->dma0ErrorStatus) |
282 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
283 | be64_to_cpu(data->dma0ErrorStatus), |
284 | be64_to_cpu(data->dma0FirstErrorStatus), | |
285 | be64_to_cpu(data->dma0ErrorLog0), | |
286 | be64_to_cpu(data->dma0ErrorLog1)); | |
b34497d1 GS |
287 | if (data->dma1ErrorStatus) |
288 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
289 | be64_to_cpu(data->dma1ErrorStatus), |
290 | be64_to_cpu(data->dma1FirstErrorStatus), | |
291 | be64_to_cpu(data->dma1ErrorLog0), | |
292 | be64_to_cpu(data->dma1ErrorLog1)); | |
93aef2a7 GS |
293 | |
294 | for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { | |
ddf0322a GC |
295 | if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 && |
296 | (be64_to_cpu(data->pestB[i]) >> 63) == 0) | |
93aef2a7 GS |
297 | continue; |
298 | ||
b34497d1 | 299 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
ddf0322a GC |
300 | i, be64_to_cpu(data->pestA[i]), |
301 | be64_to_cpu(data->pestB[i])); | |
93aef2a7 GS |
302 | } |
303 | } | |
304 | ||
305 | void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, | |
306 | unsigned char *log_buff) | |
307 | { | |
308 | struct OpalIoPhbErrorCommon *common; | |
309 | ||
310 | if (!hose || !log_buff) | |
311 | return; | |
312 | ||
313 | common = (struct OpalIoPhbErrorCommon *)log_buff; | |
ddf0322a | 314 | switch (be32_to_cpu(common->ioType)) { |
93aef2a7 GS |
315 | case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: |
316 | pnv_pci_dump_p7ioc_diag_data(hose, common); | |
317 | break; | |
318 | case OPAL_PHB_ERROR_DATA_TYPE_PHB3: | |
319 | pnv_pci_dump_phb3_diag_data(hose, common); | |
cee72d5b BH |
320 | break; |
321 | default: | |
93aef2a7 | 322 | pr_warn("%s: Unrecognized ioType %d\n", |
ddf0322a | 323 | __func__, be32_to_cpu(common->ioType)); |
cee72d5b BH |
324 | } |
325 | } | |
326 | ||
327 | static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) | |
328 | { | |
329 | unsigned long flags, rc; | |
98fd7002 | 330 | int has_diag, ret = 0; |
cee72d5b BH |
331 | |
332 | spin_lock_irqsave(&phb->lock, flags); | |
333 | ||
98fd7002 | 334 | /* Fetch PHB diag-data */ |
23773230 GS |
335 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, |
336 | PNV_PCI_DIAG_BUF_SIZE); | |
cee72d5b BH |
337 | has_diag = (rc == OPAL_SUCCESS); |
338 | ||
98fd7002 GS |
339 | /* If PHB supports compound PE, to handle it */ |
340 | if (phb->unfreeze_pe) { | |
341 | ret = phb->unfreeze_pe(phb, | |
342 | pe_no, | |
cee72d5b | 343 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
98fd7002 GS |
344 | } else { |
345 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
346 | pe_no, | |
347 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
348 | if (rc) { | |
349 | pr_warn("%s: Failure %ld clearing frozen " | |
350 | "PHB#%x-PE#%x\n", | |
351 | __func__, rc, phb->hose->global_number, | |
352 | pe_no); | |
353 | ret = -EIO; | |
354 | } | |
cee72d5b BH |
355 | } |
356 | ||
98fd7002 GS |
357 | /* |
358 | * For now, let's only display the diag buffer when we fail to clear | |
359 | * the EEH status. We'll do more sensible things later when we have | |
360 | * proper EEH support. We need to make sure we don't pollute ourselves | |
361 | * with the normal errors generated when probing empty slots | |
362 | */ | |
363 | if (has_diag && ret) | |
364 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); | |
365 | ||
cee72d5b BH |
366 | spin_unlock_irqrestore(&phb->lock, flags); |
367 | } | |
368 | ||
3532a741 | 369 | static void pnv_pci_config_check_eeh(struct pci_dn *pdn) |
61305a96 | 370 | { |
3532a741 | 371 | struct pnv_phb *phb = pdn->phb->private_data; |
61305a96 | 372 | u8 fstate; |
3a1a4661 | 373 | __be16 pcierr; |
98fd7002 GS |
374 | int pe_no; |
375 | s64 rc; | |
61305a96 | 376 | |
9bf41be6 GS |
377 | /* |
378 | * Get the PE#. During the PCI probe stage, we might not | |
379 | * setup that yet. So all ER errors should be mapped to | |
36954dc7 | 380 | * reserved PE. |
9bf41be6 | 381 | */ |
3532a741 | 382 | pe_no = pdn->pe_number; |
36954dc7 GS |
383 | if (pe_no == IODA_INVALID_PE) { |
384 | if (phb->type == PNV_PHB_P5IOC2) | |
385 | pe_no = 0; | |
386 | else | |
387 | pe_no = phb->ioda.reserved_pe; | |
388 | } | |
61305a96 | 389 | |
98fd7002 GS |
390 | /* |
391 | * Fetch frozen state. If the PHB support compound PE, | |
392 | * we need handle that case. | |
393 | */ | |
394 | if (phb->get_pe_state) { | |
395 | fstate = phb->get_pe_state(phb, pe_no); | |
396 | } else { | |
397 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
398 | pe_no, | |
399 | &fstate, | |
400 | &pcierr, | |
401 | NULL); | |
402 | if (rc) { | |
403 | pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", | |
404 | __func__, rc, phb->hose->global_number, pe_no); | |
405 | return; | |
406 | } | |
61305a96 | 407 | } |
98fd7002 | 408 | |
9bf41be6 | 409 | cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", |
3532a741 | 410 | (pdn->busno << 8) | (pdn->devfn), pe_no, fstate); |
98fd7002 GS |
411 | |
412 | /* Clear the frozen state if applicable */ | |
413 | if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || | |
414 | fstate == OPAL_EEH_STOPPED_DMA_FREEZE || | |
415 | fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { | |
416 | /* | |
417 | * If PHB supports compound PE, freeze it for | |
418 | * consistency. | |
419 | */ | |
420 | if (phb->freeze_pe) | |
421 | phb->freeze_pe(phb, pe_no); | |
422 | ||
cee72d5b | 423 | pnv_pci_handle_eeh_config(phb, pe_no); |
98fd7002 | 424 | } |
61305a96 BH |
425 | } |
426 | ||
3532a741 | 427 | int pnv_pci_cfg_read(struct pci_dn *pdn, |
9bf41be6 | 428 | int where, int size, u32 *val) |
61305a96 | 429 | { |
9bf41be6 GS |
430 | struct pnv_phb *phb = pdn->phb->private_data; |
431 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 BH |
432 | s64 rc; |
433 | ||
61305a96 BH |
434 | switch (size) { |
435 | case 1: { | |
436 | u8 v8; | |
437 | rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); | |
438 | *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; | |
439 | break; | |
440 | } | |
441 | case 2: { | |
3a1a4661 | 442 | __be16 v16; |
61305a96 BH |
443 | rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, |
444 | &v16); | |
3a1a4661 | 445 | *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; |
61305a96 BH |
446 | break; |
447 | } | |
448 | case 4: { | |
3a1a4661 | 449 | __be32 v32; |
61305a96 | 450 | rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); |
3a1a4661 | 451 | *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; |
61305a96 BH |
452 | break; |
453 | } | |
454 | default: | |
455 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
456 | } | |
d0914f50 | 457 | |
9bf41be6 GS |
458 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
459 | __func__, pdn->busno, pdn->devfn, where, size, *val); | |
61305a96 BH |
460 | return PCIBIOS_SUCCESSFUL; |
461 | } | |
462 | ||
3532a741 | 463 | int pnv_pci_cfg_write(struct pci_dn *pdn, |
9bf41be6 | 464 | int where, int size, u32 val) |
61305a96 | 465 | { |
9bf41be6 GS |
466 | struct pnv_phb *phb = pdn->phb->private_data; |
467 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 | 468 | |
9bf41be6 GS |
469 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
470 | pdn->busno, pdn->devfn, where, size, val); | |
61305a96 BH |
471 | switch (size) { |
472 | case 1: | |
473 | opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); | |
474 | break; | |
475 | case 2: | |
476 | opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); | |
477 | break; | |
478 | case 4: | |
479 | opal_pci_config_write_word(phb->opal_id, bdfn, where, val); | |
480 | break; | |
481 | default: | |
482 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
483 | } | |
be7e7446 | 484 | |
d0914f50 GS |
485 | return PCIBIOS_SUCCESSFUL; |
486 | } | |
487 | ||
488 | #if CONFIG_EEH | |
3532a741 | 489 | static bool pnv_pci_cfg_check(struct pci_dn *pdn) |
d0914f50 GS |
490 | { |
491 | struct eeh_dev *edev = NULL; | |
3532a741 | 492 | struct pnv_phb *phb = pdn->phb->private_data; |
d0914f50 GS |
493 | |
494 | /* EEH not enabled ? */ | |
f5bc6b70 | 495 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) |
d0914f50 | 496 | return true; |
61305a96 | 497 | |
d2b0f6f7 | 498 | /* PE reset or device removed ? */ |
3532a741 | 499 | edev = pdn->edev; |
d2b0f6f7 GS |
500 | if (edev) { |
501 | if (edev->pe && | |
8a6b3710 | 502 | (edev->pe->state & EEH_PE_CFG_BLOCKED)) |
d2b0f6f7 GS |
503 | return false; |
504 | ||
505 | if (edev->mode & EEH_DEV_REMOVED) | |
506 | return false; | |
507 | } | |
d0914f50 GS |
508 | |
509 | return true; | |
510 | } | |
511 | #else | |
3532a741 | 512 | static inline pnv_pci_cfg_check(struct pci_dn *pdn) |
d0914f50 GS |
513 | { |
514 | return true; | |
61305a96 | 515 | } |
d0914f50 | 516 | #endif /* CONFIG_EEH */ |
61305a96 | 517 | |
9bf41be6 GS |
518 | static int pnv_pci_read_config(struct pci_bus *bus, |
519 | unsigned int devfn, | |
520 | int where, int size, u32 *val) | |
521 | { | |
9bf41be6 | 522 | struct pci_dn *pdn; |
d0914f50 | 523 | struct pnv_phb *phb; |
d0914f50 | 524 | int ret; |
9bf41be6 | 525 | |
d0914f50 | 526 | *val = 0xFFFFFFFF; |
3532a741 GS |
527 | pdn = pci_get_pdn_by_devfn(bus, devfn); |
528 | if (!pdn) | |
529 | return PCIBIOS_DEVICE_NOT_FOUND; | |
9bf41be6 | 530 | |
3532a741 | 531 | if (!pnv_pci_cfg_check(pdn)) |
d0914f50 GS |
532 | return PCIBIOS_DEVICE_NOT_FOUND; |
533 | ||
3532a741 GS |
534 | ret = pnv_pci_cfg_read(pdn, where, size, val); |
535 | phb = pdn->phb->private_data; | |
536 | if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { | |
d0914f50 | 537 | if (*val == EEH_IO_ERROR_VALUE(size) && |
3532a741 | 538 | eeh_dev_check_failure(pdn->edev)) |
d0914f50 GS |
539 | return PCIBIOS_DEVICE_NOT_FOUND; |
540 | } else { | |
3532a741 | 541 | pnv_pci_config_check_eeh(pdn); |
d0914f50 | 542 | } |
9bf41be6 | 543 | |
d0914f50 | 544 | return ret; |
9bf41be6 GS |
545 | } |
546 | ||
547 | static int pnv_pci_write_config(struct pci_bus *bus, | |
548 | unsigned int devfn, | |
549 | int where, int size, u32 val) | |
550 | { | |
9bf41be6 | 551 | struct pci_dn *pdn; |
d0914f50 | 552 | struct pnv_phb *phb; |
d0914f50 | 553 | int ret; |
9bf41be6 | 554 | |
3532a741 GS |
555 | pdn = pci_get_pdn_by_devfn(bus, devfn); |
556 | if (!pdn) | |
557 | return PCIBIOS_DEVICE_NOT_FOUND; | |
9bf41be6 | 558 | |
3532a741 | 559 | if (!pnv_pci_cfg_check(pdn)) |
d0914f50 GS |
560 | return PCIBIOS_DEVICE_NOT_FOUND; |
561 | ||
3532a741 GS |
562 | ret = pnv_pci_cfg_write(pdn, where, size, val); |
563 | phb = pdn->phb->private_data; | |
d0914f50 | 564 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) |
3532a741 | 565 | pnv_pci_config_check_eeh(pdn); |
d0914f50 GS |
566 | |
567 | return ret; | |
9bf41be6 GS |
568 | } |
569 | ||
61305a96 | 570 | struct pci_ops pnv_pci_ops = { |
9bf41be6 | 571 | .read = pnv_pci_read_config, |
61305a96 BH |
572 | .write = pnv_pci_write_config, |
573 | }; | |
574 | ||
575 | static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, | |
576 | unsigned long uaddr, enum dma_data_direction direction, | |
8e0a1611 | 577 | struct dma_attrs *attrs, bool rm) |
61305a96 BH |
578 | { |
579 | u64 proto_tce; | |
3a1a4661 | 580 | __be64 *tcep, *tces; |
61305a96 BH |
581 | u64 rpn; |
582 | ||
583 | proto_tce = TCE_PCI_READ; // Read allowed | |
584 | ||
585 | if (direction != DMA_TO_DEVICE) | |
586 | proto_tce |= TCE_PCI_WRITE; | |
587 | ||
5e4da530 | 588 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
bc32057e | 589 | rpn = __pa(uaddr) >> tbl->it_page_shift; |
61305a96 | 590 | |
1f1616e8 | 591 | while (npages--) |
bc32057e AK |
592 | *(tcep++) = cpu_to_be64(proto_tce | |
593 | (rpn++ << tbl->it_page_shift)); | |
1f1616e8 BH |
594 | |
595 | /* Some implementations won't cache invalid TCEs and thus may not | |
596 | * need that flush. We'll probably turn it_type into a bit mask | |
597 | * of flags if that becomes the case | |
598 | */ | |
599 | if (tbl->it_type & TCE_PCI_SWINV_CREATE) | |
8e0a1611 | 600 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
61305a96 | 601 | |
61305a96 BH |
602 | return 0; |
603 | } | |
604 | ||
8e0a1611 AK |
605 | static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages, |
606 | unsigned long uaddr, | |
607 | enum dma_data_direction direction, | |
608 | struct dma_attrs *attrs) | |
609 | { | |
610 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, | |
611 | false); | |
612 | } | |
613 | ||
614 | static void pnv_tce_free(struct iommu_table *tbl, long index, long npages, | |
615 | bool rm) | |
61305a96 | 616 | { |
3a1a4661 | 617 | __be64 *tcep, *tces; |
1f1616e8 | 618 | |
5e4da530 | 619 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
61305a96 BH |
620 | |
621 | while (npages--) | |
3a1a4661 | 622 | *(tcep++) = cpu_to_be64(0); |
1f1616e8 | 623 | |
605e44d6 | 624 | if (tbl->it_type & TCE_PCI_SWINV_FREE) |
8e0a1611 AK |
625 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
626 | } | |
627 | ||
628 | static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages) | |
629 | { | |
630 | pnv_tce_free(tbl, index, npages, false); | |
61305a96 BH |
631 | } |
632 | ||
11f63d3f AK |
633 | static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) |
634 | { | |
635 | return ((u64 *)tbl->it_base)[index - tbl->it_offset]; | |
636 | } | |
637 | ||
8e0a1611 AK |
638 | static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages, |
639 | unsigned long uaddr, | |
640 | enum dma_data_direction direction, | |
641 | struct dma_attrs *attrs) | |
642 | { | |
643 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true); | |
644 | } | |
645 | ||
646 | static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages) | |
647 | { | |
648 | pnv_tce_free(tbl, index, npages, true); | |
649 | } | |
650 | ||
61305a96 BH |
651 | void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
652 | void *tce_mem, u64 tce_size, | |
8fa5d454 | 653 | u64 dma_offset, unsigned page_shift) |
61305a96 BH |
654 | { |
655 | tbl->it_blocksize = 16; | |
656 | tbl->it_base = (unsigned long)tce_mem; | |
8fa5d454 | 657 | tbl->it_page_shift = page_shift; |
3a553170 | 658 | tbl->it_offset = dma_offset >> tbl->it_page_shift; |
61305a96 BH |
659 | tbl->it_index = 0; |
660 | tbl->it_size = tce_size >> 3; | |
661 | tbl->it_busno = 0; | |
662 | tbl->it_type = TCE_PCI; | |
663 | } | |
664 | ||
cad5cef6 | 665 | static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) |
61305a96 BH |
666 | { |
667 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
668 | struct pnv_phb *phb = hose->private_data; | |
781a868f WY |
669 | #ifdef CONFIG_PCI_IOV |
670 | struct pnv_ioda_pe *pe; | |
671 | struct pci_dn *pdn; | |
672 | ||
673 | /* Fix the VF pdn PE number */ | |
674 | if (pdev->is_virtfn) { | |
675 | pdn = pci_get_pdn(pdev); | |
676 | WARN_ON(pdn->pe_number != IODA_INVALID_PE); | |
677 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
678 | if (pe->rid == ((pdev->bus->number << 8) | | |
679 | (pdev->devfn & 0xff))) { | |
680 | pdn->pe_number = pe->pe_number; | |
681 | pe->pdev = pdev; | |
682 | break; | |
683 | } | |
684 | } | |
685 | } | |
686 | #endif /* CONFIG_PCI_IOV */ | |
61305a96 | 687 | |
61305a96 BH |
688 | if (phb && phb->dma_dev_setup) |
689 | phb->dma_dev_setup(phb, pdev); | |
61305a96 BH |
690 | } |
691 | ||
cd15b048 BH |
692 | int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
693 | { | |
694 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
695 | struct pnv_phb *phb = hose->private_data; | |
696 | ||
697 | if (phb && phb->dma_set_mask) | |
698 | return phb->dma_set_mask(phb, pdev, dma_mask); | |
699 | return __dma_set_mask(&pdev->dev, dma_mask); | |
700 | } | |
701 | ||
fe7e85c6 GS |
702 | u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev) |
703 | { | |
704 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
705 | struct pnv_phb *phb = hose->private_data; | |
706 | ||
707 | if (phb && phb->dma_get_required_mask) | |
708 | return phb->dma_get_required_mask(phb, pdev); | |
709 | ||
710 | return __dma_get_required_mask(&pdev->dev); | |
711 | } | |
712 | ||
73ed148a BH |
713 | void pnv_pci_shutdown(void) |
714 | { | |
715 | struct pci_controller *hose; | |
716 | ||
717 | list_for_each_entry(hose, &hose_list, list_node) { | |
718 | struct pnv_phb *phb = hose->private_data; | |
719 | ||
720 | if (phb && phb->shutdown) | |
721 | phb->shutdown(phb); | |
722 | } | |
723 | } | |
724 | ||
aa0c033f | 725 | /* Fixup wrong class code in p7ioc and p8 root complex */ |
cad5cef6 | 726 | static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) |
ca45cfe3 BH |
727 | { |
728 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
729 | } | |
730 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); | |
731 | ||
61305a96 BH |
732 | void __init pnv_pci_init(void) |
733 | { | |
734 | struct device_node *np; | |
646b54f2 | 735 | bool found_ioda = false; |
61305a96 | 736 | |
673c9756 | 737 | pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); |
61305a96 | 738 | |
646b54f2 ME |
739 | /* If we don't have OPAL, eg. in sim, just skip PCI probe */ |
740 | if (!firmware_has_feature(FW_FEATURE_OPAL)) | |
741 | return; | |
184cd4a3 | 742 | |
646b54f2 ME |
743 | /* Look for IODA IO-Hubs. We don't support mixing IODA |
744 | * and p5ioc2 due to the need to change some global | |
745 | * probing flags | |
746 | */ | |
747 | for_each_compatible_node(np, NULL, "ibm,ioda-hub") { | |
748 | pnv_pci_init_ioda_hub(np); | |
749 | found_ioda = true; | |
750 | } | |
61305a96 | 751 | |
646b54f2 ME |
752 | /* Look for p5ioc2 IO-Hubs */ |
753 | if (!found_ioda) | |
754 | for_each_compatible_node(np, NULL, "ibm,p5ioc2") | |
755 | pnv_pci_init_p5ioc2_hub(np); | |
aa0c033f | 756 | |
646b54f2 ME |
757 | /* Look for ioda2 built-in PHB3's */ |
758 | for_each_compatible_node(np, NULL, "ibm,ioda2-phb") | |
759 | pnv_pci_init_ioda2_phb(np); | |
61305a96 BH |
760 | |
761 | /* Setup the linkage between OF nodes and PHBs */ | |
762 | pci_devs_phb_init(); | |
763 | ||
764 | /* Configure IOMMU DMA hooks */ | |
8e0a1611 AK |
765 | ppc_md.tce_build = pnv_tce_build_vm; |
766 | ppc_md.tce_free = pnv_tce_free_vm; | |
767 | ppc_md.tce_build_rm = pnv_tce_build_rm; | |
768 | ppc_md.tce_free_rm = pnv_tce_free_rm; | |
11f63d3f | 769 | ppc_md.tce_get = pnv_tce_get; |
61305a96 | 770 | set_pci_dma_ops(&dma_iommu_ops); |
61305a96 | 771 | } |
d905c5df | 772 | |
b14726c5 | 773 | machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); |
65ebf4b6 DA |
774 | |
775 | struct pci_controller_ops pnv_pci_controller_ops = { | |
776 | .dma_dev_setup = pnv_pci_dma_dev_setup, | |
d6381119 DA |
777 | #ifdef CONFIG_PCI_MSI |
778 | .setup_msi_irqs = pnv_setup_msi_irqs, | |
779 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
780 | #endif | |
65ebf4b6 | 781 | }; |