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61305a96 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Currently supports only P5IOC2 | |
5 | * | |
6 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/init.h> | |
61305a96 BH |
19 | #include <linux/irq.h> |
20 | #include <linux/io.h> | |
c1a2562a | 21 | #include <linux/msi.h> |
4e13c1ac | 22 | #include <linux/iommu.h> |
61305a96 BH |
23 | |
24 | #include <asm/sections.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/prom.h> | |
27 | #include <asm/pci-bridge.h> | |
28 | #include <asm/machdep.h> | |
fb1b55d6 | 29 | #include <asm/msi_bitmap.h> |
61305a96 BH |
30 | #include <asm/ppc-pci.h> |
31 | #include <asm/opal.h> | |
32 | #include <asm/iommu.h> | |
33 | #include <asm/tce.h> | |
f5339277 | 34 | #include <asm/firmware.h> |
be7e7446 GS |
35 | #include <asm/eeh_event.h> |
36 | #include <asm/eeh.h> | |
61305a96 BH |
37 | |
38 | #include "powernv.h" | |
39 | #include "pci.h" | |
40 | ||
82ba129b BH |
41 | /* Delay in usec */ |
42 | #define PCI_RESET_DELAY_US 3000000 | |
61305a96 BH |
43 | |
44 | #define cfg_dbg(fmt...) do { } while(0) | |
45 | //#define cfg_dbg(fmt...) printk(fmt) | |
46 | ||
c1a2562a | 47 | #ifdef CONFIG_PCI_MSI |
92ae0353 | 48 | int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) |
c1a2562a BH |
49 | { |
50 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
51 | struct pnv_phb *phb = hose->private_data; | |
52 | struct msi_desc *entry; | |
53 | struct msi_msg msg; | |
fb1b55d6 GS |
54 | int hwirq; |
55 | unsigned int virq; | |
c1a2562a BH |
56 | int rc; |
57 | ||
6b2fd7ef AG |
58 | if (WARN_ON(!phb) || !phb->msi_bmp.bitmap) |
59 | return -ENODEV; | |
60 | ||
36074381 | 61 | if (pdev->no_64bit_msi && !phb->msi32_support) |
c1a2562a BH |
62 | return -ENODEV; |
63 | ||
2921d179 | 64 | for_each_pci_msi_entry(entry, pdev) { |
c1a2562a BH |
65 | if (!entry->msi_attrib.is_64 && !phb->msi32_support) { |
66 | pr_warn("%s: Supports only 64-bit MSIs\n", | |
67 | pci_name(pdev)); | |
68 | return -ENXIO; | |
69 | } | |
fb1b55d6 GS |
70 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); |
71 | if (hwirq < 0) { | |
c1a2562a BH |
72 | pr_warn("%s: Failed to find a free MSI\n", |
73 | pci_name(pdev)); | |
74 | return -ENOSPC; | |
75 | } | |
fb1b55d6 | 76 | virq = irq_create_mapping(NULL, phb->msi_base + hwirq); |
c1a2562a BH |
77 | if (virq == NO_IRQ) { |
78 | pr_warn("%s: Failed to map MSI to linux irq\n", | |
79 | pci_name(pdev)); | |
fb1b55d6 | 80 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
81 | return -ENOMEM; |
82 | } | |
fb1b55d6 | 83 | rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, |
137436c9 | 84 | virq, entry->msi_attrib.is_64, &msg); |
c1a2562a BH |
85 | if (rc) { |
86 | pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); | |
87 | irq_dispose_mapping(virq); | |
fb1b55d6 | 88 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
89 | return rc; |
90 | } | |
91 | irq_set_msi_desc(virq, entry); | |
83a18912 | 92 | pci_write_msi_msg(virq, &msg); |
c1a2562a BH |
93 | } |
94 | return 0; | |
95 | } | |
96 | ||
92ae0353 | 97 | void pnv_teardown_msi_irqs(struct pci_dev *pdev) |
c1a2562a BH |
98 | { |
99 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
100 | struct pnv_phb *phb = hose->private_data; | |
101 | struct msi_desc *entry; | |
e297c939 | 102 | irq_hw_number_t hwirq; |
c1a2562a BH |
103 | |
104 | if (WARN_ON(!phb)) | |
105 | return; | |
106 | ||
2921d179 | 107 | for_each_pci_msi_entry(entry, pdev) { |
c1a2562a BH |
108 | if (entry->irq == NO_IRQ) |
109 | continue; | |
e297c939 | 110 | hwirq = virq_to_hw(entry->irq); |
c1a2562a | 111 | irq_set_msi_desc(entry->irq, NULL); |
c1a2562a | 112 | irq_dispose_mapping(entry->irq); |
e297c939 | 113 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1); |
c1a2562a BH |
114 | } |
115 | } | |
116 | #endif /* CONFIG_PCI_MSI */ | |
61305a96 | 117 | |
93aef2a7 GS |
118 | static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, |
119 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 120 | { |
93aef2a7 | 121 | struct OpalIoP7IOCPhbErrorData *data; |
cee72d5b BH |
122 | int i; |
123 | ||
93aef2a7 | 124 | data = (struct OpalIoP7IOCPhbErrorData *)common; |
b34497d1 | 125 | pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", |
f18440fb | 126 | hose->global_number, be32_to_cpu(common->version)); |
93aef2a7 | 127 | |
af87d2fe | 128 | if (data->brdgCtl) |
b34497d1 | 129 | pr_info("brdgCtl: %08x\n", |
f18440fb | 130 | be32_to_cpu(data->brdgCtl)); |
af87d2fe GS |
131 | if (data->portStatusReg || data->rootCmplxStatus || |
132 | data->busAgentStatus) | |
b34497d1 | 133 | pr_info("UtlSts: %08x %08x %08x\n", |
f18440fb GS |
134 | be32_to_cpu(data->portStatusReg), |
135 | be32_to_cpu(data->rootCmplxStatus), | |
136 | be32_to_cpu(data->busAgentStatus)); | |
af87d2fe GS |
137 | if (data->deviceStatus || data->slotStatus || |
138 | data->linkStatus || data->devCmdStatus || | |
139 | data->devSecStatus) | |
b34497d1 | 140 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
f18440fb GS |
141 | be32_to_cpu(data->deviceStatus), |
142 | be32_to_cpu(data->slotStatus), | |
143 | be32_to_cpu(data->linkStatus), | |
144 | be32_to_cpu(data->devCmdStatus), | |
145 | be32_to_cpu(data->devSecStatus)); | |
af87d2fe GS |
146 | if (data->rootErrorStatus || data->uncorrErrorStatus || |
147 | data->corrErrorStatus) | |
b34497d1 | 148 | pr_info("RootErrSts: %08x %08x %08x\n", |
f18440fb GS |
149 | be32_to_cpu(data->rootErrorStatus), |
150 | be32_to_cpu(data->uncorrErrorStatus), | |
151 | be32_to_cpu(data->corrErrorStatus)); | |
af87d2fe GS |
152 | if (data->tlpHdr1 || data->tlpHdr2 || |
153 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 154 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
f18440fb GS |
155 | be32_to_cpu(data->tlpHdr1), |
156 | be32_to_cpu(data->tlpHdr2), | |
157 | be32_to_cpu(data->tlpHdr3), | |
158 | be32_to_cpu(data->tlpHdr4)); | |
af87d2fe GS |
159 | if (data->sourceId || data->errorClass || |
160 | data->correlator) | |
b34497d1 | 161 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
f18440fb GS |
162 | be32_to_cpu(data->sourceId), |
163 | be64_to_cpu(data->errorClass), | |
164 | be64_to_cpu(data->correlator)); | |
af87d2fe | 165 | if (data->p7iocPlssr || data->p7iocCsr) |
b34497d1 | 166 | pr_info("PhbSts: %016llx %016llx\n", |
f18440fb GS |
167 | be64_to_cpu(data->p7iocPlssr), |
168 | be64_to_cpu(data->p7iocCsr)); | |
b34497d1 GS |
169 | if (data->lemFir) |
170 | pr_info("Lem: %016llx %016llx %016llx\n", | |
f18440fb GS |
171 | be64_to_cpu(data->lemFir), |
172 | be64_to_cpu(data->lemErrorMask), | |
173 | be64_to_cpu(data->lemWOF)); | |
b34497d1 GS |
174 | if (data->phbErrorStatus) |
175 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
176 | be64_to_cpu(data->phbErrorStatus), |
177 | be64_to_cpu(data->phbFirstErrorStatus), | |
178 | be64_to_cpu(data->phbErrorLog0), | |
179 | be64_to_cpu(data->phbErrorLog1)); | |
b34497d1 GS |
180 | if (data->mmioErrorStatus) |
181 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
182 | be64_to_cpu(data->mmioErrorStatus), |
183 | be64_to_cpu(data->mmioFirstErrorStatus), | |
184 | be64_to_cpu(data->mmioErrorLog0), | |
185 | be64_to_cpu(data->mmioErrorLog1)); | |
b34497d1 GS |
186 | if (data->dma0ErrorStatus) |
187 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
188 | be64_to_cpu(data->dma0ErrorStatus), |
189 | be64_to_cpu(data->dma0FirstErrorStatus), | |
190 | be64_to_cpu(data->dma0ErrorLog0), | |
191 | be64_to_cpu(data->dma0ErrorLog1)); | |
b34497d1 GS |
192 | if (data->dma1ErrorStatus) |
193 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
f18440fb GS |
194 | be64_to_cpu(data->dma1ErrorStatus), |
195 | be64_to_cpu(data->dma1FirstErrorStatus), | |
196 | be64_to_cpu(data->dma1ErrorLog0), | |
197 | be64_to_cpu(data->dma1ErrorLog1)); | |
cee72d5b BH |
198 | |
199 | for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { | |
200 | if ((data->pestA[i] >> 63) == 0 && | |
201 | (data->pestB[i] >> 63) == 0) | |
202 | continue; | |
93aef2a7 | 203 | |
b34497d1 | 204 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
f18440fb GS |
205 | i, be64_to_cpu(data->pestA[i]), |
206 | be64_to_cpu(data->pestB[i])); | |
cee72d5b BH |
207 | } |
208 | } | |
209 | ||
93aef2a7 GS |
210 | static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, |
211 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 212 | { |
93aef2a7 GS |
213 | struct OpalIoPhb3ErrorData *data; |
214 | int i; | |
215 | ||
216 | data = (struct OpalIoPhb3ErrorData*)common; | |
b34497d1 | 217 | pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", |
ddf0322a | 218 | hose->global_number, be32_to_cpu(common->version)); |
af87d2fe | 219 | if (data->brdgCtl) |
b34497d1 | 220 | pr_info("brdgCtl: %08x\n", |
ddf0322a | 221 | be32_to_cpu(data->brdgCtl)); |
af87d2fe GS |
222 | if (data->portStatusReg || data->rootCmplxStatus || |
223 | data->busAgentStatus) | |
b34497d1 | 224 | pr_info("UtlSts: %08x %08x %08x\n", |
ddf0322a GC |
225 | be32_to_cpu(data->portStatusReg), |
226 | be32_to_cpu(data->rootCmplxStatus), | |
227 | be32_to_cpu(data->busAgentStatus)); | |
af87d2fe GS |
228 | if (data->deviceStatus || data->slotStatus || |
229 | data->linkStatus || data->devCmdStatus || | |
230 | data->devSecStatus) | |
b34497d1 | 231 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
ddf0322a GC |
232 | be32_to_cpu(data->deviceStatus), |
233 | be32_to_cpu(data->slotStatus), | |
234 | be32_to_cpu(data->linkStatus), | |
235 | be32_to_cpu(data->devCmdStatus), | |
236 | be32_to_cpu(data->devSecStatus)); | |
af87d2fe GS |
237 | if (data->rootErrorStatus || data->uncorrErrorStatus || |
238 | data->corrErrorStatus) | |
b34497d1 | 239 | pr_info("RootErrSts: %08x %08x %08x\n", |
ddf0322a GC |
240 | be32_to_cpu(data->rootErrorStatus), |
241 | be32_to_cpu(data->uncorrErrorStatus), | |
242 | be32_to_cpu(data->corrErrorStatus)); | |
af87d2fe GS |
243 | if (data->tlpHdr1 || data->tlpHdr2 || |
244 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 245 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
ddf0322a GC |
246 | be32_to_cpu(data->tlpHdr1), |
247 | be32_to_cpu(data->tlpHdr2), | |
248 | be32_to_cpu(data->tlpHdr3), | |
249 | be32_to_cpu(data->tlpHdr4)); | |
af87d2fe GS |
250 | if (data->sourceId || data->errorClass || |
251 | data->correlator) | |
b34497d1 | 252 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
ddf0322a GC |
253 | be32_to_cpu(data->sourceId), |
254 | be64_to_cpu(data->errorClass), | |
255 | be64_to_cpu(data->correlator)); | |
b34497d1 GS |
256 | if (data->nFir) |
257 | pr_info("nFir: %016llx %016llx %016llx\n", | |
ddf0322a GC |
258 | be64_to_cpu(data->nFir), |
259 | be64_to_cpu(data->nFirMask), | |
260 | be64_to_cpu(data->nFirWOF)); | |
af87d2fe | 261 | if (data->phbPlssr || data->phbCsr) |
b34497d1 | 262 | pr_info("PhbSts: %016llx %016llx\n", |
ddf0322a GC |
263 | be64_to_cpu(data->phbPlssr), |
264 | be64_to_cpu(data->phbCsr)); | |
b34497d1 GS |
265 | if (data->lemFir) |
266 | pr_info("Lem: %016llx %016llx %016llx\n", | |
ddf0322a GC |
267 | be64_to_cpu(data->lemFir), |
268 | be64_to_cpu(data->lemErrorMask), | |
269 | be64_to_cpu(data->lemWOF)); | |
b34497d1 GS |
270 | if (data->phbErrorStatus) |
271 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
272 | be64_to_cpu(data->phbErrorStatus), |
273 | be64_to_cpu(data->phbFirstErrorStatus), | |
274 | be64_to_cpu(data->phbErrorLog0), | |
275 | be64_to_cpu(data->phbErrorLog1)); | |
b34497d1 GS |
276 | if (data->mmioErrorStatus) |
277 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
278 | be64_to_cpu(data->mmioErrorStatus), |
279 | be64_to_cpu(data->mmioFirstErrorStatus), | |
280 | be64_to_cpu(data->mmioErrorLog0), | |
281 | be64_to_cpu(data->mmioErrorLog1)); | |
b34497d1 GS |
282 | if (data->dma0ErrorStatus) |
283 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
284 | be64_to_cpu(data->dma0ErrorStatus), |
285 | be64_to_cpu(data->dma0FirstErrorStatus), | |
286 | be64_to_cpu(data->dma0ErrorLog0), | |
287 | be64_to_cpu(data->dma0ErrorLog1)); | |
b34497d1 GS |
288 | if (data->dma1ErrorStatus) |
289 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
290 | be64_to_cpu(data->dma1ErrorStatus), |
291 | be64_to_cpu(data->dma1FirstErrorStatus), | |
292 | be64_to_cpu(data->dma1ErrorLog0), | |
293 | be64_to_cpu(data->dma1ErrorLog1)); | |
93aef2a7 GS |
294 | |
295 | for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { | |
ddf0322a GC |
296 | if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 && |
297 | (be64_to_cpu(data->pestB[i]) >> 63) == 0) | |
93aef2a7 GS |
298 | continue; |
299 | ||
b34497d1 | 300 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
ddf0322a GC |
301 | i, be64_to_cpu(data->pestA[i]), |
302 | be64_to_cpu(data->pestB[i])); | |
93aef2a7 GS |
303 | } |
304 | } | |
305 | ||
306 | void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, | |
307 | unsigned char *log_buff) | |
308 | { | |
309 | struct OpalIoPhbErrorCommon *common; | |
310 | ||
311 | if (!hose || !log_buff) | |
312 | return; | |
313 | ||
314 | common = (struct OpalIoPhbErrorCommon *)log_buff; | |
ddf0322a | 315 | switch (be32_to_cpu(common->ioType)) { |
93aef2a7 GS |
316 | case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: |
317 | pnv_pci_dump_p7ioc_diag_data(hose, common); | |
318 | break; | |
319 | case OPAL_PHB_ERROR_DATA_TYPE_PHB3: | |
320 | pnv_pci_dump_phb3_diag_data(hose, common); | |
cee72d5b BH |
321 | break; |
322 | default: | |
93aef2a7 | 323 | pr_warn("%s: Unrecognized ioType %d\n", |
ddf0322a | 324 | __func__, be32_to_cpu(common->ioType)); |
cee72d5b BH |
325 | } |
326 | } | |
327 | ||
328 | static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) | |
329 | { | |
330 | unsigned long flags, rc; | |
98fd7002 | 331 | int has_diag, ret = 0; |
cee72d5b BH |
332 | |
333 | spin_lock_irqsave(&phb->lock, flags); | |
334 | ||
98fd7002 | 335 | /* Fetch PHB diag-data */ |
23773230 GS |
336 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, |
337 | PNV_PCI_DIAG_BUF_SIZE); | |
cee72d5b BH |
338 | has_diag = (rc == OPAL_SUCCESS); |
339 | ||
98fd7002 GS |
340 | /* If PHB supports compound PE, to handle it */ |
341 | if (phb->unfreeze_pe) { | |
342 | ret = phb->unfreeze_pe(phb, | |
343 | pe_no, | |
cee72d5b | 344 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
98fd7002 GS |
345 | } else { |
346 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
347 | pe_no, | |
348 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
349 | if (rc) { | |
350 | pr_warn("%s: Failure %ld clearing frozen " | |
351 | "PHB#%x-PE#%x\n", | |
352 | __func__, rc, phb->hose->global_number, | |
353 | pe_no); | |
354 | ret = -EIO; | |
355 | } | |
cee72d5b BH |
356 | } |
357 | ||
98fd7002 GS |
358 | /* |
359 | * For now, let's only display the diag buffer when we fail to clear | |
360 | * the EEH status. We'll do more sensible things later when we have | |
361 | * proper EEH support. We need to make sure we don't pollute ourselves | |
362 | * with the normal errors generated when probing empty slots | |
363 | */ | |
364 | if (has_diag && ret) | |
365 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); | |
366 | ||
cee72d5b BH |
367 | spin_unlock_irqrestore(&phb->lock, flags); |
368 | } | |
369 | ||
3532a741 | 370 | static void pnv_pci_config_check_eeh(struct pci_dn *pdn) |
61305a96 | 371 | { |
3532a741 | 372 | struct pnv_phb *phb = pdn->phb->private_data; |
61305a96 | 373 | u8 fstate; |
3a1a4661 | 374 | __be16 pcierr; |
98fd7002 GS |
375 | int pe_no; |
376 | s64 rc; | |
61305a96 | 377 | |
9bf41be6 GS |
378 | /* |
379 | * Get the PE#. During the PCI probe stage, we might not | |
380 | * setup that yet. So all ER errors should be mapped to | |
36954dc7 | 381 | * reserved PE. |
9bf41be6 | 382 | */ |
3532a741 | 383 | pe_no = pdn->pe_number; |
36954dc7 GS |
384 | if (pe_no == IODA_INVALID_PE) { |
385 | if (phb->type == PNV_PHB_P5IOC2) | |
386 | pe_no = 0; | |
387 | else | |
388 | pe_no = phb->ioda.reserved_pe; | |
389 | } | |
61305a96 | 390 | |
98fd7002 GS |
391 | /* |
392 | * Fetch frozen state. If the PHB support compound PE, | |
393 | * we need handle that case. | |
394 | */ | |
395 | if (phb->get_pe_state) { | |
396 | fstate = phb->get_pe_state(phb, pe_no); | |
397 | } else { | |
398 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
399 | pe_no, | |
400 | &fstate, | |
401 | &pcierr, | |
402 | NULL); | |
403 | if (rc) { | |
404 | pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", | |
405 | __func__, rc, phb->hose->global_number, pe_no); | |
406 | return; | |
407 | } | |
61305a96 | 408 | } |
98fd7002 | 409 | |
9bf41be6 | 410 | cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", |
3532a741 | 411 | (pdn->busno << 8) | (pdn->devfn), pe_no, fstate); |
98fd7002 GS |
412 | |
413 | /* Clear the frozen state if applicable */ | |
414 | if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || | |
415 | fstate == OPAL_EEH_STOPPED_DMA_FREEZE || | |
416 | fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { | |
417 | /* | |
418 | * If PHB supports compound PE, freeze it for | |
419 | * consistency. | |
420 | */ | |
421 | if (phb->freeze_pe) | |
422 | phb->freeze_pe(phb, pe_no); | |
423 | ||
cee72d5b | 424 | pnv_pci_handle_eeh_config(phb, pe_no); |
98fd7002 | 425 | } |
61305a96 BH |
426 | } |
427 | ||
3532a741 | 428 | int pnv_pci_cfg_read(struct pci_dn *pdn, |
9bf41be6 | 429 | int where, int size, u32 *val) |
61305a96 | 430 | { |
9bf41be6 GS |
431 | struct pnv_phb *phb = pdn->phb->private_data; |
432 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 BH |
433 | s64 rc; |
434 | ||
61305a96 BH |
435 | switch (size) { |
436 | case 1: { | |
437 | u8 v8; | |
438 | rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); | |
439 | *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; | |
440 | break; | |
441 | } | |
442 | case 2: { | |
3a1a4661 | 443 | __be16 v16; |
61305a96 BH |
444 | rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, |
445 | &v16); | |
3a1a4661 | 446 | *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; |
61305a96 BH |
447 | break; |
448 | } | |
449 | case 4: { | |
3a1a4661 | 450 | __be32 v32; |
61305a96 | 451 | rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); |
3a1a4661 | 452 | *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; |
61305a96 BH |
453 | break; |
454 | } | |
455 | default: | |
456 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
457 | } | |
d0914f50 | 458 | |
9bf41be6 GS |
459 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
460 | __func__, pdn->busno, pdn->devfn, where, size, *val); | |
61305a96 BH |
461 | return PCIBIOS_SUCCESSFUL; |
462 | } | |
463 | ||
3532a741 | 464 | int pnv_pci_cfg_write(struct pci_dn *pdn, |
9bf41be6 | 465 | int where, int size, u32 val) |
61305a96 | 466 | { |
9bf41be6 GS |
467 | struct pnv_phb *phb = pdn->phb->private_data; |
468 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 | 469 | |
9bf41be6 GS |
470 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
471 | pdn->busno, pdn->devfn, where, size, val); | |
61305a96 BH |
472 | switch (size) { |
473 | case 1: | |
474 | opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); | |
475 | break; | |
476 | case 2: | |
477 | opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); | |
478 | break; | |
479 | case 4: | |
480 | opal_pci_config_write_word(phb->opal_id, bdfn, where, val); | |
481 | break; | |
482 | default: | |
483 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
484 | } | |
be7e7446 | 485 | |
d0914f50 GS |
486 | return PCIBIOS_SUCCESSFUL; |
487 | } | |
488 | ||
489 | #if CONFIG_EEH | |
3532a741 | 490 | static bool pnv_pci_cfg_check(struct pci_dn *pdn) |
d0914f50 GS |
491 | { |
492 | struct eeh_dev *edev = NULL; | |
3532a741 | 493 | struct pnv_phb *phb = pdn->phb->private_data; |
d0914f50 GS |
494 | |
495 | /* EEH not enabled ? */ | |
f5bc6b70 | 496 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) |
d0914f50 | 497 | return true; |
61305a96 | 498 | |
d2b0f6f7 | 499 | /* PE reset or device removed ? */ |
3532a741 | 500 | edev = pdn->edev; |
d2b0f6f7 GS |
501 | if (edev) { |
502 | if (edev->pe && | |
8a6b3710 | 503 | (edev->pe->state & EEH_PE_CFG_BLOCKED)) |
d2b0f6f7 GS |
504 | return false; |
505 | ||
506 | if (edev->mode & EEH_DEV_REMOVED) | |
507 | return false; | |
508 | } | |
d0914f50 GS |
509 | |
510 | return true; | |
511 | } | |
512 | #else | |
3532a741 | 513 | static inline pnv_pci_cfg_check(struct pci_dn *pdn) |
d0914f50 GS |
514 | { |
515 | return true; | |
61305a96 | 516 | } |
d0914f50 | 517 | #endif /* CONFIG_EEH */ |
61305a96 | 518 | |
9bf41be6 GS |
519 | static int pnv_pci_read_config(struct pci_bus *bus, |
520 | unsigned int devfn, | |
521 | int where, int size, u32 *val) | |
522 | { | |
9bf41be6 | 523 | struct pci_dn *pdn; |
d0914f50 | 524 | struct pnv_phb *phb; |
d0914f50 | 525 | int ret; |
9bf41be6 | 526 | |
d0914f50 | 527 | *val = 0xFFFFFFFF; |
3532a741 GS |
528 | pdn = pci_get_pdn_by_devfn(bus, devfn); |
529 | if (!pdn) | |
530 | return PCIBIOS_DEVICE_NOT_FOUND; | |
9bf41be6 | 531 | |
3532a741 | 532 | if (!pnv_pci_cfg_check(pdn)) |
d0914f50 GS |
533 | return PCIBIOS_DEVICE_NOT_FOUND; |
534 | ||
3532a741 GS |
535 | ret = pnv_pci_cfg_read(pdn, where, size, val); |
536 | phb = pdn->phb->private_data; | |
537 | if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { | |
d0914f50 | 538 | if (*val == EEH_IO_ERROR_VALUE(size) && |
3532a741 | 539 | eeh_dev_check_failure(pdn->edev)) |
d0914f50 GS |
540 | return PCIBIOS_DEVICE_NOT_FOUND; |
541 | } else { | |
3532a741 | 542 | pnv_pci_config_check_eeh(pdn); |
d0914f50 | 543 | } |
9bf41be6 | 544 | |
d0914f50 | 545 | return ret; |
9bf41be6 GS |
546 | } |
547 | ||
548 | static int pnv_pci_write_config(struct pci_bus *bus, | |
549 | unsigned int devfn, | |
550 | int where, int size, u32 val) | |
551 | { | |
9bf41be6 | 552 | struct pci_dn *pdn; |
d0914f50 | 553 | struct pnv_phb *phb; |
d0914f50 | 554 | int ret; |
9bf41be6 | 555 | |
3532a741 GS |
556 | pdn = pci_get_pdn_by_devfn(bus, devfn); |
557 | if (!pdn) | |
558 | return PCIBIOS_DEVICE_NOT_FOUND; | |
9bf41be6 | 559 | |
3532a741 | 560 | if (!pnv_pci_cfg_check(pdn)) |
d0914f50 GS |
561 | return PCIBIOS_DEVICE_NOT_FOUND; |
562 | ||
3532a741 GS |
563 | ret = pnv_pci_cfg_write(pdn, where, size, val); |
564 | phb = pdn->phb->private_data; | |
d0914f50 | 565 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) |
3532a741 | 566 | pnv_pci_config_check_eeh(pdn); |
d0914f50 GS |
567 | |
568 | return ret; | |
9bf41be6 GS |
569 | } |
570 | ||
61305a96 | 571 | struct pci_ops pnv_pci_ops = { |
9bf41be6 | 572 | .read = pnv_pci_read_config, |
61305a96 BH |
573 | .write = pnv_pci_write_config, |
574 | }; | |
575 | ||
c5bb44ed AK |
576 | static __be64 *pnv_tce(struct iommu_table *tbl, long idx) |
577 | { | |
578 | __be64 *tmp = ((__be64 *)tbl->it_base); | |
bbb845c4 AK |
579 | int level = tbl->it_indirect_levels; |
580 | const long shift = ilog2(tbl->it_level_size); | |
581 | unsigned long mask = (tbl->it_level_size - 1) << (level * shift); | |
582 | ||
583 | while (level) { | |
584 | int n = (idx & mask) >> (level * shift); | |
585 | unsigned long tce = be64_to_cpu(tmp[n]); | |
586 | ||
587 | tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE)); | |
588 | idx &= ~mask; | |
589 | mask >>= shift; | |
590 | --level; | |
591 | } | |
c5bb44ed AK |
592 | |
593 | return tmp + idx; | |
594 | } | |
595 | ||
da004c36 AK |
596 | int pnv_tce_build(struct iommu_table *tbl, long index, long npages, |
597 | unsigned long uaddr, enum dma_data_direction direction, | |
598 | struct dma_attrs *attrs) | |
61305a96 | 599 | { |
10b35b2b | 600 | u64 proto_tce = iommu_direction_to_tce_perm(direction); |
c5bb44ed AK |
601 | u64 rpn = __pa(uaddr) >> tbl->it_page_shift; |
602 | long i; | |
61305a96 | 603 | |
c5bb44ed AK |
604 | for (i = 0; i < npages; i++) { |
605 | unsigned long newtce = proto_tce | | |
606 | ((rpn + i) << tbl->it_page_shift); | |
607 | unsigned long idx = index - tbl->it_offset + i; | |
1f1616e8 | 608 | |
c5bb44ed AK |
609 | *(pnv_tce(tbl, idx)) = cpu_to_be64(newtce); |
610 | } | |
61305a96 | 611 | |
61305a96 BH |
612 | return 0; |
613 | } | |
614 | ||
05c6cfb9 AK |
615 | #ifdef CONFIG_IOMMU_API |
616 | int pnv_tce_xchg(struct iommu_table *tbl, long index, | |
617 | unsigned long *hpa, enum dma_data_direction *direction) | |
618 | { | |
619 | u64 proto_tce = iommu_direction_to_tce_perm(*direction); | |
620 | unsigned long newtce = *hpa | proto_tce, oldtce; | |
621 | unsigned long idx = index - tbl->it_offset; | |
622 | ||
623 | BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl)); | |
624 | ||
625 | oldtce = xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce)); | |
626 | *hpa = be64_to_cpu(oldtce) & ~(TCE_PCI_READ | TCE_PCI_WRITE); | |
627 | *direction = iommu_tce_direction(oldtce); | |
628 | ||
629 | return 0; | |
630 | } | |
631 | #endif | |
632 | ||
da004c36 | 633 | void pnv_tce_free(struct iommu_table *tbl, long index, long npages) |
61305a96 | 634 | { |
c5bb44ed | 635 | long i; |
1f1616e8 | 636 | |
c5bb44ed AK |
637 | for (i = 0; i < npages; i++) { |
638 | unsigned long idx = index - tbl->it_offset + i; | |
61305a96 | 639 | |
c5bb44ed AK |
640 | *(pnv_tce(tbl, idx)) = cpu_to_be64(0); |
641 | } | |
61305a96 BH |
642 | } |
643 | ||
da004c36 | 644 | unsigned long pnv_tce_get(struct iommu_table *tbl, long index) |
11f63d3f | 645 | { |
c5bb44ed | 646 | return *(pnv_tce(tbl, index - tbl->it_offset)); |
11f63d3f AK |
647 | } |
648 | ||
0eaf4def AK |
649 | struct iommu_table *pnv_pci_table_alloc(int nid) |
650 | { | |
651 | struct iommu_table *tbl; | |
652 | ||
653 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, nid); | |
654 | INIT_LIST_HEAD_RCU(&tbl->it_group_list); | |
655 | ||
656 | return tbl; | |
657 | } | |
658 | ||
659 | long pnv_pci_link_table_and_group(int node, int num, | |
660 | struct iommu_table *tbl, | |
661 | struct iommu_table_group *table_group) | |
662 | { | |
663 | struct iommu_table_group_link *tgl = NULL; | |
664 | ||
665 | if (WARN_ON(!tbl || !table_group)) | |
666 | return -EINVAL; | |
667 | ||
668 | tgl = kzalloc_node(sizeof(struct iommu_table_group_link), GFP_KERNEL, | |
669 | node); | |
670 | if (!tgl) | |
671 | return -ENOMEM; | |
672 | ||
673 | tgl->table_group = table_group; | |
674 | list_add_rcu(&tgl->next, &tbl->it_group_list); | |
675 | ||
676 | table_group->tables[num] = tbl; | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | static void pnv_iommu_table_group_link_free(struct rcu_head *head) | |
682 | { | |
683 | struct iommu_table_group_link *tgl = container_of(head, | |
684 | struct iommu_table_group_link, rcu); | |
685 | ||
686 | kfree(tgl); | |
687 | } | |
688 | ||
689 | void pnv_pci_unlink_table_and_group(struct iommu_table *tbl, | |
690 | struct iommu_table_group *table_group) | |
691 | { | |
692 | long i; | |
693 | bool found; | |
694 | struct iommu_table_group_link *tgl; | |
695 | ||
696 | if (!tbl || !table_group) | |
697 | return; | |
698 | ||
699 | /* Remove link to a group from table's list of attached groups */ | |
700 | found = false; | |
701 | list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { | |
702 | if (tgl->table_group == table_group) { | |
703 | list_del_rcu(&tgl->next); | |
704 | call_rcu(&tgl->rcu, pnv_iommu_table_group_link_free); | |
705 | found = true; | |
706 | break; | |
707 | } | |
708 | } | |
709 | if (WARN_ON(!found)) | |
710 | return; | |
711 | ||
712 | /* Clean a pointer to iommu_table in iommu_table_group::tables[] */ | |
713 | found = false; | |
714 | for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) { | |
715 | if (table_group->tables[i] == tbl) { | |
716 | table_group->tables[i] = NULL; | |
717 | found = true; | |
718 | break; | |
719 | } | |
720 | } | |
721 | WARN_ON(!found); | |
722 | } | |
723 | ||
61305a96 BH |
724 | void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
725 | void *tce_mem, u64 tce_size, | |
8fa5d454 | 726 | u64 dma_offset, unsigned page_shift) |
61305a96 BH |
727 | { |
728 | tbl->it_blocksize = 16; | |
729 | tbl->it_base = (unsigned long)tce_mem; | |
8fa5d454 | 730 | tbl->it_page_shift = page_shift; |
3a553170 | 731 | tbl->it_offset = dma_offset >> tbl->it_page_shift; |
61305a96 BH |
732 | tbl->it_index = 0; |
733 | tbl->it_size = tce_size >> 3; | |
734 | tbl->it_busno = 0; | |
735 | tbl->it_type = TCE_PCI; | |
736 | } | |
737 | ||
92ae0353 | 738 | void pnv_pci_dma_dev_setup(struct pci_dev *pdev) |
61305a96 BH |
739 | { |
740 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
741 | struct pnv_phb *phb = hose->private_data; | |
781a868f WY |
742 | #ifdef CONFIG_PCI_IOV |
743 | struct pnv_ioda_pe *pe; | |
744 | struct pci_dn *pdn; | |
745 | ||
746 | /* Fix the VF pdn PE number */ | |
747 | if (pdev->is_virtfn) { | |
748 | pdn = pci_get_pdn(pdev); | |
749 | WARN_ON(pdn->pe_number != IODA_INVALID_PE); | |
750 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { | |
751 | if (pe->rid == ((pdev->bus->number << 8) | | |
752 | (pdev->devfn & 0xff))) { | |
753 | pdn->pe_number = pe->pe_number; | |
754 | pe->pdev = pdev; | |
755 | break; | |
756 | } | |
757 | } | |
758 | } | |
759 | #endif /* CONFIG_PCI_IOV */ | |
61305a96 | 760 | |
61305a96 BH |
761 | if (phb && phb->dma_dev_setup) |
762 | phb->dma_dev_setup(phb, pdev); | |
61305a96 BH |
763 | } |
764 | ||
73ed148a BH |
765 | void pnv_pci_shutdown(void) |
766 | { | |
767 | struct pci_controller *hose; | |
768 | ||
7a8e6bbf MN |
769 | list_for_each_entry(hose, &hose_list, list_node) |
770 | if (hose->controller_ops.shutdown) | |
771 | hose->controller_ops.shutdown(hose); | |
73ed148a BH |
772 | } |
773 | ||
aa0c033f | 774 | /* Fixup wrong class code in p7ioc and p8 root complex */ |
cad5cef6 | 775 | static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) |
ca45cfe3 BH |
776 | { |
777 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
778 | } | |
779 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); | |
780 | ||
61305a96 BH |
781 | void __init pnv_pci_init(void) |
782 | { | |
783 | struct device_node *np; | |
646b54f2 | 784 | bool found_ioda = false; |
61305a96 | 785 | |
673c9756 | 786 | pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); |
61305a96 | 787 | |
646b54f2 ME |
788 | /* If we don't have OPAL, eg. in sim, just skip PCI probe */ |
789 | if (!firmware_has_feature(FW_FEATURE_OPAL)) | |
790 | return; | |
184cd4a3 | 791 | |
646b54f2 ME |
792 | /* Look for IODA IO-Hubs. We don't support mixing IODA |
793 | * and p5ioc2 due to the need to change some global | |
794 | * probing flags | |
795 | */ | |
796 | for_each_compatible_node(np, NULL, "ibm,ioda-hub") { | |
797 | pnv_pci_init_ioda_hub(np); | |
798 | found_ioda = true; | |
799 | } | |
61305a96 | 800 | |
646b54f2 ME |
801 | /* Look for p5ioc2 IO-Hubs */ |
802 | if (!found_ioda) | |
803 | for_each_compatible_node(np, NULL, "ibm,p5ioc2") | |
804 | pnv_pci_init_p5ioc2_hub(np); | |
aa0c033f | 805 | |
646b54f2 ME |
806 | /* Look for ioda2 built-in PHB3's */ |
807 | for_each_compatible_node(np, NULL, "ibm,ioda2-phb") | |
808 | pnv_pci_init_ioda2_phb(np); | |
61305a96 BH |
809 | |
810 | /* Setup the linkage between OF nodes and PHBs */ | |
811 | pci_devs_phb_init(); | |
812 | ||
813 | /* Configure IOMMU DMA hooks */ | |
61305a96 | 814 | set_pci_dma_ops(&dma_iommu_ops); |
61305a96 | 815 | } |
d905c5df | 816 | |
b14726c5 | 817 | machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); |