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61305a96 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Currently supports only P5IOC2 | |
5 | * | |
6 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/io.h> | |
c1a2562a | 22 | #include <linux/msi.h> |
4e13c1ac | 23 | #include <linux/iommu.h> |
61305a96 BH |
24 | |
25 | #include <asm/sections.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/prom.h> | |
28 | #include <asm/pci-bridge.h> | |
29 | #include <asm/machdep.h> | |
fb1b55d6 | 30 | #include <asm/msi_bitmap.h> |
61305a96 BH |
31 | #include <asm/ppc-pci.h> |
32 | #include <asm/opal.h> | |
33 | #include <asm/iommu.h> | |
34 | #include <asm/tce.h> | |
f5339277 | 35 | #include <asm/firmware.h> |
be7e7446 GS |
36 | #include <asm/eeh_event.h> |
37 | #include <asm/eeh.h> | |
61305a96 BH |
38 | |
39 | #include "powernv.h" | |
40 | #include "pci.h" | |
41 | ||
82ba129b BH |
42 | /* Delay in usec */ |
43 | #define PCI_RESET_DELAY_US 3000000 | |
61305a96 BH |
44 | |
45 | #define cfg_dbg(fmt...) do { } while(0) | |
46 | //#define cfg_dbg(fmt...) printk(fmt) | |
47 | ||
c1a2562a BH |
48 | #ifdef CONFIG_PCI_MSI |
49 | static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) | |
50 | { | |
51 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
52 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 BH |
53 | struct pci_dn *pdn = pci_get_pdn(pdev); |
54 | ||
55 | if (pdn && pdn->force_32bit_msi && !phb->msi32_support) | |
56 | return -ENODEV; | |
c1a2562a | 57 | |
fb1b55d6 | 58 | return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV; |
c1a2562a BH |
59 | } |
60 | ||
61 | static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
62 | { | |
63 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
64 | struct pnv_phb *phb = hose->private_data; | |
65 | struct msi_desc *entry; | |
66 | struct msi_msg msg; | |
fb1b55d6 GS |
67 | int hwirq; |
68 | unsigned int virq; | |
c1a2562a BH |
69 | int rc; |
70 | ||
71 | if (WARN_ON(!phb)) | |
72 | return -ENODEV; | |
73 | ||
74 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
75 | if (!entry->msi_attrib.is_64 && !phb->msi32_support) { | |
76 | pr_warn("%s: Supports only 64-bit MSIs\n", | |
77 | pci_name(pdev)); | |
78 | return -ENXIO; | |
79 | } | |
fb1b55d6 GS |
80 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); |
81 | if (hwirq < 0) { | |
c1a2562a BH |
82 | pr_warn("%s: Failed to find a free MSI\n", |
83 | pci_name(pdev)); | |
84 | return -ENOSPC; | |
85 | } | |
fb1b55d6 | 86 | virq = irq_create_mapping(NULL, phb->msi_base + hwirq); |
c1a2562a BH |
87 | if (virq == NO_IRQ) { |
88 | pr_warn("%s: Failed to map MSI to linux irq\n", | |
89 | pci_name(pdev)); | |
fb1b55d6 | 90 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
91 | return -ENOMEM; |
92 | } | |
fb1b55d6 | 93 | rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, |
137436c9 | 94 | virq, entry->msi_attrib.is_64, &msg); |
c1a2562a BH |
95 | if (rc) { |
96 | pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); | |
97 | irq_dispose_mapping(virq); | |
fb1b55d6 | 98 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
99 | return rc; |
100 | } | |
101 | irq_set_msi_desc(virq, entry); | |
102 | write_msi_msg(virq, &msg); | |
103 | } | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void pnv_teardown_msi_irqs(struct pci_dev *pdev) | |
108 | { | |
109 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
110 | struct pnv_phb *phb = hose->private_data; | |
111 | struct msi_desc *entry; | |
112 | ||
113 | if (WARN_ON(!phb)) | |
114 | return; | |
115 | ||
116 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
117 | if (entry->irq == NO_IRQ) | |
118 | continue; | |
119 | irq_set_msi_desc(entry->irq, NULL); | |
fb1b55d6 GS |
120 | msi_bitmap_free_hwirqs(&phb->msi_bmp, |
121 | virq_to_hw(entry->irq) - phb->msi_base, 1); | |
c1a2562a BH |
122 | irq_dispose_mapping(entry->irq); |
123 | } | |
124 | } | |
125 | #endif /* CONFIG_PCI_MSI */ | |
61305a96 | 126 | |
93aef2a7 GS |
127 | static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, |
128 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 129 | { |
93aef2a7 | 130 | struct OpalIoP7IOCPhbErrorData *data; |
cee72d5b BH |
131 | int i; |
132 | ||
93aef2a7 | 133 | data = (struct OpalIoP7IOCPhbErrorData *)common; |
b34497d1 | 134 | pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", |
93aef2a7 GS |
135 | hose->global_number, common->version); |
136 | ||
af87d2fe | 137 | if (data->brdgCtl) |
b34497d1 | 138 | pr_info("brdgCtl: %08x\n", |
af87d2fe GS |
139 | data->brdgCtl); |
140 | if (data->portStatusReg || data->rootCmplxStatus || | |
141 | data->busAgentStatus) | |
b34497d1 | 142 | pr_info("UtlSts: %08x %08x %08x\n", |
af87d2fe GS |
143 | data->portStatusReg, data->rootCmplxStatus, |
144 | data->busAgentStatus); | |
145 | if (data->deviceStatus || data->slotStatus || | |
146 | data->linkStatus || data->devCmdStatus || | |
147 | data->devSecStatus) | |
b34497d1 | 148 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
af87d2fe GS |
149 | data->deviceStatus, data->slotStatus, |
150 | data->linkStatus, data->devCmdStatus, | |
151 | data->devSecStatus); | |
152 | if (data->rootErrorStatus || data->uncorrErrorStatus || | |
153 | data->corrErrorStatus) | |
b34497d1 | 154 | pr_info("RootErrSts: %08x %08x %08x\n", |
af87d2fe GS |
155 | data->rootErrorStatus, data->uncorrErrorStatus, |
156 | data->corrErrorStatus); | |
157 | if (data->tlpHdr1 || data->tlpHdr2 || | |
158 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 159 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
af87d2fe GS |
160 | data->tlpHdr1, data->tlpHdr2, |
161 | data->tlpHdr3, data->tlpHdr4); | |
162 | if (data->sourceId || data->errorClass || | |
163 | data->correlator) | |
b34497d1 | 164 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
af87d2fe GS |
165 | data->sourceId, data->errorClass, |
166 | data->correlator); | |
167 | if (data->p7iocPlssr || data->p7iocCsr) | |
b34497d1 | 168 | pr_info("PhbSts: %016llx %016llx\n", |
af87d2fe | 169 | data->p7iocPlssr, data->p7iocCsr); |
b34497d1 GS |
170 | if (data->lemFir) |
171 | pr_info("Lem: %016llx %016llx %016llx\n", | |
af87d2fe GS |
172 | data->lemFir, data->lemErrorMask, |
173 | data->lemWOF); | |
b34497d1 GS |
174 | if (data->phbErrorStatus) |
175 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
176 | data->phbErrorStatus, data->phbFirstErrorStatus, |
177 | data->phbErrorLog0, data->phbErrorLog1); | |
b34497d1 GS |
178 | if (data->mmioErrorStatus) |
179 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
180 | data->mmioErrorStatus, data->mmioFirstErrorStatus, |
181 | data->mmioErrorLog0, data->mmioErrorLog1); | |
b34497d1 GS |
182 | if (data->dma0ErrorStatus) |
183 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
184 | data->dma0ErrorStatus, data->dma0FirstErrorStatus, |
185 | data->dma0ErrorLog0, data->dma0ErrorLog1); | |
b34497d1 GS |
186 | if (data->dma1ErrorStatus) |
187 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
188 | data->dma1ErrorStatus, data->dma1FirstErrorStatus, |
189 | data->dma1ErrorLog0, data->dma1ErrorLog1); | |
cee72d5b BH |
190 | |
191 | for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { | |
192 | if ((data->pestA[i] >> 63) == 0 && | |
193 | (data->pestB[i] >> 63) == 0) | |
194 | continue; | |
93aef2a7 | 195 | |
b34497d1 | 196 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
af87d2fe | 197 | i, data->pestA[i], data->pestB[i]); |
cee72d5b BH |
198 | } |
199 | } | |
200 | ||
93aef2a7 GS |
201 | static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, |
202 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 203 | { |
93aef2a7 GS |
204 | struct OpalIoPhb3ErrorData *data; |
205 | int i; | |
206 | ||
207 | data = (struct OpalIoPhb3ErrorData*)common; | |
b34497d1 | 208 | pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", |
93aef2a7 | 209 | hose->global_number, common->version); |
af87d2fe | 210 | if (data->brdgCtl) |
b34497d1 | 211 | pr_info("brdgCtl: %08x\n", |
af87d2fe GS |
212 | data->brdgCtl); |
213 | if (data->portStatusReg || data->rootCmplxStatus || | |
214 | data->busAgentStatus) | |
b34497d1 | 215 | pr_info("UtlSts: %08x %08x %08x\n", |
af87d2fe GS |
216 | data->portStatusReg, data->rootCmplxStatus, |
217 | data->busAgentStatus); | |
218 | if (data->deviceStatus || data->slotStatus || | |
219 | data->linkStatus || data->devCmdStatus || | |
220 | data->devSecStatus) | |
b34497d1 | 221 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
af87d2fe GS |
222 | data->deviceStatus, data->slotStatus, |
223 | data->linkStatus, data->devCmdStatus, | |
224 | data->devSecStatus); | |
225 | if (data->rootErrorStatus || data->uncorrErrorStatus || | |
226 | data->corrErrorStatus) | |
b34497d1 | 227 | pr_info("RootErrSts: %08x %08x %08x\n", |
af87d2fe GS |
228 | data->rootErrorStatus, data->uncorrErrorStatus, |
229 | data->corrErrorStatus); | |
230 | if (data->tlpHdr1 || data->tlpHdr2 || | |
231 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 232 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
af87d2fe GS |
233 | data->tlpHdr1, data->tlpHdr2, |
234 | data->tlpHdr3, data->tlpHdr4); | |
235 | if (data->sourceId || data->errorClass || | |
236 | data->correlator) | |
b34497d1 | 237 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
af87d2fe GS |
238 | data->sourceId, data->errorClass, |
239 | data->correlator); | |
b34497d1 GS |
240 | if (data->nFir) |
241 | pr_info("nFir: %016llx %016llx %016llx\n", | |
af87d2fe GS |
242 | data->nFir, data->nFirMask, |
243 | data->nFirWOF); | |
244 | if (data->phbPlssr || data->phbCsr) | |
b34497d1 | 245 | pr_info("PhbSts: %016llx %016llx\n", |
af87d2fe | 246 | data->phbPlssr, data->phbCsr); |
b34497d1 GS |
247 | if (data->lemFir) |
248 | pr_info("Lem: %016llx %016llx %016llx\n", | |
af87d2fe GS |
249 | data->lemFir, data->lemErrorMask, |
250 | data->lemWOF); | |
b34497d1 GS |
251 | if (data->phbErrorStatus) |
252 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
253 | data->phbErrorStatus, data->phbFirstErrorStatus, |
254 | data->phbErrorLog0, data->phbErrorLog1); | |
b34497d1 GS |
255 | if (data->mmioErrorStatus) |
256 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
257 | data->mmioErrorStatus, data->mmioFirstErrorStatus, |
258 | data->mmioErrorLog0, data->mmioErrorLog1); | |
b34497d1 GS |
259 | if (data->dma0ErrorStatus) |
260 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
261 | data->dma0ErrorStatus, data->dma0FirstErrorStatus, |
262 | data->dma0ErrorLog0, data->dma0ErrorLog1); | |
b34497d1 GS |
263 | if (data->dma1ErrorStatus) |
264 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
265 | data->dma1ErrorStatus, data->dma1FirstErrorStatus, |
266 | data->dma1ErrorLog0, data->dma1ErrorLog1); | |
93aef2a7 GS |
267 | |
268 | for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { | |
269 | if ((data->pestA[i] >> 63) == 0 && | |
270 | (data->pestB[i] >> 63) == 0) | |
271 | continue; | |
272 | ||
b34497d1 | 273 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
af87d2fe | 274 | i, data->pestA[i], data->pestB[i]); |
93aef2a7 GS |
275 | } |
276 | } | |
277 | ||
278 | void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, | |
279 | unsigned char *log_buff) | |
280 | { | |
281 | struct OpalIoPhbErrorCommon *common; | |
282 | ||
283 | if (!hose || !log_buff) | |
284 | return; | |
285 | ||
286 | common = (struct OpalIoPhbErrorCommon *)log_buff; | |
287 | switch (common->ioType) { | |
288 | case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: | |
289 | pnv_pci_dump_p7ioc_diag_data(hose, common); | |
290 | break; | |
291 | case OPAL_PHB_ERROR_DATA_TYPE_PHB3: | |
292 | pnv_pci_dump_phb3_diag_data(hose, common); | |
cee72d5b BH |
293 | break; |
294 | default: | |
93aef2a7 GS |
295 | pr_warn("%s: Unrecognized ioType %d\n", |
296 | __func__, common->ioType); | |
cee72d5b BH |
297 | } |
298 | } | |
299 | ||
300 | static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) | |
301 | { | |
302 | unsigned long flags, rc; | |
303 | int has_diag; | |
304 | ||
305 | spin_lock_irqsave(&phb->lock, flags); | |
306 | ||
23773230 GS |
307 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, |
308 | PNV_PCI_DIAG_BUF_SIZE); | |
cee72d5b BH |
309 | has_diag = (rc == OPAL_SUCCESS); |
310 | ||
311 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, | |
312 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
313 | if (rc) { | |
314 | pr_warning("PCI %d: Failed to clear EEH freeze state" | |
315 | " for PE#%d, err %ld\n", | |
316 | phb->hose->global_number, pe_no, rc); | |
317 | ||
318 | /* For now, let's only display the diag buffer when we fail to clear | |
319 | * the EEH status. We'll do more sensible things later when we have | |
320 | * proper EEH support. We need to make sure we don't pollute ourselves | |
321 | * with the normal errors generated when probing empty slots | |
322 | */ | |
323 | if (has_diag) | |
93aef2a7 | 324 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); |
cee72d5b BH |
325 | else |
326 | pr_warning("PCI %d: No diag data available\n", | |
327 | phb->hose->global_number); | |
328 | } | |
329 | ||
330 | spin_unlock_irqrestore(&phb->lock, flags); | |
331 | } | |
332 | ||
9bf41be6 GS |
333 | static void pnv_pci_config_check_eeh(struct pnv_phb *phb, |
334 | struct device_node *dn) | |
61305a96 BH |
335 | { |
336 | s64 rc; | |
337 | u8 fstate; | |
3a1a4661 | 338 | __be16 pcierr; |
61305a96 BH |
339 | u32 pe_no; |
340 | ||
9bf41be6 GS |
341 | /* |
342 | * Get the PE#. During the PCI probe stage, we might not | |
343 | * setup that yet. So all ER errors should be mapped to | |
36954dc7 | 344 | * reserved PE. |
9bf41be6 GS |
345 | */ |
346 | pe_no = PCI_DN(dn)->pe_number; | |
36954dc7 GS |
347 | if (pe_no == IODA_INVALID_PE) { |
348 | if (phb->type == PNV_PHB_P5IOC2) | |
349 | pe_no = 0; | |
350 | else | |
351 | pe_no = phb->ioda.reserved_pe; | |
352 | } | |
61305a96 BH |
353 | |
354 | /* Read freeze status */ | |
355 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr, | |
356 | NULL); | |
357 | if (rc) { | |
9bf41be6 GS |
358 | pr_warning("%s: Can't read EEH status (PE#%d) for " |
359 | "%s, err %lld\n", | |
360 | __func__, pe_no, dn->full_name, rc); | |
61305a96 BH |
361 | return; |
362 | } | |
9bf41be6 GS |
363 | cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", |
364 | (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn), | |
365 | pe_no, fstate); | |
cee72d5b BH |
366 | if (fstate != 0) |
367 | pnv_pci_handle_eeh_config(phb, pe_no); | |
61305a96 BH |
368 | } |
369 | ||
9bf41be6 GS |
370 | int pnv_pci_cfg_read(struct device_node *dn, |
371 | int where, int size, u32 *val) | |
61305a96 | 372 | { |
9bf41be6 GS |
373 | struct pci_dn *pdn = PCI_DN(dn); |
374 | struct pnv_phb *phb = pdn->phb->private_data; | |
375 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 BH |
376 | s64 rc; |
377 | ||
61305a96 BH |
378 | switch (size) { |
379 | case 1: { | |
380 | u8 v8; | |
381 | rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); | |
382 | *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; | |
383 | break; | |
384 | } | |
385 | case 2: { | |
3a1a4661 | 386 | __be16 v16; |
61305a96 BH |
387 | rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, |
388 | &v16); | |
3a1a4661 | 389 | *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; |
61305a96 BH |
390 | break; |
391 | } | |
392 | case 4: { | |
3a1a4661 | 393 | __be32 v32; |
61305a96 | 394 | rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); |
3a1a4661 | 395 | *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; |
61305a96 BH |
396 | break; |
397 | } | |
398 | default: | |
399 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
400 | } | |
d0914f50 | 401 | |
9bf41be6 GS |
402 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
403 | __func__, pdn->busno, pdn->devfn, where, size, *val); | |
61305a96 BH |
404 | return PCIBIOS_SUCCESSFUL; |
405 | } | |
406 | ||
9bf41be6 GS |
407 | int pnv_pci_cfg_write(struct device_node *dn, |
408 | int where, int size, u32 val) | |
61305a96 | 409 | { |
9bf41be6 GS |
410 | struct pci_dn *pdn = PCI_DN(dn); |
411 | struct pnv_phb *phb = pdn->phb->private_data; | |
412 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 | 413 | |
9bf41be6 GS |
414 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
415 | pdn->busno, pdn->devfn, where, size, val); | |
61305a96 BH |
416 | switch (size) { |
417 | case 1: | |
418 | opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); | |
419 | break; | |
420 | case 2: | |
421 | opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); | |
422 | break; | |
423 | case 4: | |
424 | opal_pci_config_write_word(phb->opal_id, bdfn, where, val); | |
425 | break; | |
426 | default: | |
427 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
428 | } | |
be7e7446 | 429 | |
d0914f50 GS |
430 | return PCIBIOS_SUCCESSFUL; |
431 | } | |
432 | ||
433 | #if CONFIG_EEH | |
434 | static bool pnv_pci_cfg_check(struct pci_controller *hose, | |
435 | struct device_node *dn) | |
436 | { | |
437 | struct eeh_dev *edev = NULL; | |
438 | struct pnv_phb *phb = hose->private_data; | |
439 | ||
440 | /* EEH not enabled ? */ | |
f5bc6b70 | 441 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) |
d0914f50 | 442 | return true; |
61305a96 | 443 | |
d0914f50 GS |
444 | /* PE reset ? */ |
445 | edev = of_node_to_eeh_dev(dn); | |
446 | if (edev && edev->pe && | |
447 | (edev->pe->state & EEH_PE_RESET)) | |
448 | return false; | |
449 | ||
450 | return true; | |
451 | } | |
452 | #else | |
453 | static inline pnv_pci_cfg_check(struct pci_controller *hose, | |
454 | struct device_node *dn) | |
455 | { | |
456 | return true; | |
61305a96 | 457 | } |
d0914f50 | 458 | #endif /* CONFIG_EEH */ |
61305a96 | 459 | |
9bf41be6 GS |
460 | static int pnv_pci_read_config(struct pci_bus *bus, |
461 | unsigned int devfn, | |
462 | int where, int size, u32 *val) | |
463 | { | |
464 | struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); | |
465 | struct pci_dn *pdn; | |
d0914f50 GS |
466 | struct pnv_phb *phb; |
467 | bool found = false; | |
468 | int ret; | |
9bf41be6 | 469 | |
d0914f50 | 470 | *val = 0xFFFFFFFF; |
9bf41be6 GS |
471 | for (dn = busdn->child; dn; dn = dn->sibling) { |
472 | pdn = PCI_DN(dn); | |
d0914f50 GS |
473 | if (pdn && pdn->devfn == devfn) { |
474 | phb = pdn->phb->private_data; | |
475 | found = true; | |
476 | break; | |
477 | } | |
9bf41be6 GS |
478 | } |
479 | ||
d0914f50 GS |
480 | if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) |
481 | return PCIBIOS_DEVICE_NOT_FOUND; | |
482 | ||
483 | ret = pnv_pci_cfg_read(dn, where, size, val); | |
484 | if (phb->flags & PNV_PHB_FLAG_EEH) { | |
485 | if (*val == EEH_IO_ERROR_VALUE(size) && | |
486 | eeh_dev_check_failure(of_node_to_eeh_dev(dn))) | |
487 | return PCIBIOS_DEVICE_NOT_FOUND; | |
488 | } else { | |
489 | pnv_pci_config_check_eeh(phb, dn); | |
490 | } | |
9bf41be6 | 491 | |
d0914f50 | 492 | return ret; |
9bf41be6 GS |
493 | } |
494 | ||
495 | static int pnv_pci_write_config(struct pci_bus *bus, | |
496 | unsigned int devfn, | |
497 | int where, int size, u32 val) | |
498 | { | |
499 | struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); | |
500 | struct pci_dn *pdn; | |
d0914f50 GS |
501 | struct pnv_phb *phb; |
502 | bool found = false; | |
503 | int ret; | |
9bf41be6 GS |
504 | |
505 | for (dn = busdn->child; dn; dn = dn->sibling) { | |
506 | pdn = PCI_DN(dn); | |
d0914f50 GS |
507 | if (pdn && pdn->devfn == devfn) { |
508 | phb = pdn->phb->private_data; | |
509 | found = true; | |
510 | break; | |
511 | } | |
9bf41be6 GS |
512 | } |
513 | ||
d0914f50 GS |
514 | if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) |
515 | return PCIBIOS_DEVICE_NOT_FOUND; | |
516 | ||
517 | ret = pnv_pci_cfg_write(dn, where, size, val); | |
518 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) | |
519 | pnv_pci_config_check_eeh(phb, dn); | |
520 | ||
521 | return ret; | |
9bf41be6 GS |
522 | } |
523 | ||
61305a96 | 524 | struct pci_ops pnv_pci_ops = { |
9bf41be6 | 525 | .read = pnv_pci_read_config, |
61305a96 BH |
526 | .write = pnv_pci_write_config, |
527 | }; | |
528 | ||
529 | static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, | |
530 | unsigned long uaddr, enum dma_data_direction direction, | |
8e0a1611 | 531 | struct dma_attrs *attrs, bool rm) |
61305a96 BH |
532 | { |
533 | u64 proto_tce; | |
3a1a4661 | 534 | __be64 *tcep, *tces; |
61305a96 BH |
535 | u64 rpn; |
536 | ||
537 | proto_tce = TCE_PCI_READ; // Read allowed | |
538 | ||
539 | if (direction != DMA_TO_DEVICE) | |
540 | proto_tce |= TCE_PCI_WRITE; | |
541 | ||
5e4da530 | 542 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
1f1616e8 | 543 | rpn = __pa(uaddr) >> TCE_SHIFT; |
61305a96 | 544 | |
1f1616e8 | 545 | while (npages--) |
3a1a4661 | 546 | *(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT)); |
1f1616e8 BH |
547 | |
548 | /* Some implementations won't cache invalid TCEs and thus may not | |
549 | * need that flush. We'll probably turn it_type into a bit mask | |
550 | * of flags if that becomes the case | |
551 | */ | |
552 | if (tbl->it_type & TCE_PCI_SWINV_CREATE) | |
8e0a1611 | 553 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
61305a96 | 554 | |
61305a96 BH |
555 | return 0; |
556 | } | |
557 | ||
8e0a1611 AK |
558 | static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages, |
559 | unsigned long uaddr, | |
560 | enum dma_data_direction direction, | |
561 | struct dma_attrs *attrs) | |
562 | { | |
563 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, | |
564 | false); | |
565 | } | |
566 | ||
567 | static void pnv_tce_free(struct iommu_table *tbl, long index, long npages, | |
568 | bool rm) | |
61305a96 | 569 | { |
3a1a4661 | 570 | __be64 *tcep, *tces; |
1f1616e8 | 571 | |
5e4da530 | 572 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
61305a96 BH |
573 | |
574 | while (npages--) | |
3a1a4661 | 575 | *(tcep++) = cpu_to_be64(0); |
1f1616e8 | 576 | |
605e44d6 | 577 | if (tbl->it_type & TCE_PCI_SWINV_FREE) |
8e0a1611 AK |
578 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
579 | } | |
580 | ||
581 | static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages) | |
582 | { | |
583 | pnv_tce_free(tbl, index, npages, false); | |
61305a96 BH |
584 | } |
585 | ||
11f63d3f AK |
586 | static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) |
587 | { | |
588 | return ((u64 *)tbl->it_base)[index - tbl->it_offset]; | |
589 | } | |
590 | ||
8e0a1611 AK |
591 | static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages, |
592 | unsigned long uaddr, | |
593 | enum dma_data_direction direction, | |
594 | struct dma_attrs *attrs) | |
595 | { | |
596 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true); | |
597 | } | |
598 | ||
599 | static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages) | |
600 | { | |
601 | pnv_tce_free(tbl, index, npages, true); | |
602 | } | |
603 | ||
61305a96 BH |
604 | void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
605 | void *tce_mem, u64 tce_size, | |
606 | u64 dma_offset) | |
607 | { | |
608 | tbl->it_blocksize = 16; | |
609 | tbl->it_base = (unsigned long)tce_mem; | |
3a553170 AP |
610 | tbl->it_page_shift = IOMMU_PAGE_SHIFT_4K; |
611 | tbl->it_offset = dma_offset >> tbl->it_page_shift; | |
61305a96 BH |
612 | tbl->it_index = 0; |
613 | tbl->it_size = tce_size >> 3; | |
614 | tbl->it_busno = 0; | |
615 | tbl->it_type = TCE_PCI; | |
616 | } | |
617 | ||
cad5cef6 | 618 | static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose) |
61305a96 BH |
619 | { |
620 | struct iommu_table *tbl; | |
3a1a4661 BH |
621 | const __be64 *basep, *swinvp; |
622 | const __be32 *sizep; | |
61305a96 BH |
623 | |
624 | basep = of_get_property(hose->dn, "linux,tce-base", NULL); | |
625 | sizep = of_get_property(hose->dn, "linux,tce-size", NULL); | |
626 | if (basep == NULL || sizep == NULL) { | |
1f1616e8 BH |
627 | pr_err("PCI: %s has missing tce entries !\n", |
628 | hose->dn->full_name); | |
61305a96 BH |
629 | return NULL; |
630 | } | |
631 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); | |
632 | if (WARN_ON(!tbl)) | |
633 | return NULL; | |
634 | pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), | |
635 | be32_to_cpup(sizep), 0); | |
636 | iommu_init_table(tbl, hose->node); | |
4e13c1ac | 637 | iommu_register_group(tbl, pci_domain_nr(hose->bus), 0); |
1f1616e8 BH |
638 | |
639 | /* Deal with SW invalidated TCEs when needed (BML way) */ | |
640 | swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info", | |
641 | NULL); | |
642 | if (swinvp) { | |
5e4da530 | 643 | tbl->it_busno = be64_to_cpu(swinvp[1]); |
3a1a4661 | 644 | tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); |
1f1616e8 BH |
645 | tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; |
646 | } | |
61305a96 BH |
647 | return tbl; |
648 | } | |
649 | ||
cad5cef6 GKH |
650 | static void pnv_pci_dma_fallback_setup(struct pci_controller *hose, |
651 | struct pci_dev *pdev) | |
61305a96 BH |
652 | { |
653 | struct device_node *np = pci_bus_to_OF_node(hose->bus); | |
654 | struct pci_dn *pdn; | |
655 | ||
656 | if (np == NULL) | |
657 | return; | |
658 | pdn = PCI_DN(np); | |
659 | if (!pdn->iommu_table) | |
660 | pdn->iommu_table = pnv_pci_setup_bml_iommu(hose); | |
661 | if (!pdn->iommu_table) | |
662 | return; | |
d905c5df | 663 | set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table); |
61305a96 BH |
664 | } |
665 | ||
cad5cef6 | 666 | static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) |
61305a96 BH |
667 | { |
668 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
669 | struct pnv_phb *phb = hose->private_data; | |
670 | ||
671 | /* If we have no phb structure, try to setup a fallback based on | |
672 | * the device-tree (RTAS PCI for example) | |
673 | */ | |
674 | if (phb && phb->dma_dev_setup) | |
675 | phb->dma_dev_setup(phb, pdev); | |
676 | else | |
677 | pnv_pci_dma_fallback_setup(hose, pdev); | |
678 | } | |
679 | ||
cd15b048 BH |
680 | int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
681 | { | |
682 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
683 | struct pnv_phb *phb = hose->private_data; | |
684 | ||
685 | if (phb && phb->dma_set_mask) | |
686 | return phb->dma_set_mask(phb, pdev, dma_mask); | |
687 | return __dma_set_mask(&pdev->dev, dma_mask); | |
688 | } | |
689 | ||
73ed148a BH |
690 | void pnv_pci_shutdown(void) |
691 | { | |
692 | struct pci_controller *hose; | |
693 | ||
694 | list_for_each_entry(hose, &hose_list, list_node) { | |
695 | struct pnv_phb *phb = hose->private_data; | |
696 | ||
697 | if (phb && phb->shutdown) | |
698 | phb->shutdown(phb); | |
699 | } | |
700 | } | |
701 | ||
aa0c033f | 702 | /* Fixup wrong class code in p7ioc and p8 root complex */ |
cad5cef6 | 703 | static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) |
ca45cfe3 BH |
704 | { |
705 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
706 | } | |
707 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); | |
708 | ||
82ba129b BH |
709 | static int pnv_pci_probe_mode(struct pci_bus *bus) |
710 | { | |
711 | struct pci_controller *hose = pci_bus_to_host(bus); | |
712 | const __be64 *tstamp; | |
713 | u64 now, target; | |
714 | ||
715 | ||
716 | /* We hijack this as a way to ensure we have waited long | |
717 | * enough since the reset was lifted on the PCI bus | |
718 | */ | |
719 | if (bus != hose->bus) | |
720 | return PCI_PROBE_NORMAL; | |
721 | tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL); | |
722 | if (!tstamp || !*tstamp) | |
723 | return PCI_PROBE_NORMAL; | |
724 | ||
725 | now = mftb() / tb_ticks_per_usec; | |
726 | target = (be64_to_cpup(tstamp) / tb_ticks_per_usec) | |
727 | + PCI_RESET_DELAY_US; | |
728 | ||
729 | pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n", | |
730 | hose->global_number, target, now); | |
731 | ||
732 | if (now < target) | |
733 | msleep((target - now + 999) / 1000); | |
734 | ||
735 | return PCI_PROBE_NORMAL; | |
736 | } | |
737 | ||
61305a96 BH |
738 | void __init pnv_pci_init(void) |
739 | { | |
740 | struct device_node *np; | |
741 | ||
673c9756 | 742 | pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); |
61305a96 BH |
743 | |
744 | /* OPAL absent, try POPAL first then RTAS detection of PHBs */ | |
745 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { | |
746 | #ifdef CONFIG_PPC_POWERNV_RTAS | |
747 | init_pci_config_tokens(); | |
748 | find_and_init_phbs(); | |
749 | #endif /* CONFIG_PPC_POWERNV_RTAS */ | |
184cd4a3 BH |
750 | } |
751 | /* OPAL is here, do our normal stuff */ | |
752 | else { | |
753 | int found_ioda = 0; | |
754 | ||
755 | /* Look for IODA IO-Hubs. We don't support mixing IODA | |
756 | * and p5ioc2 due to the need to change some global | |
757 | * probing flags | |
758 | */ | |
759 | for_each_compatible_node(np, NULL, "ibm,ioda-hub") { | |
760 | pnv_pci_init_ioda_hub(np); | |
761 | found_ioda = 1; | |
762 | } | |
61305a96 BH |
763 | |
764 | /* Look for p5ioc2 IO-Hubs */ | |
184cd4a3 BH |
765 | if (!found_ioda) |
766 | for_each_compatible_node(np, NULL, "ibm,p5ioc2") | |
767 | pnv_pci_init_p5ioc2_hub(np); | |
aa0c033f GS |
768 | |
769 | /* Look for ioda2 built-in PHB3's */ | |
770 | for_each_compatible_node(np, NULL, "ibm,ioda2-phb") | |
771 | pnv_pci_init_ioda2_phb(np); | |
61305a96 BH |
772 | } |
773 | ||
774 | /* Setup the linkage between OF nodes and PHBs */ | |
775 | pci_devs_phb_init(); | |
776 | ||
777 | /* Configure IOMMU DMA hooks */ | |
778 | ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup; | |
8e0a1611 AK |
779 | ppc_md.tce_build = pnv_tce_build_vm; |
780 | ppc_md.tce_free = pnv_tce_free_vm; | |
781 | ppc_md.tce_build_rm = pnv_tce_build_rm; | |
782 | ppc_md.tce_free_rm = pnv_tce_free_rm; | |
11f63d3f | 783 | ppc_md.tce_get = pnv_tce_get; |
82ba129b | 784 | ppc_md.pci_probe_mode = pnv_pci_probe_mode; |
61305a96 BH |
785 | set_pci_dma_ops(&dma_iommu_ops); |
786 | ||
c1a2562a BH |
787 | /* Configure MSIs */ |
788 | #ifdef CONFIG_PCI_MSI | |
789 | ppc_md.msi_check_device = pnv_msi_check_device; | |
790 | ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; | |
791 | ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; | |
792 | #endif | |
61305a96 | 793 | } |
d905c5df AK |
794 | |
795 | static int tce_iommu_bus_notifier(struct notifier_block *nb, | |
796 | unsigned long action, void *data) | |
797 | { | |
798 | struct device *dev = data; | |
799 | ||
800 | switch (action) { | |
801 | case BUS_NOTIFY_ADD_DEVICE: | |
802 | return iommu_add_device(dev); | |
803 | case BUS_NOTIFY_DEL_DEVICE: | |
804 | if (dev->iommu_group) | |
805 | iommu_del_device(dev); | |
806 | return 0; | |
807 | default: | |
808 | return 0; | |
809 | } | |
810 | } | |
811 | ||
812 | static struct notifier_block tce_iommu_bus_nb = { | |
813 | .notifier_call = tce_iommu_bus_notifier, | |
814 | }; | |
815 | ||
816 | static int __init tce_iommu_bus_notifier_init(void) | |
817 | { | |
d905c5df AK |
818 | bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb); |
819 | return 0; | |
820 | } | |
821 | ||
822 | subsys_initcall_sync(tce_iommu_bus_notifier_init); |