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61305a96 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Currently supports only P5IOC2 | |
5 | * | |
6 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/io.h> | |
c1a2562a | 22 | #include <linux/msi.h> |
4e13c1ac | 23 | #include <linux/iommu.h> |
61305a96 BH |
24 | |
25 | #include <asm/sections.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/prom.h> | |
28 | #include <asm/pci-bridge.h> | |
29 | #include <asm/machdep.h> | |
fb1b55d6 | 30 | #include <asm/msi_bitmap.h> |
61305a96 BH |
31 | #include <asm/ppc-pci.h> |
32 | #include <asm/opal.h> | |
33 | #include <asm/iommu.h> | |
34 | #include <asm/tce.h> | |
f5339277 | 35 | #include <asm/firmware.h> |
be7e7446 GS |
36 | #include <asm/eeh_event.h> |
37 | #include <asm/eeh.h> | |
61305a96 BH |
38 | |
39 | #include "powernv.h" | |
40 | #include "pci.h" | |
41 | ||
82ba129b BH |
42 | /* Delay in usec */ |
43 | #define PCI_RESET_DELAY_US 3000000 | |
61305a96 BH |
44 | |
45 | #define cfg_dbg(fmt...) do { } while(0) | |
46 | //#define cfg_dbg(fmt...) printk(fmt) | |
47 | ||
c1a2562a BH |
48 | #ifdef CONFIG_PCI_MSI |
49 | static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) | |
50 | { | |
51 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
52 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 BH |
53 | struct pci_dn *pdn = pci_get_pdn(pdev); |
54 | ||
55 | if (pdn && pdn->force_32bit_msi && !phb->msi32_support) | |
56 | return -ENODEV; | |
c1a2562a | 57 | |
fb1b55d6 | 58 | return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV; |
c1a2562a BH |
59 | } |
60 | ||
61 | static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
62 | { | |
63 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
64 | struct pnv_phb *phb = hose->private_data; | |
65 | struct msi_desc *entry; | |
66 | struct msi_msg msg; | |
fb1b55d6 GS |
67 | int hwirq; |
68 | unsigned int virq; | |
c1a2562a BH |
69 | int rc; |
70 | ||
71 | if (WARN_ON(!phb)) | |
72 | return -ENODEV; | |
73 | ||
74 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
75 | if (!entry->msi_attrib.is_64 && !phb->msi32_support) { | |
76 | pr_warn("%s: Supports only 64-bit MSIs\n", | |
77 | pci_name(pdev)); | |
78 | return -ENXIO; | |
79 | } | |
fb1b55d6 GS |
80 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); |
81 | if (hwirq < 0) { | |
c1a2562a BH |
82 | pr_warn("%s: Failed to find a free MSI\n", |
83 | pci_name(pdev)); | |
84 | return -ENOSPC; | |
85 | } | |
fb1b55d6 | 86 | virq = irq_create_mapping(NULL, phb->msi_base + hwirq); |
c1a2562a BH |
87 | if (virq == NO_IRQ) { |
88 | pr_warn("%s: Failed to map MSI to linux irq\n", | |
89 | pci_name(pdev)); | |
fb1b55d6 | 90 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
91 | return -ENOMEM; |
92 | } | |
fb1b55d6 | 93 | rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, |
137436c9 | 94 | virq, entry->msi_attrib.is_64, &msg); |
c1a2562a BH |
95 | if (rc) { |
96 | pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); | |
97 | irq_dispose_mapping(virq); | |
fb1b55d6 | 98 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
99 | return rc; |
100 | } | |
101 | irq_set_msi_desc(virq, entry); | |
102 | write_msi_msg(virq, &msg); | |
103 | } | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void pnv_teardown_msi_irqs(struct pci_dev *pdev) | |
108 | { | |
109 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
110 | struct pnv_phb *phb = hose->private_data; | |
111 | struct msi_desc *entry; | |
112 | ||
113 | if (WARN_ON(!phb)) | |
114 | return; | |
115 | ||
116 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
117 | if (entry->irq == NO_IRQ) | |
118 | continue; | |
119 | irq_set_msi_desc(entry->irq, NULL); | |
fb1b55d6 GS |
120 | msi_bitmap_free_hwirqs(&phb->msi_bmp, |
121 | virq_to_hw(entry->irq) - phb->msi_base, 1); | |
c1a2562a BH |
122 | irq_dispose_mapping(entry->irq); |
123 | } | |
124 | } | |
125 | #endif /* CONFIG_PCI_MSI */ | |
61305a96 | 126 | |
93aef2a7 GS |
127 | static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, |
128 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 129 | { |
93aef2a7 | 130 | struct OpalIoP7IOCPhbErrorData *data; |
cee72d5b BH |
131 | int i; |
132 | ||
93aef2a7 | 133 | data = (struct OpalIoP7IOCPhbErrorData *)common; |
b34497d1 | 134 | pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", |
93aef2a7 GS |
135 | hose->global_number, common->version); |
136 | ||
af87d2fe | 137 | if (data->brdgCtl) |
b34497d1 | 138 | pr_info("brdgCtl: %08x\n", |
af87d2fe GS |
139 | data->brdgCtl); |
140 | if (data->portStatusReg || data->rootCmplxStatus || | |
141 | data->busAgentStatus) | |
b34497d1 | 142 | pr_info("UtlSts: %08x %08x %08x\n", |
af87d2fe GS |
143 | data->portStatusReg, data->rootCmplxStatus, |
144 | data->busAgentStatus); | |
145 | if (data->deviceStatus || data->slotStatus || | |
146 | data->linkStatus || data->devCmdStatus || | |
147 | data->devSecStatus) | |
b34497d1 | 148 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
af87d2fe GS |
149 | data->deviceStatus, data->slotStatus, |
150 | data->linkStatus, data->devCmdStatus, | |
151 | data->devSecStatus); | |
152 | if (data->rootErrorStatus || data->uncorrErrorStatus || | |
153 | data->corrErrorStatus) | |
b34497d1 | 154 | pr_info("RootErrSts: %08x %08x %08x\n", |
af87d2fe GS |
155 | data->rootErrorStatus, data->uncorrErrorStatus, |
156 | data->corrErrorStatus); | |
157 | if (data->tlpHdr1 || data->tlpHdr2 || | |
158 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 159 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
af87d2fe GS |
160 | data->tlpHdr1, data->tlpHdr2, |
161 | data->tlpHdr3, data->tlpHdr4); | |
162 | if (data->sourceId || data->errorClass || | |
163 | data->correlator) | |
b34497d1 | 164 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
af87d2fe GS |
165 | data->sourceId, data->errorClass, |
166 | data->correlator); | |
167 | if (data->p7iocPlssr || data->p7iocCsr) | |
b34497d1 | 168 | pr_info("PhbSts: %016llx %016llx\n", |
af87d2fe | 169 | data->p7iocPlssr, data->p7iocCsr); |
b34497d1 GS |
170 | if (data->lemFir) |
171 | pr_info("Lem: %016llx %016llx %016llx\n", | |
af87d2fe GS |
172 | data->lemFir, data->lemErrorMask, |
173 | data->lemWOF); | |
b34497d1 GS |
174 | if (data->phbErrorStatus) |
175 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
176 | data->phbErrorStatus, data->phbFirstErrorStatus, |
177 | data->phbErrorLog0, data->phbErrorLog1); | |
b34497d1 GS |
178 | if (data->mmioErrorStatus) |
179 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
180 | data->mmioErrorStatus, data->mmioFirstErrorStatus, |
181 | data->mmioErrorLog0, data->mmioErrorLog1); | |
b34497d1 GS |
182 | if (data->dma0ErrorStatus) |
183 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
184 | data->dma0ErrorStatus, data->dma0FirstErrorStatus, |
185 | data->dma0ErrorLog0, data->dma0ErrorLog1); | |
b34497d1 GS |
186 | if (data->dma1ErrorStatus) |
187 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
af87d2fe GS |
188 | data->dma1ErrorStatus, data->dma1FirstErrorStatus, |
189 | data->dma1ErrorLog0, data->dma1ErrorLog1); | |
cee72d5b BH |
190 | |
191 | for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { | |
192 | if ((data->pestA[i] >> 63) == 0 && | |
193 | (data->pestB[i] >> 63) == 0) | |
194 | continue; | |
93aef2a7 | 195 | |
b34497d1 | 196 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
af87d2fe | 197 | i, data->pestA[i], data->pestB[i]); |
cee72d5b BH |
198 | } |
199 | } | |
200 | ||
93aef2a7 GS |
201 | static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, |
202 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 203 | { |
93aef2a7 GS |
204 | struct OpalIoPhb3ErrorData *data; |
205 | int i; | |
206 | ||
207 | data = (struct OpalIoPhb3ErrorData*)common; | |
b34497d1 | 208 | pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", |
ddf0322a | 209 | hose->global_number, be32_to_cpu(common->version)); |
af87d2fe | 210 | if (data->brdgCtl) |
b34497d1 | 211 | pr_info("brdgCtl: %08x\n", |
ddf0322a | 212 | be32_to_cpu(data->brdgCtl)); |
af87d2fe GS |
213 | if (data->portStatusReg || data->rootCmplxStatus || |
214 | data->busAgentStatus) | |
b34497d1 | 215 | pr_info("UtlSts: %08x %08x %08x\n", |
ddf0322a GC |
216 | be32_to_cpu(data->portStatusReg), |
217 | be32_to_cpu(data->rootCmplxStatus), | |
218 | be32_to_cpu(data->busAgentStatus)); | |
af87d2fe GS |
219 | if (data->deviceStatus || data->slotStatus || |
220 | data->linkStatus || data->devCmdStatus || | |
221 | data->devSecStatus) | |
b34497d1 | 222 | pr_info("RootSts: %08x %08x %08x %08x %08x\n", |
ddf0322a GC |
223 | be32_to_cpu(data->deviceStatus), |
224 | be32_to_cpu(data->slotStatus), | |
225 | be32_to_cpu(data->linkStatus), | |
226 | be32_to_cpu(data->devCmdStatus), | |
227 | be32_to_cpu(data->devSecStatus)); | |
af87d2fe GS |
228 | if (data->rootErrorStatus || data->uncorrErrorStatus || |
229 | data->corrErrorStatus) | |
b34497d1 | 230 | pr_info("RootErrSts: %08x %08x %08x\n", |
ddf0322a GC |
231 | be32_to_cpu(data->rootErrorStatus), |
232 | be32_to_cpu(data->uncorrErrorStatus), | |
233 | be32_to_cpu(data->corrErrorStatus)); | |
af87d2fe GS |
234 | if (data->tlpHdr1 || data->tlpHdr2 || |
235 | data->tlpHdr3 || data->tlpHdr4) | |
b34497d1 | 236 | pr_info("RootErrLog: %08x %08x %08x %08x\n", |
ddf0322a GC |
237 | be32_to_cpu(data->tlpHdr1), |
238 | be32_to_cpu(data->tlpHdr2), | |
239 | be32_to_cpu(data->tlpHdr3), | |
240 | be32_to_cpu(data->tlpHdr4)); | |
af87d2fe GS |
241 | if (data->sourceId || data->errorClass || |
242 | data->correlator) | |
b34497d1 | 243 | pr_info("RootErrLog1: %08x %016llx %016llx\n", |
ddf0322a GC |
244 | be32_to_cpu(data->sourceId), |
245 | be64_to_cpu(data->errorClass), | |
246 | be64_to_cpu(data->correlator)); | |
b34497d1 GS |
247 | if (data->nFir) |
248 | pr_info("nFir: %016llx %016llx %016llx\n", | |
ddf0322a GC |
249 | be64_to_cpu(data->nFir), |
250 | be64_to_cpu(data->nFirMask), | |
251 | be64_to_cpu(data->nFirWOF)); | |
af87d2fe | 252 | if (data->phbPlssr || data->phbCsr) |
b34497d1 | 253 | pr_info("PhbSts: %016llx %016llx\n", |
ddf0322a GC |
254 | be64_to_cpu(data->phbPlssr), |
255 | be64_to_cpu(data->phbCsr)); | |
b34497d1 GS |
256 | if (data->lemFir) |
257 | pr_info("Lem: %016llx %016llx %016llx\n", | |
ddf0322a GC |
258 | be64_to_cpu(data->lemFir), |
259 | be64_to_cpu(data->lemErrorMask), | |
260 | be64_to_cpu(data->lemWOF)); | |
b34497d1 GS |
261 | if (data->phbErrorStatus) |
262 | pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
263 | be64_to_cpu(data->phbErrorStatus), |
264 | be64_to_cpu(data->phbFirstErrorStatus), | |
265 | be64_to_cpu(data->phbErrorLog0), | |
266 | be64_to_cpu(data->phbErrorLog1)); | |
b34497d1 GS |
267 | if (data->mmioErrorStatus) |
268 | pr_info("OutErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
269 | be64_to_cpu(data->mmioErrorStatus), |
270 | be64_to_cpu(data->mmioFirstErrorStatus), | |
271 | be64_to_cpu(data->mmioErrorLog0), | |
272 | be64_to_cpu(data->mmioErrorLog1)); | |
b34497d1 GS |
273 | if (data->dma0ErrorStatus) |
274 | pr_info("InAErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
275 | be64_to_cpu(data->dma0ErrorStatus), |
276 | be64_to_cpu(data->dma0FirstErrorStatus), | |
277 | be64_to_cpu(data->dma0ErrorLog0), | |
278 | be64_to_cpu(data->dma0ErrorLog1)); | |
b34497d1 GS |
279 | if (data->dma1ErrorStatus) |
280 | pr_info("InBErr: %016llx %016llx %016llx %016llx\n", | |
ddf0322a GC |
281 | be64_to_cpu(data->dma1ErrorStatus), |
282 | be64_to_cpu(data->dma1FirstErrorStatus), | |
283 | be64_to_cpu(data->dma1ErrorLog0), | |
284 | be64_to_cpu(data->dma1ErrorLog1)); | |
93aef2a7 GS |
285 | |
286 | for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { | |
ddf0322a GC |
287 | if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 && |
288 | (be64_to_cpu(data->pestB[i]) >> 63) == 0) | |
93aef2a7 GS |
289 | continue; |
290 | ||
b34497d1 | 291 | pr_info("PE[%3d] A/B: %016llx %016llx\n", |
ddf0322a GC |
292 | i, be64_to_cpu(data->pestA[i]), |
293 | be64_to_cpu(data->pestB[i])); | |
93aef2a7 GS |
294 | } |
295 | } | |
296 | ||
297 | void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, | |
298 | unsigned char *log_buff) | |
299 | { | |
300 | struct OpalIoPhbErrorCommon *common; | |
301 | ||
302 | if (!hose || !log_buff) | |
303 | return; | |
304 | ||
305 | common = (struct OpalIoPhbErrorCommon *)log_buff; | |
ddf0322a | 306 | switch (be32_to_cpu(common->ioType)) { |
93aef2a7 GS |
307 | case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: |
308 | pnv_pci_dump_p7ioc_diag_data(hose, common); | |
309 | break; | |
310 | case OPAL_PHB_ERROR_DATA_TYPE_PHB3: | |
311 | pnv_pci_dump_phb3_diag_data(hose, common); | |
cee72d5b BH |
312 | break; |
313 | default: | |
93aef2a7 | 314 | pr_warn("%s: Unrecognized ioType %d\n", |
ddf0322a | 315 | __func__, be32_to_cpu(common->ioType)); |
cee72d5b BH |
316 | } |
317 | } | |
318 | ||
319 | static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) | |
320 | { | |
321 | unsigned long flags, rc; | |
322 | int has_diag; | |
323 | ||
324 | spin_lock_irqsave(&phb->lock, flags); | |
325 | ||
23773230 GS |
326 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, |
327 | PNV_PCI_DIAG_BUF_SIZE); | |
cee72d5b BH |
328 | has_diag = (rc == OPAL_SUCCESS); |
329 | ||
330 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, | |
331 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
332 | if (rc) { | |
333 | pr_warning("PCI %d: Failed to clear EEH freeze state" | |
334 | " for PE#%d, err %ld\n", | |
335 | phb->hose->global_number, pe_no, rc); | |
336 | ||
337 | /* For now, let's only display the diag buffer when we fail to clear | |
338 | * the EEH status. We'll do more sensible things later when we have | |
339 | * proper EEH support. We need to make sure we don't pollute ourselves | |
340 | * with the normal errors generated when probing empty slots | |
341 | */ | |
342 | if (has_diag) | |
93aef2a7 | 343 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); |
cee72d5b BH |
344 | else |
345 | pr_warning("PCI %d: No diag data available\n", | |
346 | phb->hose->global_number); | |
347 | } | |
348 | ||
349 | spin_unlock_irqrestore(&phb->lock, flags); | |
350 | } | |
351 | ||
9bf41be6 GS |
352 | static void pnv_pci_config_check_eeh(struct pnv_phb *phb, |
353 | struct device_node *dn) | |
61305a96 BH |
354 | { |
355 | s64 rc; | |
356 | u8 fstate; | |
3a1a4661 | 357 | __be16 pcierr; |
61305a96 BH |
358 | u32 pe_no; |
359 | ||
9bf41be6 GS |
360 | /* |
361 | * Get the PE#. During the PCI probe stage, we might not | |
362 | * setup that yet. So all ER errors should be mapped to | |
36954dc7 | 363 | * reserved PE. |
9bf41be6 GS |
364 | */ |
365 | pe_no = PCI_DN(dn)->pe_number; | |
36954dc7 GS |
366 | if (pe_no == IODA_INVALID_PE) { |
367 | if (phb->type == PNV_PHB_P5IOC2) | |
368 | pe_no = 0; | |
369 | else | |
370 | pe_no = phb->ioda.reserved_pe; | |
371 | } | |
61305a96 BH |
372 | |
373 | /* Read freeze status */ | |
374 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr, | |
375 | NULL); | |
376 | if (rc) { | |
9bf41be6 GS |
377 | pr_warning("%s: Can't read EEH status (PE#%d) for " |
378 | "%s, err %lld\n", | |
379 | __func__, pe_no, dn->full_name, rc); | |
61305a96 BH |
380 | return; |
381 | } | |
9bf41be6 GS |
382 | cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", |
383 | (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn), | |
384 | pe_no, fstate); | |
cee72d5b BH |
385 | if (fstate != 0) |
386 | pnv_pci_handle_eeh_config(phb, pe_no); | |
61305a96 BH |
387 | } |
388 | ||
9bf41be6 GS |
389 | int pnv_pci_cfg_read(struct device_node *dn, |
390 | int where, int size, u32 *val) | |
61305a96 | 391 | { |
9bf41be6 GS |
392 | struct pci_dn *pdn = PCI_DN(dn); |
393 | struct pnv_phb *phb = pdn->phb->private_data; | |
394 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 BH |
395 | s64 rc; |
396 | ||
61305a96 BH |
397 | switch (size) { |
398 | case 1: { | |
399 | u8 v8; | |
400 | rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); | |
401 | *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; | |
402 | break; | |
403 | } | |
404 | case 2: { | |
3a1a4661 | 405 | __be16 v16; |
61305a96 BH |
406 | rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, |
407 | &v16); | |
3a1a4661 | 408 | *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; |
61305a96 BH |
409 | break; |
410 | } | |
411 | case 4: { | |
3a1a4661 | 412 | __be32 v32; |
61305a96 | 413 | rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); |
3a1a4661 | 414 | *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; |
61305a96 BH |
415 | break; |
416 | } | |
417 | default: | |
418 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
419 | } | |
d0914f50 | 420 | |
9bf41be6 GS |
421 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
422 | __func__, pdn->busno, pdn->devfn, where, size, *val); | |
61305a96 BH |
423 | return PCIBIOS_SUCCESSFUL; |
424 | } | |
425 | ||
9bf41be6 GS |
426 | int pnv_pci_cfg_write(struct device_node *dn, |
427 | int where, int size, u32 val) | |
61305a96 | 428 | { |
9bf41be6 GS |
429 | struct pci_dn *pdn = PCI_DN(dn); |
430 | struct pnv_phb *phb = pdn->phb->private_data; | |
431 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 | 432 | |
9bf41be6 GS |
433 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
434 | pdn->busno, pdn->devfn, where, size, val); | |
61305a96 BH |
435 | switch (size) { |
436 | case 1: | |
437 | opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); | |
438 | break; | |
439 | case 2: | |
440 | opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); | |
441 | break; | |
442 | case 4: | |
443 | opal_pci_config_write_word(phb->opal_id, bdfn, where, val); | |
444 | break; | |
445 | default: | |
446 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
447 | } | |
be7e7446 | 448 | |
d0914f50 GS |
449 | return PCIBIOS_SUCCESSFUL; |
450 | } | |
451 | ||
452 | #if CONFIG_EEH | |
453 | static bool pnv_pci_cfg_check(struct pci_controller *hose, | |
454 | struct device_node *dn) | |
455 | { | |
456 | struct eeh_dev *edev = NULL; | |
457 | struct pnv_phb *phb = hose->private_data; | |
458 | ||
459 | /* EEH not enabled ? */ | |
f5bc6b70 | 460 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) |
d0914f50 | 461 | return true; |
61305a96 | 462 | |
d2b0f6f7 | 463 | /* PE reset or device removed ? */ |
d0914f50 | 464 | edev = of_node_to_eeh_dev(dn); |
d2b0f6f7 GS |
465 | if (edev) { |
466 | if (edev->pe && | |
467 | (edev->pe->state & EEH_PE_RESET)) | |
468 | return false; | |
469 | ||
470 | if (edev->mode & EEH_DEV_REMOVED) | |
471 | return false; | |
472 | } | |
d0914f50 GS |
473 | |
474 | return true; | |
475 | } | |
476 | #else | |
477 | static inline pnv_pci_cfg_check(struct pci_controller *hose, | |
478 | struct device_node *dn) | |
479 | { | |
480 | return true; | |
61305a96 | 481 | } |
d0914f50 | 482 | #endif /* CONFIG_EEH */ |
61305a96 | 483 | |
9bf41be6 GS |
484 | static int pnv_pci_read_config(struct pci_bus *bus, |
485 | unsigned int devfn, | |
486 | int where, int size, u32 *val) | |
487 | { | |
488 | struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); | |
489 | struct pci_dn *pdn; | |
d0914f50 GS |
490 | struct pnv_phb *phb; |
491 | bool found = false; | |
492 | int ret; | |
9bf41be6 | 493 | |
d0914f50 | 494 | *val = 0xFFFFFFFF; |
9bf41be6 GS |
495 | for (dn = busdn->child; dn; dn = dn->sibling) { |
496 | pdn = PCI_DN(dn); | |
d0914f50 GS |
497 | if (pdn && pdn->devfn == devfn) { |
498 | phb = pdn->phb->private_data; | |
499 | found = true; | |
500 | break; | |
501 | } | |
9bf41be6 GS |
502 | } |
503 | ||
d0914f50 GS |
504 | if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) |
505 | return PCIBIOS_DEVICE_NOT_FOUND; | |
506 | ||
507 | ret = pnv_pci_cfg_read(dn, where, size, val); | |
508 | if (phb->flags & PNV_PHB_FLAG_EEH) { | |
509 | if (*val == EEH_IO_ERROR_VALUE(size) && | |
510 | eeh_dev_check_failure(of_node_to_eeh_dev(dn))) | |
511 | return PCIBIOS_DEVICE_NOT_FOUND; | |
512 | } else { | |
513 | pnv_pci_config_check_eeh(phb, dn); | |
514 | } | |
9bf41be6 | 515 | |
d0914f50 | 516 | return ret; |
9bf41be6 GS |
517 | } |
518 | ||
519 | static int pnv_pci_write_config(struct pci_bus *bus, | |
520 | unsigned int devfn, | |
521 | int where, int size, u32 val) | |
522 | { | |
523 | struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); | |
524 | struct pci_dn *pdn; | |
d0914f50 GS |
525 | struct pnv_phb *phb; |
526 | bool found = false; | |
527 | int ret; | |
9bf41be6 GS |
528 | |
529 | for (dn = busdn->child; dn; dn = dn->sibling) { | |
530 | pdn = PCI_DN(dn); | |
d0914f50 GS |
531 | if (pdn && pdn->devfn == devfn) { |
532 | phb = pdn->phb->private_data; | |
533 | found = true; | |
534 | break; | |
535 | } | |
9bf41be6 GS |
536 | } |
537 | ||
d0914f50 GS |
538 | if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) |
539 | return PCIBIOS_DEVICE_NOT_FOUND; | |
540 | ||
541 | ret = pnv_pci_cfg_write(dn, where, size, val); | |
542 | if (!(phb->flags & PNV_PHB_FLAG_EEH)) | |
543 | pnv_pci_config_check_eeh(phb, dn); | |
544 | ||
545 | return ret; | |
9bf41be6 GS |
546 | } |
547 | ||
61305a96 | 548 | struct pci_ops pnv_pci_ops = { |
9bf41be6 | 549 | .read = pnv_pci_read_config, |
61305a96 BH |
550 | .write = pnv_pci_write_config, |
551 | }; | |
552 | ||
553 | static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, | |
554 | unsigned long uaddr, enum dma_data_direction direction, | |
8e0a1611 | 555 | struct dma_attrs *attrs, bool rm) |
61305a96 BH |
556 | { |
557 | u64 proto_tce; | |
3a1a4661 | 558 | __be64 *tcep, *tces; |
61305a96 BH |
559 | u64 rpn; |
560 | ||
561 | proto_tce = TCE_PCI_READ; // Read allowed | |
562 | ||
563 | if (direction != DMA_TO_DEVICE) | |
564 | proto_tce |= TCE_PCI_WRITE; | |
565 | ||
5e4da530 | 566 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
bc32057e | 567 | rpn = __pa(uaddr) >> tbl->it_page_shift; |
61305a96 | 568 | |
1f1616e8 | 569 | while (npages--) |
bc32057e AK |
570 | *(tcep++) = cpu_to_be64(proto_tce | |
571 | (rpn++ << tbl->it_page_shift)); | |
1f1616e8 BH |
572 | |
573 | /* Some implementations won't cache invalid TCEs and thus may not | |
574 | * need that flush. We'll probably turn it_type into a bit mask | |
575 | * of flags if that becomes the case | |
576 | */ | |
577 | if (tbl->it_type & TCE_PCI_SWINV_CREATE) | |
8e0a1611 | 578 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
61305a96 | 579 | |
61305a96 BH |
580 | return 0; |
581 | } | |
582 | ||
8e0a1611 AK |
583 | static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages, |
584 | unsigned long uaddr, | |
585 | enum dma_data_direction direction, | |
586 | struct dma_attrs *attrs) | |
587 | { | |
588 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, | |
589 | false); | |
590 | } | |
591 | ||
592 | static void pnv_tce_free(struct iommu_table *tbl, long index, long npages, | |
593 | bool rm) | |
61305a96 | 594 | { |
3a1a4661 | 595 | __be64 *tcep, *tces; |
1f1616e8 | 596 | |
5e4da530 | 597 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
61305a96 BH |
598 | |
599 | while (npages--) | |
3a1a4661 | 600 | *(tcep++) = cpu_to_be64(0); |
1f1616e8 | 601 | |
605e44d6 | 602 | if (tbl->it_type & TCE_PCI_SWINV_FREE) |
8e0a1611 AK |
603 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
604 | } | |
605 | ||
606 | static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages) | |
607 | { | |
608 | pnv_tce_free(tbl, index, npages, false); | |
61305a96 BH |
609 | } |
610 | ||
11f63d3f AK |
611 | static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) |
612 | { | |
613 | return ((u64 *)tbl->it_base)[index - tbl->it_offset]; | |
614 | } | |
615 | ||
8e0a1611 AK |
616 | static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages, |
617 | unsigned long uaddr, | |
618 | enum dma_data_direction direction, | |
619 | struct dma_attrs *attrs) | |
620 | { | |
621 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true); | |
622 | } | |
623 | ||
624 | static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages) | |
625 | { | |
626 | pnv_tce_free(tbl, index, npages, true); | |
627 | } | |
628 | ||
61305a96 BH |
629 | void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
630 | void *tce_mem, u64 tce_size, | |
8fa5d454 | 631 | u64 dma_offset, unsigned page_shift) |
61305a96 BH |
632 | { |
633 | tbl->it_blocksize = 16; | |
634 | tbl->it_base = (unsigned long)tce_mem; | |
8fa5d454 | 635 | tbl->it_page_shift = page_shift; |
3a553170 | 636 | tbl->it_offset = dma_offset >> tbl->it_page_shift; |
61305a96 BH |
637 | tbl->it_index = 0; |
638 | tbl->it_size = tce_size >> 3; | |
639 | tbl->it_busno = 0; | |
640 | tbl->it_type = TCE_PCI; | |
641 | } | |
642 | ||
cad5cef6 | 643 | static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose) |
61305a96 BH |
644 | { |
645 | struct iommu_table *tbl; | |
3a1a4661 BH |
646 | const __be64 *basep, *swinvp; |
647 | const __be32 *sizep; | |
61305a96 BH |
648 | |
649 | basep = of_get_property(hose->dn, "linux,tce-base", NULL); | |
650 | sizep = of_get_property(hose->dn, "linux,tce-size", NULL); | |
651 | if (basep == NULL || sizep == NULL) { | |
1f1616e8 BH |
652 | pr_err("PCI: %s has missing tce entries !\n", |
653 | hose->dn->full_name); | |
61305a96 BH |
654 | return NULL; |
655 | } | |
656 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); | |
657 | if (WARN_ON(!tbl)) | |
658 | return NULL; | |
659 | pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), | |
8fa5d454 | 660 | be32_to_cpup(sizep), 0, IOMMU_PAGE_SHIFT_4K); |
61305a96 | 661 | iommu_init_table(tbl, hose->node); |
4e13c1ac | 662 | iommu_register_group(tbl, pci_domain_nr(hose->bus), 0); |
1f1616e8 BH |
663 | |
664 | /* Deal with SW invalidated TCEs when needed (BML way) */ | |
665 | swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info", | |
666 | NULL); | |
667 | if (swinvp) { | |
5e4da530 | 668 | tbl->it_busno = be64_to_cpu(swinvp[1]); |
3a1a4661 | 669 | tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); |
1f1616e8 BH |
670 | tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; |
671 | } | |
61305a96 BH |
672 | return tbl; |
673 | } | |
674 | ||
cad5cef6 GKH |
675 | static void pnv_pci_dma_fallback_setup(struct pci_controller *hose, |
676 | struct pci_dev *pdev) | |
61305a96 BH |
677 | { |
678 | struct device_node *np = pci_bus_to_OF_node(hose->bus); | |
679 | struct pci_dn *pdn; | |
680 | ||
681 | if (np == NULL) | |
682 | return; | |
683 | pdn = PCI_DN(np); | |
684 | if (!pdn->iommu_table) | |
685 | pdn->iommu_table = pnv_pci_setup_bml_iommu(hose); | |
686 | if (!pdn->iommu_table) | |
687 | return; | |
d905c5df | 688 | set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table); |
61305a96 BH |
689 | } |
690 | ||
cad5cef6 | 691 | static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) |
61305a96 BH |
692 | { |
693 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
694 | struct pnv_phb *phb = hose->private_data; | |
695 | ||
696 | /* If we have no phb structure, try to setup a fallback based on | |
697 | * the device-tree (RTAS PCI for example) | |
698 | */ | |
699 | if (phb && phb->dma_dev_setup) | |
700 | phb->dma_dev_setup(phb, pdev); | |
701 | else | |
702 | pnv_pci_dma_fallback_setup(hose, pdev); | |
703 | } | |
704 | ||
cd15b048 BH |
705 | int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
706 | { | |
707 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
708 | struct pnv_phb *phb = hose->private_data; | |
709 | ||
710 | if (phb && phb->dma_set_mask) | |
711 | return phb->dma_set_mask(phb, pdev, dma_mask); | |
712 | return __dma_set_mask(&pdev->dev, dma_mask); | |
713 | } | |
714 | ||
73ed148a BH |
715 | void pnv_pci_shutdown(void) |
716 | { | |
717 | struct pci_controller *hose; | |
718 | ||
719 | list_for_each_entry(hose, &hose_list, list_node) { | |
720 | struct pnv_phb *phb = hose->private_data; | |
721 | ||
722 | if (phb && phb->shutdown) | |
723 | phb->shutdown(phb); | |
724 | } | |
725 | } | |
726 | ||
aa0c033f | 727 | /* Fixup wrong class code in p7ioc and p8 root complex */ |
cad5cef6 | 728 | static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) |
ca45cfe3 BH |
729 | { |
730 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
731 | } | |
732 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); | |
733 | ||
82ba129b BH |
734 | static int pnv_pci_probe_mode(struct pci_bus *bus) |
735 | { | |
736 | struct pci_controller *hose = pci_bus_to_host(bus); | |
737 | const __be64 *tstamp; | |
738 | u64 now, target; | |
739 | ||
740 | ||
741 | /* We hijack this as a way to ensure we have waited long | |
742 | * enough since the reset was lifted on the PCI bus | |
743 | */ | |
744 | if (bus != hose->bus) | |
745 | return PCI_PROBE_NORMAL; | |
746 | tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL); | |
747 | if (!tstamp || !*tstamp) | |
748 | return PCI_PROBE_NORMAL; | |
749 | ||
750 | now = mftb() / tb_ticks_per_usec; | |
751 | target = (be64_to_cpup(tstamp) / tb_ticks_per_usec) | |
752 | + PCI_RESET_DELAY_US; | |
753 | ||
754 | pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n", | |
755 | hose->global_number, target, now); | |
756 | ||
757 | if (now < target) | |
758 | msleep((target - now + 999) / 1000); | |
759 | ||
760 | return PCI_PROBE_NORMAL; | |
761 | } | |
762 | ||
61305a96 BH |
763 | void __init pnv_pci_init(void) |
764 | { | |
765 | struct device_node *np; | |
766 | ||
673c9756 | 767 | pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); |
61305a96 BH |
768 | |
769 | /* OPAL absent, try POPAL first then RTAS detection of PHBs */ | |
770 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { | |
771 | #ifdef CONFIG_PPC_POWERNV_RTAS | |
772 | init_pci_config_tokens(); | |
773 | find_and_init_phbs(); | |
774 | #endif /* CONFIG_PPC_POWERNV_RTAS */ | |
184cd4a3 BH |
775 | } |
776 | /* OPAL is here, do our normal stuff */ | |
777 | else { | |
778 | int found_ioda = 0; | |
779 | ||
780 | /* Look for IODA IO-Hubs. We don't support mixing IODA | |
781 | * and p5ioc2 due to the need to change some global | |
782 | * probing flags | |
783 | */ | |
784 | for_each_compatible_node(np, NULL, "ibm,ioda-hub") { | |
785 | pnv_pci_init_ioda_hub(np); | |
786 | found_ioda = 1; | |
787 | } | |
61305a96 BH |
788 | |
789 | /* Look for p5ioc2 IO-Hubs */ | |
184cd4a3 BH |
790 | if (!found_ioda) |
791 | for_each_compatible_node(np, NULL, "ibm,p5ioc2") | |
792 | pnv_pci_init_p5ioc2_hub(np); | |
aa0c033f GS |
793 | |
794 | /* Look for ioda2 built-in PHB3's */ | |
795 | for_each_compatible_node(np, NULL, "ibm,ioda2-phb") | |
796 | pnv_pci_init_ioda2_phb(np); | |
61305a96 BH |
797 | } |
798 | ||
799 | /* Setup the linkage between OF nodes and PHBs */ | |
800 | pci_devs_phb_init(); | |
801 | ||
802 | /* Configure IOMMU DMA hooks */ | |
803 | ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup; | |
8e0a1611 AK |
804 | ppc_md.tce_build = pnv_tce_build_vm; |
805 | ppc_md.tce_free = pnv_tce_free_vm; | |
806 | ppc_md.tce_build_rm = pnv_tce_build_rm; | |
807 | ppc_md.tce_free_rm = pnv_tce_free_rm; | |
11f63d3f | 808 | ppc_md.tce_get = pnv_tce_get; |
82ba129b | 809 | ppc_md.pci_probe_mode = pnv_pci_probe_mode; |
61305a96 BH |
810 | set_pci_dma_ops(&dma_iommu_ops); |
811 | ||
c1a2562a BH |
812 | /* Configure MSIs */ |
813 | #ifdef CONFIG_PCI_MSI | |
814 | ppc_md.msi_check_device = pnv_msi_check_device; | |
815 | ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; | |
816 | ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; | |
817 | #endif | |
61305a96 | 818 | } |
d905c5df AK |
819 | |
820 | static int tce_iommu_bus_notifier(struct notifier_block *nb, | |
821 | unsigned long action, void *data) | |
822 | { | |
823 | struct device *dev = data; | |
824 | ||
825 | switch (action) { | |
826 | case BUS_NOTIFY_ADD_DEVICE: | |
827 | return iommu_add_device(dev); | |
828 | case BUS_NOTIFY_DEL_DEVICE: | |
829 | if (dev->iommu_group) | |
830 | iommu_del_device(dev); | |
831 | return 0; | |
832 | default: | |
833 | return 0; | |
834 | } | |
835 | } | |
836 | ||
837 | static struct notifier_block tce_iommu_bus_nb = { | |
838 | .notifier_call = tce_iommu_bus_notifier, | |
839 | }; | |
840 | ||
841 | static int __init tce_iommu_bus_notifier_init(void) | |
842 | { | |
d905c5df AK |
843 | bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb); |
844 | return 0; | |
845 | } | |
846 | ||
847 | subsys_initcall_sync(tce_iommu_bus_notifier_init); |