[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / platforms / powernv / pci.c

/*
 * Support PCI/PCIe on PowerNV platforms
 *
 * Currently supports only P5IOC2
 *
 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/msi.h>
#include <linux/iommu.h>

#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <asm/msi_bitmap.h>
#include <asm/ppc-pci.h>
#include <asm/opal.h>
#include <asm/iommu.h>
#include <asm/tce.h>
#include <asm/firmware.h>
#include <asm/eeh_event.h>
#include <asm/eeh.h>

#include "powernv.h"
#include "pci.h"

/* Delay in usec */
#define PCI_RESET_DELAY_US	3000000

#define cfg_dbg(fmt...)	do { } while(0)
//#define cfg_dbg(fmt...)	printk(fmt)

#ifdef CONFIG_PCI_MSI
static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct pci_dn *pdn = pci_get_pdn(pdev);

	if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
		return -ENODEV;

	return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
}

static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct msi_desc *entry;
	struct msi_msg msg;
	int hwirq;
	unsigned int virq;
	int rc;

	if (WARN_ON(!phb))
		return -ENODEV;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
			pr_warn("%s: Supports only 64-bit MSIs\n",
				pci_name(pdev));
			return -ENXIO;
		}
		hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
		if (hwirq < 0) {
			pr_warn("%s: Failed to find a free MSI\n",
				pci_name(pdev));
			return -ENOSPC;
		}
		virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
		if (virq == NO_IRQ) {
			pr_warn("%s: Failed to map MSI to linux irq\n",
				pci_name(pdev));
			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
			return -ENOMEM;
		}
		rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
				    virq, entry->msi_attrib.is_64, &msg);
		if (rc) {
			pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
			irq_dispose_mapping(virq);
			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
			return rc;
		}
		irq_set_msi_desc(virq, entry);
		write_msi_msg(virq, &msg);
	}
	return 0;
}

static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct msi_desc *entry;

	if (WARN_ON(!phb))
		return;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
		irq_set_msi_desc(entry->irq, NULL);
		msi_bitmap_free_hwirqs(&phb->msi_bmp,
			virq_to_hw(entry->irq) - phb->msi_base, 1);
		irq_dispose_mapping(entry->irq);
	}
}
#endif /* CONFIG_PCI_MSI */

static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
{
	struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
	int i;

	pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);

	pr_info("  brdgCtl              = 0x%08x\n", data->brdgCtl);

	pr_info("  portStatusReg        = 0x%08x\n", data->portStatusReg);
	pr_info("  rootCmplxStatus      = 0x%08x\n", data->rootCmplxStatus);
	pr_info("  busAgentStatus       = 0x%08x\n", data->busAgentStatus);

	pr_info("  deviceStatus         = 0x%08x\n", data->deviceStatus);
	pr_info("  slotStatus           = 0x%08x\n", data->slotStatus);
	pr_info("  linkStatus           = 0x%08x\n", data->linkStatus);
	pr_info("  devCmdStatus         = 0x%08x\n", data->devCmdStatus);
	pr_info("  devSecStatus         = 0x%08x\n", data->devSecStatus);

	pr_info("  rootErrorStatus      = 0x%08x\n", data->rootErrorStatus);
	pr_info("  uncorrErrorStatus    = 0x%08x\n", data->uncorrErrorStatus);
	pr_info("  corrErrorStatus      = 0x%08x\n", data->corrErrorStatus);
	pr_info("  tlpHdr1              = 0x%08x\n", data->tlpHdr1);
	pr_info("  tlpHdr2              = 0x%08x\n", data->tlpHdr2);
	pr_info("  tlpHdr3              = 0x%08x\n", data->tlpHdr3);
	pr_info("  tlpHdr4              = 0x%08x\n", data->tlpHdr4);
	pr_info("  sourceId             = 0x%08x\n", data->sourceId);

	pr_info("  errorClass           = 0x%016llx\n", data->errorClass);
	pr_info("  correlator           = 0x%016llx\n", data->correlator);

	pr_info("  p7iocPlssr           = 0x%016llx\n", data->p7iocPlssr);
	pr_info("  p7iocCsr             = 0x%016llx\n", data->p7iocCsr);
	pr_info("  lemFir               = 0x%016llx\n", data->lemFir);
	pr_info("  lemErrorMask         = 0x%016llx\n", data->lemErrorMask);
	pr_info("  lemWOF               = 0x%016llx\n", data->lemWOF);
	pr_info("  phbErrorStatus       = 0x%016llx\n", data->phbErrorStatus);
	pr_info("  phbFirstErrorStatus  = 0x%016llx\n", data->phbFirstErrorStatus);
	pr_info("  phbErrorLog0         = 0x%016llx\n", data->phbErrorLog0);
	pr_info("  phbErrorLog1         = 0x%016llx\n", data->phbErrorLog1);
	pr_info("  mmioErrorStatus      = 0x%016llx\n", data->mmioErrorStatus);
	pr_info("  mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
	pr_info("  mmioErrorLog0        = 0x%016llx\n", data->mmioErrorLog0);
	pr_info("  mmioErrorLog1        = 0x%016llx\n", data->mmioErrorLog1);
	pr_info("  dma0ErrorStatus      = 0x%016llx\n", data->dma0ErrorStatus);
	pr_info("  dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
	pr_info("  dma0ErrorLog0        = 0x%016llx\n", data->dma0ErrorLog0);
	pr_info("  dma0ErrorLog1        = 0x%016llx\n", data->dma0ErrorLog1);
	pr_info("  dma1ErrorStatus      = 0x%016llx\n", data->dma1ErrorStatus);
	pr_info("  dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
	pr_info("  dma1ErrorLog0        = 0x%016llx\n", data->dma1ErrorLog0);
	pr_info("  dma1ErrorLog1        = 0x%016llx\n", data->dma1ErrorLog1);

	for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
		if ((data->pestA[i] >> 63) == 0 &&
		    (data->pestB[i] >> 63) == 0)
			continue;
		pr_info("  PE[%3d] PESTA        = 0x%016llx\n", i, data->pestA[i]);
		pr_info("          PESTB        = 0x%016llx\n", data->pestB[i]);
	}
}

static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
{
	switch(phb->model) {
	case PNV_PHB_MODEL_P7IOC:
		pnv_pci_dump_p7ioc_diag_data(phb);
		break;
	default:
		pr_warning("PCI %d: Can't decode this PHB diag data\n",
			   phb->hose->global_number);
	}
}

static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
{
	unsigned long flags, rc;
	int has_diag;

	spin_lock_irqsave(&phb->lock, flags);

	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
					 PNV_PCI_DIAG_BUF_SIZE);
	has_diag = (rc == OPAL_SUCCESS);

	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
				       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
	if (rc) {
		pr_warning("PCI %d: Failed to clear EEH freeze state"
			   " for PE#%d, err %ld\n",
			   phb->hose->global_number, pe_no, rc);

		/* For now, let's only display the diag buffer when we fail to clear
		 * the EEH status. We'll do more sensible things later when we have
		 * proper EEH support. We need to make sure we don't pollute ourselves
		 * with the normal errors generated when probing empty slots
		 */
		if (has_diag)
			pnv_pci_dump_phb_diag_data(phb);
		else
			pr_warning("PCI %d: No diag data available\n",
				   phb->hose->global_number);
	}

	spin_unlock_irqrestore(&phb->lock, flags);
}

static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
				     struct device_node *dn)
{
	s64	rc;
	u8	fstate;
	u16	pcierr;
	u32	pe_no;

	/*
	 * Get the PE#. During the PCI probe stage, we might not
	 * setup that yet. So all ER errors should be mapped to
	 * PE#0
	 */
	pe_no = PCI_DN(dn)->pe_number;
	if (pe_no == IODA_INVALID_PE)
		pe_no = 0;

	/* Read freeze status */
	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
					NULL);
	if (rc) {
		pr_warning("%s: Can't read EEH status (PE#%d) for "
			   "%s, err %lld\n",
			   __func__, pe_no, dn->full_name, rc);
		return;
	}
	cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
		(PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
		pe_no, fstate);
	if (fstate != 0)
		pnv_pci_handle_eeh_config(phb, pe_no);
}

int pnv_pci_cfg_read(struct device_node *dn,
		     int where, int size, u32 *val)
{
	struct pci_dn *pdn = PCI_DN(dn);
	struct pnv_phb *phb = pdn->phb->private_data;
	u32 bdfn = (pdn->busno << 8) | pdn->devfn;
#ifdef CONFIG_EEH
	struct eeh_pe *phb_pe = NULL;
#endif
	s64 rc;

	switch (size) {
	case 1: {
		u8 v8;
		rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
		*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
		break;
	}
	case 2: {
		u16 v16;
		rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
						   &v16);
		*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
		break;
	}
	case 4: {
		u32 v32;
		rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
		*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
		break;
	}
	default:
		return PCIBIOS_FUNC_NOT_SUPPORTED;
	}
	cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
		__func__, pdn->busno, pdn->devfn, where, size, *val);

	/*
	 * Check if the specified PE has been put into frozen
	 * state. On the other hand, we needn't do that while
	 * the PHB has been put into frozen state because of
	 * PHB-fatal errors.
	 */
#ifdef CONFIG_EEH
	phb_pe = eeh_phb_pe_get(pdn->phb);
	if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
		return PCIBIOS_SUCCESSFUL;

	if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
		if (*val == EEH_IO_ERROR_VALUE(size) &&
		    eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
			return PCIBIOS_DEVICE_NOT_FOUND;
	} else {
		pnv_pci_config_check_eeh(phb, dn);
	}
#else
	pnv_pci_config_check_eeh(phb, dn);
#endif

	return PCIBIOS_SUCCESSFUL;
}

int pnv_pci_cfg_write(struct device_node *dn,
		      int where, int size, u32 val)
{
	struct pci_dn *pdn = PCI_DN(dn);
	struct pnv_phb *phb = pdn->phb->private_data;
	u32 bdfn = (pdn->busno << 8) | pdn->devfn;

	cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
		pdn->busno, pdn->devfn, where, size, val);
	switch (size) {
	case 1:
		opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
		break;
	case 2:
		opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
		break;
	case 4:
		opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
		break;
	default:
		return PCIBIOS_FUNC_NOT_SUPPORTED;
	}

	/* Check if the PHB got frozen due to an error (no response) */
#ifdef CONFIG_EEH
	if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
		pnv_pci_config_check_eeh(phb, dn);
#else
	pnv_pci_config_check_eeh(phb, dn);
#endif

	return PCIBIOS_SUCCESSFUL;
}

static int pnv_pci_read_config(struct pci_bus *bus,
			       unsigned int devfn,
			       int where, int size, u32 *val)
{
	struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
	struct pci_dn *pdn;

	for (dn = busdn->child; dn; dn = dn->sibling) {
		pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn)
			return pnv_pci_cfg_read(dn, where, size, val);
	}

	*val = 0xFFFFFFFF;
	return PCIBIOS_DEVICE_NOT_FOUND;

}

static int pnv_pci_write_config(struct pci_bus *bus,
				unsigned int devfn,
				int where, int size, u32 val)
{
	struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
	struct pci_dn *pdn;

	for (dn = busdn->child; dn; dn = dn->sibling) {
		pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn)
			return pnv_pci_cfg_write(dn, where, size, val);
	}

	return PCIBIOS_DEVICE_NOT_FOUND;
}

struct pci_ops pnv_pci_ops = {
	.read  = pnv_pci_read_config,
	.write = pnv_pci_write_config,
};

static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
			 unsigned long uaddr, enum dma_data_direction direction,
			 struct dma_attrs *attrs)
{
	u64 proto_tce;
	u64 *tcep, *tces;
	u64 rpn;

	proto_tce = TCE_PCI_READ; // Read allowed

	if (direction != DMA_TO_DEVICE)
		proto_tce |= TCE_PCI_WRITE;

	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
	rpn = __pa(uaddr) >> TCE_SHIFT;

	while (npages--)
		*(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);

	/* Some implementations won't cache invalid TCEs and thus may not
	 * need that flush. We'll probably turn it_type into a bit mask
	 * of flags if that becomes the case
	 */
	if (tbl->it_type & TCE_PCI_SWINV_CREATE)
		pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);

	return 0;
}

static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
{
	u64 *tcep, *tces;

	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;

	while (npages--)
		*(tcep++) = 0;

	if (tbl->it_type & TCE_PCI_SWINV_FREE)
		pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
}

static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
{
	return ((u64 *)tbl->it_base)[index - tbl->it_offset];
}

void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
			       void *tce_mem, u64 tce_size,
			       u64 dma_offset)
{
	tbl->it_blocksize = 16;
	tbl->it_base = (unsigned long)tce_mem;
	tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
	tbl->it_index = 0;
	tbl->it_size = tce_size >> 3;
	tbl->it_busno = 0;
	tbl->it_type = TCE_PCI;
}

static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
{
	struct iommu_table *tbl;
	const __be64 *basep, *swinvp;
	const __be32 *sizep;

	basep = of_get_property(hose->dn, "linux,tce-base", NULL);
	sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
	if (basep == NULL || sizep == NULL) {
		pr_err("PCI: %s has missing tce entries !\n",
		       hose->dn->full_name);
		return NULL;
	}
	tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
	if (WARN_ON(!tbl))
		return NULL;
	pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
				  be32_to_cpup(sizep), 0);
	iommu_init_table(tbl, hose->node);
	iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);

	/* Deal with SW invalidated TCEs when needed (BML way) */
	swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
				 NULL);
	if (swinvp) {
		tbl->it_busno = swinvp[1];
		tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
		tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
	}
	return tbl;
}

static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
				       struct pci_dev *pdev)
{
	struct device_node *np = pci_bus_to_OF_node(hose->bus);
	struct pci_dn *pdn;

	if (np == NULL)
		return;
	pdn = PCI_DN(np);
	if (!pdn->iommu_table)
		pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
	if (!pdn->iommu_table)
		return;
	set_iommu_table_base(&pdev->dev, pdn->iommu_table);
}

static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;

	/* If we have no phb structure, try to setup a fallback based on
	 * the device-tree (RTAS PCI for example)
	 */
	if (phb && phb->dma_dev_setup)
		phb->dma_dev_setup(phb, pdev);
	else
		pnv_pci_dma_fallback_setup(hose, pdev);
}

void pnv_pci_shutdown(void)
{
	struct pci_controller *hose;

	list_for_each_entry(hose, &hose_list, list_node) {
		struct pnv_phb *phb = hose->private_data;

		if (phb && phb->shutdown)
			phb->shutdown(phb);
	}
}

/* Fixup wrong class code in p7ioc and p8 root complex */
static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);

static int pnv_pci_probe_mode(struct pci_bus *bus)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	const __be64 *tstamp;
	u64 now, target;


	/* We hijack this as a way to ensure we have waited long
	 * enough since the reset was lifted on the PCI bus
	 */
	if (bus != hose->bus)
		return PCI_PROBE_NORMAL;
	tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
	if (!tstamp || !*tstamp)
		return PCI_PROBE_NORMAL;

	now = mftb() / tb_ticks_per_usec;
	target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
		+ PCI_RESET_DELAY_US;

	pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
		 hose->global_number, target, now);

	if (now < target)
		msleep((target - now + 999) / 1000);

	return PCI_PROBE_NORMAL;
}

void __init pnv_pci_init(void)
{
	struct device_node *np;

	pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);

	/* OPAL absent, try POPAL first then RTAS detection of PHBs */
	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
#ifdef CONFIG_PPC_POWERNV_RTAS
		init_pci_config_tokens();
		find_and_init_phbs();
#endif /* CONFIG_PPC_POWERNV_RTAS */
	}
	/* OPAL is here, do our normal stuff */
	else {
		int found_ioda = 0;

		/* Look for IODA IO-Hubs. We don't support mixing IODA
		 * and p5ioc2 due to the need to change some global
		 * probing flags
		 */
		for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
			pnv_pci_init_ioda_hub(np);
			found_ioda = 1;
		}

		/* Look for p5ioc2 IO-Hubs */
		if (!found_ioda)
			for_each_compatible_node(np, NULL, "ibm,p5ioc2")
				pnv_pci_init_p5ioc2_hub(np);

		/* Look for ioda2 built-in PHB3's */
		for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
			pnv_pci_init_ioda2_phb(np);
	}

	/* Setup the linkage between OF nodes and PHBs */
	pci_devs_phb_init();

	/* Configure IOMMU DMA hooks */
	ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
	ppc_md.tce_build = pnv_tce_build;
	ppc_md.tce_free = pnv_tce_free;
	ppc_md.tce_get = pnv_tce_get;
	ppc_md.pci_probe_mode = pnv_pci_probe_mode;
	set_pci_dma_ops(&dma_iommu_ops);

	/* Configure MSIs */
#ifdef CONFIG_PCI_MSI
	ppc_md.msi_check_device = pnv_msi_check_device;
	ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
#endif
}
Commit	Line	Data
61305a96 BH	1	/*
	2	* Support PCI/PCIe on PowerNV platforms
	3	*
	4	* Currently supports only P5IOC2
	5	*
	6	* Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/pci.h>
	16	#include <linux/delay.h>
	17	#include <linux/string.h>
	18	#include <linux/init.h>
	19	#include <linux/bootmem.h>
	20	#include <linux/irq.h>
	21	#include <linux/io.h>
c1a2562a	22	#include <linux/msi.h>
4e13c1ac	23	#include <linux/iommu.h>
61305a96 BH	24
	25	#include <asm/sections.h>
	26	#include <asm/io.h>
	27	#include <asm/prom.h>
	28	#include <asm/pci-bridge.h>
	29	#include <asm/machdep.h>
fb1b55d6	30	#include <asm/msi_bitmap.h>
61305a96 BH	31	#include <asm/ppc-pci.h>
	32	#include <asm/opal.h>
	33	#include <asm/iommu.h>
	34	#include <asm/tce.h>
f5339277	35	#include <asm/firmware.h>
be7e7446 GS	36	#include <asm/eeh_event.h>
be7e7446 GS	37	#include <asm/eeh.h>
61305a96 BH	38
	39	#include "powernv.h"
	40	#include "pci.h"
	41
82ba129b BH	42	/* Delay in usec */
82ba129b BH	43	#define PCI_RESET_DELAY_US 3000000
61305a96 BH	44
	45	#define cfg_dbg(fmt...) do { } while(0)
	46	//#define cfg_dbg(fmt...) printk(fmt)
	47
c1a2562a BH	48	#ifdef CONFIG_PCI_MSI
	49	static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
	50	{
	51	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	52	struct pnv_phb *phb = hose->private_data;
b72c1f65 BH	53	struct pci_dn *pdn = pci_get_pdn(pdev);
	54
	55	if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
	56	return -ENODEV;
c1a2562a	57
fb1b55d6	58	return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
c1a2562a BH	59	}
	60
	61	static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	62	{
	63	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	64	struct pnv_phb *phb = hose->private_data;
	65	struct msi_desc *entry;
	66	struct msi_msg msg;
fb1b55d6 GS	67	int hwirq;
fb1b55d6 GS	68	unsigned int virq;
c1a2562a BH	69	int rc;
	70
	71	if (WARN_ON(!phb))
	72	return -ENODEV;
	73
	74	list_for_each_entry(entry, &pdev->msi_list, list) {
	75	if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
	76	pr_warn("%s: Supports only 64-bit MSIs\n",
	77	pci_name(pdev));
	78	return -ENXIO;
	79	}
fb1b55d6 GS	80	hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
fb1b55d6 GS	81	if (hwirq < 0) {
c1a2562a BH	82	pr_warn("%s: Failed to find a free MSI\n",
	83	pci_name(pdev));
	84	return -ENOSPC;
	85	}
fb1b55d6	86	virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
c1a2562a BH	87	if (virq == NO_IRQ) {
	88	pr_warn("%s: Failed to map MSI to linux irq\n",
	89	pci_name(pdev));
fb1b55d6	90	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
c1a2562a BH	91	return -ENOMEM;
c1a2562a BH	92	}
fb1b55d6	93	rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
137436c9	94	virq, entry->msi_attrib.is_64, &msg);
c1a2562a BH	95	if (rc) {
	96	pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
	97	irq_dispose_mapping(virq);
fb1b55d6	98	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
c1a2562a BH	99	return rc;
	100	}
	101	irq_set_msi_desc(virq, entry);
	102	write_msi_msg(virq, &msg);
	103	}
	104	return 0;
	105	}
	106
	107	static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
	108	{
	109	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	110	struct pnv_phb *phb = hose->private_data;
	111	struct msi_desc *entry;
	112
	113	if (WARN_ON(!phb))
	114	return;
	115
	116	list_for_each_entry(entry, &pdev->msi_list, list) {
	117	if (entry->irq == NO_IRQ)
	118	continue;
	119	irq_set_msi_desc(entry->irq, NULL);
fb1b55d6 GS	120	msi_bitmap_free_hwirqs(&phb->msi_bmp,
fb1b55d6 GS	121	virq_to_hw(entry->irq) - phb->msi_base, 1);
c1a2562a BH	122	irq_dispose_mapping(entry->irq);
	123	}
	124	}
	125	#endif /* CONFIG_PCI_MSI */
61305a96	126
cee72d5b BH	127	static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
	128	{
	129	struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
	130	int i;
	131
	132	pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
	133
	134	pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl);
	135
	136	pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg);
	137	pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus);
	138	pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus);
	139
	140	pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus);
	141	pr_info(" slotStatus = 0x%08x\n", data->slotStatus);
	142	pr_info(" linkStatus = 0x%08x\n", data->linkStatus);
	143	pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus);
	144	pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus);
	145
	146	pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus);
	147	pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus);
	148	pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus);
	149	pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1);
	150	pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2);
	151	pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3);
	152	pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4);
	153	pr_info(" sourceId = 0x%08x\n", data->sourceId);
	154
	155	pr_info(" errorClass = 0x%016llx\n", data->errorClass);
	156	pr_info(" correlator = 0x%016llx\n", data->correlator);
	157
	158	pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr);
	159	pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr);
	160	pr_info(" lemFir = 0x%016llx\n", data->lemFir);
	161	pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask);
	162	pr_info(" lemWOF = 0x%016llx\n", data->lemWOF);
	163	pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus);
	164	pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus);
	165	pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0);
	166	pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1);
	167	pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus);
	168	pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
	169	pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0);
	170	pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1);
	171	pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus);
	172	pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
	173	pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0);
	174	pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1);
	175	pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus);
	176	pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
	177	pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0);
	178	pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1);
	179
	180	for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
	181	if ((data->pestA[i] >> 63) == 0 &&
	182	(data->pestB[i] >> 63) == 0)
	183	continue;
	184	pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]);
	185	pr_info(" PESTB = 0x%016llx\n", data->pestB[i]);
	186	}
	187	}
	188
	189	static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
	190	{
191	switch(phb->model) {
192	case PNV_PHB_MODEL_P7IOC:
193	pnv_pci_dump_p7ioc_diag_data(phb);
194	break;
195	default:
196	pr_warning("PCI %d: Can't decode this PHB diag data\n",
197	phb->hose->global_number);
198	}
199	}
200
201	static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
202	{
203	unsigned long flags, rc;
204	int has_diag;
205
206	spin_lock_irqsave(&phb->lock, flags);
207
23773230 GS	208	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
23773230 GS	209	PNV_PCI_DIAG_BUF_SIZE);
cee72d5b BH	210	has_diag = (rc == OPAL_SUCCESS);
	211
	212	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
	213	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
	214	if (rc) {
	215	pr_warning("PCI %d: Failed to clear EEH freeze state"
	216	" for PE#%d, err %ld\n",
	217	phb->hose->global_number, pe_no, rc);
	218
	219	/* For now, let's only display the diag buffer when we fail to clear
	220	* the EEH status. We'll do more sensible things later when we have
	221	* proper EEH support. We need to make sure we don't pollute ourselves
	222	* with the normal errors generated when probing empty slots
	223	*/
	224	if (has_diag)
	225	pnv_pci_dump_phb_diag_data(phb);
	226	else
	227	pr_warning("PCI %d: No diag data available\n",
	228	phb->hose->global_number);
	229	}
	230
	231	spin_unlock_irqrestore(&phb->lock, flags);
	232	}
	233
9bf41be6 GS	234	static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
9bf41be6 GS	235	struct device_node *dn)
61305a96 BH	236	{
	237	s64 rc;
	238	u8 fstate;
	239	u16 pcierr;
	240	u32 pe_no;
	241
9bf41be6 GS	242	/*
	243	* Get the PE#. During the PCI probe stage, we might not
	244	* setup that yet. So all ER errors should be mapped to
	245	* PE#0
	246	*/
	247	pe_no = PCI_DN(dn)->pe_number;
	248	if (pe_no == IODA_INVALID_PE)
	249	pe_no = 0;
61305a96 BH	250
	251	/* Read freeze status */
	252	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
	253	NULL);
	254	if (rc) {
9bf41be6 GS	255	pr_warning("%s: Can't read EEH status (PE#%d) for "
	256	"%s, err %lld\n",
	257	__func__, pe_no, dn->full_name, rc);
61305a96 BH	258	return;
61305a96 BH	259	}
9bf41be6 GS	260	cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
	261	(PCI_DN(dn)->busno << 8) \| (PCI_DN(dn)->devfn),
	262	pe_no, fstate);
cee72d5b BH	263	if (fstate != 0)
cee72d5b BH	264	pnv_pci_handle_eeh_config(phb, pe_no);
61305a96 BH	265	}
61305a96 BH	266
9bf41be6 GS	267	int pnv_pci_cfg_read(struct device_node *dn,
9bf41be6 GS	268	int where, int size, u32 *val)
61305a96	269	{
9bf41be6 GS	270	struct pci_dn *pdn = PCI_DN(dn);
	271	struct pnv_phb *phb = pdn->phb->private_data;
	272	u32 bdfn = (pdn->busno << 8) \| pdn->devfn;
be7e7446	273	#ifdef CONFIG_EEH
be7e7446 GS	274	struct eeh_pe *phb_pe = NULL;
be7e7446 GS	275	#endif
61305a96 BH	276	s64 rc;
61305a96 BH	277
61305a96 BH	278	switch (size) {
	279	case 1: {
	280	u8 v8;
	281	rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
	282	*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
	283	break;
	284	}
	285	case 2: {
	286	u16 v16;
	287	rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
	288	&v16);
	289	*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
	290	break;
	291	}
	292	case 4: {
	293	u32 v32;
	294	rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
	295	*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
	296	break;
	297	}
	298	default:
	299	return PCIBIOS_FUNC_NOT_SUPPORTED;
	300	}
9bf41be6 GS	301	cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
9bf41be6 GS	302	__func__, pdn->busno, pdn->devfn, where, size, *val);
61305a96	303
be7e7446 GS	304	/*
	305	* Check if the specified PE has been put into frozen
	306	* state. On the other hand, we needn't do that while
	307	* the PHB has been put into frozen state because of
	308	* PHB-fatal errors.
	309	*/
	310	#ifdef CONFIG_EEH
9bf41be6	311	phb_pe = eeh_phb_pe_get(pdn->phb);
be7e7446 GS	312	if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
	313	return PCIBIOS_SUCCESSFUL;
	314
0b9e267d	315	if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
9bf41be6 GS	316	if (*val == EEH_IO_ERROR_VALUE(size) &&
	317	eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
	318	return PCIBIOS_DEVICE_NOT_FOUND;
be7e7446	319	} else {
9bf41be6	320	pnv_pci_config_check_eeh(phb, dn);
be7e7446 GS	321	}
be7e7446 GS	322	#else
9bf41be6	323	pnv_pci_config_check_eeh(phb, dn);
be7e7446	324	#endif
61305a96 BH	325
	326	return PCIBIOS_SUCCESSFUL;
	327	}
	328
9bf41be6 GS	329	int pnv_pci_cfg_write(struct device_node *dn,
9bf41be6 GS	330	int where, int size, u32 val)
61305a96	331	{
9bf41be6 GS	332	struct pci_dn *pdn = PCI_DN(dn);
	333	struct pnv_phb *phb = pdn->phb->private_data;
	334	u32 bdfn = (pdn->busno << 8) \| pdn->devfn;
61305a96	335
9bf41be6 GS	336	cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
9bf41be6 GS	337	pdn->busno, pdn->devfn, where, size, val);
61305a96 BH	338	switch (size) {
	339	case 1:
	340	opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
	341	break;
	342	case 2:
	343	opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
	344	break;
	345	case 4:
	346	opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
	347	break;
	348	default:
	349	return PCIBIOS_FUNC_NOT_SUPPORTED;
	350	}
be7e7446	351
61305a96	352	/* Check if the PHB got frozen due to an error (no response) */
be7e7446	353	#ifdef CONFIG_EEH
0b9e267d	354	if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
9bf41be6	355	pnv_pci_config_check_eeh(phb, dn);
be7e7446	356	#else
9bf41be6	357	pnv_pci_config_check_eeh(phb, dn);
be7e7446	358	#endif
61305a96 BH	359
	360	return PCIBIOS_SUCCESSFUL;
	361	}
	362
9bf41be6 GS	363	static int pnv_pci_read_config(struct pci_bus *bus,
	364	unsigned int devfn,
	365	int where, int size, u32 *val)
	366	{
	367	struct device_node dn, busdn = pci_bus_to_OF_node(bus);
	368	struct pci_dn *pdn;
	369
	370	for (dn = busdn->child; dn; dn = dn->sibling) {
	371	pdn = PCI_DN(dn);
	372	if (pdn && pdn->devfn == devfn)
	373	return pnv_pci_cfg_read(dn, where, size, val);
	374	}
	375
	376	*val = 0xFFFFFFFF;
	377	return PCIBIOS_DEVICE_NOT_FOUND;
	378
	379	}
	380
	381	static int pnv_pci_write_config(struct pci_bus *bus,
	382	unsigned int devfn,
	383	int where, int size, u32 val)
	384	{
	385	struct device_node dn, busdn = pci_bus_to_OF_node(bus);
	386	struct pci_dn *pdn;
	387
	388	for (dn = busdn->child; dn; dn = dn->sibling) {
	389	pdn = PCI_DN(dn);
	390	if (pdn && pdn->devfn == devfn)
	391	return pnv_pci_cfg_write(dn, where, size, val);
	392	}
	393
	394	return PCIBIOS_DEVICE_NOT_FOUND;
	395	}
	396
61305a96	397	struct pci_ops pnv_pci_ops = {
9bf41be6	398	.read = pnv_pci_read_config,
61305a96 BH	399	.write = pnv_pci_write_config,
	400	};
	401
	402	static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
	403	unsigned long uaddr, enum dma_data_direction direction,
	404	struct dma_attrs *attrs)
	405	{
	406	u64 proto_tce;
1f1616e8	407	u64 tcep, tces;
61305a96 BH	408	u64 rpn;
	409
	410	proto_tce = TCE_PCI_READ; // Read allowed
	411
	412	if (direction != DMA_TO_DEVICE)
	413	proto_tce \|= TCE_PCI_WRITE;
	414
1f1616e8 BH	415	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
1f1616e8 BH	416	rpn = __pa(uaddr) >> TCE_SHIFT;
61305a96	417
1f1616e8 BH	418	while (npages--)
	419	*(tcep++) = proto_tce \| (rpn++ << TCE_RPN_SHIFT);
	420
	421	/* Some implementations won't cache invalid TCEs and thus may not
	422	* need that flush. We'll probably turn it_type into a bit mask
	423	* of flags if that becomes the case
	424	*/
	425	if (tbl->it_type & TCE_PCI_SWINV_CREATE)
4cce9550	426	pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
61305a96	427
61305a96 BH	428	return 0;
	429	}
	430
	431	static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
	432	{
1f1616e8 BH	433	u64 tcep, tces;
	434
	435	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
61305a96 BH	436
	437	while (npages--)
	438	*(tcep++) = 0;
1f1616e8	439
605e44d6	440	if (tbl->it_type & TCE_PCI_SWINV_FREE)
4cce9550	441	pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
61305a96 BH	442	}
61305a96 BH	443
11f63d3f AK	444	static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
	445	{
	446	return ((u64 *)tbl->it_base)[index - tbl->it_offset];
	447	}
	448
61305a96 BH	449	void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
	450	void *tce_mem, u64 tce_size,
	451	u64 dma_offset)
	452	{
	453	tbl->it_blocksize = 16;
	454	tbl->it_base = (unsigned long)tce_mem;
	455	tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
	456	tbl->it_index = 0;
	457	tbl->it_size = tce_size >> 3;
	458	tbl->it_busno = 0;
	459	tbl->it_type = TCE_PCI;
	460	}
	461
cad5cef6	462	static struct iommu_table pnv_pci_setup_bml_iommu(struct pci_controller hose)
61305a96 BH	463	{
61305a96 BH	464	struct iommu_table *tbl;
1f1616e8	465	const __be64 basep, swinvp;
61305a96 BH	466	const __be32 *sizep;
	467
	468	basep = of_get_property(hose->dn, "linux,tce-base", NULL);
	469	sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
	470	if (basep == NULL \|\| sizep == NULL) {
1f1616e8 BH	471	pr_err("PCI: %s has missing tce entries !\n",
1f1616e8 BH	472	hose->dn->full_name);
61305a96 BH	473	return NULL;
	474	}
	475	tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
	476	if (WARN_ON(!tbl))
	477	return NULL;
	478	pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
	479	be32_to_cpup(sizep), 0);
	480	iommu_init_table(tbl, hose->node);
4e13c1ac	481	iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
1f1616e8 BH	482
	483	/* Deal with SW invalidated TCEs when needed (BML way) */
	484	swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
	485	NULL);
	486	if (swinvp) {
	487	tbl->it_busno = swinvp[1];
	488	tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
	489	tbl->it_type = TCE_PCI_SWINV_CREATE \| TCE_PCI_SWINV_FREE;
	490	}
61305a96 BH	491	return tbl;
	492	}
	493
cad5cef6 GKH	494	static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
cad5cef6 GKH	495	struct pci_dev *pdev)
61305a96 BH	496	{
	497	struct device_node *np = pci_bus_to_OF_node(hose->bus);
	498	struct pci_dn *pdn;
	499
	500	if (np == NULL)
	501	return;
	502	pdn = PCI_DN(np);
	503	if (!pdn->iommu_table)
	504	pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
	505	if (!pdn->iommu_table)
	506	return;
	507	set_iommu_table_base(&pdev->dev, pdn->iommu_table);
	508	}
	509
cad5cef6	510	static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
61305a96 BH	511	{
	512	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	513	struct pnv_phb *phb = hose->private_data;
	514
	515	/* If we have no phb structure, try to setup a fallback based on
	516	* the device-tree (RTAS PCI for example)
	517	*/
	518	if (phb && phb->dma_dev_setup)
	519	phb->dma_dev_setup(phb, pdev);
	520	else
	521	pnv_pci_dma_fallback_setup(hose, pdev);
	522	}
	523
73ed148a BH	524	void pnv_pci_shutdown(void)
	525	{
	526	struct pci_controller *hose;
	527
	528	list_for_each_entry(hose, &hose_list, list_node) {
	529	struct pnv_phb *phb = hose->private_data;
	530
	531	if (phb && phb->shutdown)
	532	phb->shutdown(phb);
	533	}
	534	}
	535
aa0c033f	536	/* Fixup wrong class code in p7ioc and p8 root complex */
cad5cef6	537	static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
ca45cfe3 BH	538	{
	539	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
	540	}
	541	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
	542
82ba129b BH	543	static int pnv_pci_probe_mode(struct pci_bus *bus)
	544	{
	545	struct pci_controller *hose = pci_bus_to_host(bus);
	546	const __be64 *tstamp;
	547	u64 now, target;
	548
	549
	550	/* We hijack this as a way to ensure we have waited long
	551	* enough since the reset was lifted on the PCI bus
	552	*/
	553	if (bus != hose->bus)
	554	return PCI_PROBE_NORMAL;
	555	tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
	556	if (!tstamp \|\| !*tstamp)
	557	return PCI_PROBE_NORMAL;
	558
	559	now = mftb() / tb_ticks_per_usec;
	560	target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
	561	+ PCI_RESET_DELAY_US;
	562
	563	pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
	564	hose->global_number, target, now);
	565
	566	if (now < target)
	567	msleep((target - now + 999) / 1000);
	568
	569	return PCI_PROBE_NORMAL;
	570	}
	571
61305a96 BH	572	void __init pnv_pci_init(void)
	573	{
	574	struct device_node *np;
	575
673c9756	576	pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
61305a96 BH	577
	578	/* OPAL absent, try POPAL first then RTAS detection of PHBs */
	579	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
	580	#ifdef CONFIG_PPC_POWERNV_RTAS
	581	init_pci_config_tokens();
	582	find_and_init_phbs();
	583	#endif /* CONFIG_PPC_POWERNV_RTAS */
184cd4a3 BH	584	}
	585	/* OPAL is here, do our normal stuff */
	586	else {
	587	int found_ioda = 0;
	588
	589	/* Look for IODA IO-Hubs. We don't support mixing IODA
	590	* and p5ioc2 due to the need to change some global
	591	* probing flags
	592	*/
	593	for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
	594	pnv_pci_init_ioda_hub(np);
	595	found_ioda = 1;
	596	}
61305a96 BH	597
61305a96 BH	598	/* Look for p5ioc2 IO-Hubs */
184cd4a3 BH	599	if (!found_ioda)
	600	for_each_compatible_node(np, NULL, "ibm,p5ioc2")
	601	pnv_pci_init_p5ioc2_hub(np);
aa0c033f GS	602
	603	/* Look for ioda2 built-in PHB3's */
	604	for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
	605	pnv_pci_init_ioda2_phb(np);
61305a96 BH	606	}
	607
	608	/* Setup the linkage between OF nodes and PHBs */
	609	pci_devs_phb_init();
	610
	611	/* Configure IOMMU DMA hooks */
	612	ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
	613	ppc_md.tce_build = pnv_tce_build;
	614	ppc_md.tce_free = pnv_tce_free;
11f63d3f	615	ppc_md.tce_get = pnv_tce_get;
82ba129b	616	ppc_md.pci_probe_mode = pnv_pci_probe_mode;
61305a96 BH	617	set_pci_dma_ops(&dma_iommu_ops);
61305a96 BH	618
c1a2562a BH	619	/* Configure MSIs */
	620	#ifdef CONFIG_PCI_MSI
	621	ppc_md.msi_check_device = pnv_msi_check_device;
	622	ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
	623	ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
	624	#endif
61305a96	625	}