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61305a96 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Currently supports only P5IOC2 | |
5 | * | |
6 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/io.h> | |
c1a2562a | 22 | #include <linux/msi.h> |
4e13c1ac | 23 | #include <linux/iommu.h> |
61305a96 BH |
24 | |
25 | #include <asm/sections.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/prom.h> | |
28 | #include <asm/pci-bridge.h> | |
29 | #include <asm/machdep.h> | |
fb1b55d6 | 30 | #include <asm/msi_bitmap.h> |
61305a96 BH |
31 | #include <asm/ppc-pci.h> |
32 | #include <asm/opal.h> | |
33 | #include <asm/iommu.h> | |
34 | #include <asm/tce.h> | |
f5339277 | 35 | #include <asm/firmware.h> |
be7e7446 GS |
36 | #include <asm/eeh_event.h> |
37 | #include <asm/eeh.h> | |
61305a96 BH |
38 | |
39 | #include "powernv.h" | |
40 | #include "pci.h" | |
41 | ||
82ba129b BH |
42 | /* Delay in usec */ |
43 | #define PCI_RESET_DELAY_US 3000000 | |
61305a96 BH |
44 | |
45 | #define cfg_dbg(fmt...) do { } while(0) | |
46 | //#define cfg_dbg(fmt...) printk(fmt) | |
47 | ||
c1a2562a BH |
48 | #ifdef CONFIG_PCI_MSI |
49 | static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type) | |
50 | { | |
51 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
52 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 BH |
53 | struct pci_dn *pdn = pci_get_pdn(pdev); |
54 | ||
55 | if (pdn && pdn->force_32bit_msi && !phb->msi32_support) | |
56 | return -ENODEV; | |
c1a2562a | 57 | |
fb1b55d6 | 58 | return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV; |
c1a2562a BH |
59 | } |
60 | ||
61 | static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
62 | { | |
63 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
64 | struct pnv_phb *phb = hose->private_data; | |
65 | struct msi_desc *entry; | |
66 | struct msi_msg msg; | |
fb1b55d6 GS |
67 | int hwirq; |
68 | unsigned int virq; | |
c1a2562a BH |
69 | int rc; |
70 | ||
71 | if (WARN_ON(!phb)) | |
72 | return -ENODEV; | |
73 | ||
74 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
75 | if (!entry->msi_attrib.is_64 && !phb->msi32_support) { | |
76 | pr_warn("%s: Supports only 64-bit MSIs\n", | |
77 | pci_name(pdev)); | |
78 | return -ENXIO; | |
79 | } | |
fb1b55d6 GS |
80 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); |
81 | if (hwirq < 0) { | |
c1a2562a BH |
82 | pr_warn("%s: Failed to find a free MSI\n", |
83 | pci_name(pdev)); | |
84 | return -ENOSPC; | |
85 | } | |
fb1b55d6 | 86 | virq = irq_create_mapping(NULL, phb->msi_base + hwirq); |
c1a2562a BH |
87 | if (virq == NO_IRQ) { |
88 | pr_warn("%s: Failed to map MSI to linux irq\n", | |
89 | pci_name(pdev)); | |
fb1b55d6 | 90 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
91 | return -ENOMEM; |
92 | } | |
fb1b55d6 | 93 | rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, |
137436c9 | 94 | virq, entry->msi_attrib.is_64, &msg); |
c1a2562a BH |
95 | if (rc) { |
96 | pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); | |
97 | irq_dispose_mapping(virq); | |
fb1b55d6 | 98 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); |
c1a2562a BH |
99 | return rc; |
100 | } | |
101 | irq_set_msi_desc(virq, entry); | |
102 | write_msi_msg(virq, &msg); | |
103 | } | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void pnv_teardown_msi_irqs(struct pci_dev *pdev) | |
108 | { | |
109 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
110 | struct pnv_phb *phb = hose->private_data; | |
111 | struct msi_desc *entry; | |
112 | ||
113 | if (WARN_ON(!phb)) | |
114 | return; | |
115 | ||
116 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
117 | if (entry->irq == NO_IRQ) | |
118 | continue; | |
119 | irq_set_msi_desc(entry->irq, NULL); | |
fb1b55d6 GS |
120 | msi_bitmap_free_hwirqs(&phb->msi_bmp, |
121 | virq_to_hw(entry->irq) - phb->msi_base, 1); | |
c1a2562a BH |
122 | irq_dispose_mapping(entry->irq); |
123 | } | |
124 | } | |
125 | #endif /* CONFIG_PCI_MSI */ | |
61305a96 | 126 | |
93aef2a7 GS |
127 | static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, |
128 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 129 | { |
93aef2a7 | 130 | struct OpalIoP7IOCPhbErrorData *data; |
cee72d5b BH |
131 | int i; |
132 | ||
93aef2a7 GS |
133 | data = (struct OpalIoP7IOCPhbErrorData *)common; |
134 | pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n\n", | |
135 | hose->global_number, common->version); | |
136 | ||
137 | pr_info(" brdgCtl: %08x\n", data->brdgCtl); | |
138 | ||
139 | pr_info(" portStatusReg: %08x\n", data->portStatusReg); | |
140 | pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus); | |
141 | pr_info(" busAgentStatus: %08x\n", data->busAgentStatus); | |
142 | ||
143 | pr_info(" deviceStatus: %08x\n", data->deviceStatus); | |
144 | pr_info(" slotStatus: %08x\n", data->slotStatus); | |
145 | pr_info(" linkStatus: %08x\n", data->linkStatus); | |
146 | pr_info(" devCmdStatus: %08x\n", data->devCmdStatus); | |
147 | pr_info(" devSecStatus: %08x\n", data->devSecStatus); | |
148 | ||
149 | pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus); | |
150 | pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus); | |
151 | pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus); | |
152 | pr_info(" tlpHdr1: %08x\n", data->tlpHdr1); | |
153 | pr_info(" tlpHdr2: %08x\n", data->tlpHdr2); | |
154 | pr_info(" tlpHdr3: %08x\n", data->tlpHdr3); | |
155 | pr_info(" tlpHdr4: %08x\n", data->tlpHdr4); | |
156 | pr_info(" sourceId: %08x\n", data->sourceId); | |
157 | pr_info(" errorClass: %016llx\n", data->errorClass); | |
158 | pr_info(" correlator: %016llx\n", data->correlator); | |
159 | pr_info(" p7iocPlssr: %016llx\n", data->p7iocPlssr); | |
160 | pr_info(" p7iocCsr: %016llx\n", data->p7iocCsr); | |
161 | pr_info(" lemFir: %016llx\n", data->lemFir); | |
162 | pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask); | |
163 | pr_info(" lemWOF: %016llx\n", data->lemWOF); | |
164 | pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus); | |
165 | pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus); | |
166 | pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0); | |
167 | pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1); | |
168 | pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus); | |
169 | pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus); | |
170 | pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0); | |
171 | pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1); | |
172 | pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus); | |
173 | pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus); | |
174 | pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0); | |
175 | pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1); | |
176 | pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus); | |
177 | pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus); | |
178 | pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0); | |
179 | pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1); | |
cee72d5b BH |
180 | |
181 | for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { | |
182 | if ((data->pestA[i] >> 63) == 0 && | |
183 | (data->pestB[i] >> 63) == 0) | |
184 | continue; | |
93aef2a7 GS |
185 | |
186 | pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]); | |
187 | pr_info(" PESTB: %016llx\n", data->pestB[i]); | |
cee72d5b BH |
188 | } |
189 | } | |
190 | ||
93aef2a7 GS |
191 | static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, |
192 | struct OpalIoPhbErrorCommon *common) | |
cee72d5b | 193 | { |
93aef2a7 GS |
194 | struct OpalIoPhb3ErrorData *data; |
195 | int i; | |
196 | ||
197 | data = (struct OpalIoPhb3ErrorData*)common; | |
198 | pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n\n", | |
199 | hose->global_number, common->version); | |
200 | ||
201 | pr_info(" brdgCtl: %08x\n", data->brdgCtl); | |
202 | ||
203 | pr_info(" portStatusReg: %08x\n", data->portStatusReg); | |
204 | pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus); | |
205 | pr_info(" busAgentStatus: %08x\n", data->busAgentStatus); | |
206 | ||
207 | pr_info(" deviceStatus: %08x\n", data->deviceStatus); | |
208 | pr_info(" slotStatus: %08x\n", data->slotStatus); | |
209 | pr_info(" linkStatus: %08x\n", data->linkStatus); | |
210 | pr_info(" devCmdStatus: %08x\n", data->devCmdStatus); | |
211 | pr_info(" devSecStatus: %08x\n", data->devSecStatus); | |
212 | ||
213 | pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus); | |
214 | pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus); | |
215 | pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus); | |
216 | pr_info(" tlpHdr1: %08x\n", data->tlpHdr1); | |
217 | pr_info(" tlpHdr2: %08x\n", data->tlpHdr2); | |
218 | pr_info(" tlpHdr3: %08x\n", data->tlpHdr3); | |
219 | pr_info(" tlpHdr4: %08x\n", data->tlpHdr4); | |
220 | pr_info(" sourceId: %08x\n", data->sourceId); | |
221 | pr_info(" errorClass: %016llx\n", data->errorClass); | |
222 | pr_info(" correlator: %016llx\n", data->correlator); | |
223 | ||
224 | pr_info(" nFir: %016llx\n", data->nFir); | |
225 | pr_info(" nFirMask: %016llx\n", data->nFirMask); | |
226 | pr_info(" nFirWOF: %016llx\n", data->nFirWOF); | |
227 | pr_info(" PhbPlssr: %016llx\n", data->phbPlssr); | |
228 | pr_info(" PhbCsr: %016llx\n", data->phbCsr); | |
229 | pr_info(" lemFir: %016llx\n", data->lemFir); | |
230 | pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask); | |
231 | pr_info(" lemWOF: %016llx\n", data->lemWOF); | |
232 | pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus); | |
233 | pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus); | |
234 | pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0); | |
235 | pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1); | |
236 | pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus); | |
237 | pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus); | |
238 | pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0); | |
239 | pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1); | |
240 | pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus); | |
241 | pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus); | |
242 | pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0); | |
243 | pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1); | |
244 | pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus); | |
245 | pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus); | |
246 | pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0); | |
247 | pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1); | |
248 | ||
249 | for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { | |
250 | if ((data->pestA[i] >> 63) == 0 && | |
251 | (data->pestB[i] >> 63) == 0) | |
252 | continue; | |
253 | ||
254 | pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]); | |
255 | pr_info(" PESTB: %016llx\n", data->pestB[i]); | |
256 | } | |
257 | } | |
258 | ||
259 | void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, | |
260 | unsigned char *log_buff) | |
261 | { | |
262 | struct OpalIoPhbErrorCommon *common; | |
263 | ||
264 | if (!hose || !log_buff) | |
265 | return; | |
266 | ||
267 | common = (struct OpalIoPhbErrorCommon *)log_buff; | |
268 | switch (common->ioType) { | |
269 | case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: | |
270 | pnv_pci_dump_p7ioc_diag_data(hose, common); | |
271 | break; | |
272 | case OPAL_PHB_ERROR_DATA_TYPE_PHB3: | |
273 | pnv_pci_dump_phb3_diag_data(hose, common); | |
cee72d5b BH |
274 | break; |
275 | default: | |
93aef2a7 GS |
276 | pr_warn("%s: Unrecognized ioType %d\n", |
277 | __func__, common->ioType); | |
cee72d5b BH |
278 | } |
279 | } | |
280 | ||
281 | static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) | |
282 | { | |
283 | unsigned long flags, rc; | |
284 | int has_diag; | |
285 | ||
286 | spin_lock_irqsave(&phb->lock, flags); | |
287 | ||
23773230 GS |
288 | rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, |
289 | PNV_PCI_DIAG_BUF_SIZE); | |
cee72d5b BH |
290 | has_diag = (rc == OPAL_SUCCESS); |
291 | ||
292 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, | |
293 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
294 | if (rc) { | |
295 | pr_warning("PCI %d: Failed to clear EEH freeze state" | |
296 | " for PE#%d, err %ld\n", | |
297 | phb->hose->global_number, pe_no, rc); | |
298 | ||
299 | /* For now, let's only display the diag buffer when we fail to clear | |
300 | * the EEH status. We'll do more sensible things later when we have | |
301 | * proper EEH support. We need to make sure we don't pollute ourselves | |
302 | * with the normal errors generated when probing empty slots | |
303 | */ | |
304 | if (has_diag) | |
93aef2a7 | 305 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); |
cee72d5b BH |
306 | else |
307 | pr_warning("PCI %d: No diag data available\n", | |
308 | phb->hose->global_number); | |
309 | } | |
310 | ||
311 | spin_unlock_irqrestore(&phb->lock, flags); | |
312 | } | |
313 | ||
9bf41be6 GS |
314 | static void pnv_pci_config_check_eeh(struct pnv_phb *phb, |
315 | struct device_node *dn) | |
61305a96 BH |
316 | { |
317 | s64 rc; | |
318 | u8 fstate; | |
3a1a4661 | 319 | __be16 pcierr; |
61305a96 BH |
320 | u32 pe_no; |
321 | ||
9bf41be6 GS |
322 | /* |
323 | * Get the PE#. During the PCI probe stage, we might not | |
324 | * setup that yet. So all ER errors should be mapped to | |
36954dc7 | 325 | * reserved PE. |
9bf41be6 GS |
326 | */ |
327 | pe_no = PCI_DN(dn)->pe_number; | |
36954dc7 GS |
328 | if (pe_no == IODA_INVALID_PE) { |
329 | if (phb->type == PNV_PHB_P5IOC2) | |
330 | pe_no = 0; | |
331 | else | |
332 | pe_no = phb->ioda.reserved_pe; | |
333 | } | |
61305a96 BH |
334 | |
335 | /* Read freeze status */ | |
336 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr, | |
337 | NULL); | |
338 | if (rc) { | |
9bf41be6 GS |
339 | pr_warning("%s: Can't read EEH status (PE#%d) for " |
340 | "%s, err %lld\n", | |
341 | __func__, pe_no, dn->full_name, rc); | |
61305a96 BH |
342 | return; |
343 | } | |
9bf41be6 GS |
344 | cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", |
345 | (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn), | |
346 | pe_no, fstate); | |
cee72d5b BH |
347 | if (fstate != 0) |
348 | pnv_pci_handle_eeh_config(phb, pe_no); | |
61305a96 BH |
349 | } |
350 | ||
9bf41be6 GS |
351 | int pnv_pci_cfg_read(struct device_node *dn, |
352 | int where, int size, u32 *val) | |
61305a96 | 353 | { |
9bf41be6 GS |
354 | struct pci_dn *pdn = PCI_DN(dn); |
355 | struct pnv_phb *phb = pdn->phb->private_data; | |
356 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
be7e7446 | 357 | #ifdef CONFIG_EEH |
be7e7446 GS |
358 | struct eeh_pe *phb_pe = NULL; |
359 | #endif | |
61305a96 BH |
360 | s64 rc; |
361 | ||
61305a96 BH |
362 | switch (size) { |
363 | case 1: { | |
364 | u8 v8; | |
365 | rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); | |
366 | *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; | |
367 | break; | |
368 | } | |
369 | case 2: { | |
3a1a4661 | 370 | __be16 v16; |
61305a96 BH |
371 | rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, |
372 | &v16); | |
3a1a4661 | 373 | *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; |
61305a96 BH |
374 | break; |
375 | } | |
376 | case 4: { | |
3a1a4661 | 377 | __be32 v32; |
61305a96 | 378 | rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); |
3a1a4661 | 379 | *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; |
61305a96 BH |
380 | break; |
381 | } | |
382 | default: | |
383 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
384 | } | |
9bf41be6 GS |
385 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
386 | __func__, pdn->busno, pdn->devfn, where, size, *val); | |
61305a96 | 387 | |
be7e7446 GS |
388 | /* |
389 | * Check if the specified PE has been put into frozen | |
390 | * state. On the other hand, we needn't do that while | |
391 | * the PHB has been put into frozen state because of | |
392 | * PHB-fatal errors. | |
393 | */ | |
394 | #ifdef CONFIG_EEH | |
9bf41be6 | 395 | phb_pe = eeh_phb_pe_get(pdn->phb); |
be7e7446 GS |
396 | if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED)) |
397 | return PCIBIOS_SUCCESSFUL; | |
398 | ||
0b9e267d | 399 | if (phb->eeh_state & PNV_EEH_STATE_ENABLED) { |
9bf41be6 GS |
400 | if (*val == EEH_IO_ERROR_VALUE(size) && |
401 | eeh_dev_check_failure(of_node_to_eeh_dev(dn))) | |
402 | return PCIBIOS_DEVICE_NOT_FOUND; | |
be7e7446 | 403 | } else { |
9bf41be6 | 404 | pnv_pci_config_check_eeh(phb, dn); |
be7e7446 GS |
405 | } |
406 | #else | |
9bf41be6 | 407 | pnv_pci_config_check_eeh(phb, dn); |
be7e7446 | 408 | #endif |
61305a96 BH |
409 | |
410 | return PCIBIOS_SUCCESSFUL; | |
411 | } | |
412 | ||
9bf41be6 GS |
413 | int pnv_pci_cfg_write(struct device_node *dn, |
414 | int where, int size, u32 val) | |
61305a96 | 415 | { |
9bf41be6 GS |
416 | struct pci_dn *pdn = PCI_DN(dn); |
417 | struct pnv_phb *phb = pdn->phb->private_data; | |
418 | u32 bdfn = (pdn->busno << 8) | pdn->devfn; | |
61305a96 | 419 | |
9bf41be6 GS |
420 | cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", |
421 | pdn->busno, pdn->devfn, where, size, val); | |
61305a96 BH |
422 | switch (size) { |
423 | case 1: | |
424 | opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); | |
425 | break; | |
426 | case 2: | |
427 | opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); | |
428 | break; | |
429 | case 4: | |
430 | opal_pci_config_write_word(phb->opal_id, bdfn, where, val); | |
431 | break; | |
432 | default: | |
433 | return PCIBIOS_FUNC_NOT_SUPPORTED; | |
434 | } | |
be7e7446 | 435 | |
61305a96 | 436 | /* Check if the PHB got frozen due to an error (no response) */ |
be7e7446 | 437 | #ifdef CONFIG_EEH |
0b9e267d | 438 | if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED)) |
9bf41be6 | 439 | pnv_pci_config_check_eeh(phb, dn); |
be7e7446 | 440 | #else |
9bf41be6 | 441 | pnv_pci_config_check_eeh(phb, dn); |
be7e7446 | 442 | #endif |
61305a96 BH |
443 | |
444 | return PCIBIOS_SUCCESSFUL; | |
445 | } | |
446 | ||
9bf41be6 GS |
447 | static int pnv_pci_read_config(struct pci_bus *bus, |
448 | unsigned int devfn, | |
449 | int where, int size, u32 *val) | |
450 | { | |
451 | struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); | |
452 | struct pci_dn *pdn; | |
453 | ||
454 | for (dn = busdn->child; dn; dn = dn->sibling) { | |
455 | pdn = PCI_DN(dn); | |
456 | if (pdn && pdn->devfn == devfn) | |
457 | return pnv_pci_cfg_read(dn, where, size, val); | |
458 | } | |
459 | ||
460 | *val = 0xFFFFFFFF; | |
461 | return PCIBIOS_DEVICE_NOT_FOUND; | |
462 | ||
463 | } | |
464 | ||
465 | static int pnv_pci_write_config(struct pci_bus *bus, | |
466 | unsigned int devfn, | |
467 | int where, int size, u32 val) | |
468 | { | |
469 | struct device_node *dn, *busdn = pci_bus_to_OF_node(bus); | |
470 | struct pci_dn *pdn; | |
471 | ||
472 | for (dn = busdn->child; dn; dn = dn->sibling) { | |
473 | pdn = PCI_DN(dn); | |
474 | if (pdn && pdn->devfn == devfn) | |
475 | return pnv_pci_cfg_write(dn, where, size, val); | |
476 | } | |
477 | ||
478 | return PCIBIOS_DEVICE_NOT_FOUND; | |
479 | } | |
480 | ||
61305a96 | 481 | struct pci_ops pnv_pci_ops = { |
9bf41be6 | 482 | .read = pnv_pci_read_config, |
61305a96 BH |
483 | .write = pnv_pci_write_config, |
484 | }; | |
485 | ||
486 | static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, | |
487 | unsigned long uaddr, enum dma_data_direction direction, | |
8e0a1611 | 488 | struct dma_attrs *attrs, bool rm) |
61305a96 BH |
489 | { |
490 | u64 proto_tce; | |
3a1a4661 | 491 | __be64 *tcep, *tces; |
61305a96 BH |
492 | u64 rpn; |
493 | ||
494 | proto_tce = TCE_PCI_READ; // Read allowed | |
495 | ||
496 | if (direction != DMA_TO_DEVICE) | |
497 | proto_tce |= TCE_PCI_WRITE; | |
498 | ||
5e4da530 | 499 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
1f1616e8 | 500 | rpn = __pa(uaddr) >> TCE_SHIFT; |
61305a96 | 501 | |
1f1616e8 | 502 | while (npages--) |
3a1a4661 | 503 | *(tcep++) = cpu_to_be64(proto_tce | (rpn++ << TCE_RPN_SHIFT)); |
1f1616e8 BH |
504 | |
505 | /* Some implementations won't cache invalid TCEs and thus may not | |
506 | * need that flush. We'll probably turn it_type into a bit mask | |
507 | * of flags if that becomes the case | |
508 | */ | |
509 | if (tbl->it_type & TCE_PCI_SWINV_CREATE) | |
8e0a1611 | 510 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
61305a96 | 511 | |
61305a96 BH |
512 | return 0; |
513 | } | |
514 | ||
8e0a1611 AK |
515 | static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages, |
516 | unsigned long uaddr, | |
517 | enum dma_data_direction direction, | |
518 | struct dma_attrs *attrs) | |
519 | { | |
520 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, | |
521 | false); | |
522 | } | |
523 | ||
524 | static void pnv_tce_free(struct iommu_table *tbl, long index, long npages, | |
525 | bool rm) | |
61305a96 | 526 | { |
3a1a4661 | 527 | __be64 *tcep, *tces; |
1f1616e8 | 528 | |
5e4da530 | 529 | tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; |
61305a96 BH |
530 | |
531 | while (npages--) | |
3a1a4661 | 532 | *(tcep++) = cpu_to_be64(0); |
1f1616e8 | 533 | |
605e44d6 | 534 | if (tbl->it_type & TCE_PCI_SWINV_FREE) |
8e0a1611 AK |
535 | pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); |
536 | } | |
537 | ||
538 | static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages) | |
539 | { | |
540 | pnv_tce_free(tbl, index, npages, false); | |
61305a96 BH |
541 | } |
542 | ||
11f63d3f AK |
543 | static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) |
544 | { | |
545 | return ((u64 *)tbl->it_base)[index - tbl->it_offset]; | |
546 | } | |
547 | ||
8e0a1611 AK |
548 | static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages, |
549 | unsigned long uaddr, | |
550 | enum dma_data_direction direction, | |
551 | struct dma_attrs *attrs) | |
552 | { | |
553 | return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true); | |
554 | } | |
555 | ||
556 | static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages) | |
557 | { | |
558 | pnv_tce_free(tbl, index, npages, true); | |
559 | } | |
560 | ||
61305a96 BH |
561 | void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
562 | void *tce_mem, u64 tce_size, | |
563 | u64 dma_offset) | |
564 | { | |
565 | tbl->it_blocksize = 16; | |
566 | tbl->it_base = (unsigned long)tce_mem; | |
e589a440 | 567 | tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT_4K; |
61305a96 BH |
568 | tbl->it_index = 0; |
569 | tbl->it_size = tce_size >> 3; | |
570 | tbl->it_busno = 0; | |
571 | tbl->it_type = TCE_PCI; | |
572 | } | |
573 | ||
cad5cef6 | 574 | static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose) |
61305a96 BH |
575 | { |
576 | struct iommu_table *tbl; | |
3a1a4661 BH |
577 | const __be64 *basep, *swinvp; |
578 | const __be32 *sizep; | |
61305a96 BH |
579 | |
580 | basep = of_get_property(hose->dn, "linux,tce-base", NULL); | |
581 | sizep = of_get_property(hose->dn, "linux,tce-size", NULL); | |
582 | if (basep == NULL || sizep == NULL) { | |
1f1616e8 BH |
583 | pr_err("PCI: %s has missing tce entries !\n", |
584 | hose->dn->full_name); | |
61305a96 BH |
585 | return NULL; |
586 | } | |
587 | tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node); | |
588 | if (WARN_ON(!tbl)) | |
589 | return NULL; | |
590 | pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)), | |
591 | be32_to_cpup(sizep), 0); | |
592 | iommu_init_table(tbl, hose->node); | |
4e13c1ac | 593 | iommu_register_group(tbl, pci_domain_nr(hose->bus), 0); |
1f1616e8 BH |
594 | |
595 | /* Deal with SW invalidated TCEs when needed (BML way) */ | |
596 | swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info", | |
597 | NULL); | |
598 | if (swinvp) { | |
5e4da530 | 599 | tbl->it_busno = be64_to_cpu(swinvp[1]); |
3a1a4661 | 600 | tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8); |
1f1616e8 BH |
601 | tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE; |
602 | } | |
61305a96 BH |
603 | return tbl; |
604 | } | |
605 | ||
cad5cef6 GKH |
606 | static void pnv_pci_dma_fallback_setup(struct pci_controller *hose, |
607 | struct pci_dev *pdev) | |
61305a96 BH |
608 | { |
609 | struct device_node *np = pci_bus_to_OF_node(hose->bus); | |
610 | struct pci_dn *pdn; | |
611 | ||
612 | if (np == NULL) | |
613 | return; | |
614 | pdn = PCI_DN(np); | |
615 | if (!pdn->iommu_table) | |
616 | pdn->iommu_table = pnv_pci_setup_bml_iommu(hose); | |
617 | if (!pdn->iommu_table) | |
618 | return; | |
d905c5df | 619 | set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table); |
61305a96 BH |
620 | } |
621 | ||
cad5cef6 | 622 | static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) |
61305a96 BH |
623 | { |
624 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); | |
625 | struct pnv_phb *phb = hose->private_data; | |
626 | ||
627 | /* If we have no phb structure, try to setup a fallback based on | |
628 | * the device-tree (RTAS PCI for example) | |
629 | */ | |
630 | if (phb && phb->dma_dev_setup) | |
631 | phb->dma_dev_setup(phb, pdev); | |
632 | else | |
633 | pnv_pci_dma_fallback_setup(hose, pdev); | |
634 | } | |
635 | ||
73ed148a BH |
636 | void pnv_pci_shutdown(void) |
637 | { | |
638 | struct pci_controller *hose; | |
639 | ||
640 | list_for_each_entry(hose, &hose_list, list_node) { | |
641 | struct pnv_phb *phb = hose->private_data; | |
642 | ||
643 | if (phb && phb->shutdown) | |
644 | phb->shutdown(phb); | |
645 | } | |
646 | } | |
647 | ||
aa0c033f | 648 | /* Fixup wrong class code in p7ioc and p8 root complex */ |
cad5cef6 | 649 | static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) |
ca45cfe3 BH |
650 | { |
651 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
652 | } | |
653 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); | |
654 | ||
82ba129b BH |
655 | static int pnv_pci_probe_mode(struct pci_bus *bus) |
656 | { | |
657 | struct pci_controller *hose = pci_bus_to_host(bus); | |
658 | const __be64 *tstamp; | |
659 | u64 now, target; | |
660 | ||
661 | ||
662 | /* We hijack this as a way to ensure we have waited long | |
663 | * enough since the reset was lifted on the PCI bus | |
664 | */ | |
665 | if (bus != hose->bus) | |
666 | return PCI_PROBE_NORMAL; | |
667 | tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL); | |
668 | if (!tstamp || !*tstamp) | |
669 | return PCI_PROBE_NORMAL; | |
670 | ||
671 | now = mftb() / tb_ticks_per_usec; | |
672 | target = (be64_to_cpup(tstamp) / tb_ticks_per_usec) | |
673 | + PCI_RESET_DELAY_US; | |
674 | ||
675 | pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n", | |
676 | hose->global_number, target, now); | |
677 | ||
678 | if (now < target) | |
679 | msleep((target - now + 999) / 1000); | |
680 | ||
681 | return PCI_PROBE_NORMAL; | |
682 | } | |
683 | ||
61305a96 BH |
684 | void __init pnv_pci_init(void) |
685 | { | |
686 | struct device_node *np; | |
687 | ||
673c9756 | 688 | pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); |
61305a96 BH |
689 | |
690 | /* OPAL absent, try POPAL first then RTAS detection of PHBs */ | |
691 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { | |
692 | #ifdef CONFIG_PPC_POWERNV_RTAS | |
693 | init_pci_config_tokens(); | |
694 | find_and_init_phbs(); | |
695 | #endif /* CONFIG_PPC_POWERNV_RTAS */ | |
184cd4a3 BH |
696 | } |
697 | /* OPAL is here, do our normal stuff */ | |
698 | else { | |
699 | int found_ioda = 0; | |
700 | ||
701 | /* Look for IODA IO-Hubs. We don't support mixing IODA | |
702 | * and p5ioc2 due to the need to change some global | |
703 | * probing flags | |
704 | */ | |
705 | for_each_compatible_node(np, NULL, "ibm,ioda-hub") { | |
706 | pnv_pci_init_ioda_hub(np); | |
707 | found_ioda = 1; | |
708 | } | |
61305a96 BH |
709 | |
710 | /* Look for p5ioc2 IO-Hubs */ | |
184cd4a3 BH |
711 | if (!found_ioda) |
712 | for_each_compatible_node(np, NULL, "ibm,p5ioc2") | |
713 | pnv_pci_init_p5ioc2_hub(np); | |
aa0c033f GS |
714 | |
715 | /* Look for ioda2 built-in PHB3's */ | |
716 | for_each_compatible_node(np, NULL, "ibm,ioda2-phb") | |
717 | pnv_pci_init_ioda2_phb(np); | |
61305a96 BH |
718 | } |
719 | ||
720 | /* Setup the linkage between OF nodes and PHBs */ | |
721 | pci_devs_phb_init(); | |
722 | ||
723 | /* Configure IOMMU DMA hooks */ | |
724 | ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup; | |
8e0a1611 AK |
725 | ppc_md.tce_build = pnv_tce_build_vm; |
726 | ppc_md.tce_free = pnv_tce_free_vm; | |
727 | ppc_md.tce_build_rm = pnv_tce_build_rm; | |
728 | ppc_md.tce_free_rm = pnv_tce_free_rm; | |
11f63d3f | 729 | ppc_md.tce_get = pnv_tce_get; |
82ba129b | 730 | ppc_md.pci_probe_mode = pnv_pci_probe_mode; |
61305a96 BH |
731 | set_pci_dma_ops(&dma_iommu_ops); |
732 | ||
c1a2562a BH |
733 | /* Configure MSIs */ |
734 | #ifdef CONFIG_PCI_MSI | |
735 | ppc_md.msi_check_device = pnv_msi_check_device; | |
736 | ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; | |
737 | ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; | |
738 | #endif | |
61305a96 | 739 | } |
d905c5df AK |
740 | |
741 | static int tce_iommu_bus_notifier(struct notifier_block *nb, | |
742 | unsigned long action, void *data) | |
743 | { | |
744 | struct device *dev = data; | |
745 | ||
746 | switch (action) { | |
747 | case BUS_NOTIFY_ADD_DEVICE: | |
748 | return iommu_add_device(dev); | |
749 | case BUS_NOTIFY_DEL_DEVICE: | |
750 | if (dev->iommu_group) | |
751 | iommu_del_device(dev); | |
752 | return 0; | |
753 | default: | |
754 | return 0; | |
755 | } | |
756 | } | |
757 | ||
758 | static struct notifier_block tce_iommu_bus_nb = { | |
759 | .notifier_call = tce_iommu_bus_notifier, | |
760 | }; | |
761 | ||
762 | static int __init tce_iommu_bus_notifier_init(void) | |
763 | { | |
e589a440 | 764 | BUILD_BUG_ON(PAGE_SIZE < IOMMU_PAGE_SIZE_4K); |
d905c5df AK |
765 | |
766 | bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb); | |
767 | return 0; | |
768 | } | |
769 | ||
770 | subsys_initcall_sync(tce_iommu_bus_notifier_init); |