[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / platforms / powernv / pci.c

/*
 * Support PCI/PCIe on PowerNV platforms
 *
 * Currently supports only P5IOC2
 *
 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/msi.h>
#include <linux/iommu.h>

#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <asm/msi_bitmap.h>
#include <asm/ppc-pci.h>
#include <asm/opal.h>
#include <asm/iommu.h>
#include <asm/tce.h>
#include <asm/firmware.h>

#include "powernv.h"
#include "pci.h"

/* Delay in usec */
#define PCI_RESET_DELAY_US	3000000

#define cfg_dbg(fmt...)	do { } while(0)
//#define cfg_dbg(fmt...)	printk(fmt)

#ifdef CONFIG_PCI_MSI
static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct pci_dn *pdn = pci_get_pdn(pdev);

	if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
		return -ENODEV;

	return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
}

static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct msi_desc *entry;
	struct msi_msg msg;
	int hwirq;
	unsigned int virq;
	int rc;

	if (WARN_ON(!phb))
		return -ENODEV;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
			pr_warn("%s: Supports only 64-bit MSIs\n",
				pci_name(pdev));
			return -ENXIO;
		}
		hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
		if (hwirq < 0) {
			pr_warn("%s: Failed to find a free MSI\n",
				pci_name(pdev));
			return -ENOSPC;
		}
		virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
		if (virq == NO_IRQ) {
			pr_warn("%s: Failed to map MSI to linux irq\n",
				pci_name(pdev));
			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
			return -ENOMEM;
		}
		rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
				    virq, entry->msi_attrib.is_64, &msg);
		if (rc) {
			pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
			irq_dispose_mapping(virq);
			msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
			return rc;
		}
		irq_set_msi_desc(virq, entry);
		write_msi_msg(virq, &msg);
	}
	return 0;
}

static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct msi_desc *entry;

	if (WARN_ON(!phb))
		return;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
		irq_set_msi_desc(entry->irq, NULL);
		msi_bitmap_free_hwirqs(&phb->msi_bmp,
			virq_to_hw(entry->irq) - phb->msi_base, 1);
		irq_dispose_mapping(entry->irq);
	}
}
#endif /* CONFIG_PCI_MSI */

static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
{
	struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
	int i;

	pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);

	pr_info("  brdgCtl              = 0x%08x\n", data->brdgCtl);

	pr_info("  portStatusReg        = 0x%08x\n", data->portStatusReg);
	pr_info("  rootCmplxStatus      = 0x%08x\n", data->rootCmplxStatus);
	pr_info("  busAgentStatus       = 0x%08x\n", data->busAgentStatus);

	pr_info("  deviceStatus         = 0x%08x\n", data->deviceStatus);
	pr_info("  slotStatus           = 0x%08x\n", data->slotStatus);
	pr_info("  linkStatus           = 0x%08x\n", data->linkStatus);
	pr_info("  devCmdStatus         = 0x%08x\n", data->devCmdStatus);
	pr_info("  devSecStatus         = 0x%08x\n", data->devSecStatus);

	pr_info("  rootErrorStatus      = 0x%08x\n", data->rootErrorStatus);
	pr_info("  uncorrErrorStatus    = 0x%08x\n", data->uncorrErrorStatus);
	pr_info("  corrErrorStatus      = 0x%08x\n", data->corrErrorStatus);
	pr_info("  tlpHdr1              = 0x%08x\n", data->tlpHdr1);
	pr_info("  tlpHdr2              = 0x%08x\n", data->tlpHdr2);
	pr_info("  tlpHdr3              = 0x%08x\n", data->tlpHdr3);
	pr_info("  tlpHdr4              = 0x%08x\n", data->tlpHdr4);
	pr_info("  sourceId             = 0x%08x\n", data->sourceId);

	pr_info("  errorClass           = 0x%016llx\n", data->errorClass);
	pr_info("  correlator           = 0x%016llx\n", data->correlator);

	pr_info("  p7iocPlssr           = 0x%016llx\n", data->p7iocPlssr);
	pr_info("  p7iocCsr             = 0x%016llx\n", data->p7iocCsr);
	pr_info("  lemFir               = 0x%016llx\n", data->lemFir);
	pr_info("  lemErrorMask         = 0x%016llx\n", data->lemErrorMask);
	pr_info("  lemWOF               = 0x%016llx\n", data->lemWOF);
	pr_info("  phbErrorStatus       = 0x%016llx\n", data->phbErrorStatus);
	pr_info("  phbFirstErrorStatus  = 0x%016llx\n", data->phbFirstErrorStatus);
	pr_info("  phbErrorLog0         = 0x%016llx\n", data->phbErrorLog0);
	pr_info("  phbErrorLog1         = 0x%016llx\n", data->phbErrorLog1);
	pr_info("  mmioErrorStatus      = 0x%016llx\n", data->mmioErrorStatus);
	pr_info("  mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
	pr_info("  mmioErrorLog0        = 0x%016llx\n", data->mmioErrorLog0);
	pr_info("  mmioErrorLog1        = 0x%016llx\n", data->mmioErrorLog1);
	pr_info("  dma0ErrorStatus      = 0x%016llx\n", data->dma0ErrorStatus);
	pr_info("  dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
	pr_info("  dma0ErrorLog0        = 0x%016llx\n", data->dma0ErrorLog0);
	pr_info("  dma0ErrorLog1        = 0x%016llx\n", data->dma0ErrorLog1);
	pr_info("  dma1ErrorStatus      = 0x%016llx\n", data->dma1ErrorStatus);
	pr_info("  dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
	pr_info("  dma1ErrorLog0        = 0x%016llx\n", data->dma1ErrorLog0);
	pr_info("  dma1ErrorLog1        = 0x%016llx\n", data->dma1ErrorLog1);

	for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
		if ((data->pestA[i] >> 63) == 0 &&
		    (data->pestB[i] >> 63) == 0)
			continue;
		pr_info("  PE[%3d] PESTA        = 0x%016llx\n", i, data->pestA[i]);
		pr_info("          PESTB        = 0x%016llx\n", data->pestB[i]);
	}
}

static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
{
	switch(phb->model) {
	case PNV_PHB_MODEL_P7IOC:
		pnv_pci_dump_p7ioc_diag_data(phb);
		break;
	default:
		pr_warning("PCI %d: Can't decode this PHB diag data\n",
			   phb->hose->global_number);
	}
}

static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
{
	unsigned long flags, rc;
	int has_diag;

	spin_lock_irqsave(&phb->lock, flags);

	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
					 PNV_PCI_DIAG_BUF_SIZE);
	has_diag = (rc == OPAL_SUCCESS);

	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
				       OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
	if (rc) {
		pr_warning("PCI %d: Failed to clear EEH freeze state"
			   " for PE#%d, err %ld\n",
			   phb->hose->global_number, pe_no, rc);

		/* For now, let's only display the diag buffer when we fail to clear
		 * the EEH status. We'll do more sensible things later when we have
		 * proper EEH support. We need to make sure we don't pollute ourselves
		 * with the normal errors generated when probing empty slots
		 */
		if (has_diag)
			pnv_pci_dump_phb_diag_data(phb);
		else
			pr_warning("PCI %d: No diag data available\n",
				   phb->hose->global_number);
	}

	spin_unlock_irqrestore(&phb->lock, flags);
}

static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
				     u32 bdfn)
{
	s64	rc;
	u8	fstate;
	u16	pcierr;
	u32	pe_no;

	/* Get PE# if we support IODA */
	pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;

	/* Read freeze status */
	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
					NULL);
	if (rc) {
		pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
			   " err %lld\n", phb->hose->global_number, pe_no, rc);
		return;
	}
	cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
		bdfn, pe_no, fstate);
	if (fstate != 0)
		pnv_pci_handle_eeh_config(phb, pe_no);
}

static int pnv_pci_read_config(struct pci_bus *bus,
			       unsigned int devfn,
			       int where, int size, u32 *val)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	struct pnv_phb *phb = hose->private_data;
	u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
	s64 rc;

	if (hose == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	switch (size) {
	case 1: {
		u8 v8;
		rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
		*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
		break;
	}
	case 2: {
		u16 v16;
		rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
						   &v16);
		*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
		break;
	}
	case 4: {
		u32 v32;
		rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
		*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
		break;
	}
	default:
		return PCIBIOS_FUNC_NOT_SUPPORTED;
	}
	cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
		bus->number, devfn, where, size, *val);

	/* Check if the PHB got frozen due to an error (no response) */
	pnv_pci_config_check_eeh(phb, bus, bdfn);

	return PCIBIOS_SUCCESSFUL;
}

static int pnv_pci_write_config(struct pci_bus *bus,
				unsigned int devfn,
				int where, int size, u32 val)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	struct pnv_phb *phb = hose->private_data;
	u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;

	if (hose == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
		bus->number, devfn, where, size, val);
	switch (size) {
	case 1:
		opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
		break;
	case 2:
		opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
		break;
	case 4:
		opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
		break;
	default:
		return PCIBIOS_FUNC_NOT_SUPPORTED;
	}
	/* Check if the PHB got frozen due to an error (no response) */
	pnv_pci_config_check_eeh(phb, bus, bdfn);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops pnv_pci_ops = {
	.read = pnv_pci_read_config,
	.write = pnv_pci_write_config,
};

static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
			 unsigned long uaddr, enum dma_data_direction direction,
			 struct dma_attrs *attrs)
{
	u64 proto_tce;
	u64 *tcep, *tces;
	u64 rpn;

	proto_tce = TCE_PCI_READ; // Read allowed

	if (direction != DMA_TO_DEVICE)
		proto_tce |= TCE_PCI_WRITE;

	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
	rpn = __pa(uaddr) >> TCE_SHIFT;

	while (npages--)
		*(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);

	/* Some implementations won't cache invalid TCEs and thus may not
	 * need that flush. We'll probably turn it_type into a bit mask
	 * of flags if that becomes the case
	 */
	if (tbl->it_type & TCE_PCI_SWINV_CREATE)
		pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);

	return 0;
}

static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
{
	u64 *tcep, *tces;

	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;

	while (npages--)
		*(tcep++) = 0;

	if (tbl->it_type & TCE_PCI_SWINV_FREE)
		pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
}

static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
{
	return ((u64 *)tbl->it_base)[index - tbl->it_offset];
}

void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
			       void *tce_mem, u64 tce_size,
			       u64 dma_offset)
{
	tbl->it_blocksize = 16;
	tbl->it_base = (unsigned long)tce_mem;
	tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
	tbl->it_index = 0;
	tbl->it_size = tce_size >> 3;
	tbl->it_busno = 0;
	tbl->it_type = TCE_PCI;
}

static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
{
	struct iommu_table *tbl;
	const __be64 *basep, *swinvp;
	const __be32 *sizep;

	basep = of_get_property(hose->dn, "linux,tce-base", NULL);
	sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
	if (basep == NULL || sizep == NULL) {
		pr_err("PCI: %s has missing tce entries !\n",
		       hose->dn->full_name);
		return NULL;
	}
	tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
	if (WARN_ON(!tbl))
		return NULL;
	pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
				  be32_to_cpup(sizep), 0);
	iommu_init_table(tbl, hose->node);
	iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);

	/* Deal with SW invalidated TCEs when needed (BML way) */
	swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
				 NULL);
	if (swinvp) {
		tbl->it_busno = swinvp[1];
		tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
		tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
	}
	return tbl;
}

static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
				       struct pci_dev *pdev)
{
	struct device_node *np = pci_bus_to_OF_node(hose->bus);
	struct pci_dn *pdn;

	if (np == NULL)
		return;
	pdn = PCI_DN(np);
	if (!pdn->iommu_table)
		pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
	if (!pdn->iommu_table)
		return;
	set_iommu_table_base(&pdev->dev, pdn->iommu_table);
}

static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;

	/* If we have no phb structure, try to setup a fallback based on
	 * the device-tree (RTAS PCI for example)
	 */
	if (phb && phb->dma_dev_setup)
		phb->dma_dev_setup(phb, pdev);
	else
		pnv_pci_dma_fallback_setup(hose, pdev);
}

void pnv_pci_shutdown(void)
{
	struct pci_controller *hose;

	list_for_each_entry(hose, &hose_list, list_node) {
		struct pnv_phb *phb = hose->private_data;

		if (phb && phb->shutdown)
			phb->shutdown(phb);
	}
}

/* Fixup wrong class code in p7ioc and p8 root complex */
static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);

static int pnv_pci_probe_mode(struct pci_bus *bus)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	const __be64 *tstamp;
	u64 now, target;


	/* We hijack this as a way to ensure we have waited long
	 * enough since the reset was lifted on the PCI bus
	 */
	if (bus != hose->bus)
		return PCI_PROBE_NORMAL;
	tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
	if (!tstamp || !*tstamp)
		return PCI_PROBE_NORMAL;

	now = mftb() / tb_ticks_per_usec;
	target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
		+ PCI_RESET_DELAY_US;

	pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
		 hose->global_number, target, now);

	if (now < target)
		msleep((target - now + 999) / 1000);

	return PCI_PROBE_NORMAL;
}

void __init pnv_pci_init(void)
{
	struct device_node *np;

	pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);

	/* OPAL absent, try POPAL first then RTAS detection of PHBs */
	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
#ifdef CONFIG_PPC_POWERNV_RTAS
		init_pci_config_tokens();
		find_and_init_phbs();
#endif /* CONFIG_PPC_POWERNV_RTAS */
	}
	/* OPAL is here, do our normal stuff */
	else {
		int found_ioda = 0;

		/* Look for IODA IO-Hubs. We don't support mixing IODA
		 * and p5ioc2 due to the need to change some global
		 * probing flags
		 */
		for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
			pnv_pci_init_ioda_hub(np);
			found_ioda = 1;
		}

		/* Look for p5ioc2 IO-Hubs */
		if (!found_ioda)
			for_each_compatible_node(np, NULL, "ibm,p5ioc2")
				pnv_pci_init_p5ioc2_hub(np);

		/* Look for ioda2 built-in PHB3's */
		for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
			pnv_pci_init_ioda2_phb(np);
	}

	/* Setup the linkage between OF nodes and PHBs */
	pci_devs_phb_init();

	/* Configure IOMMU DMA hooks */
	ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
	ppc_md.tce_build = pnv_tce_build;
	ppc_md.tce_free = pnv_tce_free;
	ppc_md.tce_get = pnv_tce_get;
	ppc_md.pci_probe_mode = pnv_pci_probe_mode;
	set_pci_dma_ops(&dma_iommu_ops);

	/* Configure MSIs */
#ifdef CONFIG_PCI_MSI
	ppc_md.msi_check_device = pnv_msi_check_device;
	ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
	ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
#endif
}
Commit	Line	Data
61305a96 BH	1	/*
	2	* Support PCI/PCIe on PowerNV platforms
	3	*
	4	* Currently supports only P5IOC2
	5	*
	6	* Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/pci.h>
	16	#include <linux/delay.h>
	17	#include <linux/string.h>
	18	#include <linux/init.h>
	19	#include <linux/bootmem.h>
	20	#include <linux/irq.h>
	21	#include <linux/io.h>
c1a2562a	22	#include <linux/msi.h>
4e13c1ac	23	#include <linux/iommu.h>
61305a96 BH	24
	25	#include <asm/sections.h>
	26	#include <asm/io.h>
	27	#include <asm/prom.h>
	28	#include <asm/pci-bridge.h>
	29	#include <asm/machdep.h>
fb1b55d6	30	#include <asm/msi_bitmap.h>
61305a96 BH	31	#include <asm/ppc-pci.h>
	32	#include <asm/opal.h>
	33	#include <asm/iommu.h>
	34	#include <asm/tce.h>
f5339277	35	#include <asm/firmware.h>
61305a96 BH	36
	37	#include "powernv.h"
	38	#include "pci.h"
	39
82ba129b BH	40	/* Delay in usec */
82ba129b BH	41	#define PCI_RESET_DELAY_US 3000000
61305a96 BH	42
	43	#define cfg_dbg(fmt...) do { } while(0)
	44	//#define cfg_dbg(fmt...) printk(fmt)
	45
c1a2562a BH	46	#ifdef CONFIG_PCI_MSI
	47	static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
	48	{
	49	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	50	struct pnv_phb *phb = hose->private_data;
b72c1f65 BH	51	struct pci_dn *pdn = pci_get_pdn(pdev);
	52
	53	if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
	54	return -ENODEV;
c1a2562a	55
fb1b55d6	56	return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
c1a2562a BH	57	}
	58
	59	static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	60	{
	61	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	62	struct pnv_phb *phb = hose->private_data;
	63	struct msi_desc *entry;
	64	struct msi_msg msg;
fb1b55d6 GS	65	int hwirq;
fb1b55d6 GS	66	unsigned int virq;
c1a2562a BH	67	int rc;
	68
	69	if (WARN_ON(!phb))
	70	return -ENODEV;
	71
	72	list_for_each_entry(entry, &pdev->msi_list, list) {
	73	if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
	74	pr_warn("%s: Supports only 64-bit MSIs\n",
	75	pci_name(pdev));
	76	return -ENXIO;
	77	}
fb1b55d6 GS	78	hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
fb1b55d6 GS	79	if (hwirq < 0) {
c1a2562a BH	80	pr_warn("%s: Failed to find a free MSI\n",
	81	pci_name(pdev));
	82	return -ENOSPC;
	83	}
fb1b55d6	84	virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
c1a2562a BH	85	if (virq == NO_IRQ) {
	86	pr_warn("%s: Failed to map MSI to linux irq\n",
	87	pci_name(pdev));
fb1b55d6	88	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
c1a2562a BH	89	return -ENOMEM;
c1a2562a BH	90	}
fb1b55d6	91	rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
137436c9	92	virq, entry->msi_attrib.is_64, &msg);
c1a2562a BH	93	if (rc) {
	94	pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
	95	irq_dispose_mapping(virq);
fb1b55d6	96	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
c1a2562a BH	97	return rc;
	98	}
	99	irq_set_msi_desc(virq, entry);
	100	write_msi_msg(virq, &msg);
	101	}
	102	return 0;
	103	}
	104
	105	static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
	106	{
	107	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	108	struct pnv_phb *phb = hose->private_data;
	109	struct msi_desc *entry;
	110
	111	if (WARN_ON(!phb))
	112	return;
	113
	114	list_for_each_entry(entry, &pdev->msi_list, list) {
	115	if (entry->irq == NO_IRQ)
	116	continue;
	117	irq_set_msi_desc(entry->irq, NULL);
fb1b55d6 GS	118	msi_bitmap_free_hwirqs(&phb->msi_bmp,
fb1b55d6 GS	119	virq_to_hw(entry->irq) - phb->msi_base, 1);
c1a2562a BH	120	irq_dispose_mapping(entry->irq);
	121	}
	122	}
	123	#endif /* CONFIG_PCI_MSI */
61305a96	124
cee72d5b BH	125	static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
	126	{
	127	struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
	128	int i;
	129
	130	pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
	131
	132	pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl);
	133
	134	pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg);
	135	pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus);
	136	pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus);
	137
	138	pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus);
	139	pr_info(" slotStatus = 0x%08x\n", data->slotStatus);
	140	pr_info(" linkStatus = 0x%08x\n", data->linkStatus);
	141	pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus);
	142	pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus);
	143
	144	pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus);
	145	pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus);
	146	pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus);
	147	pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1);
	148	pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2);
	149	pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3);
	150	pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4);
	151	pr_info(" sourceId = 0x%08x\n", data->sourceId);
	152
	153	pr_info(" errorClass = 0x%016llx\n", data->errorClass);
	154	pr_info(" correlator = 0x%016llx\n", data->correlator);
	155
	156	pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr);
	157	pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr);
	158	pr_info(" lemFir = 0x%016llx\n", data->lemFir);
	159	pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask);
	160	pr_info(" lemWOF = 0x%016llx\n", data->lemWOF);
	161	pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus);
	162	pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus);
	163	pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0);
	164	pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1);
	165	pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus);
	166	pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
	167	pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0);
	168	pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1);
	169	pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus);
	170	pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
	171	pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0);
	172	pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1);
	173	pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus);
	174	pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
	175	pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0);
	176	pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1);
	177
	178	for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
	179	if ((data->pestA[i] >> 63) == 0 &&
	180	(data->pestB[i] >> 63) == 0)
	181	continue;
	182	pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]);
	183	pr_info(" PESTB = 0x%016llx\n", data->pestB[i]);
	184	}
	185	}
	186
	187	static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
	188	{
189	switch(phb->model) {
190	case PNV_PHB_MODEL_P7IOC:
191	pnv_pci_dump_p7ioc_diag_data(phb);
192	break;
193	default:
194	pr_warning("PCI %d: Can't decode this PHB diag data\n",
195	phb->hose->global_number);
196	}
197	}
198
199	static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
200	{
201	unsigned long flags, rc;
202	int has_diag;
203
204	spin_lock_irqsave(&phb->lock, flags);
205
23773230 GS	206	rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
23773230 GS	207	PNV_PCI_DIAG_BUF_SIZE);
cee72d5b BH	208	has_diag = (rc == OPAL_SUCCESS);
	209
	210	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
	211	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
	212	if (rc) {
	213	pr_warning("PCI %d: Failed to clear EEH freeze state"
	214	" for PE#%d, err %ld\n",
	215	phb->hose->global_number, pe_no, rc);
	216
	217	/* For now, let's only display the diag buffer when we fail to clear
	218	* the EEH status. We'll do more sensible things later when we have
	219	* proper EEH support. We need to make sure we don't pollute ourselves
	220	* with the normal errors generated when probing empty slots
	221	*/
	222	if (has_diag)
	223	pnv_pci_dump_phb_diag_data(phb);
	224	else
	225	pr_warning("PCI %d: No diag data available\n",
	226	phb->hose->global_number);
	227	}
	228
	229	spin_unlock_irqrestore(&phb->lock, flags);
	230	}
	231
61305a96 BH	232	static void pnv_pci_config_check_eeh(struct pnv_phb phb, struct pci_bus bus,
	233	u32 bdfn)
	234	{
	235	s64 rc;
	236	u8 fstate;
	237	u16 pcierr;
	238	u32 pe_no;
	239
	240	/* Get PE# if we support IODA */
	241	pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
	242
	243	/* Read freeze status */
	244	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
	245	NULL);
	246	if (rc) {
	247	pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
	248	" err %lld\n", phb->hose->global_number, pe_no, rc);
	249	return;
	250	}
	251	cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
	252	bdfn, pe_no, fstate);
cee72d5b BH	253	if (fstate != 0)
cee72d5b BH	254	pnv_pci_handle_eeh_config(phb, pe_no);
61305a96 BH	255	}
	256
	257	static int pnv_pci_read_config(struct pci_bus *bus,
	258	unsigned int devfn,
	259	int where, int size, u32 *val)
	260	{
	261	struct pci_controller *hose = pci_bus_to_host(bus);
	262	struct pnv_phb *phb = hose->private_data;
	263	u32 bdfn = (((uint64_t)bus->number) << 8) \| devfn;
	264	s64 rc;
	265
	266	if (hose == NULL)
	267	return PCIBIOS_DEVICE_NOT_FOUND;
	268
	269	switch (size) {
	270	case 1: {
	271	u8 v8;
	272	rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
	273	*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
	274	break;
	275	}
	276	case 2: {
	277	u16 v16;
	278	rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
	279	&v16);
	280	*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
	281	break;
	282	}
	283	case 4: {
	284	u32 v32;
	285	rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
	286	*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
	287	break;
	288	}
	289	default:
	290	return PCIBIOS_FUNC_NOT_SUPPORTED;
	291	}
	292	cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
	293	bus->number, devfn, where, size, *val);
	294
	295	/* Check if the PHB got frozen due to an error (no response) */
	296	pnv_pci_config_check_eeh(phb, bus, bdfn);
	297
	298	return PCIBIOS_SUCCESSFUL;
	299	}
	300
	301	static int pnv_pci_write_config(struct pci_bus *bus,
	302	unsigned int devfn,
	303	int where, int size, u32 val)
	304	{
	305	struct pci_controller *hose = pci_bus_to_host(bus);
	306	struct pnv_phb *phb = hose->private_data;
	307	u32 bdfn = (((uint64_t)bus->number) << 8) \| devfn;
	308
	309	if (hose == NULL)
	310	return PCIBIOS_DEVICE_NOT_FOUND;
	311
	312	cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
	313	bus->number, devfn, where, size, val);
	314	switch (size) {
	315	case 1:
	316	opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
	317	break;
	318	case 2:
319	opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
320	break;
321	case 4:
322	opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
323	break;
324	default:
325	return PCIBIOS_FUNC_NOT_SUPPORTED;
326	}
327	/* Check if the PHB got frozen due to an error (no response) */
328	pnv_pci_config_check_eeh(phb, bus, bdfn);
329
330	return PCIBIOS_SUCCESSFUL;
331	}
332
333	struct pci_ops pnv_pci_ops = {
334	.read = pnv_pci_read_config,
335	.write = pnv_pci_write_config,
336	};
337
338	static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
339	unsigned long uaddr, enum dma_data_direction direction,
340	struct dma_attrs *attrs)
341	{
342	u64 proto_tce;
1f1616e8	343	u64 tcep, tces;
61305a96 BH	344	u64 rpn;
	345
	346	proto_tce = TCE_PCI_READ; // Read allowed
	347
	348	if (direction != DMA_TO_DEVICE)
	349	proto_tce \|= TCE_PCI_WRITE;
	350
1f1616e8 BH	351	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
1f1616e8 BH	352	rpn = __pa(uaddr) >> TCE_SHIFT;
61305a96	353
1f1616e8 BH	354	while (npages--)
	355	*(tcep++) = proto_tce \| (rpn++ << TCE_RPN_SHIFT);
	356
	357	/* Some implementations won't cache invalid TCEs and thus may not
	358	* need that flush. We'll probably turn it_type into a bit mask
	359	* of flags if that becomes the case
	360	*/
	361	if (tbl->it_type & TCE_PCI_SWINV_CREATE)
4cce9550	362	pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
61305a96	363
61305a96 BH	364	return 0;
	365	}
	366
	367	static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
	368	{
1f1616e8 BH	369	u64 tcep, tces;
	370
	371	tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
61305a96 BH	372
	373	while (npages--)
	374	*(tcep++) = 0;
1f1616e8	375
605e44d6	376	if (tbl->it_type & TCE_PCI_SWINV_FREE)
4cce9550	377	pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
61305a96 BH	378	}
61305a96 BH	379
11f63d3f AK	380	static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
	381	{
	382	return ((u64 *)tbl->it_base)[index - tbl->it_offset];
	383	}
	384
61305a96 BH	385	void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
	386	void *tce_mem, u64 tce_size,
	387	u64 dma_offset)
	388	{
	389	tbl->it_blocksize = 16;
	390	tbl->it_base = (unsigned long)tce_mem;
	391	tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
	392	tbl->it_index = 0;
	393	tbl->it_size = tce_size >> 3;
	394	tbl->it_busno = 0;
	395	tbl->it_type = TCE_PCI;
	396	}
	397
cad5cef6	398	static struct iommu_table pnv_pci_setup_bml_iommu(struct pci_controller hose)
61305a96 BH	399	{
61305a96 BH	400	struct iommu_table *tbl;
1f1616e8	401	const __be64 basep, swinvp;
61305a96 BH	402	const __be32 *sizep;
	403
	404	basep = of_get_property(hose->dn, "linux,tce-base", NULL);
	405	sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
	406	if (basep == NULL \|\| sizep == NULL) {
1f1616e8 BH	407	pr_err("PCI: %s has missing tce entries !\n",
1f1616e8 BH	408	hose->dn->full_name);
61305a96 BH	409	return NULL;
	410	}
	411	tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
	412	if (WARN_ON(!tbl))
	413	return NULL;
	414	pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
	415	be32_to_cpup(sizep), 0);
	416	iommu_init_table(tbl, hose->node);
4e13c1ac	417	iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
1f1616e8 BH	418
	419	/* Deal with SW invalidated TCEs when needed (BML way) */
	420	swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
	421	NULL);
	422	if (swinvp) {
	423	tbl->it_busno = swinvp[1];
	424	tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
	425	tbl->it_type = TCE_PCI_SWINV_CREATE \| TCE_PCI_SWINV_FREE;
	426	}
61305a96 BH	427	return tbl;
	428	}
	429
cad5cef6 GKH	430	static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
cad5cef6 GKH	431	struct pci_dev *pdev)
61305a96 BH	432	{
	433	struct device_node *np = pci_bus_to_OF_node(hose->bus);
	434	struct pci_dn *pdn;
	435
	436	if (np == NULL)
	437	return;
	438	pdn = PCI_DN(np);
	439	if (!pdn->iommu_table)
	440	pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
	441	if (!pdn->iommu_table)
	442	return;
	443	set_iommu_table_base(&pdev->dev, pdn->iommu_table);
	444	}
	445
cad5cef6	446	static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
61305a96 BH	447	{
	448	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	449	struct pnv_phb *phb = hose->private_data;
	450
	451	/* If we have no phb structure, try to setup a fallback based on
	452	* the device-tree (RTAS PCI for example)
	453	*/
	454	if (phb && phb->dma_dev_setup)
	455	phb->dma_dev_setup(phb, pdev);
	456	else
	457	pnv_pci_dma_fallback_setup(hose, pdev);
	458	}
	459
73ed148a BH	460	void pnv_pci_shutdown(void)
	461	{
	462	struct pci_controller *hose;
	463
	464	list_for_each_entry(hose, &hose_list, list_node) {
	465	struct pnv_phb *phb = hose->private_data;
	466
	467	if (phb && phb->shutdown)
	468	phb->shutdown(phb);
	469	}
	470	}
	471
aa0c033f	472	/* Fixup wrong class code in p7ioc and p8 root complex */
cad5cef6	473	static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
ca45cfe3 BH	474	{
	475	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
	476	}
	477	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
	478
82ba129b BH	479	static int pnv_pci_probe_mode(struct pci_bus *bus)
	480	{
	481	struct pci_controller *hose = pci_bus_to_host(bus);
	482	const __be64 *tstamp;
	483	u64 now, target;
	484
	485
	486	/* We hijack this as a way to ensure we have waited long
	487	* enough since the reset was lifted on the PCI bus
	488	*/
	489	if (bus != hose->bus)
	490	return PCI_PROBE_NORMAL;
	491	tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
	492	if (!tstamp \|\| !*tstamp)
	493	return PCI_PROBE_NORMAL;
	494
	495	now = mftb() / tb_ticks_per_usec;
	496	target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
	497	+ PCI_RESET_DELAY_US;
	498
	499	pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
	500	hose->global_number, target, now);
	501
	502	if (now < target)
	503	msleep((target - now + 999) / 1000);
	504
	505	return PCI_PROBE_NORMAL;
	506	}
	507
61305a96 BH	508	void __init pnv_pci_init(void)
	509	{
	510	struct device_node *np;
	511
673c9756	512	pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
61305a96 BH	513
	514	/* OPAL absent, try POPAL first then RTAS detection of PHBs */
	515	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
	516	#ifdef CONFIG_PPC_POWERNV_RTAS
	517	init_pci_config_tokens();
	518	find_and_init_phbs();
	519	#endif /* CONFIG_PPC_POWERNV_RTAS */
184cd4a3 BH	520	}
	521	/* OPAL is here, do our normal stuff */
	522	else {
	523	int found_ioda = 0;
	524
	525	/* Look for IODA IO-Hubs. We don't support mixing IODA
	526	* and p5ioc2 due to the need to change some global
	527	* probing flags
	528	*/
	529	for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
	530	pnv_pci_init_ioda_hub(np);
	531	found_ioda = 1;
	532	}
61305a96 BH	533
61305a96 BH	534	/* Look for p5ioc2 IO-Hubs */
184cd4a3 BH	535	if (!found_ioda)
	536	for_each_compatible_node(np, NULL, "ibm,p5ioc2")
	537	pnv_pci_init_p5ioc2_hub(np);
aa0c033f GS	538
	539	/* Look for ioda2 built-in PHB3's */
	540	for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
	541	pnv_pci_init_ioda2_phb(np);
61305a96 BH	542	}
	543
	544	/* Setup the linkage between OF nodes and PHBs */
	545	pci_devs_phb_init();
	546
	547	/* Configure IOMMU DMA hooks */
	548	ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
	549	ppc_md.tce_build = pnv_tce_build;
	550	ppc_md.tce_free = pnv_tce_free;
11f63d3f	551	ppc_md.tce_get = pnv_tce_get;
82ba129b	552	ppc_md.pci_probe_mode = pnv_pci_probe_mode;
61305a96 BH	553	set_pci_dma_ops(&dma_iommu_ops);
61305a96 BH	554
c1a2562a BH	555	/* Configure MSIs */
	556	#ifdef CONFIG_PCI_MSI
	557	ppc_md.msi_check_device = pnv_msi_check_device;
	558	ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
	559	ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
	560	#endif
61305a96	561	}