[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / platforms / powernv / pci.h

#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

struct pci_dn;

enum pnv_phb_type {
	PNV_PHB_P5IOC2,
	PNV_PHB_IODA1,
	PNV_PHB_IODA2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P5IOC2,
	PNV_PHB_MODEL_P7IOC,
};

#define PNV_PCI_DIAG_BUF_SIZE	4096
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_ioda_pe {
	unsigned long		flags;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Weight" assigned to the PE for the sake of DMA resource
	 * allocations
	 */
	unsigned int		dma_weight;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	int			tce32_seg;
	int			tce32_segcount;
	struct iommu_table	tce32_table;

	/* XXX TODO: Add support for additional 64-bit iommus */

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* Link in list of PE#s */
	struct list_head	dma_link;
	struct list_head	list;
};

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			opal_id;
	void __iomem		*regs;
	spinlock_t		lock;

#ifdef CONFIG_PCI_MSI
	unsigned long		*msi_map;
	unsigned int		msi_base;
	unsigned int		msi_count;
	unsigned int		msi_next;
	unsigned int		msi32_support;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int is_64,
			 struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	void (*fixup_phb)(struct pci_controller *hose);
	u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);

	union {
		struct {
			struct iommu_table iommu_table;
		} p5ioc2;

		struct {
			/* Global bridge info */
			unsigned int		total_pe;
			unsigned int		m32_size;
			unsigned int		m32_segsize;
			unsigned int		m32_pci_base;
			unsigned int		io_size;
			unsigned int		io_segsize;
			unsigned int		io_pci_base;

			/* PE allocation bitmap */
			unsigned long		*pe_alloc;

			/* M32 & IO segment maps */
			unsigned int		*m32_segmap;
			unsigned int		*io_segmap;
			struct pnv_ioda_pe	*pe_array;

			/* Sorted list of used PE's based
			 * on the sequence of creation
			 */
			struct list_head	pe_list;

			/* Reverse map of PEs, will have to extend if
			 * we are to support more than 256 PEs, indexed
			 * bus { bus, devfn }
			 */
			unsigned char		pe_rmap[0x10000];

			/* 32-bit TCE tables allocation */
			unsigned long		tce32_count;

			/* Total "weight" for the sake of DMA resources
			 * allocation
			 */
			unsigned int		dma_weight;
			unsigned int		dma_pe_count;

			/* Sorted list of used PE's, sorted at
			 * boot for resource allocation purposes
			 */
			struct list_head	pe_dma_list;
		} ioda;
	};

	/* PHB status structure */
	union {
		unsigned char			blob[PNV_PCI_DIAG_BUF_SIZE];
		struct OpalIoP7IOCPhbErrorData	p7ioc;
	} diag;
};

extern struct pci_ops pnv_pci_ops;

extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset);
extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
extern void pnv_pci_init_ioda_hub(struct device_node *np);


#endif /* __POWERNV_PCI_H */
Commit	Line	Data
61305a96 BH	1	#ifndef __POWERNV_PCI_H
	2	#define __POWERNV_PCI_H
	3
	4	struct pci_dn;
	5
	6	enum pnv_phb_type {
	7	PNV_PHB_P5IOC2,
	8	PNV_PHB_IODA1,
	9	PNV_PHB_IODA2,
	10	};
	11
cee72d5b BH	12	/* Precise PHB model for error management */
	13	enum pnv_phb_model {
	14	PNV_PHB_MODEL_UNKNOWN,
	15	PNV_PHB_MODEL_P5IOC2,
	16	PNV_PHB_MODEL_P7IOC,
	17	};
	18
	19	#define PNV_PCI_DIAG_BUF_SIZE 4096
7ebdf956 GS	20	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	21	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	22	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
cee72d5b	23
184cd4a3 BH	24	/* Data associated with a PE, including IOMMU tracking etc.. */
184cd4a3 BH	25	struct pnv_ioda_pe {
7ebdf956 GS	26	unsigned long flags;
7ebdf956 GS	27
184cd4a3 BH	28	/* A PE can be associated with a single device or an
	29	* entire bus (& children). In the former case, pdev
	30	* is populated, in the later case, pbus is.
	31	*/
	32	struct pci_dev *pdev;
	33	struct pci_bus *pbus;
	34
	35	/* Effective RID (device RID for a device PE and base bus
	36	* RID with devfn 0 for a bus PE)
	37	*/
	38	unsigned int rid;
	39
	40	/* PE number */
	41	unsigned int pe_number;
	42
	43	/* "Weight" assigned to the PE for the sake of DMA resource
	44	* allocations
	45	*/
	46	unsigned int dma_weight;
	47
184cd4a3 BH	48	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	49	int tce32_seg;
	50	int tce32_segcount;
	51	struct iommu_table tce32_table;
	52
	53	/* XXX TODO: Add support for additional 64-bit iommus */
	54
	55	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	56	* and -1 if not supported. (It's actually identical to the
	57	* PE number)
	58	*/
	59	int mve_number;
	60
	61	/* Link in list of PE#s */
7ebdf956 GS	62	struct list_head dma_link;
7ebdf956 GS	63	struct list_head list;
184cd4a3 BH	64	};
184cd4a3 BH	65
61305a96 BH	66	struct pnv_phb {
	67	struct pci_controller *hose;
	68	enum pnv_phb_type type;
cee72d5b	69	enum pnv_phb_model model;
61305a96 BH	70	u64 opal_id;
	71	void __iomem *regs;
	72	spinlock_t lock;
	73
c1a2562a BH	74	#ifdef CONFIG_PCI_MSI
	75	unsigned long *msi_map;
	76	unsigned int msi_base;
	77	unsigned int msi_count;
	78	unsigned int msi_next;
	79	unsigned int msi32_support;
	80	#endif
	81	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
	82	unsigned int hwirq, unsigned int is_64,
	83	struct msi_msg *msg);
61305a96 BH	84	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
	85	void (fixup_phb)(struct pci_controller hose);
	86	u32 (bdfn_to_pe)(struct pnv_phb phb, struct pci_bus *bus, u32 devfn);
	87
	88	union {
	89	struct {
	90	struct iommu_table iommu_table;
	91	} p5ioc2;
184cd4a3 BH	92
	93	struct {
	94	/* Global bridge info */
	95	unsigned int total_pe;
	96	unsigned int m32_size;
	97	unsigned int m32_segsize;
	98	unsigned int m32_pci_base;
	99	unsigned int io_size;
	100	unsigned int io_segsize;
	101	unsigned int io_pci_base;
	102
	103	/* PE allocation bitmap */
	104	unsigned long *pe_alloc;
	105
	106	/* M32 & IO segment maps */
	107	unsigned int *m32_segmap;
	108	unsigned int *io_segmap;
	109	struct pnv_ioda_pe *pe_array;
	110
7ebdf956 GS	111	/* Sorted list of used PE's based
	112	* on the sequence of creation
	113	*/
	114	struct list_head pe_list;
	115
184cd4a3 BH	116	/* Reverse map of PEs, will have to extend if
	117	* we are to support more than 256 PEs, indexed
	118	* bus { bus, devfn }
	119	*/
	120	unsigned char pe_rmap[0x10000];
	121
	122	/* 32-bit TCE tables allocation */
	123	unsigned long tce32_count;
	124
	125	/* Total "weight" for the sake of DMA resources
	126	* allocation
	127	*/
	128	unsigned int dma_weight;
	129	unsigned int dma_pe_count;
	130
	131	/* Sorted list of used PE's, sorted at
	132	* boot for resource allocation purposes
	133	*/
7ebdf956	134	struct list_head pe_dma_list;
184cd4a3	135	} ioda;
61305a96	136	};
cee72d5b BH	137
	138	/* PHB status structure */
	139	union {
	140	unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
	141	struct OpalIoP7IOCPhbErrorData p7ioc;
	142	} diag;
61305a96 BH	143	};
	144
	145	extern struct pci_ops pnv_pci_ops;
	146
	147	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
	148	void *tce_mem, u64 tce_size,
	149	u64 dma_offset);
	150	extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
184cd4a3	151	extern void pnv_pci_init_ioda_hub(struct device_node *np);
61305a96 BH	152
	153
	154	#endif /* __POWERNV_PCI_H */