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61305a96 BH |
1 | #ifndef __POWERNV_PCI_H |
2 | #define __POWERNV_PCI_H | |
3 | ||
4 | struct pci_dn; | |
5 | ||
6 | enum pnv_phb_type { | |
aa0c033f GS |
7 | PNV_PHB_P5IOC2 = 0, |
8 | PNV_PHB_IODA1 = 1, | |
9 | PNV_PHB_IODA2 = 2, | |
61305a96 BH |
10 | }; |
11 | ||
cee72d5b BH |
12 | /* Precise PHB model for error management */ |
13 | enum pnv_phb_model { | |
14 | PNV_PHB_MODEL_UNKNOWN, | |
15 | PNV_PHB_MODEL_P5IOC2, | |
16 | PNV_PHB_MODEL_P7IOC, | |
aa0c033f | 17 | PNV_PHB_MODEL_PHB3, |
cee72d5b BH |
18 | }; |
19 | ||
20 | #define PNV_PCI_DIAG_BUF_SIZE 4096 | |
7ebdf956 GS |
21 | #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ |
22 | #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ | |
23 | #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ | |
cee72d5b | 24 | |
184cd4a3 | 25 | /* Data associated with a PE, including IOMMU tracking etc.. */ |
4cce9550 | 26 | struct pnv_phb; |
184cd4a3 | 27 | struct pnv_ioda_pe { |
7ebdf956 | 28 | unsigned long flags; |
4cce9550 | 29 | struct pnv_phb *phb; |
7ebdf956 | 30 | |
184cd4a3 BH |
31 | /* A PE can be associated with a single device or an |
32 | * entire bus (& children). In the former case, pdev | |
33 | * is populated, in the later case, pbus is. | |
34 | */ | |
35 | struct pci_dev *pdev; | |
36 | struct pci_bus *pbus; | |
37 | ||
38 | /* Effective RID (device RID for a device PE and base bus | |
39 | * RID with devfn 0 for a bus PE) | |
40 | */ | |
41 | unsigned int rid; | |
42 | ||
43 | /* PE number */ | |
44 | unsigned int pe_number; | |
45 | ||
46 | /* "Weight" assigned to the PE for the sake of DMA resource | |
47 | * allocations | |
48 | */ | |
49 | unsigned int dma_weight; | |
50 | ||
184cd4a3 BH |
51 | /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ |
52 | int tce32_seg; | |
53 | int tce32_segcount; | |
54 | struct iommu_table tce32_table; | |
55 | ||
56 | /* XXX TODO: Add support for additional 64-bit iommus */ | |
57 | ||
58 | /* MSIs. MVE index is identical for for 32 and 64 bit MSI | |
59 | * and -1 if not supported. (It's actually identical to the | |
60 | * PE number) | |
61 | */ | |
62 | int mve_number; | |
63 | ||
64 | /* Link in list of PE#s */ | |
7ebdf956 GS |
65 | struct list_head dma_link; |
66 | struct list_head list; | |
184cd4a3 BH |
67 | }; |
68 | ||
61305a96 BH |
69 | struct pnv_phb { |
70 | struct pci_controller *hose; | |
71 | enum pnv_phb_type type; | |
cee72d5b | 72 | enum pnv_phb_model model; |
61305a96 BH |
73 | u64 opal_id; |
74 | void __iomem *regs; | |
db1266c8 | 75 | int initialized; |
61305a96 BH |
76 | spinlock_t lock; |
77 | ||
c1a2562a | 78 | #ifdef CONFIG_PCI_MSI |
c1a2562a | 79 | unsigned int msi_base; |
c1a2562a | 80 | unsigned int msi32_support; |
fb1b55d6 | 81 | struct msi_bitmap msi_bmp; |
c1a2562a BH |
82 | #endif |
83 | int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, | |
137436c9 GS |
84 | unsigned int hwirq, unsigned int virq, |
85 | unsigned int is_64, struct msi_msg *msg); | |
61305a96 BH |
86 | void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); |
87 | void (*fixup_phb)(struct pci_controller *hose); | |
88 | u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); | |
73ed148a | 89 | void (*shutdown)(struct pnv_phb *phb); |
61305a96 BH |
90 | |
91 | union { | |
92 | struct { | |
93 | struct iommu_table iommu_table; | |
94 | } p5ioc2; | |
184cd4a3 BH |
95 | |
96 | struct { | |
97 | /* Global bridge info */ | |
98 | unsigned int total_pe; | |
99 | unsigned int m32_size; | |
100 | unsigned int m32_segsize; | |
101 | unsigned int m32_pci_base; | |
102 | unsigned int io_size; | |
103 | unsigned int io_segsize; | |
104 | unsigned int io_pci_base; | |
105 | ||
106 | /* PE allocation bitmap */ | |
107 | unsigned long *pe_alloc; | |
108 | ||
109 | /* M32 & IO segment maps */ | |
110 | unsigned int *m32_segmap; | |
111 | unsigned int *io_segmap; | |
112 | struct pnv_ioda_pe *pe_array; | |
113 | ||
137436c9 GS |
114 | /* IRQ chip */ |
115 | int irq_chip_init; | |
116 | struct irq_chip irq_chip; | |
117 | ||
7ebdf956 GS |
118 | /* Sorted list of used PE's based |
119 | * on the sequence of creation | |
120 | */ | |
121 | struct list_head pe_list; | |
122 | ||
184cd4a3 BH |
123 | /* Reverse map of PEs, will have to extend if |
124 | * we are to support more than 256 PEs, indexed | |
125 | * bus { bus, devfn } | |
126 | */ | |
127 | unsigned char pe_rmap[0x10000]; | |
128 | ||
129 | /* 32-bit TCE tables allocation */ | |
130 | unsigned long tce32_count; | |
131 | ||
132 | /* Total "weight" for the sake of DMA resources | |
133 | * allocation | |
134 | */ | |
135 | unsigned int dma_weight; | |
136 | unsigned int dma_pe_count; | |
137 | ||
138 | /* Sorted list of used PE's, sorted at | |
139 | * boot for resource allocation purposes | |
140 | */ | |
7ebdf956 | 141 | struct list_head pe_dma_list; |
184cd4a3 | 142 | } ioda; |
61305a96 | 143 | }; |
cee72d5b BH |
144 | |
145 | /* PHB status structure */ | |
146 | union { | |
147 | unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; | |
148 | struct OpalIoP7IOCPhbErrorData p7ioc; | |
149 | } diag; | |
61305a96 BH |
150 | }; |
151 | ||
152 | extern struct pci_ops pnv_pci_ops; | |
153 | ||
154 | extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, | |
155 | void *tce_mem, u64 tce_size, | |
156 | u64 dma_offset); | |
157 | extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); | |
184cd4a3 | 158 | extern void pnv_pci_init_ioda_hub(struct device_node *np); |
aa0c033f | 159 | extern void pnv_pci_init_ioda2_phb(struct device_node *np); |
4cce9550 GS |
160 | extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, |
161 | u64 *startp, u64 *endp); | |
73ed148a | 162 | |
61305a96 | 163 | #endif /* __POWERNV_PCI_H */ |