[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / powernv / pci.h

#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

#include <linux/iommu.h>
#include <asm/iommu.h>
#include <asm/msi_bitmap.h>

struct pci_dn;

/* Maximum possible number of ATSD MMIO registers per NPU */
#define NV_NMMU_ATSD_REGS 8

enum pnv_phb_type {
	PNV_PHB_IODA1	= 0,
	PNV_PHB_IODA2	= 1,
	PNV_PHB_NPU	= 2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
	PNV_PHB_MODEL_NPU,
	PNV_PHB_MODEL_NPU2,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/

/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
#define PNV_IODA_STOPPED_STATE	0x8000000000000000

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;
	int			device_count;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
#ifdef CONFIG_PCI_IOV
	struct pci_dev          *parent_dev;
#endif
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	struct iommu_table_group table_group;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* PEs in compound case */
	struct pnv_ioda_pe	*master;
	struct list_head	slaves;

	/* Link in list of PE#s */
	struct list_head	list;
};

#define PNV_PHB_FLAG_EEH	(1 << 0)
#define PNV_PHB_FLAG_CXL	(1 << 1) /* Real PHB supporting the cxl kernel API */

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	int			flags;
	void __iomem		*regs;
	u64			regs_phys;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_DEBUG_FS
	int			has_dbgfs;
	struct dentry		*dbgfs;
#endif

#ifdef CONFIG_PCI_MSI
	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	void (*fixup_phb)(struct pci_controller *hose);
	int (*init_m64)(struct pnv_phb *phb);
	void (*reserve_m64_pe)(struct pci_bus *bus,
			       unsigned long *pe_bitmap, bool all);
	struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

	struct {
		/* Global bridge info */
		unsigned int		total_pe_num;
		unsigned int		reserved_pe_idx;
		unsigned int		root_pe_idx;
		bool			root_pe_populated;

		/* 32-bit MMIO window */
		unsigned int		m32_size;
		unsigned int		m32_segsize;
		unsigned int		m32_pci_base;

		/* 64-bit MMIO window */
		unsigned int		m64_bar_idx;
		unsigned long		m64_size;
		unsigned long		m64_segsize;
		unsigned long		m64_base;
		unsigned long		m64_bar_alloc;

		/* IO ports */
		unsigned int		io_size;
		unsigned int		io_segsize;
		unsigned int		io_pci_base;

		/* PE allocation */
		struct mutex		pe_alloc_mutex;
		unsigned long		*pe_alloc;
		struct pnv_ioda_pe	*pe_array;

		/* M32 & IO segment maps */
		unsigned int		*m64_segmap;
		unsigned int		*m32_segmap;
		unsigned int		*io_segmap;

		/* DMA32 segment maps - IODA1 only */
		unsigned int		dma32_count;
		unsigned int		*dma32_segmap;

		/* IRQ chip */
		int			irq_chip_init;
		struct irq_chip		irq_chip;

		/* Sorted list of used PE's based
		 * on the sequence of creation
		 */
		struct list_head	pe_list;
		struct mutex            pe_list_mutex;

		/* Reverse map of PEs, indexed by {bus, devfn} */
		unsigned int		pe_rmap[0x10000];
	} ioda;

	/* PHB and hub diagnostics */
	unsigned int		diag_data_size;
	u8			*diag_data;

	/* Nvlink2 data */
	struct npu {
		int index;
		__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
		unsigned int mmio_atsd_count;

		/* Bitmask for MMIO register usage */
		unsigned long mmio_atsd_usage;
	} npu;

#ifdef CONFIG_CXL_BASE
	struct cxl_afu *cxl_afu;
#endif
};

extern struct pci_ops pnv_pci_ops;
extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
		unsigned long uaddr, enum dma_data_direction direction,
		unsigned long attrs);
extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction);
extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct pci_dn *pdn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct pci_dn *pdn,
		      int where, int size, u32 val);
extern struct iommu_table *pnv_pci_table_alloc(int nid);

extern long pnv_pci_link_table_and_group(int node, int num,
		struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset, unsigned page_shift);
extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_init_npu_phb(struct device_node *np);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);

extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);

extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
			    const char *fmt, ...);
#define pe_err(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
#define pe_warn(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
#define pe_info(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)

/* Nvlink functions */
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
		struct iommu_table *tbl);
extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
extern int pnv_npu2_init(struct pnv_phb *phb);

/* cxl functions */
extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
extern void pnv_cxl_disable_device(struct pci_dev *dev);
extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);


/* phb ops (cxl switches these when enabling the kernel api on the phb) */
extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
61305a96 BH	1	#ifndef __POWERNV_PCI_H
	2	#define __POWERNV_PCI_H
	3
f456834a IM	4	#include <linux/iommu.h>
	5	#include <asm/iommu.h>
	6	#include <asm/msi_bitmap.h>
	7
61305a96 BH	8	struct pci_dn;
61305a96 BH	9
1ab66d1f AP	10	/* Maximum possible number of ATSD MMIO registers per NPU */
	11	#define NV_NMMU_ATSD_REGS 8
	12
61305a96	13	enum pnv_phb_type {
2de50e96 RC	14	PNV_PHB_IODA1 = 0,
	15	PNV_PHB_IODA2 = 1,
	16	PNV_PHB_NPU = 2,
61305a96 BH	17	};
61305a96 BH	18
cee72d5b BH	19	/* Precise PHB model for error management */
	20	enum pnv_phb_model {
	21	PNV_PHB_MODEL_UNKNOWN,
cee72d5b	22	PNV_PHB_MODEL_P7IOC,
aa0c033f	23	PNV_PHB_MODEL_PHB3,
5d2aa710	24	PNV_PHB_MODEL_NPU,
616badd2	25	PNV_PHB_MODEL_NPU2,
cee72d5b BH	26	};
cee72d5b BH	27
5c9d6d75	28	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	29	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	30	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	31	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
262af557 GC	32	#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
262af557 GC	33	#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
781a868f	34	#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
cee72d5b	35
31bbd45a RC	36	/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
	37	#define PNV_IODA_STOPPED_STATE 0x8000000000000000
	38
184cd4a3	39	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	40	struct pnv_phb;
184cd4a3	41	struct pnv_ioda_pe {
7ebdf956	42	unsigned long flags;
4cce9550	43	struct pnv_phb *phb;
c5f7700b	44	int device_count;
7ebdf956	45
184cd4a3 BH	46	/* A PE can be associated with a single device or an
	47	* entire bus (& children). In the former case, pdev
	48	* is populated, in the later case, pbus is.
	49	*/
781a868f WY	50	#ifdef CONFIG_PCI_IOV
	51	struct pci_dev *parent_dev;
	52	#endif
184cd4a3 BH	53	struct pci_dev *pdev;
	54	struct pci_bus *pbus;
	55
	56	/* Effective RID (device RID for a device PE and base bus
	57	* RID with devfn 0 for a bus PE)
	58	*/
	59	unsigned int rid;
	60
	61	/* PE number */
	62	unsigned int pe_number;
	63
184cd4a3	64	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
b348aa65	65	struct iommu_table_group table_group;
184cd4a3	66
cd15b048 BH	67	/* 64-bit TCE bypass region */
	68	bool tce_bypass_enabled;
	69	uint64_t tce_bypass_base;
184cd4a3 BH	70
	71	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	72	* and -1 if not supported. (It's actually identical to the
	73	* PE number)
	74	*/
	75	int mve_number;
	76
262af557 GC	77	/* PEs in compound case */
	78	struct pnv_ioda_pe *master;
	79	struct list_head slaves;
	80
184cd4a3	81	/* Link in list of PE#s */
7ebdf956	82	struct list_head list;
184cd4a3 BH	83	};
184cd4a3 BH	84
f5bc6b70	85	#define PNV_PHB_FLAG_EEH (1 << 0)
4361b034	86	#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
f5bc6b70	87
61305a96 BH	88	struct pnv_phb {
	89	struct pci_controller *hose;
	90	enum pnv_phb_type type;
cee72d5b	91	enum pnv_phb_model model;
8747f363	92	u64 hub_id;
61305a96	93	u64 opal_id;
f5bc6b70	94	int flags;
61305a96	95	void __iomem *regs;
fd141d1a	96	u64 regs_phys;
db1266c8	97	int initialized;
61305a96 BH	98	spinlock_t lock;
61305a96 BH	99
37c367f2	100	#ifdef CONFIG_DEBUG_FS
7f52a526	101	int has_dbgfs;
37c367f2 GS	102	struct dentry *dbgfs;
	103	#endif
	104
c1a2562a	105	#ifdef CONFIG_PCI_MSI
c1a2562a	106	unsigned int msi_base;
c1a2562a	107	unsigned int msi32_support;
fb1b55d6	108	struct msi_bitmap msi_bmp;
c1a2562a BH	109	#endif
c1a2562a BH	110	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	111	unsigned int hwirq, unsigned int virq,
137436c9 GS	112	unsigned int is_64, struct msi_msg *msg);
61305a96 BH	113	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
61305a96 BH	114	void (fixup_phb)(struct pci_controller hose);
262af557	115	int (init_m64)(struct pnv_phb phb);
96a2f92b GS	116	void (reserve_m64_pe)(struct pci_bus bus,
96a2f92b GS	117	unsigned long *pe_bitmap, bool all);
1e916772	118	struct pnv_ioda_pe (pick_m64_pe)(struct pci_bus *bus, bool all);
49dec922 GS	119	int (get_pe_state)(struct pnv_phb phb, int pe_no);
	120	void (freeze_pe)(struct pnv_phb phb, int pe_no);
	121	int (unfreeze_pe)(struct pnv_phb phb, int pe_no, int opt);
61305a96	122
2de50e96 RC	123	struct {
2de50e96 RC	124	/* Global bridge info */
92b8f137 GS	125	unsigned int total_pe_num;
92b8f137 GS	126	unsigned int reserved_pe_idx;
63803c39 GS	127	unsigned int root_pe_idx;
63803c39 GS	128	bool root_pe_populated;
2de50e96 RC	129
	130	/* 32-bit MMIO window */
	131	unsigned int m32_size;
	132	unsigned int m32_segsize;
	133	unsigned int m32_pci_base;
	134
	135	/* 64-bit MMIO window */
	136	unsigned int m64_bar_idx;
	137	unsigned long m64_size;
	138	unsigned long m64_segsize;
	139	unsigned long m64_base;
	140	unsigned long m64_bar_alloc;
	141
	142	/* IO ports */
	143	unsigned int io_size;
	144	unsigned int io_segsize;
	145	unsigned int io_pci_base;
	146
13ce7598	147	/* PE allocation */
2de50e96	148	struct mutex pe_alloc_mutex;
13ce7598 GS	149	unsigned long *pe_alloc;
13ce7598 GS	150	struct pnv_ioda_pe *pe_array;
2de50e96 RC	151
2de50e96 RC	152	/* M32 & IO segment maps */
93289d8c	153	unsigned int *m64_segmap;
2de50e96 RC	154	unsigned int *m32_segmap;
2de50e96 RC	155	unsigned int *io_segmap;
2de50e96	156
2b923ed1 GS	157	/* DMA32 segment maps - IODA1 only */
	158	unsigned int dma32_count;
	159	unsigned int *dma32_segmap;
	160
2de50e96 RC	161	/* IRQ chip */
	162	int irq_chip_init;
	163	struct irq_chip irq_chip;
	164
	165	/* Sorted list of used PE's based
	166	* on the sequence of creation
	167	*/
	168	struct list_head pe_list;
	169	struct mutex pe_list_mutex;
	170
c127562a GS	171	/* Reverse map of PEs, indexed by {bus, devfn} */
c127562a GS	172	unsigned int pe_rmap[0x10000];
2de50e96	173	} ioda;
cee72d5b	174
5cb1f8fd RC	175	/* PHB and hub diagnostics */
	176	unsigned int diag_data_size;
	177	u8 *diag_data;
ca1de5de	178
1ab66d1f AP	179	/* Nvlink2 data */
	180	struct npu {
	181	int index;
	182	__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
	183	unsigned int mmio_atsd_count;
	184
	185	/* Bitmask for MMIO register usage */
	186	unsigned long mmio_atsd_usage;
	187	} npu;
	188
4361b034 IM	189	#ifdef CONFIG_CXL_BASE
	190	struct cxl_afu *cxl_afu;
	191	#endif
61305a96 BH	192	};
	193
	194	extern struct pci_ops pnv_pci_ops;
da004c36 AK	195	extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
da004c36 AK	196	unsigned long uaddr, enum dma_data_direction direction,
00085f1e	197	unsigned long attrs);
da004c36	198	extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
05c6cfb9 AK	199	extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
05c6cfb9 AK	200	unsigned long hpa, enum dma_data_direction direction);
da004c36	201	extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
61305a96	202
93aef2a7 GS	203	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	204	unsigned char *log_buff);
3532a741	205	int pnv_pci_cfg_read(struct pci_dn *pdn,
9bf41be6	206	int where, int size, u32 *val);
3532a741	207	int pnv_pci_cfg_write(struct pci_dn *pdn,
9bf41be6	208	int where, int size, u32 val);
0eaf4def AK	209	extern struct iommu_table *pnv_pci_table_alloc(int nid);
	210
	211	extern long pnv_pci_link_table_and_group(int node, int num,
	212	struct iommu_table *tbl,
	213	struct iommu_table_group *table_group);
	214	extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
	215	struct iommu_table_group *table_group);
61305a96 BH	216	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
61305a96 BH	217	void *tce_mem, u64 tce_size,
8fa5d454	218	u64 dma_offset, unsigned page_shift);
184cd4a3	219	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	220	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
5d2aa710	221	extern void pnv_pci_init_npu_phb(struct device_node *np);
d92a208d	222	extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
cadf364d	223	extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
73ed148a	224
92ae0353	225	extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
1bc74f1c	226	extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
92ae0353 DA	227	extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
92ae0353 DA	228	extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
f456834a IM	229	extern struct pnv_ioda_pe pnv_ioda_get_pe(struct pci_dev dev);
f456834a IM	230	extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
4361b034	231	extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
92ae0353	232
7d623e42 AK	233	extern void pe_level_printk(const struct pnv_ioda_pe pe, const char level,
	234	const char *fmt, ...);
	235	#define pe_err(pe, fmt, ...) \
	236	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
	237	#define pe_warn(pe, fmt, ...) \
	238	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
	239	#define pe_info(pe, fmt, ...) \
	240	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
	241
5d2aa710	242	/* Nvlink functions */
f9f83456	243	extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
6b3d12a9	244	extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
b5cb9ab1 AK	245	extern struct pnv_ioda_pe pnv_pci_npu_setup_iommu(struct pnv_ioda_pe npe);
	246	extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
	247	struct iommu_table *tbl);
	248	extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
	249	extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
	250	extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
1ab66d1f	251	extern int pnv_npu2_init(struct pnv_phb *phb);
4361b034 IM	252
	253	/* cxl functions */
	254	extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
	255	extern void pnv_cxl_disable_device(struct pci_dev *dev);
a2f67d5e IM	256	extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
a2f67d5e IM	257	extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
4361b034 IM	258
	259
	260	/* phb ops (cxl switches these when enabling the kernel api on the phb) */
	261	extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
	262
61305a96	263	#endif /* __POWERNV_PCI_H */