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61305a96 BH |
1 | #ifndef __POWERNV_PCI_H |
2 | #define __POWERNV_PCI_H | |
3 | ||
4 | struct pci_dn; | |
5 | ||
6 | enum pnv_phb_type { | |
aa0c033f GS |
7 | PNV_PHB_P5IOC2 = 0, |
8 | PNV_PHB_IODA1 = 1, | |
9 | PNV_PHB_IODA2 = 2, | |
61305a96 BH |
10 | }; |
11 | ||
cee72d5b BH |
12 | /* Precise PHB model for error management */ |
13 | enum pnv_phb_model { | |
14 | PNV_PHB_MODEL_UNKNOWN, | |
15 | PNV_PHB_MODEL_P5IOC2, | |
16 | PNV_PHB_MODEL_P7IOC, | |
aa0c033f | 17 | PNV_PHB_MODEL_PHB3, |
cee72d5b BH |
18 | }; |
19 | ||
20 | #define PNV_PCI_DIAG_BUF_SIZE 4096 | |
7ebdf956 GS |
21 | #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */ |
22 | #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */ | |
23 | #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ | |
cee72d5b | 24 | |
184cd4a3 | 25 | /* Data associated with a PE, including IOMMU tracking etc.. */ |
4cce9550 | 26 | struct pnv_phb; |
184cd4a3 | 27 | struct pnv_ioda_pe { |
7ebdf956 | 28 | unsigned long flags; |
4cce9550 | 29 | struct pnv_phb *phb; |
7ebdf956 | 30 | |
184cd4a3 BH |
31 | /* A PE can be associated with a single device or an |
32 | * entire bus (& children). In the former case, pdev | |
33 | * is populated, in the later case, pbus is. | |
34 | */ | |
35 | struct pci_dev *pdev; | |
36 | struct pci_bus *pbus; | |
37 | ||
38 | /* Effective RID (device RID for a device PE and base bus | |
39 | * RID with devfn 0 for a bus PE) | |
40 | */ | |
41 | unsigned int rid; | |
42 | ||
43 | /* PE number */ | |
44 | unsigned int pe_number; | |
45 | ||
46 | /* "Weight" assigned to the PE for the sake of DMA resource | |
47 | * allocations | |
48 | */ | |
49 | unsigned int dma_weight; | |
50 | ||
184cd4a3 BH |
51 | /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ |
52 | int tce32_seg; | |
53 | int tce32_segcount; | |
54 | struct iommu_table tce32_table; | |
8e0a1611 | 55 | phys_addr_t tce_inval_reg_phys; |
184cd4a3 BH |
56 | |
57 | /* XXX TODO: Add support for additional 64-bit iommus */ | |
58 | ||
59 | /* MSIs. MVE index is identical for for 32 and 64 bit MSI | |
60 | * and -1 if not supported. (It's actually identical to the | |
61 | * PE number) | |
62 | */ | |
63 | int mve_number; | |
64 | ||
65 | /* Link in list of PE#s */ | |
7ebdf956 GS |
66 | struct list_head dma_link; |
67 | struct list_head list; | |
184cd4a3 BH |
68 | }; |
69 | ||
8747f363 GS |
70 | /* IOC dependent EEH operations */ |
71 | #ifdef CONFIG_EEH | |
72 | struct pnv_eeh_ops { | |
73 | int (*post_init)(struct pci_controller *hose); | |
74 | int (*set_option)(struct eeh_pe *pe, int option); | |
75 | int (*get_state)(struct eeh_pe *pe); | |
76 | int (*reset)(struct eeh_pe *pe, int option); | |
77 | int (*get_log)(struct eeh_pe *pe, int severity, | |
78 | char *drv_log, unsigned long len); | |
79 | int (*configure_bridge)(struct eeh_pe *pe); | |
80 | int (*next_error)(struct eeh_pe **pe); | |
81 | }; | |
0b9e267d GS |
82 | |
83 | #define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */ | |
84 | #define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */ | |
85 | ||
8747f363 GS |
86 | #endif /* CONFIG_EEH */ |
87 | ||
61305a96 BH |
88 | struct pnv_phb { |
89 | struct pci_controller *hose; | |
90 | enum pnv_phb_type type; | |
cee72d5b | 91 | enum pnv_phb_model model; |
8747f363 | 92 | u64 hub_id; |
61305a96 BH |
93 | u64 opal_id; |
94 | void __iomem *regs; | |
db1266c8 | 95 | int initialized; |
61305a96 BH |
96 | spinlock_t lock; |
97 | ||
8747f363 GS |
98 | #ifdef CONFIG_EEH |
99 | struct pnv_eeh_ops *eeh_ops; | |
0b9e267d | 100 | int eeh_state; |
8747f363 GS |
101 | #endif |
102 | ||
37c367f2 GS |
103 | #ifdef CONFIG_DEBUG_FS |
104 | struct dentry *dbgfs; | |
105 | #endif | |
106 | ||
c1a2562a | 107 | #ifdef CONFIG_PCI_MSI |
c1a2562a | 108 | unsigned int msi_base; |
c1a2562a | 109 | unsigned int msi32_support; |
fb1b55d6 | 110 | struct msi_bitmap msi_bmp; |
c1a2562a BH |
111 | #endif |
112 | int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev, | |
137436c9 GS |
113 | unsigned int hwirq, unsigned int virq, |
114 | unsigned int is_64, struct msi_msg *msg); | |
61305a96 BH |
115 | void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev); |
116 | void (*fixup_phb)(struct pci_controller *hose); | |
117 | u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn); | |
73ed148a | 118 | void (*shutdown)(struct pnv_phb *phb); |
61305a96 BH |
119 | |
120 | union { | |
121 | struct { | |
122 | struct iommu_table iommu_table; | |
123 | } p5ioc2; | |
184cd4a3 BH |
124 | |
125 | struct { | |
126 | /* Global bridge info */ | |
127 | unsigned int total_pe; | |
128 | unsigned int m32_size; | |
129 | unsigned int m32_segsize; | |
130 | unsigned int m32_pci_base; | |
131 | unsigned int io_size; | |
132 | unsigned int io_segsize; | |
133 | unsigned int io_pci_base; | |
134 | ||
135 | /* PE allocation bitmap */ | |
136 | unsigned long *pe_alloc; | |
137 | ||
138 | /* M32 & IO segment maps */ | |
139 | unsigned int *m32_segmap; | |
140 | unsigned int *io_segmap; | |
141 | struct pnv_ioda_pe *pe_array; | |
142 | ||
137436c9 GS |
143 | /* IRQ chip */ |
144 | int irq_chip_init; | |
145 | struct irq_chip irq_chip; | |
146 | ||
7ebdf956 GS |
147 | /* Sorted list of used PE's based |
148 | * on the sequence of creation | |
149 | */ | |
150 | struct list_head pe_list; | |
151 | ||
184cd4a3 BH |
152 | /* Reverse map of PEs, will have to extend if |
153 | * we are to support more than 256 PEs, indexed | |
154 | * bus { bus, devfn } | |
155 | */ | |
156 | unsigned char pe_rmap[0x10000]; | |
157 | ||
158 | /* 32-bit TCE tables allocation */ | |
159 | unsigned long tce32_count; | |
160 | ||
161 | /* Total "weight" for the sake of DMA resources | |
162 | * allocation | |
163 | */ | |
164 | unsigned int dma_weight; | |
165 | unsigned int dma_pe_count; | |
166 | ||
167 | /* Sorted list of used PE's, sorted at | |
168 | * boot for resource allocation purposes | |
169 | */ | |
7ebdf956 | 170 | struct list_head pe_dma_list; |
184cd4a3 | 171 | } ioda; |
61305a96 | 172 | }; |
cee72d5b BH |
173 | |
174 | /* PHB status structure */ | |
175 | union { | |
176 | unsigned char blob[PNV_PCI_DIAG_BUF_SIZE]; | |
177 | struct OpalIoP7IOCPhbErrorData p7ioc; | |
178 | } diag; | |
61305a96 BH |
179 | }; |
180 | ||
181 | extern struct pci_ops pnv_pci_ops; | |
8747f363 GS |
182 | #ifdef CONFIG_EEH |
183 | extern struct pnv_eeh_ops ioda_eeh_ops; | |
184 | #endif | |
61305a96 | 185 | |
9bf41be6 GS |
186 | int pnv_pci_cfg_read(struct device_node *dn, |
187 | int where, int size, u32 *val); | |
188 | int pnv_pci_cfg_write(struct device_node *dn, | |
189 | int where, int size, u32 val); | |
61305a96 BH |
190 | extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, |
191 | void *tce_mem, u64 tce_size, | |
192 | u64 dma_offset); | |
193 | extern void pnv_pci_init_p5ioc2_hub(struct device_node *np); | |
184cd4a3 | 194 | extern void pnv_pci_init_ioda_hub(struct device_node *np); |
aa0c033f | 195 | extern void pnv_pci_init_ioda2_phb(struct device_node *np); |
4cce9550 | 196 | extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, |
8e0a1611 | 197 | u64 *startp, u64 *endp, bool rm); |
73ed148a | 198 | |
61305a96 | 199 | #endif /* __POWERNV_PCI_H */ |