[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / platforms / powernv / pci.h

#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

struct pci_dn;

enum pnv_phb_type {
	PNV_PHB_P5IOC2	= 0,
	PNV_PHB_IODA1	= 1,
	PNV_PHB_IODA2	= 2,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P5IOC2,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
#ifdef CONFIG_PCI_IOV
	struct pci_dev          *parent_dev;
#endif
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Weight" assigned to the PE for the sake of DMA resource
	 * allocations
	 */
	unsigned int		dma_weight;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	int			tce32_seg;
	int			tce32_segcount;
	struct iommu_table	*tce32_table;
	phys_addr_t		tce_inval_reg_phys;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* PEs in compound case */
	struct pnv_ioda_pe	*master;
	struct list_head	slaves;

	/* Link in list of PE#s */
	struct list_head	dma_link;
	struct list_head	list;
};

#define PNV_PHB_FLAG_EEH	(1 << 0)

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	int			flags;
	void __iomem		*regs;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_DEBUG_FS
	int			has_dbgfs;
	struct dentry		*dbgfs;
#endif

#ifdef CONFIG_PCI_MSI
	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
#endif
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
			    u64 dma_mask);
	u64 (*dma_get_required_mask)(struct pnv_phb *phb,
				     struct pci_dev *pdev);
	void (*fixup_phb)(struct pci_controller *hose);
	u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
	void (*shutdown)(struct pnv_phb *phb);
	int (*init_m64)(struct pnv_phb *phb);
	void (*reserve_m64_pe)(struct pnv_phb *phb);
	int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

	union {
		struct {
			struct iommu_table iommu_table;
		} p5ioc2;

		struct {
			/* Global bridge info */
			unsigned int		total_pe;
			unsigned int		reserved_pe;

			/* 32-bit MMIO window */
			unsigned int		m32_size;
			unsigned int		m32_segsize;
			unsigned int		m32_pci_base;

			/* 64-bit MMIO window */
			unsigned int		m64_bar_idx;
			unsigned long		m64_size;
			unsigned long		m64_segsize;
			unsigned long		m64_base;
			unsigned long		m64_bar_alloc;

			/* IO ports */
			unsigned int		io_size;
			unsigned int		io_segsize;
			unsigned int		io_pci_base;

			/* PE allocation bitmap */
			unsigned long		*pe_alloc;
			/* PE allocation mutex */
			struct mutex		pe_alloc_mutex;

			/* M32 & IO segment maps */
			unsigned int		*m32_segmap;
			unsigned int		*io_segmap;
			struct pnv_ioda_pe	*pe_array;

			/* IRQ chip */
			int			irq_chip_init;
			struct irq_chip		irq_chip;

			/* Sorted list of used PE's based
			 * on the sequence of creation
			 */
			struct list_head	pe_list;
			struct mutex            pe_list_mutex;

			/* Reverse map of PEs, will have to extend if
			 * we are to support more than 256 PEs, indexed
			 * bus { bus, devfn }
			 */
			unsigned char		pe_rmap[0x10000];

			/* 32-bit TCE tables allocation */
			unsigned long		tce32_count;

			/* Total "weight" for the sake of DMA resources
			 * allocation
			 */
			unsigned int		dma_weight;
			unsigned int		dma_pe_count;

			/* Sorted list of used PE's, sorted at
			 * boot for resource allocation purposes
			 */
			struct list_head	pe_dma_list;
		} ioda;
	};

	/* PHB and hub status structure */
	union {
		unsigned char			blob[PNV_PCI_DIAG_BUF_SIZE];
		struct OpalIoP7IOCPhbErrorData	p7ioc;
		struct OpalIoPhb3ErrorData	phb3;
		struct OpalIoP7IOCErrorData 	hub_diag;
	} diag;

};

extern struct pci_ops pnv_pci_ops;

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct pci_dn *pdn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct pci_dn *pdn,
		      int where, int size, u32 val);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
				      void *tce_mem, u64 tce_size,
				      u64 dma_offset, unsigned page_shift);
extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
					__be64 *startp, __be64 *endp, bool rm);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);

extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
61305a96 BH	1	#ifndef __POWERNV_PCI_H
	2	#define __POWERNV_PCI_H
	3
	4	struct pci_dn;
	5
	6	enum pnv_phb_type {
aa0c033f GS	7	PNV_PHB_P5IOC2 = 0,
	8	PNV_PHB_IODA1 = 1,
	9	PNV_PHB_IODA2 = 2,
61305a96 BH	10	};
61305a96 BH	11
cee72d5b BH	12	/* Precise PHB model for error management */
	13	enum pnv_phb_model {
	14	PNV_PHB_MODEL_UNKNOWN,
	15	PNV_PHB_MODEL_P5IOC2,
	16	PNV_PHB_MODEL_P7IOC,
aa0c033f	17	PNV_PHB_MODEL_PHB3,
cee72d5b BH	18	};
cee72d5b BH	19
5c9d6d75	20	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	21	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	22	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	23	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
262af557 GC	24	#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
262af557 GC	25	#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
781a868f	26	#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
cee72d5b	27
184cd4a3	28	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	29	struct pnv_phb;
184cd4a3	30	struct pnv_ioda_pe {
7ebdf956	31	unsigned long flags;
4cce9550	32	struct pnv_phb *phb;
7ebdf956	33
184cd4a3 BH	34	/* A PE can be associated with a single device or an
	35	* entire bus (& children). In the former case, pdev
	36	* is populated, in the later case, pbus is.
	37	*/
781a868f WY	38	#ifdef CONFIG_PCI_IOV
	39	struct pci_dev *parent_dev;
	40	#endif
184cd4a3 BH	41	struct pci_dev *pdev;
	42	struct pci_bus *pbus;
	43
	44	/* Effective RID (device RID for a device PE and base bus
	45	* RID with devfn 0 for a bus PE)
	46	*/
	47	unsigned int rid;
	48
	49	/* PE number */
	50	unsigned int pe_number;
	51
	52	/* "Weight" assigned to the PE for the sake of DMA resource
	53	* allocations
	54	*/
	55	unsigned int dma_weight;
	56
184cd4a3 BH	57	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	58	int tce32_seg;
	59	int tce32_segcount;
9e8d4a19	60	struct iommu_table *tce32_table;
8e0a1611	61	phys_addr_t tce_inval_reg_phys;
184cd4a3	62
cd15b048 BH	63	/* 64-bit TCE bypass region */
	64	bool tce_bypass_enabled;
	65	uint64_t tce_bypass_base;
184cd4a3 BH	66
	67	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	68	* and -1 if not supported. (It's actually identical to the
	69	* PE number)
	70	*/
	71	int mve_number;
	72
262af557 GC	73	/* PEs in compound case */
	74	struct pnv_ioda_pe *master;
	75	struct list_head slaves;
	76
184cd4a3	77	/* Link in list of PE#s */
7ebdf956 GS	78	struct list_head dma_link;
7ebdf956 GS	79	struct list_head list;
184cd4a3 BH	80	};
184cd4a3 BH	81
f5bc6b70 GS	82	#define PNV_PHB_FLAG_EEH (1 << 0)
f5bc6b70 GS	83
61305a96 BH	84	struct pnv_phb {
	85	struct pci_controller *hose;
	86	enum pnv_phb_type type;
cee72d5b	87	enum pnv_phb_model model;
8747f363	88	u64 hub_id;
61305a96	89	u64 opal_id;
f5bc6b70	90	int flags;
61305a96	91	void __iomem *regs;
db1266c8	92	int initialized;
61305a96 BH	93	spinlock_t lock;
61305a96 BH	94
37c367f2	95	#ifdef CONFIG_DEBUG_FS
7f52a526	96	int has_dbgfs;
37c367f2 GS	97	struct dentry *dbgfs;
	98	#endif
	99
c1a2562a	100	#ifdef CONFIG_PCI_MSI
c1a2562a	101	unsigned int msi_base;
c1a2562a	102	unsigned int msi32_support;
fb1b55d6	103	struct msi_bitmap msi_bmp;
c1a2562a BH	104	#endif
c1a2562a BH	105	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	106	unsigned int hwirq, unsigned int virq,
137436c9 GS	107	unsigned int is_64, struct msi_msg *msg);
61305a96	108	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
cd15b048 BH	109	int (dma_set_mask)(struct pnv_phb phb, struct pci_dev *pdev,
cd15b048 BH	110	u64 dma_mask);
fe7e85c6 GS	111	u64 (dma_get_required_mask)(struct pnv_phb phb,
fe7e85c6 GS	112	struct pci_dev *pdev);
61305a96 BH	113	void (fixup_phb)(struct pci_controller hose);
61305a96 BH	114	u32 (bdfn_to_pe)(struct pnv_phb phb, struct pci_bus *bus, u32 devfn);
73ed148a	115	void (shutdown)(struct pnv_phb phb);
262af557	116	int (init_m64)(struct pnv_phb phb);
5ef73567	117	void (reserve_m64_pe)(struct pnv_phb phb);
262af557	118	int (pick_m64_pe)(struct pnv_phb phb, struct pci_bus *bus, int all);
49dec922 GS	119	int (get_pe_state)(struct pnv_phb phb, int pe_no);
	120	void (freeze_pe)(struct pnv_phb phb, int pe_no);
	121	int (unfreeze_pe)(struct pnv_phb phb, int pe_no, int opt);
61305a96 BH	122
	123	union {
	124	struct {
	125	struct iommu_table iommu_table;
	126	} p5ioc2;
184cd4a3 BH	127
	128	struct {
	129	/* Global bridge info */
	130	unsigned int total_pe;
36954dc7	131	unsigned int reserved_pe;
262af557 GC	132
262af557 GC	133	/* 32-bit MMIO window */
184cd4a3 BH	134	unsigned int m32_size;
	135	unsigned int m32_segsize;
	136	unsigned int m32_pci_base;
262af557 GC	137
	138	/* 64-bit MMIO window */
	139	unsigned int m64_bar_idx;
	140	unsigned long m64_size;
	141	unsigned long m64_segsize;
	142	unsigned long m64_base;
	143	unsigned long m64_bar_alloc;
	144
	145	/* IO ports */
184cd4a3 BH	146	unsigned int io_size;
	147	unsigned int io_segsize;
	148	unsigned int io_pci_base;
	149
	150	/* PE allocation bitmap */
	151	unsigned long *pe_alloc;
781a868f WY	152	/* PE allocation mutex */
781a868f WY	153	struct mutex pe_alloc_mutex;
184cd4a3 BH	154
	155	/* M32 & IO segment maps */
	156	unsigned int *m32_segmap;
	157	unsigned int *io_segmap;
	158	struct pnv_ioda_pe *pe_array;
	159
137436c9 GS	160	/* IRQ chip */
	161	int irq_chip_init;
	162	struct irq_chip irq_chip;
	163
7ebdf956 GS	164	/* Sorted list of used PE's based
	165	* on the sequence of creation
	166	*/
	167	struct list_head pe_list;
781a868f	168	struct mutex pe_list_mutex;
7ebdf956	169
184cd4a3 BH	170	/* Reverse map of PEs, will have to extend if
	171	* we are to support more than 256 PEs, indexed
	172	* bus { bus, devfn }
	173	*/
	174	unsigned char pe_rmap[0x10000];
	175
	176	/* 32-bit TCE tables allocation */
	177	unsigned long tce32_count;
	178
	179	/* Total "weight" for the sake of DMA resources
	180	* allocation
	181	*/
	182	unsigned int dma_weight;
	183	unsigned int dma_pe_count;
	184
	185	/* Sorted list of used PE's, sorted at
	186	* boot for resource allocation purposes
	187	*/
7ebdf956	188	struct list_head pe_dma_list;
184cd4a3	189	} ioda;
61305a96	190	};
cee72d5b	191
ca1de5de	192	/* PHB and hub status structure */
cee72d5b BH	193	union {
	194	unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
	195	struct OpalIoP7IOCPhbErrorData p7ioc;
93aef2a7	196	struct OpalIoPhb3ErrorData phb3;
ca1de5de	197	struct OpalIoP7IOCErrorData hub_diag;
cee72d5b	198	} diag;
ca1de5de	199
61305a96 BH	200	};
	201
	202	extern struct pci_ops pnv_pci_ops;
	203
93aef2a7 GS	204	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	205	unsigned char *log_buff);
3532a741	206	int pnv_pci_cfg_read(struct pci_dn *pdn,
9bf41be6	207	int where, int size, u32 *val);
3532a741	208	int pnv_pci_cfg_write(struct pci_dn *pdn,
9bf41be6	209	int where, int size, u32 val);
61305a96 BH	210	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
61305a96 BH	211	void *tce_mem, u64 tce_size,
8fa5d454	212	u64 dma_offset, unsigned page_shift);
61305a96	213	extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
184cd4a3	214	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	215	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
4cce9550	216	extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
3ad26e5c	217	__be64 startp, __be64 endp, bool rm);
d92a208d	218	extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
cadf364d	219	extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
73ed148a	220
92ae0353 DA	221	extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
	222	extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
	223	extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
	224
61305a96	225	#endif /* __POWERNV_PCI_H */